| 1 | /* |
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| 2 | * Common prep/pmac/chrp boot and setup code. |
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| 3 | */ |
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| 4 | |
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| 5 | #include <linux/module.h> |
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| 6 | #include <linux/string.h> |
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| 7 | #include <linux/sched.h> |
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| 8 | #include <linux/init.h> |
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| 9 | #include <linux/kernel.h> |
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| 10 | #include <linux/reboot.h> |
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| 11 | #include <linux/delay.h> |
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| 12 | #include <linux/initrd.h> |
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| 13 | #include <linux/tty.h> |
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| 14 | #include <linux/bootmem.h> |
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| 15 | #include <linux/seq_file.h> |
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| 16 | #include <linux/root_dev.h> |
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| 17 | #include <linux/cpu.h> |
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| 18 | #include <linux/console.h> |
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| 19 | #include <linux/memblock.h> |
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| 20 | |
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| 21 | #include <asm/io.h> |
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| 22 | #include <asm/prom.h> |
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| 23 | #include <asm/processor.h> |
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| 24 | #include <asm/pgtable.h> |
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| 25 | #include <asm/setup.h> |
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| 26 | #include <asm/smp.h> |
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| 27 | #include <asm/elf.h> |
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| 28 | #include <asm/cputable.h> |
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| 29 | #include <asm/bootx.h> |
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| 30 | #include <asm/btext.h> |
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| 31 | #include <asm/machdep.h> |
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| 32 | #include <asm/uaccess.h> |
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| 33 | #include <asm/system.h> |
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| 34 | #include <asm/pmac_feature.h> |
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| 35 | #include <asm/sections.h> |
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| 36 | #include <asm/nvram.h> |
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| 37 | #include <asm/xmon.h> |
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| 38 | #include <asm/time.h> |
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| 39 | #include <asm/serial.h> |
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| 40 | #include <asm/udbg.h> |
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| 41 | #include <asm/mmu_context.h> |
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| 42 | |
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| 43 | #include "setup.h" |
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| 44 | |
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| 45 | #define DBG(fmt...) |
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| 46 | |
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| 47 | extern void bootx_init(unsigned long r4, unsigned long phys); |
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| 48 | |
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| 49 | int boot_cpuid = -1; |
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| 50 | EXPORT_SYMBOL_GPL(boot_cpuid); |
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| 51 | int boot_cpuid_phys; |
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| 52 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
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| 53 | |
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| 54 | int smp_hw_index[NR_CPUS]; |
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| 55 | |
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| 56 | unsigned long ISA_DMA_THRESHOLD; |
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| 57 | unsigned int DMA_MODE_READ; |
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| 58 | unsigned int DMA_MODE_WRITE; |
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| 59 | |
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| 60 | #ifdef CONFIG_VGA_CONSOLE |
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| 61 | unsigned long vgacon_remap_base; |
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| 62 | EXPORT_SYMBOL(vgacon_remap_base); |
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| 63 | #endif |
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| 64 | |
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| 65 | /* |
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| 66 | * These are used in binfmt_elf.c to put aux entries on the stack |
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| 67 | * for each elf executable being started. |
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| 68 | */ |
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| 69 | int dcache_bsize; |
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| 70 | int icache_bsize; |
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| 71 | int ucache_bsize; |
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| 72 | |
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| 73 | /* |
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| 74 | * We're called here very early in the boot. We determine the machine |
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| 75 | * type and call the appropriate low-level setup functions. |
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| 76 | * -- Cort <cort@fsmlabs.com> |
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| 77 | * |
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| 78 | * Note that the kernel may be running at an address which is different |
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| 79 | * from the address that it was linked at, so we must use RELOC/PTRRELOC |
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| 80 | * to access static data (including strings). -- paulus |
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| 81 | */ |
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| 82 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
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| 83 | { |
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| 84 | unsigned long offset = reloc_offset(); |
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| 85 | struct cpu_spec *spec; |
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| 86 | |
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| 87 | /* First zero the BSS -- use memset_io, some platforms don't have |
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| 88 | * caches on yet */ |
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| 89 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
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| 90 | __bss_stop - __bss_start); |
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| 91 | |
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| 92 | /* |
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| 93 | * Identify the CPU type and fix up code sections |
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| 94 | * that depend on which cpu we have. |
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| 95 | */ |
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| 96 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
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| 97 | |
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| 98 | do_feature_fixups(spec->cpu_features, |
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| 99 | PTRRELOC(&__start___ftr_fixup), |
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| 100 | PTRRELOC(&__stop___ftr_fixup)); |
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| 101 | |
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| 102 | do_feature_fixups(spec->mmu_features, |
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| 103 | PTRRELOC(&__start___mmu_ftr_fixup), |
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| 104 | PTRRELOC(&__stop___mmu_ftr_fixup)); |
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| 105 | |
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| 106 | do_lwsync_fixups(spec->cpu_features, |
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| 107 | PTRRELOC(&__start___lwsync_fixup), |
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| 108 | PTRRELOC(&__stop___lwsync_fixup)); |
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| 109 | |
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| 110 | return KERNELBASE + offset; |
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| 111 | } |
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| 112 | |
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| 113 | |
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| 114 | /* |
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| 115 | * Find out what kind of machine we're on and save any data we need |
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| 116 | * from the early boot process (devtree is copied on pmac by prom_init()). |
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| 117 | * This is called very early on the boot process, after a minimal |
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| 118 | * MMU environment has been set up but before MMU_init is called. |
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| 119 | */ |
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| 120 | notrace void __init machine_init(unsigned long dt_ptr) |
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| 121 | { |
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| 122 | lockdep_init(); |
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| 123 | |
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| 124 | /* Enable early debugging if any specified (see udbg.h) */ |
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| 125 | udbg_early_init(); |
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| 126 | |
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| 127 | /* Do some early initialization based on the flat device tree */ |
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| 128 | early_init_devtree(__va(dt_ptr)); |
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| 129 | |
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| 130 | early_init_mmu(); |
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| 131 | |
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| 132 | probe_machine(); |
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| 133 | |
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| 134 | setup_kdump_trampoline(); |
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| 135 | |
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| 136 | #ifdef CONFIG_6xx |
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| 137 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
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| 138 | cpu_has_feature(CPU_FTR_CAN_NAP)) |
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| 139 | ppc_md.power_save = ppc6xx_idle; |
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| 140 | #endif |
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| 141 | |
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| 142 | #ifdef CONFIG_E500 |
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| 143 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
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| 144 | cpu_has_feature(CPU_FTR_CAN_NAP)) |
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| 145 | ppc_md.power_save = e500_idle; |
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| 146 | #endif |
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| 147 | if (ppc_md.progress) |
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| 148 | ppc_md.progress("id mach(): done", 0x200); |
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| 149 | } |
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| 150 | |
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| 151 | #ifdef CONFIG_BOOKE_WDT |
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| 152 | /* Checks wdt=x and wdt_period=xx command-line option */ |
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| 153 | notrace int __init early_parse_wdt(char *p) |
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| 154 | { |
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| 155 | if (p && strncmp(p, "0", 1) != 0) |
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| 156 | booke_wdt_enabled = 1; |
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| 157 | |
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| 158 | return 0; |
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| 159 | } |
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| 160 | early_param("wdt", early_parse_wdt); |
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| 161 | |
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| 162 | int __init early_parse_wdt_period (char *p) |
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| 163 | { |
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| 164 | if (p) |
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| 165 | booke_wdt_period = simple_strtoul(p, NULL, 0); |
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| 166 | |
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| 167 | return 0; |
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| 168 | } |
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| 169 | early_param("wdt_period", early_parse_wdt_period); |
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| 170 | #endif /* CONFIG_BOOKE_WDT */ |
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| 171 | |
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| 172 | /* Checks "l2cr=xxxx" command-line option */ |
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| 173 | int __init ppc_setup_l2cr(char *str) |
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| 174 | { |
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| 175 | if (cpu_has_feature(CPU_FTR_L2CR)) { |
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| 176 | unsigned long val = simple_strtoul(str, NULL, 0); |
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| 177 | printk(KERN_INFO "l2cr set to %lx\n", val); |
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| 178 | _set_L2CR(0); /* force invalidate by disable cache */ |
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| 179 | _set_L2CR(val); /* and enable it */ |
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| 180 | } |
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| 181 | return 1; |
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| 182 | } |
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| 183 | __setup("l2cr=", ppc_setup_l2cr); |
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| 184 | |
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| 185 | /* Checks "l3cr=xxxx" command-line option */ |
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| 186 | int __init ppc_setup_l3cr(char *str) |
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| 187 | { |
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| 188 | if (cpu_has_feature(CPU_FTR_L3CR)) { |
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| 189 | unsigned long val = simple_strtoul(str, NULL, 0); |
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| 190 | printk(KERN_INFO "l3cr set to %lx\n", val); |
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| 191 | _set_L3CR(val); /* and enable it */ |
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| 192 | } |
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| 193 | return 1; |
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| 194 | } |
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| 195 | __setup("l3cr=", ppc_setup_l3cr); |
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| 196 | |
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| 197 | #ifdef CONFIG_GENERIC_NVRAM |
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| 198 | |
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| 199 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ |
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| 200 | unsigned char nvram_read_byte(int addr) |
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| 201 | { |
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| 202 | if (ppc_md.nvram_read_val) |
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| 203 | return ppc_md.nvram_read_val(addr); |
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| 204 | return 0xff; |
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| 205 | } |
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| 206 | EXPORT_SYMBOL(nvram_read_byte); |
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| 207 | |
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| 208 | void nvram_write_byte(unsigned char val, int addr) |
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| 209 | { |
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| 210 | if (ppc_md.nvram_write_val) |
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| 211 | ppc_md.nvram_write_val(addr, val); |
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| 212 | } |
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| 213 | EXPORT_SYMBOL(nvram_write_byte); |
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| 214 | |
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| 215 | ssize_t nvram_get_size(void) |
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| 216 | { |
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| 217 | if (ppc_md.nvram_size) |
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| 218 | return ppc_md.nvram_size(); |
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| 219 | return -1; |
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| 220 | } |
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| 221 | EXPORT_SYMBOL(nvram_get_size); |
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| 222 | |
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| 223 | void nvram_sync(void) |
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| 224 | { |
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| 225 | if (ppc_md.nvram_sync) |
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| 226 | ppc_md.nvram_sync(); |
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| 227 | } |
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| 228 | EXPORT_SYMBOL(nvram_sync); |
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| 229 | |
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| 230 | #endif /* CONFIG_NVRAM */ |
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| 231 | |
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| 232 | int __init ppc_init(void) |
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| 233 | { |
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| 234 | /* clear the progress line */ |
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| 235 | if (ppc_md.progress) |
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| 236 | ppc_md.progress(" ", 0xffff); |
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| 237 | |
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| 238 | /* call platform init */ |
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| 239 | if (ppc_md.init != NULL) { |
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| 240 | ppc_md.init(); |
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| 241 | } |
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| 242 | return 0; |
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| 243 | } |
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| 244 | |
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| 245 | arch_initcall(ppc_init); |
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| 246 | |
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| 247 | static void __init irqstack_early_init(void) |
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| 248 | { |
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| 249 | unsigned int i; |
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| 250 | |
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| 251 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 |
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| 252 | * as the memblock is limited to lowmem by default */ |
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| 253 | for_each_possible_cpu(i) { |
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| 254 | softirq_ctx[i] = (struct thread_info *) |
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| 255 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
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| 256 | hardirq_ctx[i] = (struct thread_info *) |
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| 257 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
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| 258 | } |
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| 259 | } |
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| 260 | |
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| 261 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
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| 262 | static void __init exc_lvl_early_init(void) |
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| 263 | { |
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| 264 | unsigned int i, hw_cpu; |
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| 265 | |
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| 266 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 |
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| 267 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
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| 268 | for_each_possible_cpu(i) { |
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| 269 | hw_cpu = get_hard_smp_processor_id(i); |
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| 270 | critirq_ctx[hw_cpu] = (struct thread_info *) |
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| 271 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
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| 272 | #ifdef CONFIG_BOOKE |
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| 273 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
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| 274 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
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| 275 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
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| 276 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
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| 277 | #endif |
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| 278 | } |
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| 279 | } |
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| 280 | #else |
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| 281 | #define exc_lvl_early_init() |
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| 282 | #endif |
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| 283 | |
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| 284 | /* Warning, IO base is not yet inited */ |
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| 285 | void __init setup_arch(char **cmdline_p) |
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| 286 | { |
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| 287 | *cmdline_p = cmd_line; |
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| 288 | |
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| 289 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
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| 290 | loops_per_jiffy = 500000000 / HZ; |
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| 291 | |
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| 292 | unflatten_device_tree(); |
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| 293 | check_for_initrd(); |
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| 294 | |
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| 295 | if (ppc_md.init_early) |
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| 296 | ppc_md.init_early(); |
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| 297 | |
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| 298 | find_legacy_serial_ports(); |
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| 299 | |
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| 300 | smp_setup_cpu_maps(); |
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| 301 | |
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| 302 | /* Register early console */ |
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| 303 | register_early_udbg_console(); |
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| 304 | |
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| 305 | xmon_setup(); |
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| 306 | |
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| 307 | /* |
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| 308 | * Set cache line size based on type of cpu as a default. |
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| 309 | * Systems with OF can look in the properties on the cpu node(s) |
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| 310 | * for a possibly more accurate value. |
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| 311 | */ |
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| 312 | dcache_bsize = cur_cpu_spec->dcache_bsize; |
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| 313 | icache_bsize = cur_cpu_spec->icache_bsize; |
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| 314 | ucache_bsize = 0; |
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| 315 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) |
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| 316 | ucache_bsize = icache_bsize = dcache_bsize; |
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| 317 | |
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| 318 | /* reboot on panic */ |
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| 319 | panic_timeout = 180; |
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| 320 | |
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| 321 | if (ppc_md.panic) |
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| 322 | setup_panic(); |
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| 323 | |
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| 324 | init_mm.start_code = (unsigned long)_stext; |
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| 325 | init_mm.end_code = (unsigned long) _etext; |
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| 326 | init_mm.end_data = (unsigned long) _edata; |
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| 327 | init_mm.brk = klimit; |
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| 328 | |
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| 329 | exc_lvl_early_init(); |
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| 330 | |
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| 331 | irqstack_early_init(); |
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| 332 | |
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| 333 | /* set up the bootmem stuff with available memory */ |
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| 334 | do_init_bootmem(); |
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| 335 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab); |
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| 336 | |
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| 337 | #ifdef CONFIG_DUMMY_CONSOLE |
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| 338 | conswitchp = &dummy_con; |
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| 339 | #endif |
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| 340 | |
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| 341 | if (ppc_md.setup_arch) |
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| 342 | ppc_md.setup_arch(); |
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| 343 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
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| 344 | |
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| 345 | paging_init(); |
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| 346 | |
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| 347 | /* Initialize the MMU context management stuff */ |
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| 348 | mmu_context_init(); |
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| 349 | |
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| 350 | } |
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