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source: src/linux/pb42/linux-3.2/drivers/net/ethernet/ag71xx/ag71xx_dev.c @ 18138

Last change on this file since 18138 was 18138, checked in by BrainSlayer, 17 months ago
add support for dir825, wndr3700 and so on
File size: 23.7 KB

Line
1	/*
2	* Atheros AR71xx SoC platform devices
3	*
4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5	* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7	*
8	* Parts of this file are based on Atheros 2.6.15 BSP
9	* Parts of this file are based on Atheros 2.6.31 BSP
10	*
11	* This program is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU General Public License version 2 as published
13	* by the Free Software Foundation.
14	*/
15
16	#include <linux/kernel.h>
17	#include <linux/init.h>
18	#include <linux/delay.h>
19	#include <linux/etherdevice.h>
20	#include <linux/platform_device.h>
21	#include <linux/serial_8250.h>
22	#include <linux/phy.h>
23	#include <linux/rtl8366.h>
24
25	#include <asm/mach-ar71xx/ar71xx.h>
26	#include <asm/mach-ar71xx/platform.h>
27
28	static struct resource ar71xx_mdio0_resources[] = {
29	{
30	.name = "mdio_base",
31	.flags = IORESOURCE_MEM,
32	.start = AR71XX_GE0_BASE,
33	.end = AR71XX_GE0_BASE + 0x200 - 1,
34	}
35	};
36
37	static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
38
39	struct platform_device ar71xx_mdio0_device = {
40	.name = "ag71xx-mdio",
41	.id = 0,
42	.resource = ar71xx_mdio0_resources,
43	.num_resources = ARRAY_SIZE(ar71xx_mdio0_resources),
44	.dev = {
45	.platform_data = &ar71xx_mdio0_data,
46	},
47	};
48
49	static struct resource ar71xx_mdio1_resources[] = {
50	{
51	.name = "mdio_base",
52	.flags = IORESOURCE_MEM,
53	.start = AR71XX_GE1_BASE,
54	.end = AR71XX_GE1_BASE + 0x200 - 1,
55	}
56	};
57
58	static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
59
60	struct platform_device ar71xx_mdio1_device = {
61	.name = "ag71xx-mdio",
62	.id = 1,
63	.resource = ar71xx_mdio1_resources,
64	.num_resources = ARRAY_SIZE(ar71xx_mdio1_resources),
65	.dev = {
66	.platform_data = &ar71xx_mdio1_data,
67	},
68	};
69
70	static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
71	{
72	void __iomem *base;
73	u32 t;
74
75	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
76
77	t = __raw_readl(base + cfg_reg);
78	t &= ~(3 << shift);
79	t \|= (2 << shift);
80	__raw_writel(t, base + cfg_reg);
81	udelay(100);
82
83	__raw_writel(pll_val, base + pll_reg);
84
85	t \|= (3 << shift);
86	__raw_writel(t, base + cfg_reg);
87	udelay(100);
88
89	t &= ~(3 << shift);
90	__raw_writel(t, base + cfg_reg);
91	udelay(100);
92
93	printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
94	(unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
95
96	iounmap(base);
97	}
98
99	static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
100	unsigned int mii_if)
101	{
102	void __iomem *base;
103	u32 t;
104
105	base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
106
107	t = __raw_readl(base + reg);
108	t &= ~(MII_CTRL_IF_MASK);
109	t \|= (mii_if & MII_CTRL_IF_MASK);
110	__raw_writel(t, base + reg);
111
112	iounmap(base);
113	}
114
115	static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
116	{
117	void __iomem *base;
118	unsigned int mii_speed;
119	u32 t;
120
121	switch (speed) {
122	case SPEED_10:
123	mii_speed = MII_CTRL_SPEED_10;
124	break;
125	case SPEED_100:
126	mii_speed = MII_CTRL_SPEED_100;
127	break;
128	case SPEED_1000:
129	mii_speed = MII_CTRL_SPEED_1000;
130	break;
131	default:
132	BUG();
133	return;
134	}
135
136	base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
137
138	t = __raw_readl(base + reg);
139	t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
140	t \|= mii_speed << MII_CTRL_SPEED_SHIFT;
141	__raw_writel(t, base + reg);
142
143	iounmap(base);
144	}
145
146	void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
147	{
148	struct platform_device *mdio_dev;
149	struct ag71xx_mdio_platform_data *mdio_data;
150	unsigned int max_id;
151
152	if (ar71xx_soc == AR71XX_SOC_AR9341 \|\|
153	ar71xx_soc == AR71XX_SOC_AR9342 \|\|
154	ar71xx_soc == AR71XX_SOC_AR9344)
155	max_id = 1;
156	else
157	max_id = 0;
158
159	if (id > max_id) {
160	printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
161	return;
162	}
163
164	switch (ar71xx_soc) {
165	case AR71XX_SOC_AR7241:
166	case AR71XX_SOC_AR9330:
167	case AR71XX_SOC_AR9331:
168	mdio_dev = &ar71xx_mdio1_device;
169	mdio_data = &ar71xx_mdio1_data;
170	break;
171
172	case AR71XX_SOC_AR9341:
173	case AR71XX_SOC_AR9342:
174	case AR71XX_SOC_AR9344:
175	if (id == 0) {
176	mdio_dev = &ar71xx_mdio0_device;
177	mdio_data = &ar71xx_mdio0_data;
178	} else {
179	mdio_dev = &ar71xx_mdio1_device;
180	mdio_data = &ar71xx_mdio1_data;
181	}
182	break;
183
184	case AR71XX_SOC_AR7242:
185	ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
186	AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
187	AR71XX_ETH0_PLL_SHIFT);
188	/* fall through */
189	default:
190	mdio_dev = &ar71xx_mdio0_device;
191	mdio_data = &ar71xx_mdio0_data;
192	break;
193	}
194
195	mdio_data->phy_mask = phy_mask;
196
197	switch (ar71xx_soc) {
198	case AR71XX_SOC_AR7240:
199	case AR71XX_SOC_AR7241:
200	case AR71XX_SOC_AR9330:
201	case AR71XX_SOC_AR9331:
202	mdio_data->is_ar7240 = 1;
203	break;
204
205	case AR71XX_SOC_AR9341:
206	case AR71XX_SOC_AR9342:
207	case AR71XX_SOC_AR9344:
208	if (id == 1)
209	mdio_data->is_ar7240 = 1;
210	break;
211
212	default:
213	break;
214	}
215
216	platform_device_register(mdio_dev);
217	}
218
219	struct ar71xx_eth_pll_data {
220	u32 pll_10;
221	u32 pll_100;
222	u32 pll_1000;
223	};
224
225	static struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
226	static struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
227
228	static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
229	{
230	struct ar71xx_eth_pll_data *pll_data;
231	u32 pll_val;
232
233	switch (mac) {
234	case 0:
235	pll_data = &ar71xx_eth0_pll_data;
236	break;
237	case 1:
238	pll_data = &ar71xx_eth1_pll_data;
239	break;
240	default:
241	BUG();
242	return 0;
243	}
244
245	switch (speed) {
246	case SPEED_10:
247	pll_val = pll_data->pll_10;
248	break;
249	case SPEED_100:
250	pll_val = pll_data->pll_100;
251	break;
252	case SPEED_1000:
253	pll_val = pll_data->pll_1000;
254	break;
255	default:
256	BUG();
257	return 0;
258	}
259
260	return pll_val;
261	}
262
263	static void ar71xx_set_speed_ge0(int speed)
264	{
265	u32 val = ar71xx_get_eth_pll(0, speed);
266
267	ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
268	val, AR71XX_ETH0_PLL_SHIFT);
269	ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
270	}
271
272	static void ar71xx_set_speed_ge1(int speed)
273	{
274	u32 val = ar71xx_get_eth_pll(1, speed);
275
276	ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
277	val, AR71XX_ETH1_PLL_SHIFT);
278	ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
279	}
280
281	static void ar724x_set_speed_ge0(int speed)
282	{
283	/* TODO */
284	}
285
286	static void ar724x_set_speed_ge1(int speed)
287	{
288	/* TODO */
289	}
290
291	static void ar7242_set_speed_ge0(int speed)
292	{
293	u32 val = ar71xx_get_eth_pll(0, speed);
294	void __iomem *base;
295
296	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
297	__raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
298	iounmap(base);
299	}
300
301	static void ar91xx_set_speed_ge0(int speed)
302	{
303	u32 val = ar71xx_get_eth_pll(0, speed);
304
305	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
306	val, AR91XX_ETH0_PLL_SHIFT);
307	ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
308	}
309
310	static void ar91xx_set_speed_ge1(int speed)
311	{
312	u32 val = ar71xx_get_eth_pll(1, speed);
313
314	ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
315	val, AR91XX_ETH1_PLL_SHIFT);
316	ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
317	}
318
319	static void ar933x_set_speed_ge0(int speed)
320	{
321	/* TODO */
322	}
323
324	static void ar933x_set_speed_ge1(int speed)
325	{
326	/* TODO */
327	}
328
329	static void ar934x_set_speed_ge0(int speed)
330	{
331	/* TODO */
332	}
333
334	static void ar934x_set_speed_ge1(int speed)
335	{
336	/* TODO */
337	}
338
339	static void ar71xx_ddr_flush_ge0(void)
340	{
341	ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
342	}
343
344	static void ar71xx_ddr_flush_ge1(void)
345	{
346	ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
347	}
348
349	static void ar724x_ddr_flush_ge0(void)
350	{
351	ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
352	}
353
354	static void ar724x_ddr_flush_ge1(void)
355	{
356	ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
357	}
358
359	static void ar91xx_ddr_flush_ge0(void)
360	{
361	ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
362	}
363
364	static void ar91xx_ddr_flush_ge1(void)
365	{
366	ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
367	}
368
369	static void ar933x_ddr_flush_ge0(void)
370	{
371	ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
372	}
373
374	static void ar933x_ddr_flush_ge1(void)
375	{
376	ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
377	}
378
379	static void ar934x_ddr_flush_ge0(void)
380	{
381	ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
382	}
383
384	static void ar934x_ddr_flush_ge1(void)
385	{
386	ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
387	}
388
389	static struct resource ar71xx_eth0_resources[] = {
390	{
391	.name = "mac_base",
392	.flags = IORESOURCE_MEM,
393	.start = AR71XX_GE0_BASE,
394	.end = AR71XX_GE0_BASE + 0x200 - 1,
395	}, {
396	.name = "mac_irq",
397	.flags = IORESOURCE_IRQ,
398	.start = AR71XX_CPU_IRQ_GE0,
399	.end = AR71XX_CPU_IRQ_GE0,
400	},
401	};
402
403	struct ag71xx_platform_data ar71xx_eth0_data = {
404	.reset_bit = RESET_MODULE_GE0_MAC,
405	.mac_addr = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
406	};
407
408	struct platform_device ar71xx_eth0_device = {
409	.name = "ag71xx",
410	.id = 0,
411	.resource = ar71xx_eth0_resources,
412	.num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
413	.dev = {
414	.platform_data = &ar71xx_eth0_data,
415	},
416	};
417
418	static struct resource ar71xx_eth1_resources[] = {
419	{
420	.name = "mac_base",
421	.flags = IORESOURCE_MEM,
422	.start = AR71XX_GE1_BASE,
423	.end = AR71XX_GE1_BASE + 0x200 - 1,
424	}, {
425	.name = "mac_irq",
426	.flags = IORESOURCE_IRQ,
427	.start = AR71XX_CPU_IRQ_GE1,
428	.end = AR71XX_CPU_IRQ_GE1,
429	},
430	};
431
432	struct ag71xx_platform_data ar71xx_eth1_data = {
433	.reset_bit = RESET_MODULE_GE1_MAC,
434	.mac_addr = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
435	};
436
437	struct platform_device ar71xx_eth1_device = {
438	.name = "ag71xx",
439	.id = 1,
440	.resource = ar71xx_eth1_resources,
441	.num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
442	.dev = {
443	.platform_data = &ar71xx_eth1_data,
444	},
445	};
446
447	struct ag71xx_switch_platform_data ar71xx_switch_data;
448
449	#define AR71XX_PLL_VAL_1000 0x00110000
450	#define AR71XX_PLL_VAL_100 0x00001099
451	#define AR71XX_PLL_VAL_10 0x00991099
452
453	#define AR724X_PLL_VAL_1000 0x00110000
454	#define AR724X_PLL_VAL_100 0x00001099
455	#define AR724X_PLL_VAL_10 0x00991099
456
457	#define AR7242_PLL_VAL_1000 0x16000000
458	#define AR7242_PLL_VAL_100 0x00000101
459	#define AR7242_PLL_VAL_10 0x00001616
460
461	#define AR91XX_PLL_VAL_1000 0x1a000000
462	#define AR91XX_PLL_VAL_100 0x13000a44
463	#define AR91XX_PLL_VAL_10 0x00441099
464
465	#define AR933X_PLL_VAL_1000 0x00110000
466	#define AR933X_PLL_VAL_100 0x00001099
467	#define AR933X_PLL_VAL_10 0x00991099
468
469	#define AR934X_PLL_VAL_1000 0x00110000
470	#define AR934X_PLL_VAL_100 0x00001099
471	#define AR934X_PLL_VAL_10 0x00991099
472
473	static void __init ar71xx_init_eth_pll_data(unsigned int id)
474	{
475	struct ar71xx_eth_pll_data *pll_data;
476	u32 pll_10, pll_100, pll_1000;
477
478	switch (id) {
479	case 0:
480	pll_data = &ar71xx_eth0_pll_data;
481	break;
482	case 1:
483	pll_data = &ar71xx_eth1_pll_data;
484	break;
485	default:
486	BUG();
487	}
488
489	switch (ar71xx_soc) {
490	case AR71XX_SOC_AR7130:
491	case AR71XX_SOC_AR7141:
492	case AR71XX_SOC_AR7161:
493	pll_10 = AR71XX_PLL_VAL_10;
494	pll_100 = AR71XX_PLL_VAL_100;
495	pll_1000 = AR71XX_PLL_VAL_1000;
496	break;
497
498	case AR71XX_SOC_AR7240:
499	case AR71XX_SOC_AR7241:
500	pll_10 = AR724X_PLL_VAL_10;
501	pll_100 = AR724X_PLL_VAL_100;
502	pll_1000 = AR724X_PLL_VAL_1000;
503	break;
504
505	case AR71XX_SOC_AR7242:
506	pll_10 = AR7242_PLL_VAL_10;
507	pll_100 = AR7242_PLL_VAL_100;
508	pll_1000 = AR7242_PLL_VAL_1000;
509	break;
510
511	case AR71XX_SOC_AR9130:
512	case AR71XX_SOC_AR9132:
513	pll_10 = AR91XX_PLL_VAL_10;
514	pll_100 = AR91XX_PLL_VAL_100;
515	pll_1000 = AR91XX_PLL_VAL_1000;
516	break;
517
518	case AR71XX_SOC_AR9330:
519	case AR71XX_SOC_AR9331:
520	pll_10 = AR933X_PLL_VAL_10;
521	pll_100 = AR933X_PLL_VAL_100;
522	pll_1000 = AR933X_PLL_VAL_1000;
523	break;
524
525	case AR71XX_SOC_AR9341:
526	case AR71XX_SOC_AR9342:
527	case AR71XX_SOC_AR9344:
528	pll_10 = AR934X_PLL_VAL_10;
529	pll_100 = AR934X_PLL_VAL_100;
530	pll_1000 = AR934X_PLL_VAL_1000;
531	break;
532
533	default:
534	BUG();
535	return;
536	}
537
538	if (!pll_data->pll_10)
539	pll_data->pll_10 = pll_10;
540
541	if (!pll_data->pll_100)
542	pll_data->pll_100 = pll_100;
543
544	if (!pll_data->pll_1000)
545	pll_data->pll_1000 = pll_1000;
546	}
547
548	static int __init ar71xx_setup_phy_if_mode(unsigned int id,
549	struct ag71xx_platform_data *pdata)
550	{
551	unsigned int mii_if;
552
553	switch (id) {
554	case 0:
555	switch (ar71xx_soc) {
556	case AR71XX_SOC_AR7130:
557	case AR71XX_SOC_AR7141:
558	case AR71XX_SOC_AR7161:
559	case AR71XX_SOC_AR9130:
560	case AR71XX_SOC_AR9132:
561	switch (pdata->phy_if_mode) {
562	case PHY_INTERFACE_MODE_MII:
563	mii_if = MII0_CTRL_IF_MII;
564	break;
565	case PHY_INTERFACE_MODE_GMII:
566	mii_if = MII0_CTRL_IF_GMII;
567	break;
568	case PHY_INTERFACE_MODE_RGMII:
569	mii_if = MII0_CTRL_IF_RGMII;
570	break;
571	case PHY_INTERFACE_MODE_RMII:
572	mii_if = MII0_CTRL_IF_RMII;
573	break;
574	default:
575	return -EINVAL;
576	}
577	ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
578	break;
579
580	case AR71XX_SOC_AR7240:
581	case AR71XX_SOC_AR7241:
582	case AR71XX_SOC_AR9330:
583	case AR71XX_SOC_AR9331:
584	pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
585	break;
586
587	case AR71XX_SOC_AR7242:
588	/* FIXME */
589
590	case AR71XX_SOC_AR9341:
591	case AR71XX_SOC_AR9342:
592	case AR71XX_SOC_AR9344:
593	switch (pdata->phy_if_mode) {
594	case PHY_INTERFACE_MODE_MII:
595	case PHY_INTERFACE_MODE_GMII:
596	case PHY_INTERFACE_MODE_RGMII:
597	case PHY_INTERFACE_MODE_RMII:
598	break;
599	default:
600	return -EINVAL;
601	}
602	break;
603
604	default:
605	BUG();
606	}
607	break;
608	case 1:
609	switch (ar71xx_soc) {
610	case AR71XX_SOC_AR7130:
611	case AR71XX_SOC_AR7141:
612	case AR71XX_SOC_AR7161:
613	case AR71XX_SOC_AR9130:
614	case AR71XX_SOC_AR9132:
615	switch (pdata->phy_if_mode) {
616	case PHY_INTERFACE_MODE_RMII:
617	mii_if = MII1_CTRL_IF_RMII;
618	break;
619	case PHY_INTERFACE_MODE_RGMII:
620	mii_if = MII1_CTRL_IF_RGMII;
621	break;
622	default:
623	return -EINVAL;
624	}
625	ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
626	break;
627
628	case AR71XX_SOC_AR7240:
629	case AR71XX_SOC_AR7241:
630	case AR71XX_SOC_AR9330:
631	case AR71XX_SOC_AR9331:
632	pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
633	break;
634
635	case AR71XX_SOC_AR7242:
636	/* FIXME */
637
638	case AR71XX_SOC_AR9341:
639	case AR71XX_SOC_AR9342:
640	case AR71XX_SOC_AR9344:
641	switch (pdata->phy_if_mode) {
642	case PHY_INTERFACE_MODE_MII:
643	case PHY_INTERFACE_MODE_GMII:
644	break;
645	default:
646	return -EINVAL;
647	}
648	break;
649
650	default:
651	BUG();
652	}
653	break;
654	}
655
656	return 0;
657	}
658
659	static int ar71xx_eth_instance __initdata;
660	void __init ar71xx_add_device_eth(unsigned int id)
661	{
662	struct platform_device *pdev;
663	struct ag71xx_platform_data *pdata;
664	int err;
665
666	if (id > 1) {
667	printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
668	return;
669	}
670
671	ar71xx_init_eth_pll_data(id);
672
673	if (id == 0)
674	pdev = &ar71xx_eth0_device;
675	else
676	pdev = &ar71xx_eth1_device;
677
678	pdata = pdev->dev.platform_data;
679
680	err = ar71xx_setup_phy_if_mode(id, pdata);
681	if (err) {
682	printk(KERN_ERR
683	"ar71xx: invalid PHY interface mode for GE%u\n", id);
684	return;
685	}
686
687	switch (ar71xx_soc) {
688	case AR71XX_SOC_AR7130:
689	if (id == 0) {
690	pdata->ddr_flush = ar71xx_ddr_flush_ge0;
691	pdata->set_speed = ar71xx_set_speed_ge0;
692	} else {
693	pdata->ddr_flush = ar71xx_ddr_flush_ge1;
694	pdata->set_speed = ar71xx_set_speed_ge1;
695	}
696	break;
697
698	case AR71XX_SOC_AR7141:
699	case AR71XX_SOC_AR7161:
700	if (id == 0) {
701	pdata->ddr_flush = ar71xx_ddr_flush_ge0;
702	pdata->set_speed = ar71xx_set_speed_ge0;
703	} else {
704	pdata->ddr_flush = ar71xx_ddr_flush_ge1;
705	pdata->set_speed = ar71xx_set_speed_ge1;
706	}
707	pdata->has_gbit = 1;
708	break;
709
710	case AR71XX_SOC_AR7242:
711	if (id == 0) {
712	pdata->reset_bit \|= AR724X_RESET_GE0_MDIO \|
713	RESET_MODULE_GE0_PHY;
714	pdata->ddr_flush = ar724x_ddr_flush_ge0;
715	pdata->set_speed = ar7242_set_speed_ge0;
716	} else {
717	pdata->reset_bit \|= AR724X_RESET_GE1_MDIO \|
718	RESET_MODULE_GE1_PHY;
719	pdata->ddr_flush = ar724x_ddr_flush_ge1;
720	pdata->set_speed = ar724x_set_speed_ge1;
721	}
722	pdata->has_gbit = 1;
723	pdata->is_ar724x = 1;
724
725	if (!pdata->fifo_cfg1)
726	pdata->fifo_cfg1 = 0x0010ffff;
727	if (!pdata->fifo_cfg2)
728	pdata->fifo_cfg2 = 0x015500aa;
729	if (!pdata->fifo_cfg3)
730	pdata->fifo_cfg3 = 0x01f00140;
731	break;
732
733	case AR71XX_SOC_AR7241:
734	if (id == 0)
735	pdata->reset_bit \|= AR724X_RESET_GE0_MDIO;
736	else
737	pdata->reset_bit \|= AR724X_RESET_GE1_MDIO;
738	/* fall through */
739	case AR71XX_SOC_AR7240:
740	if (id == 0) {
741	pdata->reset_bit \|= RESET_MODULE_GE0_PHY;
742	pdata->ddr_flush = ar724x_ddr_flush_ge0;
743	pdata->set_speed = ar724x_set_speed_ge0;
744
745	pdata->phy_mask = BIT(4);
746	} else {
747	pdata->reset_bit \|= RESET_MODULE_GE1_PHY;
748	pdata->ddr_flush = ar724x_ddr_flush_ge1;
749	pdata->set_speed = ar724x_set_speed_ge1;
750
751	pdata->speed = SPEED_1000;
752	pdata->duplex = DUPLEX_FULL;
753	pdata->switch_data = &ar71xx_switch_data;
754	}
755	pdata->has_gbit = 1;
756	pdata->is_ar724x = 1;
757	if (ar71xx_soc == AR71XX_SOC_AR7240)
758	pdata->is_ar7240 = 1;
759
760	if (!pdata->fifo_cfg1)
761	pdata->fifo_cfg1 = 0x0010ffff;
762	if (!pdata->fifo_cfg2)
763	pdata->fifo_cfg2 = 0x015500aa;
764	if (!pdata->fifo_cfg3)
765	pdata->fifo_cfg3 = 0x01f00140;
766	break;
767
768	case AR71XX_SOC_AR9130:
769	if (id == 0) {
770	pdata->ddr_flush = ar91xx_ddr_flush_ge0;
771	pdata->set_speed = ar91xx_set_speed_ge0;
772	} else {
773	pdata->ddr_flush = ar91xx_ddr_flush_ge1;
774	pdata->set_speed = ar91xx_set_speed_ge1;
775	}
776	pdata->is_ar91xx = 1;
777	break;
778
779	case AR71XX_SOC_AR9132:
780	if (id == 0) {
781	pdata->ddr_flush = ar91xx_ddr_flush_ge0;
782	pdata->set_speed = ar91xx_set_speed_ge0;
783	} else {
784	pdata->ddr_flush = ar91xx_ddr_flush_ge1;
785	pdata->set_speed = ar91xx_set_speed_ge1;
786	}
787	pdata->is_ar91xx = 1;
788	pdata->has_gbit = 1;
789	break;
790
791	case AR71XX_SOC_AR9330:
792	case AR71XX_SOC_AR9331:
793	if (id == 0) {
794	pdata->reset_bit = AR933X_RESET_GE0_MAC \|
795	AR933X_RESET_GE0_MDIO;
796	pdata->ddr_flush = ar933x_ddr_flush_ge0;
797	pdata->set_speed = ar933x_set_speed_ge0;
798
799	pdata->phy_mask = BIT(4);
800	} else {
801	pdata->reset_bit = AR933X_RESET_GE1_MAC \|
802	AR933X_RESET_GE1_MDIO;
803	pdata->ddr_flush = ar933x_ddr_flush_ge1;
804	pdata->set_speed = ar933x_set_speed_ge1;
805
806	pdata->speed = SPEED_1000;
807	pdata->duplex = DUPLEX_FULL;
808	pdata->switch_data = &ar71xx_switch_data;
809	}
810
811	pdata->has_gbit = 1;
812	pdata->is_ar724x = 1;
813
814	if (!pdata->fifo_cfg1)
815	pdata->fifo_cfg1 = 0x0010ffff;
816	if (!pdata->fifo_cfg2)
817	pdata->fifo_cfg2 = 0x015500aa;
818	if (!pdata->fifo_cfg3)
819	pdata->fifo_cfg3 = 0x01f00140;
820	break;
821
822	case AR71XX_SOC_AR9341:
823	case AR71XX_SOC_AR9342:
824	case AR71XX_SOC_AR9344:
825	if (id == 0) {
826	pdata->reset_bit = AR934X_RESET_GE0_MAC \|
827	AR934X_RESET_GE0_MDIO;
828	pdata->ddr_flush =ar934x_ddr_flush_ge0;
829	pdata->set_speed = ar934x_set_speed_ge0;
830	} else {
831	pdata->reset_bit = AR934X_RESET_GE1_MAC \|
832	AR934X_RESET_GE1_MDIO;
833	pdata->ddr_flush = ar934x_ddr_flush_ge1;
834	pdata->set_speed = ar934x_set_speed_ge1;
835
836	pdata->switch_data = &ar71xx_switch_data;
837	}
838
839	pdata->has_gbit = 1;
840	pdata->is_ar724x = 1;
841
842	if (!pdata->fifo_cfg1)
843	pdata->fifo_cfg1 = 0x0010ffff;
844	if (!pdata->fifo_cfg2)
845	pdata->fifo_cfg2 = 0x015500aa;
846	if (!pdata->fifo_cfg3)
847	pdata->fifo_cfg3 = 0x01f00140;
848	break;
849
850	default:
851	BUG();
852	}
853
854	switch (pdata->phy_if_mode) {
855	case PHY_INTERFACE_MODE_GMII:
856	case PHY_INTERFACE_MODE_RGMII:
857	if (!pdata->has_gbit) {
858	printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
859	id);
860	return;
861	}
862	/* fallthrough */
863	default:
864	break;
865	}
866
867	if (!is_valid_ether_addr(pdata->mac_addr)) {
868	random_ether_addr(pdata->mac_addr);
869	printk(KERN_DEBUG
870	"ar71xx: using random MAC address for eth%d\n",
871	ar71xx_eth_instance);
872	}
873
874	if (pdata->mii_bus_dev == NULL) {
875	switch (ar71xx_soc) {
876	case AR71XX_SOC_AR9341:
877	case AR71XX_SOC_AR9342:
878	case AR71XX_SOC_AR9344:
879	if (id == 0)
880	pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
881	else
882	pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
883	break;
884
885	case AR71XX_SOC_AR7241:
886	case AR71XX_SOC_AR9330:
887	case AR71XX_SOC_AR9331:
888	pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
889	break;
890
891	default:
892	pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
893	break;
894	}
895	}
896
897	/* Reset the device */
898	ar71xx_device_stop(pdata->reset_bit);
899	mdelay(100);
900
901	ar71xx_device_start(pdata->reset_bit);
902	mdelay(100);
903
904	platform_device_register(pdev);
905	ar71xx_eth_instance++;
906	}
907
908	static enum ar71xx_soc_type ar71xx_get_soc_type(void)
909	{
910	u32 id;
911	u32 major;
912	u32 minor;
913	u32 rev = 0;
914
915	id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
916	major = id & REV_ID_MAJOR_MASK;
917
918	switch (major) {
919	case REV_ID_MAJOR_AR71XX:
920	minor = id & AR71XX_REV_ID_MINOR_MASK;
921	rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
922	rev &= AR71XX_REV_ID_REVISION_MASK;
923	switch (minor) {
924	case AR71XX_REV_ID_MINOR_AR7130:
925	return AR71XX_SOC_AR7130;
926
927	case AR71XX_REV_ID_MINOR_AR7141:
928	return AR71XX_SOC_AR7141;
929
930	case AR71XX_REV_ID_MINOR_AR7161:
931	return AR71XX_SOC_AR7161;
932	}
933	break;
934
935	case REV_ID_MAJOR_AR7240:
936	return AR71XX_SOC_AR7240;
937
938	case REV_ID_MAJOR_AR7241:
939	return AR71XX_SOC_AR7241;
940
941	case REV_ID_MAJOR_AR7242:
942	return AR71XX_SOC_AR7242;
943
944	case REV_ID_MAJOR_AR913X:
945	minor = id & AR91XX_REV_ID_MINOR_MASK;
946	rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
947	rev &= AR91XX_REV_ID_REVISION_MASK;
948	switch (minor) {
949	case AR91XX_REV_ID_MINOR_AR9130:
950	return AR71XX_SOC_AR9130;
951
952	case AR91XX_REV_ID_MINOR_AR9132:
953	return AR71XX_SOC_AR9132;
954	}
955	break;
956
957	case REV_ID_MAJOR_AR9330:
958	return AR71XX_SOC_AR9330;
959
960	case REV_ID_MAJOR_AR9331:
961	return AR71XX_SOC_AR9331;
962
963	case REV_ID_MAJOR_AR9341:
964	return AR71XX_SOC_AR9341;
965
966	case REV_ID_MAJOR_AR9342:
967	return AR71XX_SOC_AR9342;
968
969	case REV_ID_MAJOR_AR9344:
970	return AR71XX_SOC_AR9344;
971
972	default:
973	panic("ar71xx: unknown chip id:0x%08x\n", id);
974	}
975
976	return 0;
977	}
978
979
980	#if defined(CONFIG_RTL8366_SMI) \|\| defined(CONFIG_RTL8366_SMI_MODULE)
981
982	#ifdef CONFIG_TPLINK
983
984	/* TL-WR1043ND */
985
986	#define GPIO_RTL8366_SDA 18//gpio 19
987	#define GPIO_RTL8366_SCK 19//gpio 20
988	#elif CONFIG_BUFFALO
989	/* WZR-HP-G300NH */
990
991	#define GPIO_RTL8366_SDA 19//gpio 19
992	#define GPIO_RTL8366_SCK 20//gpio 20
993	#else
994	/* DLINK-DIR825 or WNDR3700*/
995	#define GPIO_RTL8366_SDA 5//gpio 19
996	#define GPIO_RTL8366_SCK 7//gpio 20
997	#endif
998
999	#ifdef CONFIG_DIR825
1000	static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = {
1001	{ .reg = 0x06, .val = 0x0108 },
1002	};
1003	#endif
1004
1005	static struct rtl8366_platform_data rtl8366_dev_data = {
1006	.gpio_sda = GPIO_RTL8366_SDA,
1007	.gpio_sck = GPIO_RTL8366_SCK,
1008	#ifdef CONFIG_DIR825
1009	.num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals),
1010	.initvals = dir825b1_rtl8366s_initvals,
1011	#endif
1012	};
1013
1014	static struct platform_device rtl8366_device = {
1015	.name = RTL8366RB_DRIVER_NAME,
1016	.id = -1,
1017	.dev = {
1018	.platform_data = &rtl8366_dev_data,
1019	}
1020	};
1021
1022
1023	static void phy_dev_init(void)
1024	{
1025	#ifdef CONFIG_BUFFALO
1026	if (rtl8366_smi_detect(&rtl8366_dev_data) == RTL8366_TYPE_RB) {
1027	ar71xx_eth0_pll_data.pll_1000 = 0x1f000000;
1028	ar71xx_eth1_pll_data.pll_1000 = 0x100;
1029	} else {
1030	rtl8366_device.name = RTL8366S_DRIVER_NAME;
1031	ar71xx_eth0_pll_data.pll_1000 = 0x1e000100;
1032	ar71xx_eth1_pll_data.pll_1000 = 0x1e000100;
1033	}
1034	#endif
1035	#if defined(CONFIG_DIR825) \|\| defined(CONFIG_WNDR3700)
1036	ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
1037	ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
1038	#endif
1039
1040	ar71xx_eth0_data.mii_bus_dev = &rtl8366_device.dev;
1041	ar71xx_eth1_data.mii_bus_dev = &rtl8366_device.dev;
1042	ar71xx_eth1_data.phy_mask = 0x10;
1043
1044	platform_device_register(&rtl8366_device);
1045	}
1046
1047	#else
1048
1049	static inline void phy_dev_init(void)
1050	{
1051	/* defaults for many switches */
1052	ar71xx_eth0_data.phy_mask = BIT(0);
1053	ar71xx_eth1_data.phy_mask = BIT(4);
1054
1055	ar71xx_add_device_mdio(0, ~(ar71xx_eth0_data.phy_mask \| ar71xx_eth1_data.phy_mask));
1056	}
1057
1058	#endif
1059
1060	static int __init ar71xx_eth_dev_register(void)
1061	{
1062	ar71xx_soc = ar71xx_get_soc_type();
1063
1064	ar71xx_eth0_data.speed = SPEED_1000;
1065
1066	#if defined(CONFIG_AG7100_GE0_MII)
1067	ar71xx_eth0_data.speed = SPEED_100;
1068	ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
1069	#elif defined(CONFIG_AG7100_GE0_RMII)
1070	ar71xx_eth0_data.speed = SPEED_100;
1071	ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
1072	#elif defined(CONFIG_AG7100_GE0_GMII)
1073	ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
1074	#elif defined(CONFIG_AG7100_GE0_RGMII)
1075	ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
1076	#endif
1077
1078	#if defined(CONFIG_AG7100_GE1_MII)
1079	ar71xx_eth1_data.speed = SPEED_100;
1080	ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
1081	#elif defined(CONFIG_AG7100_GE1_RMII)
1082	ar71xx_eth1_data.speed = SPEED_100;
1083	ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
1084	#elif defined(CONFIG_AG7100_GE1_GMII)
1085	ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
1086	#elif defined(CONFIG_AG7100_GE1_RGMII)
1087	ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
1088	#endif
1089
1090	ar71xx_eth0_data.duplex = DUPLEX_FULL;
1091
1092	phy_dev_init();
1093
1094	ar71xx_add_device_eth(0);
1095	#ifdef CONFIG_AG7100_GE1_IS_CONNECTED
1096	ar71xx_add_device_eth(1);
1097	#endif
1098
1099	return 0;
1100	}
1101	module_init(ar71xx_eth_dev_register);

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