source: src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_driver.c @ 12859

Last change on this file since 12859 was 12859, checked in by BrainSlayer, 4 years ago

AR670W support
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1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
3 * $Revision: 1.7 $
4 * $Date: 2008-11-21 05:39:15 $
5 * $Change: 791271 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34/** @file
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
40 *
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
48 * device.
49 */
50
51#include <linux/kernel.h>
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/init.h>
55#include <linux/device.h>
56#include <linux/errno.h>
57#include <linux/types.h>
58#include <linux/stat.h>  /* permission constants */
59#include <linux/version.h>
60
61#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
62# include <linux/irq.h>
63#endif
64
65#include <asm/io.h>
66
67#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
68# include <asm/irq.h>
69#endif
70
71//#include <asm/arch/lm.h>
72#include <asm/rt2880/lm.h>
73#include <asm/rt2880/sizes.h>
74#include <asm/rt2880/rt_mmap.h>
75//#include <asm/sizes.h>
76
77#include "linux/dwc_otg_plat.h"
78#include "dwc_otg_attr.h"
79#include "dwc_otg_driver.h"
80#include "dwc_otg_cil.h"
81#include "dwc_otg_pcd.h"
82#include "dwc_otg_hcd.h"
83
84#define DWC_DRIVER_VERSION      "2.72a 24-JUN-2008"
85#define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
86
87static const char dwc_driver_name[] = "dwc_otg";
88
89/*-------------------------------------------------------------------------*/
90/* Encapsulate the module parameter settings */
91
92static dwc_otg_core_params_t dwc_otg_module_params = {
93        .opt = -1,
94        .otg_cap = -1,
95        .dma_enable = -1,
96        .dma_desc_enable = -1,
97        .dma_burst_size = -1,
98        .speed = -1,
99        .host_support_fs_ls_low_power = -1,
100        .host_ls_low_power_phy_clk = -1,
101        .enable_dynamic_fifo = -1,
102        .data_fifo_size = -1,
103        .dev_rx_fifo_size = -1,
104        .dev_nperio_tx_fifo_size = -1,
105        .dev_perio_tx_fifo_size = {
106                /* dev_perio_tx_fifo_size_1 */
107                -1,
108                -1,
109                -1,
110                -1,
111                -1,
112                -1,
113                -1,
114                -1,
115                -1,
116                -1,
117                -1,
118                -1,
119                -1,
120                -1,
121                -1
122                /* 15 */
123        },
124        .host_rx_fifo_size = -1,
125        .host_nperio_tx_fifo_size = -1,
126        .host_perio_tx_fifo_size = -1,
127        .max_transfer_size = -1,
128        .max_packet_count = -1,
129        .host_channels = -1,
130        .dev_endpoints = -1,
131        .phy_type = -1,
132        .phy_utmi_width = -1,
133        .phy_ulpi_ddr = -1,
134        .phy_ulpi_ext_vbus = -1,
135        .i2c_enable = -1,
136        .ulpi_fs_ls = -1,
137        .ts_dline = -1,
138        .en_multiple_tx_fifo = -1,
139        .dev_tx_fifo_size = {
140                /* dev_tx_fifo_size */
141                -1,
142                -1,
143                -1,
144                -1,
145                -1,
146                -1,
147                -1,
148                -1,
149                -1,
150                -1,
151                -1,
152                -1,
153                -1,
154                -1,
155                -1
156                /* 15 */
157        },
158        .thr_ctl = -1,
159        .tx_thr_length = -1,
160        .rx_thr_length = -1,
161        .pti_enable = -1,
162        .mpi_enable = -1,
163};
164
165/**
166 * This function shows the Driver Version.
167 */
168static ssize_t version_show(struct device_driver *dev, char *buf)
169{
170        return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n",
171                        DWC_DRIVER_VERSION);
172}
173static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
174
175/**
176 * Global Debug Level Mask.
177 */
178uint32_t g_dbg_lvl = 0; /* OFF */
179
180/**
181 * This function shows the driver Debug Level.
182 */
183static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
184{
185        return sprintf(buf, "0x%0x\n", g_dbg_lvl);
186}
187
188/**
189 * This function stores the driver Debug Level.
190 */
191static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
192                               size_t count)
193{
194        g_dbg_lvl = simple_strtoul(buf, NULL, 16);
195                return count;
196}
197static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
198
199/**
200 * This function is called during module intialization to verify that
201 * the module parameters are in a valid state.
202 */
203static int check_parameters(dwc_otg_core_if_t *core_if)
204{
205        int i;
206        int retval = 0;
207       
208/* Checks if the parameter is outside of its valid range of values */
209#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
210                ((dwc_otg_module_params._param_ < (_low_)) || \
211                (dwc_otg_module_params._param_ > (_high_)))
212
213/* If the parameter has been set by the user, check that the parameter value is
214 * within the value range of values.  If not, report a module error. */
215#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
216                do { \
217                        if (dwc_otg_module_params._param_ != -1) { \
218                                if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
219                                        DWC_ERROR("`%d' invalid for parameter `%s'\n", \
220                                                  dwc_otg_module_params._param_, _string_); \
221                                        dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
222                                        retval++; \
223                                } \
224                        } \
225                } while (0)
226
227        DWC_OTG_PARAM_ERR(opt,0,1,"opt");
228        DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
229        DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
230        DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
231        DWC_OTG_PARAM_ERR(speed,0,1,"speed");
232        DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
233        DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
234        DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
235        DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
236        DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
237        DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
238        DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
239        DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
240        DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
241        DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
242        DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
243        DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
244        DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
245        DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
246        DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
247        DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
248        DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
249        DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
250        DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
251
252        if (dwc_otg_module_params.dma_burst_size != -1) {
253                if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
254                    DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
255                    DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
256                    DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
257                    DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
258                    DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
259                    DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
260                    DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
261                        DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
262                                  dwc_otg_module_params.dma_burst_size);
263                        dwc_otg_module_params.dma_burst_size = 32;
264                        retval++;
265                }
266
267                {
268                        uint8_t brst_sz = 0;
269                        while(dwc_otg_module_params.dma_burst_size > 1) {
270                                brst_sz ++;
271                                dwc_otg_module_params.dma_burst_size >>= 1;
272                        }
273                        dwc_otg_module_params.dma_burst_size = brst_sz;
274                }
275        }
276
277        if (dwc_otg_module_params.phy_utmi_width != -1) {
278                if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
279                    DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
280                        DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
281                                  dwc_otg_module_params.phy_utmi_width);
282                        dwc_otg_module_params.phy_utmi_width = 16;
283                        retval++;
284                }
285        }
286
287        for (i = 0; i < 15; i++) {
288                /** @todo should be like above */
289                //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
290                if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
291                        if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
292                                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
293                                          dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
294                                dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
295                                retval++;
296                        }
297                }
298        }
299
300        DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
301
302        for (i = 0; i < 15; i++) {
303                /** @todo should be like above */
304                //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
305                if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
306                        if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
307                                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
308                                          dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
309                                dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
310                                retval++;
311                        }
312                }
313        }
314
315        DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
316        DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
317        DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
318
319        DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
320        DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
321
322        /* At this point, all module parameters that have been set by the user
323         * are valid, and those that have not are left unset.  Now set their
324         * default values and/or check the parameters against the hardware
325         * configurations of the OTG core. */
326
327/* This sets the parameter to the default value if it has not been set by the
328 * user */
329#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
330        ({ \
331                int changed = 1; \
332                if (dwc_otg_module_params._param_ == -1) { \
333                        changed = 0; \
334                        dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
335                } \
336                changed; \
337        })
338
339/* This checks the macro agains the hardware configuration to see if it is
340 * valid.  It is possible that the default value could be invalid. In this
341 * case, it will report a module error if the user touched the parameter.
342 * Otherwise it will adjust the value without any error. */
343#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
344        ({ \
345                int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
346                int error = 0; \
347                if (!(_is_valid_)) { \
348                        if (changed) { \
349                                DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
350                                error = 1; \
351                        } \
352                        dwc_otg_module_params._param_ = (_set_valid_); \
353                } \
354                error; \
355        })
356
357        /* OTG Cap */
358        retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
359                                ({
360                                        int valid;
361                                        valid = 1;
362                                        switch (dwc_otg_module_params.otg_cap) {
363                                        case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
364                                                if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
365                                                        valid = 0;
366                                                break;
367                                        case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
368                                                if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
369                                                    (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
370                                                    (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
371                                                    (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
372                                                        valid = 0;
373                                                }
374                                                break;
375                                        case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
376                                                /* always valid */
377                                                break;
378                                        }
379                                        valid;
380                                }),
381                                (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
382                                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
383                                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
384                                  (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
385                                 DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
386                                 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
387
388        retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
389                                ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
390                                0);
391
392        retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
393                                ((dwc_otg_module_params.dma_desc_enable == 1) &&
394                                 ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
395                                0);
396
397        retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
398
399        DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
400
401        retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
402                                "host_support_fs_ls_low_power",
403                                1, 0);
404
405        retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
406                                        "enable_dynamic_fifo",
407                                        ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
408                                        (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
409
410        retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
411                                        "data_fifo_size",
412                                        (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
413                                        core_if->hwcfg3.b.dfifo_depth);
414
415        retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
416                                        "dev_rx_fifo_size",
417                                        (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
418                                        dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
419
420        retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
421                                        "dev_nperio_tx_fifo_size",
422                                        (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
423                                        (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
424
425        retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
426                                        "host_rx_fifo_size",
427                                        (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
428                                        dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
429
430        retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
431                                        "host_nperio_tx_fifo_size",
432                                        (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
433                                        (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
434
435        retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
436                                        "host_perio_tx_fifo_size",
437                                        (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
438                                        ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
439
440        retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
441                                        "max_transfer_size",
442                                        (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
443                                        ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
444
445        retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
446                                        "max_packet_count",
447                                        (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
448                                        ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
449
450        retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
451                                        "host_channels",
452                                        (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
453                                        (core_if->hwcfg2.b.num_host_chan + 1));
454
455        retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
456                                        "dev_endpoints",
457                                        (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
458                                        core_if->hwcfg2.b.num_dev_ep);
459
460/*
461 * Define the following to disable the FS PHY Hardware checking.  This is for
462 * internal testing only.
463 *
464 * #define NO_FS_PHY_HW_CHECKS
465 */
466
467#ifdef NO_FS_PHY_HW_CHECKS
468        retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
469                                "phy_type", 1, 0);
470#else
471        retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
472                                "phy_type",
473                                ({
474                                        int valid = 0;
475                                        if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
476                                        ((core_if->hwcfg2.b.hs_phy_type == 1) ||
477                                         (core_if->hwcfg2.b.hs_phy_type == 3))) {
478                                                valid = 1;
479                                        }
480                                        else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
481                                                 ((core_if->hwcfg2.b.hs_phy_type == 2) ||
482                                                  (core_if->hwcfg2.b.hs_phy_type == 3))) {
483                                                valid = 1;
484                                        }
485                                        else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
486                                                 (core_if->hwcfg2.b.fs_phy_type == 1)) {
487                                                valid = 1;
488                                        }
489                                        valid;
490                                }),
491                                ({
492                                        int set = DWC_PHY_TYPE_PARAM_FS;
493                                        if (core_if->hwcfg2.b.hs_phy_type) {
494                                                if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
495                                                (core_if->hwcfg2.b.hs_phy_type == 1)) {
496                                                        set = DWC_PHY_TYPE_PARAM_UTMI;
497                                                }
498                                                else {
499                                                        set = DWC_PHY_TYPE_PARAM_ULPI;
500                                                }
501                                        }
502                                        set;
503                                }));
504#endif
505
506        retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
507                                (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
508                                dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
509
510        retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
511                                "host_ls_low_power_phy_clk",
512                                ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
513                                ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
514
515        DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
516        DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
517        DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
518        DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
519        DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
520
521#ifdef NO_FS_PHY_HW_CHECKS
522        retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
523#else
524        retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
525                                "i2c_enable",
526                                (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
527                                0);
528#endif
529
530        for (i = 0; i < 15; i++) {
531                int changed = 1;
532                int error = 0;
533
534                if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
535                        changed = 0;
536                        dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
537                }
538                if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
539                        if (changed) {
540                                DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
541                                error = 1;
542                        }
543                        dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
544                }
545                retval += error;
546        }
547
548        retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
549                                                ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
550                                                0);
551
552        for (i = 0; i < 15; i++) {
553                int changed = 1;
554                int error = 0;
555
556                if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
557                        changed = 0;
558                        dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
559                }
560                if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
561                        if (changed) {
562                                DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
563                                error = 1;
564                        }
565                        dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
566                }
567                retval += error;
568        }
569
570        retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
571                                ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
572                                0);
573
574        DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
575        DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
576
577        retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
578                ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
579                        0);
580
581        retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
582                        ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
583                        0);
584        return retval;
585}
586
587/**
588 * This function is the top level interrupt handler for the Common
589 * (Device and host modes) interrupts.
590 */
591static irqreturn_t dwc_otg_common_irq(int irq, void *dev
592#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
593                                      , struct pt_regs *r
594#endif
595                                     )
596{
597        dwc_otg_device_t *otg_dev = dev;
598        int32_t retval = IRQ_NONE;
599
600        retval = dwc_otg_handle_common_intr(otg_dev->core_if);
601        return IRQ_RETVAL(retval);
602}
603
604/**
605 * This function is called when a lm_device is unregistered with the
606 * dwc_otg_driver. This happens, for example, when the rmmod command is
607 * executed. The device may or may not be electrically present. If it is
608 * present, the driver stops device processing. Any resources used on behalf
609 * of this device are freed.
610 *
611 * @param[in] lmdev
612 */
613static void dwc_otg_driver_remove(struct lm_device *lmdev)
614{
615        dwc_otg_device_t *otg_dev = lm_get_drvdata(lmdev);
616        DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, lmdev);
617
618        if (!otg_dev) {
619                /* Memory allocation for the dwc_otg_device failed. */
620                DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
621                return;
622        }
623
624        /*
625         * Free the IRQ
626         */
627        if (otg_dev->common_irq_installed) {
628                free_irq(lmdev->irq, otg_dev);
629        }
630
631#ifndef DWC_DEVICE_ONLY
632        if (otg_dev->hcd) {
633                dwc_otg_hcd_remove(lmdev);
634        } else {
635                DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
636                return;
637        }
638#endif
639
640#ifndef DWC_HOST_ONLY
641        if (otg_dev->pcd) {
642                dwc_otg_pcd_remove(lmdev);
643        }
644#endif
645        if (otg_dev->core_if) {
646                dwc_otg_cil_remove(otg_dev->core_if);
647        }
648
649        /*
650         * Remove the device attributes
651         */
652        dwc_otg_attr_remove(lmdev);
653
654        /*
655         * Return the memory.
656         */
657        if (otg_dev->base) {
658                iounmap(otg_dev->base);
659        }
660        kfree(otg_dev);
661
662        /*
663         * Clear the drvdata pointer.
664         */
665        lm_set_drvdata(lmdev, 0);
666}
667
668/**
669 * This function is called when an lm_device is bound to a
670 * dwc_otg_driver. It creates the driver components required to
671 * control the device (CIL, HCD, and PCD) and it initializes the
672 * device. The driver components are stored in a dwc_otg_device
673 * structure. A reference to the dwc_otg_device is saved in the
674 * lm_device. This allows the driver to access the dwc_otg_device
675 * structure on subsequent calls to driver methods for this device.
676 *
677 * @param[in] lmdev  lm_device definition
678 */
679static int dwc_otg_driver_probe(struct lm_device *lmdev)
680{
681        int retval = 0;
682        uint32_t snpsid;
683        dwc_otg_device_t *dwc_otg_device;
684
685        dev_dbg(&lmdev->dev, "dwc_otg_driver_probe(%p)\n", lmdev);
686        dev_dbg(&lmdev->dev, "start=0x%08x\n", (unsigned)lmdev->resource.start);
687
688        dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
689
690        if (!dwc_otg_device) {
691                dev_err(&lmdev->dev, "kmalloc of dwc_otg_device failed\n");
692                retval = -ENOMEM;
693                goto fail;
694        }
695
696        memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
697        dwc_otg_device->reg_offset = 0xFFFFFFFF;
698
699        /*
700         * Map the DWC_otg Core memory into virtual address space.
701         */
702        dwc_otg_device->base = ioremap(lmdev->resource.start, SZ_256K);
703
704        if (!dwc_otg_device->base) {
705                dev_err(&lmdev->dev, "ioremap() failed\n");
706                retval = -ENOMEM;
707                goto fail;
708        }
709        dev_dbg(&lmdev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
710
711        /*
712         * Attempt to ensure this device is really a DWC_otg Controller.
713         * Read and verify the SNPSID register contents. The value should be
714         * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
715         */
716        snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
717
718        if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
719                dev_err(&lmdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
720                retval = -EINVAL;
721                goto fail;
722        }
723
724        DWC_PRINT("Core Release: %x.%x%x%x\n",
725                        (snpsid >> 12 & 0xF),
726                        (snpsid >> 8 & 0xF),
727                        (snpsid >> 4 & 0xF),
728                        (snpsid & 0xF));
729
730        /*
731         * Initialize driver data to point to the global DWC_otg
732         * Device structure.
733         */
734        lm_set_drvdata(lmdev, dwc_otg_device);
735        dev_dbg(&lmdev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
736
737        dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base,
738                                                   &dwc_otg_module_params);
739       
740        dwc_otg_device->core_if->snpsid = snpsid;
741       
742        if (!dwc_otg_device->core_if) {
743                dev_err(&lmdev->dev, "CIL initialization failed!\n");
744                retval = -ENOMEM;
745                goto fail;
746        }
747
748        /*
749         * Validate parameter values.
750         */
751        if (check_parameters(dwc_otg_device->core_if)) {
752                retval = -EINVAL;
753                goto fail;
754        }
755
756        /*
757         * Create Device Attributes in sysfs
758         */
759        dwc_otg_attr_create(lmdev);
760
761        /*
762         * Disable the global interrupt until all the interrupt
763         * handlers are installed.
764         */
765        dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
766
767        /*
768         * Install the interrupt handler for the common interrupts before
769         * enabling common interrupts in core_init below.
770         */
771        DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
772                    lmdev->irq);
773        retval = request_irq(lmdev->irq, dwc_otg_common_irq,
774                             SA_SHIRQ, "dwc_otg", dwc_otg_device);
775        if (retval) {
776                DWC_ERROR("request of irq%d failed\n", lmdev->irq);
777                retval = -EBUSY;
778                goto fail;
779        } else {
780                dwc_otg_device->common_irq_installed = 1;
781        }
782
783        /*
784         * Initialize the DWC_otg core.
785         */
786        dwc_otg_core_init(dwc_otg_device->core_if);
787
788#ifndef DWC_HOST_ONLY
789        /*
790         * Initialize the PCD
791         */
792        retval = dwc_otg_pcd_init(lmdev);
793        if (retval != 0) {
794                DWC_ERROR("dwc_otg_pcd_init failed\n");
795                dwc_otg_device->pcd = NULL;
796                goto fail;
797        }
798#endif
799#ifndef DWC_DEVICE_ONLY
800        /*
801         * Initialize the HCD
802         */
803        retval = dwc_otg_hcd_init(lmdev);
804        if (retval != 0) {
805                DWC_ERROR("dwc_otg_hcd_init failed\n");
806                dwc_otg_device->hcd = NULL;
807                goto fail;
808        }
809#endif
810
811        /*
812         * Enable the global interrupt after all the interrupt
813         * handlers are installed.
814         */
815        dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
816
817        return 0;
818
819 fail:
820        dwc_otg_driver_remove(lmdev);
821        return retval;
822}
823
824/**
825 * This structure defines the methods to be called by a bus driver
826 * during the lifecycle of a device on that bus. Both drivers and
827 * devices are registered with a bus driver. The bus driver matches
828 * devices to drivers based on information in the device and driver
829 * structures.
830 *
831 * The probe function is called when the bus driver matches a device
832 * to this driver. The remove function is called when a device is
833 * unregistered with the bus driver.
834 */
835static struct lm_driver dwc_otg_driver = {
836        .drv = {
837                .name   = (char *)dwc_driver_name,
838        },
839        .probe          = dwc_otg_driver_probe,
840        .remove         = dwc_otg_driver_remove,
841};
842#define RALINK_PIO_BASE                 0xA0300600
843
844#define RALINK_PRGIO_ADDR               RALINK_PIO_BASE // Programmable I/O
845
846#define RALINK_REG_PIOINT               (RALINK_PRGIO_ADDR + 0)
847#define RALINK_REG_PIOEDGE              (RALINK_PRGIO_ADDR + 0x04)
848#define RALINK_REG_PIORENA              (RALINK_PRGIO_ADDR + 0x08)
849#define RALINK_REG_PIOFENA              (RALINK_PRGIO_ADDR + 0x0C)
850#define RALINK_REG_PIODATA              (RALINK_PRGIO_ADDR + 0x20)
851#define RALINK_REG_PIODIR               (RALINK_PRGIO_ADDR + 0x24)
852#define RALINK_REG_PIOSET               (RALINK_PRGIO_ADDR + 0x2C)
853#define RALINK_REG_PIORESET             (RALINK_PRGIO_ADDR + 0x30)
854
855void ralink_gpio_control(int gpio,int level)
856{
857   unsigned long piodir,piodata;
858
859       piodir = le32_to_cpu(*(volatile u32 *)(RALINK_REG_PIODIR));
860       piodir |= (1L << gpio);
861       *(volatile u32 *)(RALINK_REG_PIODIR) = cpu_to_le32(piodir);
862       piodata = le32_to_cpu(*(volatile u32 *)(RALINK_REG_PIODATA));
863
864       if(level)
865          piodata |= (1L << gpio);
866       else
867          piodata &= ~(1L << gpio);
868
869       *(volatile u32 *)(RALINK_REG_PIODATA) = cpu_to_le32(piodata);
870}
871
872/**
873 * This function is called when the dwc_otg_driver is installed with the
874 * insmod command. It registers the dwc_otg_driver structure with the
875 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
876 * to be called. In addition, the bus driver will automatically expose
877 * attributes defined for the device and driver in the special sysfs file
878 * system.
879 *
880 * @return
881 */
882static int __init dwc_otg_driver_init(void)
883{
884        int retval = 0;
885        struct lm_device *lmdev;
886        int error;
887       
888        *(unsigned long *)(KSEG1ADDR(RALINK_USB_OTG_BASE+0xE00)) = 0x0; //Enable USB Port
889//      ralink_gpio_control(6,1); // turn on 5V
890        lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
891        if (!lmdev)
892        {
893                printk("\n %s ,kzalloc(lm_device),fail   \n", __func__);
894                return -ENOMEM;
895        }
896
897        lmdev->resource.start = RALINK_USB_OTG_BASE;
898        lmdev->resource.end = RALINK_USB_OTG_BASE + SZ_256K - 1;
899        lmdev->resource.flags = IORESOURCE_MEM;
900        lmdev->irq = RALINK_INTCTL_OTG_IRQN;
901        lmdev->id = 0;
902
903        lm_device_register(lmdev);
904        printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
905        retval = lm_driver_register(&dwc_otg_driver);
906        if (retval < 0) {
907                printk(KERN_ERR "%s retval=%d\n", __func__, retval);
908                return retval;
909        }
910        error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
911        error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
912
913        return retval;
914}
915module_init(dwc_otg_driver_init);
916
917/**
918 * This function is called when the driver is removed from the kernel
919 * with the rmmod command. The driver unregisters itself with its bus
920 * driver.
921 *
922 */
923static void __exit dwc_otg_driver_cleanup(void)
924{
925        printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
926
927        driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
928        driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
929
930        lm_driver_unregister(&dwc_otg_driver);
931//      ralink_gpio_control(6,0); // turn off 5V
932        *(unsigned long *)(KSEG1ADDR(RALINK_USB_OTG_BASE+0xE00)) = 0xF; //Disable USB Port
933        printk(KERN_INFO "%s module removed\n", dwc_driver_name);
934}
935module_exit(dwc_otg_driver_cleanup);
936
937MODULE_DESCRIPTION(DWC_DRIVER_DESC);
938MODULE_AUTHOR("Synopsys Inc.");
939MODULE_LICENSE("GPL");
940
941module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
942MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
943module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
944MODULE_PARM_DESC(opt, "OPT Mode");
945module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
946MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
947
948module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
949MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
950
951module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
952MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
953module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
954MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
955module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
956MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
957module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
958MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
959module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
960MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
961module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
962MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
963module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
964MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
965module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
966MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
967module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
968MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
969module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
970MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
971module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
972MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
973module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
974MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
975module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
976MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
977module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
978MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
979module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
980MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
981module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
982MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
983module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
984MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
985module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
986MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
987module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
988MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
989module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
990MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
991module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
992MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
993module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
994MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
995module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
996MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
997module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
998MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
999module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1000MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
1001module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1002MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
1003module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
1004/** @todo Set the max to 512K, modify checks */
1005MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
1006module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
1007MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
1008module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
1009MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
1010module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
1011MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
1012module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1013MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1014module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1015MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1016module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1017MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1018module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1019MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1020module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1021MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1022module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1023MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1024module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1025MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1026module_param_named(debug, g_dbg_lvl, int, 0444);
1027MODULE_PARM_DESC(debug, "");
1028
1029module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1030MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1031module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1032MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1033module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1034MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1035module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1036MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1037module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1038MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1039module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1040MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1041module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1042MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1043module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1044MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1045module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1046MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1047module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1048MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1049module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1050MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1051module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1052MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1053module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1054MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1055module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1056MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1057module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1058MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1059module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1060MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1061
1062module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1063MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1064module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1065MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1066module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
1067MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1068
1069module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1070MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
1071
1072module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1073MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
1074
1075/** @page "Module Parameters"
1076 *
1077 * The following parameters may be specified when starting the module.
1078 * These parameters define how the DWC_otg controller should be
1079 * configured. Parameter values are passed to the CIL initialization
1080 * function dwc_otg_cil_init
1081 *
1082 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1083 *
1084
1085 <table>
1086 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1087
1088 <tr>
1089 <td>otg_cap</td>
1090 <td>Specifies the OTG capabilities. The driver will automatically detect the
1091 value for this parameter if none is specified.
1092 - 0: HNP and SRP capable (default, if available)
1093 - 1: SRP Only capable
1094 - 2: No HNP/SRP capable
1095 </td></tr>
1096
1097 <tr>
1098 <td>dma_enable</td>
1099 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1100 The driver will automatically detect the value for this parameter if none is
1101 specified.
1102 - 0: Slave
1103 - 1: DMA (default, if available)
1104 </td></tr>
1105
1106 <tr>
1107 <td>dma_burst_size</td>
1108 <td>The DMA Burst size (applicable only for External DMA Mode).
1109 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1110 </td></tr>
1111
1112 <tr>
1113 <td>speed</td>
1114 <td>Specifies the maximum speed of operation in host and device mode. The
1115 actual speed depends on the speed of the attached device and the value of
1116 phy_type.
1117 - 0: High Speed (default)
1118 - 1: Full Speed
1119 </td></tr>
1120
1121 <tr>
1122 <td>host_support_fs_ls_low_power</td>
1123 <td>Specifies whether low power mode is supported when attached to a Full
1124 Speed or Low Speed device in host mode.
1125 - 0: Don't support low power mode (default)
1126 - 1: Support low power mode
1127 </td></tr>
1128
1129 <tr>
1130 <td>host_ls_low_power_phy_clk</td>
1131 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1132 Speed device in host mode. This parameter is applicable only if
1133 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1134 - 0: 48 MHz (default)
1135 - 1: 6 MHz
1136 </td></tr>
1137
1138 <tr>
1139 <td>enable_dynamic_fifo</td>
1140 <td> Specifies whether FIFOs may be resized by the driver software.
1141 - 0: Use cC FIFO size parameters
1142 - 1: Allow dynamic FIFO sizing (default)
1143 </td></tr>
1144
1145 <tr>
1146 <td>data_fifo_size</td>
1147 <td>Total number of 4-byte words in the data FIFO memory. This memory
1148 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1149 - Values: 32 to 32768 (default 8192)
1150
1151 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1152 </td></tr>
1153
1154 <tr>
1155 <td>dev_rx_fifo_size</td>
1156 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1157 FIFO sizing is enabled.
1158 - Values: 16 to 32768 (default 1064)
1159 </td></tr>
1160
1161 <tr>
1162 <td>dev_nperio_tx_fifo_size</td>
1163 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1164 dynamic FIFO sizing is enabled.
1165 - Values: 16 to 32768 (default 1024)
1166 </td></tr>
1167
1168 <tr>
1169 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1170 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1171 when dynamic FIFO sizing is enabled.
1172 - Values: 4 to 768 (default 256)
1173 </td></tr>
1174
1175 <tr>
1176 <td>host_rx_fifo_size</td>
1177 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1178 sizing is enabled.
1179 - Values: 16 to 32768 (default 1024)
1180 </td></tr>
1181
1182 <tr>
1183 <td>host_nperio_tx_fifo_size</td>
1184 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1185 dynamic FIFO sizing is enabled in the core.
1186 - Values: 16 to 32768 (default 1024)
1187 </td></tr>
1188
1189 <tr>
1190 <td>host_perio_tx_fifo_size</td>
1191 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1192 sizing is enabled.
1193 - Values: 16 to 32768 (default 1024)
1194 </td></tr>
1195
1196 <tr>
1197 <td>max_transfer_size</td>
1198 <td>The maximum transfer size supported in bytes.
1199 - Values: 2047 to 65,535 (default 65,535)
1200 </td></tr>
1201
1202 <tr>
1203 <td>max_packet_count</td>
1204 <td>The maximum number of packets in a transfer.
1205 - Values: 15 to 511 (default 511)
1206 </td></tr>
1207
1208 <tr>
1209 <td>host_channels</td>
1210 <td>The number of host channel registers to use.
1211 - Values: 1 to 16 (default 12)
1212
1213 Note: The FPGA configuration supports a maximum of 12 host channels.
1214 </td></tr>
1215
1216 <tr>
1217 <td>dev_endpoints</td>
1218 <td>The number of endpoints in addition to EP0 available for device mode
1219 operations.
1220 - Values: 1 to 15 (default 6 IN and OUT)
1221
1222 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1223 addition to EP0.
1224 </td></tr>
1225
1226 <tr>
1227 <td>phy_type</td>
1228 <td>Specifies the type of PHY interface to use. By default, the driver will
1229 automatically detect the phy_type.
1230 - 0: Full Speed
1231 - 1: UTMI+ (default, if available)
1232 - 2: ULPI
1233 </td></tr>
1234
1235 <tr>
1236 <td>phy_utmi_width</td>
1237 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1238 phy_type of UTMI+. Also, this parameter is applicable only if the
1239 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1240 core has been configured to work at either data path width.
1241 - Values: 8 or 16 bits (default 16)
1242 </td></tr>
1243
1244 <tr>
1245 <td>phy_ulpi_ddr</td>
1246 <td>Specifies whether the ULPI operates at double or single data rate. This
1247 parameter is only applicable if phy_type is ULPI.
1248 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1249 - 1: double data rate ULPI interface with 4 bit wide data bus
1250 </td></tr>
1251
1252 <tr>
1253 <td>i2c_enable</td>
1254 <td>Specifies whether to use the I2C interface for full speed PHY. This
1255 parameter is only applicable if PHY_TYPE is FS.
1256 - 0: Disabled (default)
1257 - 1: Enabled
1258 </td></tr>
1259
1260 <tr>
1261 <td>otg_en_multiple_tx_fifo</td>
1262 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1263 The driver will automatically detect the value for this parameter if none is
1264 specified.
1265 - 0: Disabled
1266 - 1: Enabled (default, if available)
1267 </td></tr>
1268
1269 <tr>
1270 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1271 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1272 when dynamic FIFO sizing is enabled.
1273 - Values: 4 to 768 (default 256)
1274 </td></tr>
1275
1276*/
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