source: src/linux/universal/linux-3.18/drivers/net/ethernet/intel/igb/e1000_phy.c @ 31885

Last change on this file since 31885 was 31885, checked in by brainslayer, 3 months ago

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1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24#include <linux/if_ether.h>
25#include <linux/delay.h>
26
27#include "e1000_mac.h"
28#include "e1000_phy.h"
29
30static s32  igb_phy_setup_autoneg(struct e1000_hw *hw);
31static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
32                                             u16 *phy_ctrl);
33static s32  igb_wait_autoneg(struct e1000_hw *hw);
34static s32  igb_set_master_slave_mode(struct e1000_hw *hw);
35
36/* Cable length tables */
37static const u16 e1000_m88_cable_length_table[] = {
38        0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
39#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
40        (sizeof(e1000_m88_cable_length_table) / \
41        sizeof(e1000_m88_cable_length_table[0]))
42
43static const u16 e1000_igp_2_cable_length_table[] = {
44        0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45        0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46        6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47        21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48        40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49        60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50        83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51        104, 109, 114, 118, 121, 124};
52#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53        (sizeof(e1000_igp_2_cable_length_table) / \
54         sizeof(e1000_igp_2_cable_length_table[0]))
55
56/**
57 *  igb_check_reset_block - Check if PHY reset is blocked
58 *  @hw: pointer to the HW structure
59 *
60 *  Read the PHY management control register and check whether a PHY reset
61 *  is blocked.  If a reset is not blocked return 0, otherwise
62 *  return E1000_BLK_PHY_RESET (12).
63 **/
64s32 igb_check_reset_block(struct e1000_hw *hw)
65{
66        u32 manc;
67
68        manc = rd32(E1000_MANC);
69
70        return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
71}
72
73/**
74 *  igb_get_phy_id - Retrieve the PHY ID and revision
75 *  @hw: pointer to the HW structure
76 *
77 *  Reads the PHY registers and stores the PHY ID and possibly the PHY
78 *  revision in the hardware structure.
79 **/
80s32 igb_get_phy_id(struct e1000_hw *hw)
81{
82        struct e1000_phy_info *phy = &hw->phy;
83        s32 ret_val = 0;
84        u16 phy_id;
85
86        /* ensure PHY page selection to fix misconfigured i210 */
87        if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
88                phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
89
90        ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
91        if (ret_val)
92                goto out;
93
94        phy->id = (u32)(phy_id << 16);
95        udelay(20);
96        ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
97        if (ret_val)
98                goto out;
99
100        phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
101        phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102
103out:
104        return ret_val;
105}
106
107/**
108 *  igb_phy_reset_dsp - Reset PHY DSP
109 *  @hw: pointer to the HW structure
110 *
111 *  Reset the digital signal processor.
112 **/
113static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
114{
115        s32 ret_val = 0;
116
117        if (!(hw->phy.ops.write_reg))
118                goto out;
119
120        ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
121        if (ret_val)
122                goto out;
123
124        ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
125
126out:
127        return ret_val;
128}
129
130/**
131 *  igb_read_phy_reg_mdic - Read MDI control register
132 *  @hw: pointer to the HW structure
133 *  @offset: register offset to be read
134 *  @data: pointer to the read data
135 *
136 *  Reads the MDI control regsiter in the PHY at offset and stores the
137 *  information read to data.
138 **/
139s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
140{
141        u32 i, mdicnfg, mdic = 0;
142        s32 ret_val = 0;
143
144        if (offset > MAX_PHY_REG_ADDRESS) {
145                hw_dbg("PHY Address %d is out of range\n", offset);
146                ret_val = -E1000_ERR_PARAM;
147                goto out;
148        }
149
150        /* Set up Op-code, Phy Address, and register offset in the MDI
151         * Control register.  The MAC will take care of interfacing with the
152         * PHY to retrieve the desired data.
153         */
154        switch (hw->mac.type) {
155        case e1000_i210:
156        case e1000_i211:
157                mdicnfg = rd32(E1000_MDICNFG);
158                mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
159                mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
160                wr32(E1000_MDICNFG, mdicnfg);
161                mdic = ((offset << E1000_MDIC_REG_SHIFT) |
162                        (E1000_MDIC_OP_READ));
163                break;
164        default:
165                mdic = ((offset << E1000_MDIC_REG_SHIFT) |
166                        (addr << E1000_MDIC_PHY_SHIFT) |
167                        (E1000_MDIC_OP_READ));
168                break;
169        }
170
171        wr32(E1000_MDIC, mdic);
172        wrfl();
173
174        /* Poll the ready bit to see if the MDI read completed
175         * Increasing the time out as testing showed failures with
176         * the lower time out
177         */
178        for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
179                udelay(50);
180                mdic = rd32(E1000_MDIC);
181                if (mdic & E1000_MDIC_READY)
182                        break;
183        }
184        if (!(mdic & E1000_MDIC_READY)) {
185                hw_dbg("MDI Read did not complete\n");
186                ret_val = -E1000_ERR_PHY;
187                goto out;
188        }
189        if (mdic & E1000_MDIC_ERROR) {
190                hw_dbg("MDI Error\n");
191                ret_val = -E1000_ERR_PHY;
192                goto out;
193        }
194        *data = (u16) mdic;
195
196out:
197        switch (hw->mac.type) {
198                /* restore MDICNFG to have phy's addr */
199                case e1000_i210:
200                case e1000_i211:
201                        mdicnfg = rd32(E1000_MDICNFG);
202                        mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
203                        mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
204                        wr32(E1000_MDICNFG, mdicnfg);
205                        break;
206                default:
207                        break;
208        }
209        return ret_val;
210}
211
212/**
213 *  igb_write_phy_reg_mdic - Write MDI control register
214 *  @hw: pointer to the HW structure
215 *  @offset: register offset to write to
216 *  @data: data to write to register at offset
217 *
218 *  Writes data to MDI control register in the PHY at offset.
219 **/
220s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
221{
222        u32 i, mdicnfg, mdic = 0;
223        s32 ret_val = 0;
224
225        if (offset > MAX_PHY_REG_ADDRESS) {
226                hw_dbg("PHY Address %d is out of range\n", offset);
227                ret_val = -E1000_ERR_PARAM;
228                goto out;
229        }
230
231        /* Set up Op-code, Phy Address, and register offset in the MDI
232         * Control register.  The MAC will take care of interfacing with the
233         * PHY to retrieve the desired data.
234         */
235        switch (hw->mac.type) {
236                case e1000_i210:
237                case e1000_i211:
238                        mdicnfg = rd32(E1000_MDICNFG);
239                        mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
240                        mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
241                        wr32(E1000_MDICNFG, mdicnfg);
242                        mdic = (((u32)data) |
243                                (offset << E1000_MDIC_REG_SHIFT) |
244                                (E1000_MDIC_OP_WRITE));
245                        break;
246                default:
247                        mdic = (((u32)data) |
248                                (offset << E1000_MDIC_REG_SHIFT) |
249                                (addr << E1000_MDIC_PHY_SHIFT) |
250                                (E1000_MDIC_OP_WRITE));
251                        break;
252        }
253
254        wr32(E1000_MDIC, mdic);
255        wrfl();
256
257        /* Poll the ready bit to see if the MDI read completed
258         * Increasing the time out as testing showed failures with
259         * the lower time out
260         */
261        for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
262                udelay(50);
263                mdic = rd32(E1000_MDIC);
264                if (mdic & E1000_MDIC_READY)
265                        break;
266        }
267        if (!(mdic & E1000_MDIC_READY)) {
268                hw_dbg("MDI Write did not complete\n");
269                ret_val = -E1000_ERR_PHY;
270                goto out;
271        }
272        if (mdic & E1000_MDIC_ERROR) {
273                hw_dbg("MDI Error\n");
274                ret_val = -E1000_ERR_PHY;
275                goto out;
276        }
277
278out:
279        switch (hw->mac.type) {
280                /* restore MDICNFG to have phy's addr */
281                case e1000_i210:
282                case e1000_i211:
283                        mdicnfg = rd32(E1000_MDICNFG);
284                        mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
285                        mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
286                        wr32(E1000_MDICNFG, mdicnfg);
287                        break;
288                default:
289                        break;
290        }
291        return ret_val;
292}
293
294/**
295 *  igb_read_phy_reg_i2c - Read PHY register using i2c
296 *  @hw: pointer to the HW structure
297 *  @offset: register offset to be read
298 *  @data: pointer to the read data
299 *
300 *  Reads the PHY register at offset using the i2c interface and stores the
301 *  retrieved information in data.
302 **/
303s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
304{
305        struct e1000_phy_info *phy = &hw->phy;
306        u32 i, i2ccmd = 0;
307
308        /* Set up Op-code, Phy Address, and register address in the I2CCMD
309         * register.  The MAC will take care of interfacing with the
310         * PHY to retrieve the desired data.
311         */
312        i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
313                  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
314                  (E1000_I2CCMD_OPCODE_READ));
315
316        wr32(E1000_I2CCMD, i2ccmd);
317
318        /* Poll the ready bit to see if the I2C read completed */
319        for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
320                udelay(50);
321                i2ccmd = rd32(E1000_I2CCMD);
322                if (i2ccmd & E1000_I2CCMD_READY)
323                        break;
324        }
325        if (!(i2ccmd & E1000_I2CCMD_READY)) {
326                hw_dbg("I2CCMD Read did not complete\n");
327                return -E1000_ERR_PHY;
328        }
329        if (i2ccmd & E1000_I2CCMD_ERROR) {
330                hw_dbg("I2CCMD Error bit set\n");
331                return -E1000_ERR_PHY;
332        }
333
334        /* Need to byte-swap the 16-bit value. */
335        *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
336
337        return 0;
338}
339
340/**
341 *  igb_write_phy_reg_i2c - Write PHY register using i2c
342 *  @hw: pointer to the HW structure
343 *  @offset: register offset to write to
344 *  @data: data to write at register offset
345 *
346 *  Writes the data to PHY register at the offset using the i2c interface.
347 **/
348s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
349{
350        struct e1000_phy_info *phy = &hw->phy;
351        u32 i, i2ccmd = 0;
352        u16 phy_data_swapped;
353
354        /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
355        if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
356                hw_dbg("PHY I2C Address %d is out of range.\n",
357                          hw->phy.addr);
358                return -E1000_ERR_CONFIG;
359        }
360
361        /* Swap the data bytes for the I2C interface */
362        phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
363
364        /* Set up Op-code, Phy Address, and register address in the I2CCMD
365         * register.  The MAC will take care of interfacing with the
366         * PHY to retrieve the desired data.
367         */
368        i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
369                  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
370                  E1000_I2CCMD_OPCODE_WRITE |
371                  phy_data_swapped);
372
373        wr32(E1000_I2CCMD, i2ccmd);
374
375        /* Poll the ready bit to see if the I2C read completed */
376        for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
377                udelay(50);
378                i2ccmd = rd32(E1000_I2CCMD);
379                if (i2ccmd & E1000_I2CCMD_READY)
380                        break;
381        }
382        if (!(i2ccmd & E1000_I2CCMD_READY)) {
383                hw_dbg("I2CCMD Write did not complete\n");
384                return -E1000_ERR_PHY;
385        }
386        if (i2ccmd & E1000_I2CCMD_ERROR) {
387                hw_dbg("I2CCMD Error bit set\n");
388                return -E1000_ERR_PHY;
389        }
390
391        return 0;
392}
393
394/**
395 *  igb_read_sfp_data_byte - Reads SFP module data.
396 *  @hw: pointer to the HW structure
397 *  @offset: byte location offset to be read
398 *  @data: read data buffer pointer
399 *
400 *  Reads one byte from SFP module data stored
401 *  in SFP resided EEPROM memory or SFP diagnostic area.
402 *  Function should be called with
403 *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
404 *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
405 *  access
406 **/
407s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
408{
409        u32 i = 0;
410        u32 i2ccmd = 0;
411        u32 data_local = 0;
412
413        if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
414                hw_dbg("I2CCMD command address exceeds upper limit\n");
415                return -E1000_ERR_PHY;
416        }
417
418        /* Set up Op-code, EEPROM Address,in the I2CCMD
419         * register. The MAC will take care of interfacing with the
420         * EEPROM to retrieve the desired data.
421         */
422        i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
423                  E1000_I2CCMD_OPCODE_READ);
424
425        wr32(E1000_I2CCMD, i2ccmd);
426
427        /* Poll the ready bit to see if the I2C read completed */
428        for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
429                udelay(50);
430                data_local = rd32(E1000_I2CCMD);
431                if (data_local & E1000_I2CCMD_READY)
432                        break;
433        }
434        if (!(data_local & E1000_I2CCMD_READY)) {
435                hw_dbg("I2CCMD Read did not complete\n");
436                return -E1000_ERR_PHY;
437        }
438        if (data_local & E1000_I2CCMD_ERROR) {
439                hw_dbg("I2CCMD Error bit set\n");
440                return -E1000_ERR_PHY;
441        }
442        *data = (u8) data_local & 0xFF;
443
444        return 0;
445}
446
447/**
448 *  igb_read_phy_reg_igp - Read igp PHY register
449 *  @hw: pointer to the HW structure
450 *  @offset: register offset to be read
451 *  @data: pointer to the read data
452 *
453 *  Acquires semaphore, if necessary, then reads the PHY register at offset
454 *  and storing the retrieved information in data.  Release any acquired
455 *  semaphores before exiting.
456 **/
457s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
458{
459        s32 ret_val = 0;
460
461        if (!(hw->phy.ops.acquire))
462                goto out;
463
464        ret_val = hw->phy.ops.acquire(hw);
465        if (ret_val)
466                goto out;
467
468        if (offset > MAX_PHY_MULTI_PAGE_REG) {
469                ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
470                                                 IGP01E1000_PHY_PAGE_SELECT,
471                                                 (u16)offset);
472                if (ret_val) {
473                        hw->phy.ops.release(hw);
474                        goto out;
475                }
476        }
477
478        ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
479                                        MAX_PHY_REG_ADDRESS & offset, data);
480
481        hw->phy.ops.release(hw);
482
483out:
484        return ret_val;
485}
486
487/**
488 *  igb_write_phy_reg_igp - Write igp PHY register
489 *  @hw: pointer to the HW structure
490 *  @offset: register offset to write to
491 *  @data: data to write at register offset
492 *
493 *  Acquires semaphore, if necessary, then writes the data to PHY register
494 *  at the offset.  Release any acquired semaphores before exiting.
495 **/
496s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
497{
498        s32 ret_val = 0;
499
500        if (!(hw->phy.ops.acquire))
501                goto out;
502
503        ret_val = hw->phy.ops.acquire(hw);
504        if (ret_val)
505                goto out;
506
507        if (offset > MAX_PHY_MULTI_PAGE_REG) {
508                ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
509                                                 IGP01E1000_PHY_PAGE_SELECT,
510                                                 (u16)offset);
511                if (ret_val) {
512                        hw->phy.ops.release(hw);
513                        goto out;
514                }
515        }
516
517        ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
518                                         MAX_PHY_REG_ADDRESS & offset, data);
519
520        hw->phy.ops.release(hw);
521
522out:
523        return ret_val;
524}
525
526/**
527 *  igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
528 *  @hw: pointer to the HW structure
529 *
530 *  Sets up Carrier-sense on Transmit and downshift values.
531 **/
532s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
533{
534        struct e1000_phy_info *phy = &hw->phy;
535        s32 ret_val;
536        u16 phy_data;
537
538        if (phy->reset_disable) {
539                ret_val = 0;
540                goto out;
541        }
542
543        if (phy->type == e1000_phy_82580) {
544                ret_val = hw->phy.ops.reset(hw);
545                if (ret_val) {
546                        hw_dbg("Error resetting the PHY.\n");
547                        goto out;
548                }
549        }
550
551        /* Enable CRS on TX. This must be set for half-duplex operation. */
552        ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
553        if (ret_val)
554                goto out;
555
556        phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
557
558        /* Enable downshift */
559        phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
560
561        ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
562        if (ret_val)
563                goto out;
564
565        /* Set MDI/MDIX mode */
566        ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
567        if (ret_val)
568                goto out;
569        phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
570        /* Options:
571         *   0 - Auto (default)
572         *   1 - MDI mode
573         *   2 - MDI-X mode
574         */
575        switch (hw->phy.mdix) {
576        case 1:
577                break;
578        case 2:
579                phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
580                break;
581        case 0:
582        default:
583                phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
584                break;
585        }
586        ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
587
588out:
589        return ret_val;
590}
591
592/**
593 *  igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
594 *  @hw: pointer to the HW structure
595 *
596 *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
597 *  and downshift values are set also.
598 **/
599s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
600{
601        struct e1000_phy_info *phy = &hw->phy;
602        s32 ret_val;
603        u16 phy_data;
604
605        if (phy->reset_disable) {
606                ret_val = 0;
607                goto out;
608        }
609
610        /* Enable CRS on TX. This must be set for half-duplex operation. */
611        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
612        if (ret_val)
613                goto out;
614
615        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
616
617        /* Options:
618         *   MDI/MDI-X = 0 (default)
619         *   0 - Auto for all speeds
620         *   1 - MDI mode
621         *   2 - MDI-X mode
622         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
623         */
624        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
625
626        switch (phy->mdix) {
627        case 1:
628                phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
629                break;
630        case 2:
631                phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
632                break;
633        case 3:
634                phy_data |= M88E1000_PSCR_AUTO_X_1000T;
635                break;
636        case 0:
637        default:
638                phy_data |= M88E1000_PSCR_AUTO_X_MODE;
639                break;
640        }
641
642        /* Options:
643         *   disable_polarity_correction = 0 (default)
644         *       Automatic Correction for Reversed Cable Polarity
645         *   0 - Disabled
646         *   1 - Enabled
647         */
648        phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
649        if (phy->disable_polarity_correction == 1)
650                phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
651
652        ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
653        if (ret_val)
654                goto out;
655
656        if (phy->revision < E1000_REVISION_4) {
657                /* Force TX_CLK in the Extended PHY Specific Control Register
658                 * to 25MHz clock.
659                 */
660                ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
661                                            &phy_data);
662                if (ret_val)
663                        goto out;
664
665                phy_data |= M88E1000_EPSCR_TX_CLK_25;
666
667                if ((phy->revision == E1000_REVISION_2) &&
668                    (phy->id == M88E1111_I_PHY_ID)) {
669                        /* 82573L PHY - set the downshift counter to 5x. */
670                        phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
671                        phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
672                } else {
673                        /* Configure Master and Slave downshift values */
674                        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
675                                      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
676                        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
677                                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
678                }
679                ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
680                                             phy_data);
681                if (ret_val)
682                        goto out;
683        }
684
685        /* Commit the changes. */
686        ret_val = igb_phy_sw_reset(hw);
687        if (ret_val) {
688                hw_dbg("Error committing the PHY changes\n");
689                goto out;
690        }
691
692out:
693        return ret_val;
694}
695
696/**
697 *  igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
698 *  @hw: pointer to the HW structure
699 *
700 *  Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
701 *  Also enables and sets the downshift parameters.
702 **/
703s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
704{
705        struct e1000_phy_info *phy = &hw->phy;
706        s32 ret_val;
707        u16 phy_data;
708
709        if (phy->reset_disable)
710                return 0;
711
712        /* Enable CRS on Tx. This must be set for half-duplex operation. */
713        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
714        if (ret_val)
715                return ret_val;
716
717        /* Options:
718         *   MDI/MDI-X = 0 (default)
719         *   0 - Auto for all speeds
720         *   1 - MDI mode
721         *   2 - MDI-X mode
722         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
723         */
724        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
725
726        switch (phy->mdix) {
727        case 1:
728                phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
729                break;
730        case 2:
731                phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
732                break;
733        case 3:
734                /* M88E1112 does not support this mode) */
735                if (phy->id != M88E1112_E_PHY_ID) {
736                        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
737                        break;
738                }
739        case 0:
740        default:
741                phy_data |= M88E1000_PSCR_AUTO_X_MODE;
742                break;
743        }
744
745        /* Options:
746         *   disable_polarity_correction = 0 (default)
747         *       Automatic Correction for Reversed Cable Polarity
748         *   0 - Disabled
749         *   1 - Enabled
750         */
751        phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
752        if (phy->disable_polarity_correction == 1)
753                phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
754
755        /* Enable downshift and setting it to X6 */
756        if (phy->id == M88E1543_E_PHY_ID) {
757                phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
758                ret_val =
759                    phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
760                if (ret_val)
761                        return ret_val;
762
763                ret_val = igb_phy_sw_reset(hw);
764                if (ret_val) {
765                        hw_dbg("Error committing the PHY changes\n");
766                        return ret_val;
767                }
768        }
769
770        phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
771        phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
772        phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
773
774        ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
775        if (ret_val)
776                return ret_val;
777
778        /* Commit the changes. */
779        ret_val = igb_phy_sw_reset(hw);
780        if (ret_val) {
781                hw_dbg("Error committing the PHY changes\n");
782                return ret_val;
783        }
784        ret_val = igb_set_master_slave_mode(hw);
785        if (ret_val)
786                return ret_val;
787
788        return 0;
789}
790
791/**
792 *  igb_copper_link_setup_igp - Setup igp PHY's for copper link
793 *  @hw: pointer to the HW structure
794 *
795 *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
796 *  igp PHY's.
797 **/
798s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
799{
800        struct e1000_phy_info *phy = &hw->phy;
801        s32 ret_val;
802        u16 data;
803
804        if (phy->reset_disable) {
805                ret_val = 0;
806                goto out;
807        }
808
809        ret_val = phy->ops.reset(hw);
810        if (ret_val) {
811                hw_dbg("Error resetting the PHY.\n");
812                goto out;
813        }
814
815        /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
816         * timeout issues when LFS is enabled.
817         */
818        msleep(100);
819
820        /* The NVM settings will configure LPLU in D3 for
821         * non-IGP1 PHYs.
822         */
823        if (phy->type == e1000_phy_igp) {
824                /* disable lplu d3 during driver init */
825                if (phy->ops.set_d3_lplu_state)
826                        ret_val = phy->ops.set_d3_lplu_state(hw, false);
827                if (ret_val) {
828                        hw_dbg("Error Disabling LPLU D3\n");
829                        goto out;
830                }
831        }
832
833        /* disable lplu d0 during driver init */
834        ret_val = phy->ops.set_d0_lplu_state(hw, false);
835        if (ret_val) {
836                hw_dbg("Error Disabling LPLU D0\n");
837                goto out;
838        }
839        /* Configure mdi-mdix settings */
840        ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
841        if (ret_val)
842                goto out;
843
844        data &= ~IGP01E1000_PSCR_AUTO_MDIX;
845
846        switch (phy->mdix) {
847        case 1:
848                data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
849                break;
850        case 2:
851                data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
852                break;
853        case 0:
854        default:
855                data |= IGP01E1000_PSCR_AUTO_MDIX;
856                break;
857        }
858        ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
859        if (ret_val)
860                goto out;
861
862        /* set auto-master slave resolution settings */
863        if (hw->mac.autoneg) {
864                /* when autonegotiation advertisement is only 1000Mbps then we
865                 * should disable SmartSpeed and enable Auto MasterSlave
866                 * resolution as hardware default.
867                 */
868                if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
869                        /* Disable SmartSpeed */
870                        ret_val = phy->ops.read_reg(hw,
871                                                    IGP01E1000_PHY_PORT_CONFIG,
872                                                    &data);
873                        if (ret_val)
874                                goto out;
875
876                        data &= ~IGP01E1000_PSCFR_SMART_SPEED;
877                        ret_val = phy->ops.write_reg(hw,
878                                                     IGP01E1000_PHY_PORT_CONFIG,
879                                                     data);
880                        if (ret_val)
881                                goto out;
882
883                        /* Set auto Master/Slave resolution process */
884                        ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
885                        if (ret_val)
886                                goto out;
887
888                        data &= ~CR_1000T_MS_ENABLE;
889                        ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
890                        if (ret_val)
891                                goto out;
892                }
893
894                ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
895                if (ret_val)
896                        goto out;
897
898                /* load defaults for future use */
899                phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
900                        ((data & CR_1000T_MS_VALUE) ?
901                        e1000_ms_force_master :
902                        e1000_ms_force_slave) :
903                        e1000_ms_auto;
904
905                switch (phy->ms_type) {
906                case e1000_ms_force_master:
907                        data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
908                        break;
909                case e1000_ms_force_slave:
910                        data |= CR_1000T_MS_ENABLE;
911                        data &= ~(CR_1000T_MS_VALUE);
912                        break;
913                case e1000_ms_auto:
914                        data &= ~CR_1000T_MS_ENABLE;
915                default:
916                        break;
917                }
918                ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
919                if (ret_val)
920                        goto out;
921        }
922
923out:
924        return ret_val;
925}
926
927/**
928 *  igb_copper_link_autoneg - Setup/Enable autoneg for copper link
929 *  @hw: pointer to the HW structure
930 *
931 *  Performs initial bounds checking on autoneg advertisement parameter, then
932 *  configure to advertise the full capability.  Setup the PHY to autoneg
933 *  and restart the negotiation process between the link partner.  If
934 *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
935 **/
936static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
937{
938        struct e1000_phy_info *phy = &hw->phy;
939        s32 ret_val;
940        u16 phy_ctrl;
941
942        /* Perform some bounds checking on the autoneg advertisement
943         * parameter.
944         */
945        phy->autoneg_advertised &= phy->autoneg_mask;
946
947        /* If autoneg_advertised is zero, we assume it was not defaulted
948         * by the calling code so we set to advertise full capability.
949         */
950        if (phy->autoneg_advertised == 0)
951                phy->autoneg_advertised = phy->autoneg_mask;
952
953        hw_dbg("Reconfiguring auto-neg advertisement params\n");
954        ret_val = igb_phy_setup_autoneg(hw);
955        if (ret_val) {
956                hw_dbg("Error Setting up Auto-Negotiation\n");
957                goto out;
958        }
959        hw_dbg("Restarting Auto-Neg\n");
960
961        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
962         * the Auto Neg Restart bit in the PHY control register.
963         */
964        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
965        if (ret_val)
966                goto out;
967
968        phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
969        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
970        if (ret_val)
971                goto out;
972
973        /* Does the user want to wait for Auto-Neg to complete here, or
974         * check at a later time (for example, callback routine).
975         */
976        if (phy->autoneg_wait_to_complete) {
977                ret_val = igb_wait_autoneg(hw);
978                if (ret_val) {
979                        hw_dbg("Error while waiting for autoneg to complete\n");
980                        goto out;
981                }
982        }
983
984        hw->mac.get_link_status = true;
985
986out:
987        return ret_val;
988}
989
990/**
991 *  igb_phy_setup_autoneg - Configure PHY for auto-negotiation
992 *  @hw: pointer to the HW structure
993 *
994 *  Reads the MII auto-neg advertisement register and/or the 1000T control
995 *  register and if the PHY is already setup for auto-negotiation, then
996 *  return successful.  Otherwise, setup advertisement and flow control to
997 *  the appropriate values for the wanted auto-negotiation.
998 **/
999static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
1000{
1001        struct e1000_phy_info *phy = &hw->phy;
1002        s32 ret_val;
1003        u16 mii_autoneg_adv_reg;
1004        u16 mii_1000t_ctrl_reg = 0;
1005
1006        phy->autoneg_advertised &= phy->autoneg_mask;
1007
1008        /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1009        ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1010        if (ret_val)
1011                goto out;
1012
1013        if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1014                /* Read the MII 1000Base-T Control Register (Address 9). */
1015                ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1016                                            &mii_1000t_ctrl_reg);
1017                if (ret_val)
1018                        goto out;
1019        }
1020
1021        /* Need to parse both autoneg_advertised and fc and set up
1022         * the appropriate PHY registers.  First we will parse for
1023         * autoneg_advertised software override.  Since we can advertise
1024         * a plethora of combinations, we need to check each bit
1025         * individually.
1026         */
1027
1028        /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1029         * Advertisement Register (Address 4) and the 1000 mb speed bits in
1030         * the  1000Base-T Control Register (Address 9).
1031         */
1032        mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1033                                 NWAY_AR_100TX_HD_CAPS |
1034                                 NWAY_AR_10T_FD_CAPS   |
1035                                 NWAY_AR_10T_HD_CAPS);
1036        mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1037
1038        hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
1039
1040        /* Do we want to advertise 10 Mb Half Duplex? */
1041        if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1042                hw_dbg("Advertise 10mb Half duplex\n");
1043                mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1044        }
1045
1046        /* Do we want to advertise 10 Mb Full Duplex? */
1047        if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1048                hw_dbg("Advertise 10mb Full duplex\n");
1049                mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1050        }
1051
1052        /* Do we want to advertise 100 Mb Half Duplex? */
1053        if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1054                hw_dbg("Advertise 100mb Half duplex\n");
1055                mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1056        }
1057
1058        /* Do we want to advertise 100 Mb Full Duplex? */
1059        if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1060                hw_dbg("Advertise 100mb Full duplex\n");
1061                mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1062        }
1063
1064        /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1065        if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1066                hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1067
1068        /* Do we want to advertise 1000 Mb Full Duplex? */
1069        if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1070                hw_dbg("Advertise 1000mb Full duplex\n");
1071                mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1072        }
1073
1074        /* Check for a software override of the flow control settings, and
1075         * setup the PHY advertisement registers accordingly.  If
1076         * auto-negotiation is enabled, then software will have to set the
1077         * "PAUSE" bits to the correct value in the Auto-Negotiation
1078         * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1079         * negotiation.
1080         *
1081         * The possible values of the "fc" parameter are:
1082         *      0:  Flow control is completely disabled
1083         *      1:  Rx flow control is enabled (we can receive pause frames
1084         *          but not send pause frames).
1085         *      2:  Tx flow control is enabled (we can send pause frames
1086         *          but we do not support receiving pause frames).
1087         *      3:  Both Rx and TX flow control (symmetric) are enabled.
1088         *  other:  No software override.  The flow control configuration
1089         *          in the EEPROM is used.
1090         */
1091        switch (hw->fc.current_mode) {
1092        case e1000_fc_none:
1093                /* Flow control (RX & TX) is completely disabled by a
1094                 * software over-ride.
1095                 */
1096                mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1097                break;
1098        case e1000_fc_rx_pause:
1099                /* RX Flow control is enabled, and TX Flow control is
1100                 * disabled, by a software over-ride.
1101                 *
1102                 * Since there really isn't a way to advertise that we are
1103                 * capable of RX Pause ONLY, we will advertise that we
1104                 * support both symmetric and asymmetric RX PAUSE.  Later
1105                 * (in e1000_config_fc_after_link_up) we will disable the
1106                 * hw's ability to send PAUSE frames.
1107                 */
1108                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1109                break;
1110        case e1000_fc_tx_pause:
1111                /* TX Flow control is enabled, and RX Flow control is
1112                 * disabled, by a software over-ride.
1113                 */
1114                mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1115                mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1116                break;
1117        case e1000_fc_full:
1118                /* Flow control (both RX and TX) is enabled by a software
1119                 * over-ride.
1120                 */
1121                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1122                break;
1123        default:
1124                hw_dbg("Flow control param set incorrectly\n");
1125                ret_val = -E1000_ERR_CONFIG;
1126                goto out;
1127        }
1128
1129        ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1130        if (ret_val)
1131                goto out;
1132
1133        hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1134
1135        if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1136                ret_val = phy->ops.write_reg(hw,
1137                                             PHY_1000T_CTRL,
1138                                             mii_1000t_ctrl_reg);
1139                if (ret_val)
1140                        goto out;
1141        }
1142
1143out:
1144        return ret_val;
1145}
1146
1147/**
1148 *  igb_setup_copper_link - Configure copper link settings
1149 *  @hw: pointer to the HW structure
1150 *
1151 *  Calls the appropriate function to configure the link for auto-neg or forced
1152 *  speed and duplex.  Then we check for link, once link is established calls
1153 *  to configure collision distance and flow control are called.  If link is
1154 *  not established, we return -E1000_ERR_PHY (-2).
1155 **/
1156s32 igb_setup_copper_link(struct e1000_hw *hw)
1157{
1158        s32 ret_val;
1159        bool link;
1160
1161        if (hw->mac.autoneg) {
1162                /* Setup autoneg and flow control advertisement and perform
1163                 * autonegotiation.
1164                 */
1165                ret_val = igb_copper_link_autoneg(hw);
1166                if (ret_val)
1167                        goto out;
1168        } else {
1169                /* PHY will be set to 10H, 10F, 100H or 100F
1170                 * depending on user settings.
1171                 */
1172                hw_dbg("Forcing Speed and Duplex\n");
1173                ret_val = hw->phy.ops.force_speed_duplex(hw);
1174                if (ret_val) {
1175                        hw_dbg("Error Forcing Speed and Duplex\n");
1176                        goto out;
1177                }
1178        }
1179
1180        /* Check link status. Wait up to 100 microseconds for link to become
1181         * valid.
1182         */
1183        ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1184        if (ret_val)
1185                goto out;
1186
1187        if (link) {
1188                hw_dbg("Valid link established!!!\n");
1189                igb_config_collision_dist(hw);
1190                ret_val = igb_config_fc_after_link_up(hw);
1191        } else {
1192                hw_dbg("Unable to establish link!!!\n");
1193        }
1194
1195out:
1196        return ret_val;
1197}
1198
1199/**
1200 *  igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1201 *  @hw: pointer to the HW structure
1202 *
1203 *  Calls the PHY setup function to force speed and duplex.  Clears the
1204 *  auto-crossover to force MDI manually.  Waits for link and returns
1205 *  successful if link up is successful, else -E1000_ERR_PHY (-2).
1206 **/
1207s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1208{
1209        struct e1000_phy_info *phy = &hw->phy;
1210        s32 ret_val;
1211        u16 phy_data;
1212        bool link;
1213
1214        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1215        if (ret_val)
1216                goto out;
1217
1218        igb_phy_force_speed_duplex_setup(hw, &phy_data);
1219
1220        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1221        if (ret_val)
1222                goto out;
1223
1224        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
1225         * forced whenever speed and duplex are forced.
1226         */
1227        ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1228        if (ret_val)
1229                goto out;
1230
1231        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1232        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1233
1234        ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1235        if (ret_val)
1236                goto out;
1237
1238        hw_dbg("IGP PSCR: %X\n", phy_data);
1239
1240        udelay(1);
1241
1242        if (phy->autoneg_wait_to_complete) {
1243                hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1244
1245                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1246                if (ret_val)
1247                        goto out;
1248
1249                if (!link)
1250                        hw_dbg("Link taking longer than expected.\n");
1251
1252                /* Try once more */
1253                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1254                if (ret_val)
1255                        goto out;
1256        }
1257
1258out:
1259        return ret_val;
1260}
1261
1262/**
1263 *  igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1264 *  @hw: pointer to the HW structure
1265 *
1266 *  Calls the PHY setup function to force speed and duplex.  Clears the
1267 *  auto-crossover to force MDI manually.  Resets the PHY to commit the
1268 *  changes.  If time expires while waiting for link up, we reset the DSP.
1269 *  After reset, TX_CLK and CRS on TX must be set.  Return successful upon
1270 *  successful completion, else return corresponding error code.
1271 **/
1272s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1273{
1274        struct e1000_phy_info *phy = &hw->phy;
1275        s32 ret_val;
1276        u16 phy_data;
1277        bool link;
1278
1279        /* I210 and I211 devices support Auto-Crossover in forced operation. */
1280        if (phy->type != e1000_phy_i210) {
1281                /* Clear Auto-Crossover to force MDI manually.  M88E1000
1282                 * requires MDI forced whenever speed and duplex are forced.
1283                 */
1284                ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1285                                            &phy_data);
1286                if (ret_val)
1287                        goto out;
1288
1289                phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1290                ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1291                                             phy_data);
1292                if (ret_val)
1293                        goto out;
1294
1295                hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1296        }
1297
1298        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1299        if (ret_val)
1300                goto out;
1301
1302        igb_phy_force_speed_duplex_setup(hw, &phy_data);
1303
1304        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1305        if (ret_val)
1306                goto out;
1307
1308        /* Reset the phy to commit changes. */
1309        ret_val = igb_phy_sw_reset(hw);
1310        if (ret_val)
1311                goto out;
1312
1313        if (phy->autoneg_wait_to_complete) {
1314                hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1315
1316                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1317                if (ret_val)
1318                        goto out;
1319
1320                if (!link) {
1321                        bool reset_dsp = true;
1322
1323                        switch (hw->phy.id) {
1324                        case I347AT4_E_PHY_ID:
1325                        case M88E1112_E_PHY_ID:
1326                        case I210_I_PHY_ID:
1327                                reset_dsp = false;
1328                                break;
1329                        default:
1330                                if (hw->phy.type != e1000_phy_m88)
1331                                        reset_dsp = false;
1332                                break;
1333                        }
1334                        if (!reset_dsp)
1335                                hw_dbg("Link taking longer than expected.\n");
1336                        else {
1337                                /* We didn't get link.
1338                                 * Reset the DSP and cross our fingers.
1339                                 */
1340                                ret_val = phy->ops.write_reg(hw,
1341                                                M88E1000_PHY_PAGE_SELECT,
1342                                                0x001d);
1343                                if (ret_val)
1344                                        goto out;
1345                                ret_val = igb_phy_reset_dsp(hw);
1346                                if (ret_val)
1347                                        goto out;
1348                        }
1349                }
1350
1351                /* Try once more */
1352                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1353                                           100000, &link);
1354                if (ret_val)
1355                        goto out;
1356        }
1357
1358        if (hw->phy.type != e1000_phy_m88 ||
1359            hw->phy.id == I347AT4_E_PHY_ID ||
1360            hw->phy.id == M88E1112_E_PHY_ID ||
1361            hw->phy.id == I210_I_PHY_ID)
1362                goto out;
1363
1364        ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1365        if (ret_val)
1366                goto out;
1367
1368        /* Resetting the phy means we need to re-force TX_CLK in the
1369         * Extended PHY Specific Control Register to 25MHz clock from
1370         * the reset value of 2.5MHz.
1371         */
1372        phy_data |= M88E1000_EPSCR_TX_CLK_25;
1373        ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1374        if (ret_val)
1375                goto out;
1376
1377        /* In addition, we must re-enable CRS on Tx for both half and full
1378         * duplex.
1379         */
1380        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1381        if (ret_val)
1382                goto out;
1383
1384        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1385        ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1386
1387out:
1388        return ret_val;
1389}
1390
1391/**
1392 *  igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1393 *  @hw: pointer to the HW structure
1394 *  @phy_ctrl: pointer to current value of PHY_CONTROL
1395 *
1396 *  Forces speed and duplex on the PHY by doing the following: disable flow
1397 *  control, force speed/duplex on the MAC, disable auto speed detection,
1398 *  disable auto-negotiation, configure duplex, configure speed, configure
1399 *  the collision distance, write configuration to CTRL register.  The
1400 *  caller must write to the PHY_CONTROL register for these settings to
1401 *  take affect.
1402 **/
1403static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1404                                             u16 *phy_ctrl)
1405{
1406        struct e1000_mac_info *mac = &hw->mac;
1407        u32 ctrl;
1408
1409        /* Turn off flow control when forcing speed/duplex */
1410        hw->fc.current_mode = e1000_fc_none;
1411
1412        /* Force speed/duplex on the mac */
1413        ctrl = rd32(E1000_CTRL);
1414        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1415        ctrl &= ~E1000_CTRL_SPD_SEL;
1416
1417        /* Disable Auto Speed Detection */
1418        ctrl &= ~E1000_CTRL_ASDE;
1419
1420        /* Disable autoneg on the phy */
1421        *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1422
1423        /* Forcing Full or Half Duplex? */
1424        if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1425                ctrl &= ~E1000_CTRL_FD;
1426                *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1427                hw_dbg("Half Duplex\n");
1428        } else {
1429                ctrl |= E1000_CTRL_FD;
1430                *phy_ctrl |= MII_CR_FULL_DUPLEX;
1431                hw_dbg("Full Duplex\n");
1432        }
1433
1434        /* Forcing 10mb or 100mb? */
1435        if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1436                ctrl |= E1000_CTRL_SPD_100;
1437                *phy_ctrl |= MII_CR_SPEED_100;
1438                *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1439                hw_dbg("Forcing 100mb\n");
1440        } else {
1441                ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1442                *phy_ctrl |= MII_CR_SPEED_10;
1443                *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1444                hw_dbg("Forcing 10mb\n");
1445        }
1446
1447        igb_config_collision_dist(hw);
1448
1449        wr32(E1000_CTRL, ctrl);
1450}
1451
1452/**
1453 *  igb_set_d3_lplu_state - Sets low power link up state for D3
1454 *  @hw: pointer to the HW structure
1455 *  @active: boolean used to enable/disable lplu
1456 *
1457 *  Success returns 0, Failure returns 1
1458 *
1459 *  The low power link up (lplu) state is set to the power management level D3
1460 *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1461 *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1462 *  is used during Dx states where the power conservation is most important.
1463 *  During driver activity, SmartSpeed should be enabled so performance is
1464 *  maintained.
1465 **/
1466s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1467{
1468        struct e1000_phy_info *phy = &hw->phy;
1469        s32 ret_val = 0;
1470        u16 data;
1471
1472        if (!(hw->phy.ops.read_reg))
1473                goto out;
1474
1475        ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1476        if (ret_val)
1477                goto out;
1478
1479        if (!active) {
1480                data &= ~IGP02E1000_PM_D3_LPLU;
1481                ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1482                                             data);
1483                if (ret_val)
1484                        goto out;
1485                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1486                 * during Dx states where the power conservation is most
1487                 * important.  During driver activity we should enable
1488                 * SmartSpeed, so performance is maintained.
1489                 */
1490                if (phy->smart_speed == e1000_smart_speed_on) {
1491                        ret_val = phy->ops.read_reg(hw,
1492                                                    IGP01E1000_PHY_PORT_CONFIG,
1493                                                    &data);
1494                        if (ret_val)
1495                                goto out;
1496
1497                        data |= IGP01E1000_PSCFR_SMART_SPEED;
1498                        ret_val = phy->ops.write_reg(hw,
1499                                                     IGP01E1000_PHY_PORT_CONFIG,
1500                                                     data);
1501                        if (ret_val)
1502                                goto out;
1503                } else if (phy->smart_speed == e1000_smart_speed_off) {
1504                        ret_val = phy->ops.read_reg(hw,
1505                                                     IGP01E1000_PHY_PORT_CONFIG,
1506                                                     &data);
1507                        if (ret_val)
1508                                goto out;
1509
1510                        data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1511                        ret_val = phy->ops.write_reg(hw,
1512                                                     IGP01E1000_PHY_PORT_CONFIG,
1513                                                     data);
1514                        if (ret_val)
1515                                goto out;
1516                }
1517        } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1518                   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1519                   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1520                data |= IGP02E1000_PM_D3_LPLU;
1521                ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1522                                              data);
1523                if (ret_val)
1524                        goto out;
1525
1526                /* When LPLU is enabled, we should disable SmartSpeed */
1527                ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1528                                            &data);
1529                if (ret_val)
1530                        goto out;
1531
1532                data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1533                ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1534                                             data);
1535        }
1536
1537out:
1538        return ret_val;
1539}
1540
1541/**
1542 *  igb_check_downshift - Checks whether a downshift in speed occurred
1543 *  @hw: pointer to the HW structure
1544 *
1545 *  Success returns 0, Failure returns 1
1546 *
1547 *  A downshift is detected by querying the PHY link health.
1548 **/
1549s32 igb_check_downshift(struct e1000_hw *hw)
1550{
1551        struct e1000_phy_info *phy = &hw->phy;
1552        s32 ret_val;
1553        u16 phy_data, offset, mask;
1554
1555        switch (phy->type) {
1556        case e1000_phy_i210:
1557        case e1000_phy_m88:
1558        case e1000_phy_gg82563:
1559                offset  = M88E1000_PHY_SPEC_STATUS;
1560                mask    = M88E1000_PSSR_DOWNSHIFT;
1561                break;
1562        case e1000_phy_igp_2:
1563        case e1000_phy_igp:
1564        case e1000_phy_igp_3:
1565                offset  = IGP01E1000_PHY_LINK_HEALTH;
1566                mask    = IGP01E1000_PLHR_SS_DOWNGRADE;
1567                break;
1568        default:
1569                /* speed downshift not supported */
1570                phy->speed_downgraded = false;
1571                ret_val = 0;
1572                goto out;
1573        }
1574
1575        ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1576
1577        if (!ret_val)
1578                phy->speed_downgraded = (phy_data & mask) ? true : false;
1579
1580out:
1581        return ret_val;
1582}
1583
1584/**
1585 *  igb_check_polarity_m88 - Checks the polarity.
1586 *  @hw: pointer to the HW structure
1587 *
1588 *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1589 *
1590 *  Polarity is determined based on the PHY specific status register.
1591 **/
1592s32 igb_check_polarity_m88(struct e1000_hw *hw)
1593{
1594        struct e1000_phy_info *phy = &hw->phy;
1595        s32 ret_val;
1596        u16 data;
1597
1598        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1599
1600        if (!ret_val)
1601                phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1602                                      ? e1000_rev_polarity_reversed
1603                                      : e1000_rev_polarity_normal;
1604
1605        return ret_val;
1606}
1607
1608/**
1609 *  igb_check_polarity_igp - Checks the polarity.
1610 *  @hw: pointer to the HW structure
1611 *
1612 *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1613 *
1614 *  Polarity is determined based on the PHY port status register, and the
1615 *  current speed (since there is no polarity at 100Mbps).
1616 **/
1617static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1618{
1619        struct e1000_phy_info *phy = &hw->phy;
1620        s32 ret_val;
1621        u16 data, offset, mask;
1622
1623        /* Polarity is determined based on the speed of
1624         * our connection.
1625         */
1626        ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1627        if (ret_val)
1628                goto out;
1629
1630        if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1631            IGP01E1000_PSSR_SPEED_1000MBPS) {
1632                offset  = IGP01E1000_PHY_PCS_INIT_REG;
1633                mask    = IGP01E1000_PHY_POLARITY_MASK;
1634        } else {
1635                /* This really only applies to 10Mbps since
1636                 * there is no polarity for 100Mbps (always 0).
1637                 */
1638                offset  = IGP01E1000_PHY_PORT_STATUS;
1639                mask    = IGP01E1000_PSSR_POLARITY_REVERSED;
1640        }
1641
1642        ret_val = phy->ops.read_reg(hw, offset, &data);
1643
1644        if (!ret_val)
1645                phy->cable_polarity = (data & mask)
1646                                      ? e1000_rev_polarity_reversed
1647                                      : e1000_rev_polarity_normal;
1648
1649out:
1650        return ret_val;
1651}
1652
1653/**
1654 *  igb_wait_autoneg - Wait for auto-neg completion
1655 *  @hw: pointer to the HW structure
1656 *
1657 *  Waits for auto-negotiation to complete or for the auto-negotiation time
1658 *  limit to expire, which ever happens first.
1659 **/
1660static s32 igb_wait_autoneg(struct e1000_hw *hw)
1661{
1662        s32 ret_val = 0;
1663        u16 i, phy_status;
1664
1665        /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1666        for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1667                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1668                if (ret_val)
1669                        break;
1670                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1671                if (ret_val)
1672                        break;
1673                if (phy_status & MII_SR_AUTONEG_COMPLETE)
1674                        break;
1675                msleep(100);
1676        }
1677
1678        /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1679         * has completed.
1680         */
1681        return ret_val;
1682}
1683
1684/**
1685 *  igb_phy_has_link - Polls PHY for link
1686 *  @hw: pointer to the HW structure
1687 *  @iterations: number of times to poll for link
1688 *  @usec_interval: delay between polling attempts
1689 *  @success: pointer to whether polling was successful or not
1690 *
1691 *  Polls the PHY status register for link, 'iterations' number of times.
1692 **/
1693s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1694                     u32 usec_interval, bool *success)
1695{
1696        s32 ret_val = 0;
1697        u16 i, phy_status;
1698
1699        for (i = 0; i < iterations; i++) {
1700                /* Some PHYs require the PHY_STATUS register to be read
1701                 * twice due to the link bit being sticky.  No harm doing
1702                 * it across the board.
1703                 */
1704                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1705                if (ret_val && usec_interval > 0) {
1706                        /* If the first read fails, another entity may have
1707                         * ownership of the resources, wait and try again to
1708                         * see if they have relinquished the resources yet.
1709                         */
1710                        if (usec_interval >= 1000)
1711                                mdelay(usec_interval/1000);
1712                        else
1713                                udelay(usec_interval);
1714                }
1715                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1716                if (ret_val)
1717                        break;
1718                if (phy_status & MII_SR_LINK_STATUS)
1719                        break;
1720                if (usec_interval >= 1000)
1721                        mdelay(usec_interval/1000);
1722                else
1723                        udelay(usec_interval);
1724        }
1725
1726        *success = (i < iterations) ? true : false;
1727
1728        return ret_val;
1729}
1730
1731/**
1732 *  igb_get_cable_length_m88 - Determine cable length for m88 PHY
1733 *  @hw: pointer to the HW structure
1734 *
1735 *  Reads the PHY specific status register to retrieve the cable length
1736 *  information.  The cable length is determined by averaging the minimum and
1737 *  maximum values to get the "average" cable length.  The m88 PHY has four
1738 *  possible cable length values, which are:
1739 *      Register Value          Cable Length
1740 *      0                       < 50 meters
1741 *      1                       50 - 80 meters
1742 *      2                       80 - 110 meters
1743 *      3                       110 - 140 meters
1744 *      4                       > 140 meters
1745 **/
1746s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1747{
1748        struct e1000_phy_info *phy = &hw->phy;
1749        s32 ret_val;
1750        u16 phy_data, index;
1751
1752        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1753        if (ret_val)
1754                goto out;
1755
1756        index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1757                M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1758        if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1759                ret_val = -E1000_ERR_PHY;
1760                goto out;
1761        }
1762
1763        phy->min_cable_length = e1000_m88_cable_length_table[index];
1764        phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1765
1766        phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1767
1768out:
1769        return ret_val;
1770}
1771
1772s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1773{
1774        struct e1000_phy_info *phy = &hw->phy;
1775        s32 ret_val;
1776        u16 phy_data, phy_data2, index, default_page, is_cm;
1777
1778        switch (hw->phy.id) {
1779        case I210_I_PHY_ID:
1780                /* Get cable length from PHY Cable Diagnostics Control Reg */
1781                ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1782                                            (I347AT4_PCDL + phy->addr),
1783                                            &phy_data);
1784                if (ret_val)
1785                        return ret_val;
1786
1787                /* Check if the unit of cable length is meters or cm */
1788                ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1789                                            I347AT4_PCDC, &phy_data2);
1790                if (ret_val)
1791                        return ret_val;
1792
1793                is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1794
1795                /* Populate the phy structure with cable length in meters */
1796                phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1797                phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1798                phy->cable_length = phy_data / (is_cm ? 100 : 1);
1799                break;
1800        case M88E1543_E_PHY_ID:
1801        case I347AT4_E_PHY_ID:
1802                /* Remember the original page select and set it to 7 */
1803                ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1804                                            &default_page);
1805                if (ret_val)
1806                        goto out;
1807
1808                ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1809                if (ret_val)
1810                        goto out;
1811
1812                /* Get cable length from PHY Cable Diagnostics Control Reg */
1813                ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1814                                            &phy_data);
1815                if (ret_val)
1816                        goto out;
1817
1818                /* Check if the unit of cable length is meters or cm */
1819                ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1820                if (ret_val)
1821                        goto out;
1822
1823                is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1824
1825                /* Populate the phy structure with cable length in meters */
1826                phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1827                phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1828                phy->cable_length = phy_data / (is_cm ? 100 : 1);
1829
1830                /* Reset the page selec to its original value */
1831                ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1832                                             default_page);
1833                if (ret_val)
1834                        goto out;
1835                break;
1836        case M88E1112_E_PHY_ID:
1837                /* Remember the original page select and set it to 5 */
1838                ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1839                                            &default_page);
1840                if (ret_val)
1841                        goto out;
1842
1843                ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1844                if (ret_val)
1845                        goto out;
1846
1847                ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1848                                            &phy_data);
1849                if (ret_val)
1850                        goto out;
1851
1852                index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1853                        M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1854                if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1855                        ret_val = -E1000_ERR_PHY;
1856                        goto out;
1857                }
1858
1859                phy->min_cable_length = e1000_m88_cable_length_table[index];
1860                phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1861
1862                phy->cable_length = (phy->min_cable_length +
1863                                     phy->max_cable_length) / 2;
1864
1865                /* Reset the page select to its original value */
1866                ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1867                                             default_page);
1868                if (ret_val)
1869                        goto out;
1870
1871                break;
1872        default:
1873                ret_val = -E1000_ERR_PHY;
1874                goto out;
1875        }
1876
1877out:
1878        return ret_val;
1879}
1880
1881/**
1882 *  igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1883 *  @hw: pointer to the HW structure
1884 *
1885 *  The automatic gain control (agc) normalizes the amplitude of the
1886 *  received signal, adjusting for the attenuation produced by the
1887 *  cable.  By reading the AGC registers, which represent the
1888 *  combination of coarse and fine gain value, the value can be put
1889 *  into a lookup table to obtain the approximate cable length
1890 *  for each channel.
1891 **/
1892s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1893{
1894        struct e1000_phy_info *phy = &hw->phy;
1895        s32 ret_val = 0;
1896        u16 phy_data, i, agc_value = 0;
1897        u16 cur_agc_index, max_agc_index = 0;
1898        u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1899        static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1900                IGP02E1000_PHY_AGC_A,
1901                IGP02E1000_PHY_AGC_B,
1902                IGP02E1000_PHY_AGC_C,
1903                IGP02E1000_PHY_AGC_D
1904        };
1905
1906        /* Read the AGC registers for all channels */
1907        for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1908                ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1909                if (ret_val)
1910                        goto out;
1911
1912                /* Getting bits 15:9, which represent the combination of
1913                 * coarse and fine gain values.  The result is a number
1914                 * that can be put into the lookup table to obtain the
1915                 * approximate cable length.
1916                 */
1917                cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1918                                IGP02E1000_AGC_LENGTH_MASK;
1919
1920                /* Array index bound check. */
1921                if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1922                    (cur_agc_index == 0)) {
1923                        ret_val = -E1000_ERR_PHY;
1924                        goto out;
1925                }
1926
1927                /* Remove min & max AGC values from calculation. */
1928                if (e1000_igp_2_cable_length_table[min_agc_index] >
1929                    e1000_igp_2_cable_length_table[cur_agc_index])
1930                        min_agc_index = cur_agc_index;
1931                if (e1000_igp_2_cable_length_table[max_agc_index] <
1932                    e1000_igp_2_cable_length_table[cur_agc_index])
1933                        max_agc_index = cur_agc_index;
1934
1935                agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1936        }
1937
1938        agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1939                      e1000_igp_2_cable_length_table[max_agc_index]);
1940        agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1941
1942        /* Calculate cable length with the error range of +/- 10 meters. */
1943        phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1944                                 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1945        phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1946
1947        phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1948
1949out:
1950        return ret_val;
1951}
1952
1953/**
1954 *  igb_get_phy_info_m88 - Retrieve PHY information
1955 *  @hw: pointer to the HW structure
1956 *
1957 *  Valid for only copper links.  Read the PHY status register (sticky read)
1958 *  to verify that link is up.  Read the PHY special control register to
1959 *  determine the polarity and 10base-T extended distance.  Read the PHY
1960 *  special status register to determine MDI/MDIx and current speed.  If
1961 *  speed is 1000, then determine cable length, local and remote receiver.
1962 **/
1963s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1964{
1965        struct e1000_phy_info *phy = &hw->phy;
1966        s32  ret_val;
1967        u16 phy_data;
1968        bool link;
1969
1970        if (phy->media_type != e1000_media_type_copper) {
1971                hw_dbg("Phy info is only valid for copper media\n");
1972                ret_val = -E1000_ERR_CONFIG;
1973                goto out;
1974        }
1975
1976        ret_val = igb_phy_has_link(hw, 1, 0, &link);
1977        if (ret_val)
1978                goto out;
1979
1980        if (!link) {
1981                hw_dbg("Phy info is only valid if link is up\n");
1982                ret_val = -E1000_ERR_CONFIG;
1983                goto out;
1984        }
1985
1986        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1987        if (ret_val)
1988                goto out;
1989
1990        phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1991                                   ? true : false;
1992
1993        ret_val = igb_check_polarity_m88(hw);
1994        if (ret_val)
1995                goto out;
1996
1997        ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1998        if (ret_val)
1999                goto out;
2000
2001        phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
2002
2003        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2004                ret_val = phy->ops.get_cable_length(hw);
2005                if (ret_val)
2006                        goto out;
2007
2008                ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2009                if (ret_val)
2010                        goto out;
2011
2012                phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2013                                ? e1000_1000t_rx_status_ok
2014                                : e1000_1000t_rx_status_not_ok;
2015
2016                phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2017                                 ? e1000_1000t_rx_status_ok
2018                                 : e1000_1000t_rx_status_not_ok;
2019        } else {
2020                /* Set values to "undefined" */
2021                phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2022                phy->local_rx = e1000_1000t_rx_status_undefined;
2023                phy->remote_rx = e1000_1000t_rx_status_undefined;
2024        }
2025
2026out:
2027        return ret_val;
2028}
2029
2030/**
2031 *  igb_get_phy_info_igp - Retrieve igp PHY information
2032 *  @hw: pointer to the HW structure
2033 *
2034 *  Read PHY status to determine if link is up.  If link is up, then
2035 *  set/determine 10base-T extended distance and polarity correction.  Read
2036 *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
2037 *  determine on the cable length, local and remote receiver.
2038 **/
2039s32 igb_get_phy_info_igp(struct e1000_hw *hw)
2040{
2041        struct e1000_phy_info *phy = &hw->phy;
2042        s32 ret_val;
2043        u16 data;
2044        bool link;
2045
2046        ret_val = igb_phy_has_link(hw, 1, 0, &link);
2047        if (ret_val)
2048                goto out;
2049
2050        if (!link) {
2051                hw_dbg("Phy info is only valid if link is up\n");
2052                ret_val = -E1000_ERR_CONFIG;
2053                goto out;
2054        }
2055
2056        phy->polarity_correction = true;
2057
2058        ret_val = igb_check_polarity_igp(hw);
2059        if (ret_val)
2060                goto out;
2061
2062        ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2063        if (ret_val)
2064                goto out;
2065
2066        phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2067
2068        if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2069            IGP01E1000_PSSR_SPEED_1000MBPS) {
2070                ret_val = phy->ops.get_cable_length(hw);
2071                if (ret_val)
2072                        goto out;
2073
2074                ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2075                if (ret_val)
2076                        goto out;
2077
2078                phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2079                                ? e1000_1000t_rx_status_ok
2080                                : e1000_1000t_rx_status_not_ok;
2081
2082                phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2083                                 ? e1000_1000t_rx_status_ok
2084                                 : e1000_1000t_rx_status_not_ok;
2085        } else {
2086                phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2087                phy->local_rx = e1000_1000t_rx_status_undefined;
2088                phy->remote_rx = e1000_1000t_rx_status_undefined;
2089        }
2090
2091out:
2092        return ret_val;
2093}
2094
2095/**
2096 *  igb_phy_sw_reset - PHY software reset
2097 *  @hw: pointer to the HW structure
2098 *
2099 *  Does a software reset of the PHY by reading the PHY control register and
2100 *  setting/write the control register reset bit to the PHY.
2101 **/
2102s32 igb_phy_sw_reset(struct e1000_hw *hw)
2103{
2104        s32 ret_val = 0;
2105        u16 phy_ctrl;
2106
2107        if (!(hw->phy.ops.read_reg))
2108                goto out;
2109
2110        ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2111        if (ret_val)
2112                goto out;
2113
2114        phy_ctrl |= MII_CR_RESET;
2115        ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2116        if (ret_val)
2117                goto out;
2118
2119        udelay(1);
2120
2121out:
2122        return ret_val;
2123}
2124
2125/**
2126 *  igb_phy_hw_reset - PHY hardware reset
2127 *  @hw: pointer to the HW structure
2128 *
2129 *  Verify the reset block is not blocking us from resetting.  Acquire
2130 *  semaphore (if necessary) and read/set/write the device control reset
2131 *  bit in the PHY.  Wait the appropriate delay time for the device to
2132 *  reset and release the semaphore (if necessary).
2133 **/
2134s32 igb_phy_hw_reset(struct e1000_hw *hw)
2135{
2136        struct e1000_phy_info *phy = &hw->phy;
2137        s32  ret_val;
2138        u32 ctrl;
2139
2140        ret_val = igb_check_reset_block(hw);
2141        if (ret_val) {
2142                ret_val = 0;
2143                goto out;
2144        }
2145
2146        ret_val = phy->ops.acquire(hw);
2147        if (ret_val)
2148                goto out;
2149
2150        ctrl = rd32(E1000_CTRL);
2151        wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2152        wrfl();
2153
2154        udelay(phy->reset_delay_us);
2155
2156        wr32(E1000_CTRL, ctrl);
2157        wrfl();
2158
2159        udelay(150);
2160
2161        phy->ops.release(hw);
2162
2163        ret_val = phy->ops.get_cfg_done(hw);
2164
2165out:
2166        return ret_val;
2167}
2168
2169/**
2170 *  igb_phy_init_script_igp3 - Inits the IGP3 PHY
2171 *  @hw: pointer to the HW structure
2172 *
2173 *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2174 **/
2175s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2176{
2177        hw_dbg("Running IGP 3 PHY init script\n");
2178
2179        /* PHY init IGP 3 */
2180        /* Enable rise/fall, 10-mode work in class-A */
2181        hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2182        /* Remove all caps from Replica path filter */
2183        hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2184        /* Bias trimming for ADC, AFE and Driver (Default) */
2185        hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2186        /* Increase Hybrid poly bias */
2187        hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2188        /* Add 4% to TX amplitude in Giga mode */
2189        hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2190        /* Disable trimming (TTT) */
2191        hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2192        /* Poly DC correction to 94.6% + 2% for all channels */
2193        hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2194        /* ABS DC correction to 95.9% */
2195        hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2196        /* BG temp curve trim */
2197        hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2198        /* Increasing ADC OPAMP stage 1 currents to max */
2199        hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2200        /* Force 1000 ( required for enabling PHY regs configuration) */
2201        hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2202        /* Set upd_freq to 6 */
2203        hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2204        /* Disable NPDFE */
2205        hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2206        /* Disable adaptive fixed FFE (Default) */
2207        hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2208        /* Enable FFE hysteresis */
2209        hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2210        /* Fixed FFE for short cable lengths */
2211        hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2212        /* Fixed FFE for medium cable lengths */
2213        hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2214        /* Fixed FFE for long cable lengths */
2215        hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2216        /* Enable Adaptive Clip Threshold */
2217        hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2218        /* AHT reset limit to 1 */
2219        hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2220        /* Set AHT master delay to 127 msec */
2221        hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2222        /* Set scan bits for AHT */
2223        hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2224        /* Set AHT Preset bits */
2225        hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2226        /* Change integ_factor of channel A to 3 */
2227        hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2228        /* Change prop_factor of channels BCD to 8 */
2229        hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2230        /* Change cg_icount + enable integbp for channels BCD */
2231        hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2232        /* Change cg_icount + enable integbp + change prop_factor_master
2233         * to 8 for channel A
2234         */
2235        hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2236        /* Disable AHT in Slave mode on channel A */
2237        hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2238        /* Enable LPLU and disable AN to 1000 in non-D0a states,
2239         * Enable SPD+B2B
2240         */
2241        hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2242        /* Enable restart AN on an1000_dis change */
2243        hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2244        /* Enable wh_fifo read clock in 10/100 modes */
2245        hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2246        /* Restart AN, Speed selection is 1000 */
2247        hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2248
2249        return 0;
2250}
2251
2252/**
2253 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2254 * @hw: pointer to the HW structure
2255 *
2256 * In the case of a PHY power down to save power, or to turn off link during a
2257 * driver unload, restore the link to previous settings.
2258 **/
2259void igb_power_up_phy_copper(struct e1000_hw *hw)
2260{
2261        u16 mii_reg = 0;
2262
2263        /* The PHY will retain its settings across a power down/up cycle */
2264        hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2265        mii_reg &= ~MII_CR_POWER_DOWN;
2266        hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2267}
2268
2269/**
2270 * igb_power_down_phy_copper - Power down copper PHY
2271 * @hw: pointer to the HW structure
2272 *
2273 * Power down PHY to save power when interface is down and wake on lan
2274 * is not enabled.
2275 **/
2276void igb_power_down_phy_copper(struct e1000_hw *hw)
2277{
2278        u16 mii_reg = 0;
2279
2280        /* The PHY will retain its settings across a power down/up cycle */
2281        hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2282        mii_reg |= MII_CR_POWER_DOWN;
2283        hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2284        usleep_range(1000, 2000);
2285}
2286
2287/**
2288 *  igb_check_polarity_82580 - Checks the polarity.
2289 *  @hw: pointer to the HW structure
2290 *
2291 *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2292 *
2293 *  Polarity is determined based on the PHY specific status register.
2294 **/
2295static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2296{
2297        struct e1000_phy_info *phy = &hw->phy;
2298        s32 ret_val;
2299        u16 data;
2300
2301
2302        ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2303
2304        if (!ret_val)
2305                phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2306                                      ? e1000_rev_polarity_reversed
2307                                      : e1000_rev_polarity_normal;
2308
2309        return ret_val;
2310}
2311
2312/**
2313 *  igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2314 *  @hw: pointer to the HW structure
2315 *
2316 *  Calls the PHY setup function to force speed and duplex.  Clears the
2317 *  auto-crossover to force MDI manually.  Waits for link and returns
2318 *  successful if link up is successful, else -E1000_ERR_PHY (-2).
2319 **/
2320s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2321{
2322        struct e1000_phy_info *phy = &hw->phy;
2323        s32 ret_val;
2324        u16 phy_data;
2325        bool link;
2326
2327        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2328        if (ret_val)
2329                goto out;
2330
2331        igb_phy_force_speed_duplex_setup(hw, &phy_data);
2332
2333        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2334        if (ret_val)
2335                goto out;
2336
2337        /* Clear Auto-Crossover to force MDI manually.  82580 requires MDI
2338         * forced whenever speed and duplex are forced.
2339         */
2340        ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2341        if (ret_val)
2342                goto out;
2343
2344        phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2345
2346        ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2347        if (ret_val)
2348                goto out;
2349
2350        hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2351
2352        udelay(1);
2353
2354        if (phy->autoneg_wait_to_complete) {
2355                hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2356
2357                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2358                if (ret_val)
2359                        goto out;
2360
2361                if (!link)
2362                        hw_dbg("Link taking longer than expected.\n");
2363
2364                /* Try once more */
2365                ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2366                if (ret_val)
2367                        goto out;
2368        }
2369
2370out:
2371        return ret_val;
2372}
2373
2374/**
2375 *  igb_get_phy_info_82580 - Retrieve I82580 PHY information
2376 *  @hw: pointer to the HW structure
2377 *
2378 *  Read PHY status to determine if link is up.  If link is up, then
2379 *  set/determine 10base-T extended distance and polarity correction.  Read
2380 *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
2381 *  determine on the cable length, local and remote receiver.
2382 **/
2383s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2384{
2385        struct e1000_phy_info *phy = &hw->phy;
2386        s32 ret_val;
2387        u16 data;
2388        bool link;
2389
2390        ret_val = igb_phy_has_link(hw, 1, 0, &link);
2391        if (ret_val)
2392                goto out;
2393
2394        if (!link) {
2395                hw_dbg("Phy info is only valid if link is up\n");
2396                ret_val = -E1000_ERR_CONFIG;
2397                goto out;
2398        }
2399
2400        phy->polarity_correction = true;
2401
2402        ret_val = igb_check_polarity_82580(hw);
2403        if (ret_val)
2404                goto out;
2405
2406        ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2407        if (ret_val)
2408                goto out;
2409
2410        phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2411
2412        if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2413            I82580_PHY_STATUS2_SPEED_1000MBPS) {
2414                ret_val = hw->phy.ops.get_cable_length(hw);
2415                if (ret_val)
2416                        goto out;
2417
2418                ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2419                if (ret_val)
2420                        goto out;
2421
2422                phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2423                                ? e1000_1000t_rx_status_ok
2424                                : e1000_1000t_rx_status_not_ok;
2425
2426                phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2427                                 ? e1000_1000t_rx_status_ok
2428                                 : e1000_1000t_rx_status_not_ok;
2429        } else {
2430                phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2431                phy->local_rx = e1000_1000t_rx_status_undefined;
2432                phy->remote_rx = e1000_1000t_rx_status_undefined;
2433        }
2434
2435out:
2436        return ret_val;
2437}
2438
2439/**
2440 *  igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2441 *  @hw: pointer to the HW structure
2442 *
2443 * Reads the diagnostic status register and verifies result is valid before
2444 * placing it in the phy_cable_length field.
2445 **/
2446s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2447{
2448        struct e1000_phy_info *phy = &hw->phy;
2449        s32 ret_val;
2450        u16 phy_data, length;
2451
2452        ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2453        if (ret_val)
2454                goto out;
2455
2456        length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2457                 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2458
2459        if (length == E1000_CABLE_LENGTH_UNDEFINED)
2460                ret_val = -E1000_ERR_PHY;
2461
2462        phy->cable_length = length;
2463
2464out:
2465        return ret_val;
2466}
2467
2468/**
2469 *  igb_write_reg_gs40g - Write GS40G PHY register
2470 *  @hw: pointer to the HW structure
2471 *  @addr: phy address to write to
2472 *  @offset: lower half is register offset to write to
2473 *     upper half is page to use.
2474 *  @data: data to write at register offset
2475 *
2476 *  Acquires semaphore, if necessary, then writes the data to PHY register
2477 *  at the offset.  Release any acquired semaphores before exiting.
2478 **/
2479s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
2480{
2481        s32 ret_val;
2482        u16 page = offset >> GS40G_PAGE_SHIFT;
2483
2484        offset = offset & GS40G_OFFSET_MASK;
2485        ret_val = hw->phy.ops.acquire(hw);
2486        if (ret_val)
2487                return ret_val;
2488
2489        ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
2490        if (ret_val)
2491                goto release;
2492        ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
2493
2494release:
2495        hw->phy.ops.release(hw);
2496        return ret_val;
2497}
2498
2499/**
2500 *  igb_write_phy_reg_gs40g - Write GS40G PHY register
2501 *  @hw: pointer to the HW structure
2502 *  @offset: lower half is register offset to write to
2503 *     upper half is page to use.
2504 *  @data: data to write at register offset
2505 *
2506 *  Acquires semaphore, if necessary, then writes the data to PHY register
2507 *  at the offset.  Release any acquired semaphores before exiting.
2508 **/
2509s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2510{
2511        return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
2512}
2513
2514/**
2515 *  igb_read_reg_gs40g - Read GS40G  PHY register
2516 *  @hw: pointer to the HW structure
2517 *  @addr: phy address to read from
2518 *  @offset: lower half is register offset to read to
2519 *     upper half is page to use.
2520 *  @data: data to read at register offset
2521 *
2522 *  Acquires semaphore, if necessary, then reads the data in the PHY register
2523 *  at the offset.  Release any acquired semaphores before exiting.
2524 **/
2525s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
2526{
2527        s32 ret_val;
2528        u16 page = offset >> GS40G_PAGE_SHIFT;
2529
2530        offset = offset & GS40G_OFFSET_MASK;
2531        ret_val = hw->phy.ops.acquire(hw);
2532        if (ret_val)
2533                return ret_val;
2534
2535        ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
2536        if (ret_val)
2537                goto release;
2538        ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
2539
2540release:
2541        hw->phy.ops.release(hw);
2542        return ret_val;
2543}
2544
2545/**
2546 *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
2547 *  @hw: pointer to the HW structure
2548 *  @offset: lower half is register offset to read to
2549 *     upper half is page to use.
2550 *  @data: data to read at register offset
2551 *
2552 *  Acquires semaphore, if necessary, then reads the data in the PHY register
2553 *  at the offset.  Release any acquired semaphores before exiting.
2554 **/
2555s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2556{
2557        return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
2558}
2559
2560/**
2561 *  igb_set_master_slave_mode - Setup PHY for Master/slave mode
2562 *  @hw: pointer to the HW structure
2563 *
2564 *  Sets up Master/slave mode
2565 **/
2566static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2567{
2568        s32 ret_val;
2569        u16 phy_data;
2570
2571        /* Resolve Master/Slave mode */
2572        ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2573        if (ret_val)
2574                return ret_val;
2575
2576        /* load defaults for future use */
2577        hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2578                                   ((phy_data & CR_1000T_MS_VALUE) ?
2579                                    e1000_ms_force_master :
2580                                    e1000_ms_force_slave) : e1000_ms_auto;
2581
2582        switch (hw->phy.ms_type) {
2583        case e1000_ms_force_master:
2584                phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2585                break;
2586        case e1000_ms_force_slave:
2587                phy_data |= CR_1000T_MS_ENABLE;
2588                phy_data &= ~(CR_1000T_MS_VALUE);
2589                break;
2590        case e1000_ms_auto:
2591                phy_data &= ~CR_1000T_MS_ENABLE;
2592                /* fall-through */
2593        default:
2594                break;
2595        }
2596
2597        return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2598}
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