source: src/linux/universal/linux-3.2/arch/mips/lantiq/devices.c @ 18225

Last change on this file since 18225 was 18225, checked in by BrainSlayer, 16 months ago

arch code

File size: 2.6 KB
Line 
1/*
2 *  This program is free software; you can redistribute it and/or modify it
3 *  under the terms of the GNU General Public License version 2 as published
4 *  by the Free Software Foundation.
5 *
6 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/types.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/reboot.h>
15#include <linux/platform_device.h>
16#include <linux/leds.h>
17#include <linux/etherdevice.h>
18#include <linux/time.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/dma-mapping.h>
22
23#include <asm/bootinfo.h>
24#include <asm/irq.h>
25
26#include <lantiq_soc.h>
27
28#include "devices.h"
29
30/* nor flash */
31static struct resource ltq_nor_resource =
32        MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
33
34static struct platform_device ltq_nor = {
35        .name           = "ltq_nor",
36        .resource       = &ltq_nor_resource,
37        .num_resources  = 1,
38};
39
40void __init ltq_register_nor(struct physmap_flash_data *data)
41{
42        ltq_nor.dev.platform_data = data;
43        platform_device_register(&ltq_nor);
44}
45
46/* watchdog */
47static struct resource ltq_wdt_resource =
48        MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
49
50void __init ltq_register_wdt(void)
51{
52        platform_device_register_simple("ltq_wdt", 0, &ltq_wdt_resource, 1);
53}
54
55/* asc ports */
56static struct resource ltq_asc0_resources[] = {
57        MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
58        IRQ_RES(tx, LTQ_ASC_TIR(0)),
59        IRQ_RES(rx, LTQ_ASC_RIR(0)),
60        IRQ_RES(err, LTQ_ASC_EIR(0)),
61};
62
63static struct resource ltq_asc1_resources[] = {
64        MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
65        IRQ_RES(tx, LTQ_ASC_TIR(1)),
66        IRQ_RES(rx, LTQ_ASC_RIR(1)),
67        IRQ_RES(err, LTQ_ASC_EIR(1)),
68};
69
70void __init ltq_register_asc(int port)
71{
72        switch (port) {
73        case 0:
74                platform_device_register_simple("ltq_asc", 0,
75                        ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources));
76                break;
77        case 1:
78                platform_device_register_simple("ltq_asc", 1,
79                        ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources));
80                break;
81        default:
82                break;
83        }
84}
85
86#ifdef CONFIG_PCI
87/* pci */
88static struct platform_device ltq_pci = {
89        .name           = "ltq_pci",
90        .num_resources  = 0,
91};
92
93void __init ltq_register_pci(struct ltq_pci_data *data)
94{
95        ltq_pci.dev.platform_data = data;
96        platform_device_register(&ltq_pci);
97}
98#else
99void __init ltq_register_pci(struct ltq_pci_data *data)
100{
101        pr_err("kernel is compiled without PCI support\n");
102}
103#endif
104
105static unsigned int *cp1_base = 0;
106unsigned int*
107ltq_get_cp1_base(void)
108{
109        return cp1_base;
110}
111EXPORT_SYMBOL(ltq_get_cp1_base);
112
113void __init
114ltq_register_tapi(void)
115{
116#define CP1_SIZE       (1 << 20)
117        dma_addr_t dma;
118        cp1_base =
119                (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
120}
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