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source: src/linux/universal/linux-3.2/drivers/net/ethernet/ag934x/ag71xx_ar7240.c @ 18801

Last change on this file since 18801 was 18801, checked in by BrainSlayer, 14 months ago
update db120 platform and fix newer switch driver
File size: 29.3 KB

Line
1	/*
2	* Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3	* Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4	* Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5	*
6	* This program is free software; you can redistribute it and/or modify it
7	* under the terms of the GNU General Public License version 2 as published
8	* by the Free Software Foundation.
9	*
10	*/
11
12	#include <linux/etherdevice.h>
13	#include <linux/list.h>
14	#include <linux/netdevice.h>
15	#include <linux/phy.h>
16	#include <linux/mii.h>
17	#include <linux/bitops.h>
18	#include <linux/switch.h>
19	#include "ag71xx.h"
20
21	#define BITM(_count) (BIT(_count) - 1)
22	#define BITS(_shift, _count) (BITM(_count) << _shift)
23
24	#define AR7240_REG_MASK_CTRL 0x00
25	#define AR7240_MASK_CTRL_REVISION_M BITM(8)
26	#define AR7240_MASK_CTRL_VERSION_M BITM(8)
27	#define AR7240_MASK_CTRL_VERSION_S 8
28	#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29	#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30	#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32	#define AR7240_REG_MAC_ADDR0 0x20
33	#define AR7240_REG_MAC_ADDR1 0x24
34
35	#define AR7240_REG_FLOOD_MASK 0x2c
36	#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38	#define AR7240_REG_GLOBAL_CTRL 0x30
39	#define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41	#define AR7240_REG_VTU 0x0040
42	#define AR7240_VTU_OP BITM(3)
43	#define AR7240_VTU_OP_NOOP 0x0
44	#define AR7240_VTU_OP_FLUSH 0x1
45	#define AR7240_VTU_OP_LOAD 0x2
46	#define AR7240_VTU_OP_PURGE 0x3
47	#define AR7240_VTU_OP_REMOVE_PORT 0x4
48	#define AR7240_VTU_ACTIVE BIT(3)
49	#define AR7240_VTU_FULL BIT(4)
50	#define AR7240_VTU_PORT BITS(8, 4)
51	#define AR7240_VTU_PORT_S 8
52	#define AR7240_VTU_VID BITS(16, 12)
53	#define AR7240_VTU_VID_S 16
54	#define AR7240_VTU_PRIO BITS(28, 3)
55	#define AR7240_VTU_PRIO_S 28
56	#define AR7240_VTU_PRIO_EN BIT(31)
57
58	#define AR7240_REG_VTU_DATA 0x0044
59	#define AR7240_VTUDATA_MEMBER BITS(0, 10)
60	#define AR7240_VTUDATA_VALID BIT(11)
61
62	#define AR7240_REG_ATU 0x50
63	#define AR7240_ATU_FLUSH_ALL 0x1
64
65	#define AR7240_REG_AT_CTRL 0x5c
66	#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67	#define AR7240_AT_CTRL_AGE_EN BIT(17)
68	#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69	#define AR7240_AT_CTRL_RESERVED BIT(19)
70	#define AR7240_AT_CTRL_ARP_EN BIT(20)
71
72	#define AR7240_REG_TAG_PRIORITY 0x70
73
74	#define AR7240_REG_SERVICE_TAG 0x74
75	#define AR7240_SERVICE_TAG_M BITM(16)
76
77	#define AR7240_REG_CPU_PORT 0x78
78	#define AR7240_MIRROR_PORT_S 4
79	#define AR7240_CPU_PORT_EN BIT(8)
80
81	#define AR7240_REG_MIB_FUNCTION0 0x80
82	#define AR7240_MIB_TIMER_M BITM(16)
83	#define AR7240_MIB_AT_HALF_EN BIT(16)
84	#define AR7240_MIB_BUSY BIT(17)
85	#define AR7240_MIB_FUNC_S 24
86	#define AR7240_MIB_FUNC_NO_OP 0x0
87	#define AR7240_MIB_FUNC_FLUSH 0x1
88	#define AR7240_MIB_FUNC_CAPTURE 0x3
89
90	#define AR7240_REG_MDIO_CTRL 0x98
91	#define AR7240_MDIO_CTRL_DATA_M BITM(16)
92	#define AR7240_MDIO_CTRL_REG_ADDR_S 16
93	#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
94	#define AR7240_MDIO_CTRL_CMD_WRITE 0
95	#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
96	#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
97	#define AR7240_MDIO_CTRL_BUSY BIT(31)
98
99	#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100
101	#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
102	#define AR7240_PORT_STATUS_SPEED_S 0
103	#define AR7240_PORT_STATUS_SPEED_M BITM(2)
104	#define AR7240_PORT_STATUS_SPEED_10 0
105	#define AR7240_PORT_STATUS_SPEED_100 1
106	#define AR7240_PORT_STATUS_SPEED_1000 2
107	#define AR7240_PORT_STATUS_TXMAC BIT(2)
108	#define AR7240_PORT_STATUS_RXMAC BIT(3)
109	#define AR7240_PORT_STATUS_TXFLOW BIT(4)
110	#define AR7240_PORT_STATUS_RXFLOW BIT(5)
111	#define AR7240_PORT_STATUS_DUPLEX BIT(6)
112	#define AR7240_PORT_STATUS_LINK_UP BIT(8)
113	#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
114	#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115
116	#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
117	#define AR7240_PORT_CTRL_STATE_M BITM(3)
118	#define AR7240_PORT_CTRL_STATE_DISABLED 0
119	#define AR7240_PORT_CTRL_STATE_BLOCK 1
120	#define AR7240_PORT_CTRL_STATE_LISTEN 2
121	#define AR7240_PORT_CTRL_STATE_LEARN 3
122	#define AR7240_PORT_CTRL_STATE_FORWARD 4
123	#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
124	#define AR7240_PORT_CTRL_VLAN_MODE_S 8
125	#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
126	#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
127	#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
128	#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
129	#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
130	#define AR7240_PORT_CTRL_HEADER BIT(11)
131	#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
132	#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
133	#define AR7240_PORT_CTRL_LEARN BIT(14)
134	#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
135	#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
136	#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137
138	#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139
140	#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
141	#define AR7240_PORT_VLAN_DEST_PORTS_S 16
142	#define AR7240_PORT_VLAN_MODE_S 30
143	#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
144	#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
145	#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
146	#define AR7240_PORT_VLAN_MODE_SECURE 3
147
148
149	#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150
151	#define AR7240_STATS_RXBROAD 0x00
152	#define AR7240_STATS_RXPAUSE 0x04
153	#define AR7240_STATS_RXMULTI 0x08
154	#define AR7240_STATS_RXFCSERR 0x0c
155	#define AR7240_STATS_RXALIGNERR 0x10
156	#define AR7240_STATS_RXRUNT 0x14
157	#define AR7240_STATS_RXFRAGMENT 0x18
158	#define AR7240_STATS_RX64BYTE 0x1c
159	#define AR7240_STATS_RX128BYTE 0x20
160	#define AR7240_STATS_RX256BYTE 0x24
161	#define AR7240_STATS_RX512BYTE 0x28
162	#define AR7240_STATS_RX1024BYTE 0x2c
163	#define AR7240_STATS_RX1518BYTE 0x30
164	#define AR7240_STATS_RXMAXBYTE 0x34
165	#define AR7240_STATS_RXTOOLONG 0x38
166	#define AR7240_STATS_RXGOODBYTE 0x3c
167	#define AR7240_STATS_RXBADBYTE 0x44
168	#define AR7240_STATS_RXOVERFLOW 0x4c
169	#define AR7240_STATS_FILTERED 0x50
170	#define AR7240_STATS_TXBROAD 0x54
171	#define AR7240_STATS_TXPAUSE 0x58
172	#define AR7240_STATS_TXMULTI 0x5c
173	#define AR7240_STATS_TXUNDERRUN 0x60
174	#define AR7240_STATS_TX64BYTE 0x64
175	#define AR7240_STATS_TX128BYTE 0x68
176	#define AR7240_STATS_TX256BYTE 0x6c
177	#define AR7240_STATS_TX512BYTE 0x70
178	#define AR7240_STATS_TX1024BYTE 0x74
179	#define AR7240_STATS_TX1518BYTE 0x78
180	#define AR7240_STATS_TXMAXBYTE 0x7c
181	#define AR7240_STATS_TXOVERSIZE 0x80
182	#define AR7240_STATS_TXBYTE 0x84
183	#define AR7240_STATS_TXCOLLISION 0x8c
184	#define AR7240_STATS_TXABORTCOL 0x90
185	#define AR7240_STATS_TXMULTICOL 0x94
186	#define AR7240_STATS_TXSINGLECOL 0x98
187	#define AR7240_STATS_TXEXCDEFER 0x9c
188	#define AR7240_STATS_TXDEFER 0xa0
189	#define AR7240_STATS_TXLATECOL 0xa4
190
191	#define AR7240_PORT_CPU 0
192	#define AR7240_NUM_PORTS 6
193	#define AR7240_NUM_PHYS 5
194
195	#define AR7240_PHY_ID1 0x004d
196	#define AR7240_PHY_ID2 0xd041
197
198	#define AR934X_PHY_ID1 0x004d
199	#define AR934X_PHY_ID2 0xd042
200
201	#define AR7240_MAX_VLANS 16
202
203	#define AR934X_REG_OPER_MODE0 0x04
204	#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
205	#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206
207	#define AR934X_REG_OPER_MODE1 0x08
208	#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
209
210	#define AR934X_REG_FLOOD_MASK 0x2c
211	#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
212
213	#define AR934X_REG_QM_CTRL 0x3c
214	#define AR934X_QM_CTRL_ARP_EN BIT(15)
215
216	#define AR934X_REG_AT_CTRL 0x5c
217	#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
218	#define AR934X_AT_CTRL_AGE_EN BIT(17)
219	#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
220
221	#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
222
223	#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
224	#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
225	#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
226	#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
227	#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
228	#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
229	#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
230	#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
231	#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
232
233	#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
234	#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
235	#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
236	#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
237	#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
238	#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
239	#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
240
241	#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
242
243	struct ar7240sw_port_stat {
244	unsigned long rx_broadcast;
245	unsigned long rx_pause;
246	unsigned long rx_multicast;
247	unsigned long rx_fcs_error;
248	unsigned long rx_align_error;
249	unsigned long rx_runt;
250	unsigned long rx_fragments;
251	unsigned long rx_64byte;
252	unsigned long rx_128byte;
253	unsigned long rx_256byte;
254	unsigned long rx_512byte;
255	unsigned long rx_1024byte;
256	unsigned long rx_1518byte;
257	unsigned long rx_maxbyte;
258	unsigned long rx_toolong;
259	unsigned long rx_good_byte;
260	unsigned long rx_bad_byte;
261	unsigned long rx_overflow;
262	unsigned long filtered;
263
264	unsigned long tx_broadcast;
265	unsigned long tx_pause;
266	unsigned long tx_multicast;
267	unsigned long tx_underrun;
268	unsigned long tx_64byte;
269	unsigned long tx_128byte;
270	unsigned long tx_256byte;
271	unsigned long tx_512byte;
272	unsigned long tx_1024byte;
273	unsigned long tx_1518byte;
274	unsigned long tx_maxbyte;
275	unsigned long tx_oversize;
276	unsigned long tx_byte;
277	unsigned long tx_collision;
278	unsigned long tx_abortcol;
279	unsigned long tx_multicol;
280	unsigned long tx_singlecol;
281	unsigned long tx_excdefer;
282	unsigned long tx_defer;
283	unsigned long tx_xlatecol;
284	};
285
286	struct ar7240sw {
287	struct mii_bus *mii_bus;
288	struct ag71xx_switch_platform_data *swdata;
289	struct switch_dev swdev;
290	int num_ports;
291	u8 ver;
292	bool vlan;
293	u16 vlan_id[AR7240_MAX_VLANS];
294	u8 vlan_table[AR7240_MAX_VLANS];
295	u8 vlan_tagged;
296	u16 pvid[AR7240_NUM_PORTS];
297	char buf[80];
298
299	rwlock_t stats_lock;
300	struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
301	};
302
303	struct ar7240sw_hw_stat {
304	char string[ETH_GSTRING_LEN];
305	int sizeof_stat;
306	int reg;
307	};
308
309	static DEFINE_MUTEX(reg_mutex);
310
311	static inline int sw_is_ar7240(struct ar7240sw *as)
312	{
313	return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
314	}
315
316	static inline int sw_is_ar934x(struct ar7240sw *as)
317	{
318	return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
319	}
320
321	static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
322	{
323	return BIT(port);
324	}
325
326	static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
327	{
328	return BIT(as->swdev.ports) - 1;
329	}
330
331	static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
332	{
333	return ar7240sw_port_mask_all(as) & ~BIT(port);
334	}
335
336	static inline u16 mk_phy_addr(u32 reg)
337	{
338	return 0x17 & ((reg >> 4) \| 0x10);
339	}
340
341	static inline u16 mk_phy_reg(u32 reg)
342	{
343	return (reg << 1) & 0x1e;
344	}
345
346	static inline u16 mk_high_addr(u32 reg)
347	{
348	return (reg >> 7) & 0x1ff;
349	}
350
351	static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
352	{
353	unsigned long flags;
354	u16 phy_addr;
355	u16 phy_reg;
356	u32 hi, lo;
357
358	reg = (reg & 0xfffffffc) >> 2;
359	phy_addr = mk_phy_addr(reg);
360	phy_reg = mk_phy_reg(reg);
361
362	local_irq_save(flags);
363	ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
364	lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
365	hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
366	local_irq_restore(flags);
367
368	return (hi << 16) \| lo;
369	}
370
371	static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
372	{
373	unsigned long flags;
374	u16 phy_addr;
375	u16 phy_reg;
376
377	reg = (reg & 0xfffffffc) >> 2;
378	phy_addr = mk_phy_addr(reg);
379	phy_reg = mk_phy_reg(reg);
380
381	local_irq_save(flags);
382	ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
383	ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
384	ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
385	local_irq_restore(flags);
386	}
387
388	static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
389	{
390	u32 ret;
391
392	mutex_lock(&reg_mutex);
393	ret = __ar7240sw_reg_read(mii, reg_addr);
394	mutex_unlock(&reg_mutex);
395
396	return ret;
397	}
398
399	static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
400	{
401	mutex_lock(&reg_mutex);
402	__ar7240sw_reg_write(mii, reg_addr, reg_val);
403	mutex_unlock(&reg_mutex);
404	}
405
406	static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
407	{
408	u32 t;
409
410	mutex_lock(&reg_mutex);
411	t = __ar7240sw_reg_read(mii, reg);
412	t &= ~mask;
413	t \|= val;
414	__ar7240sw_reg_write(mii, reg, t);
415	mutex_unlock(&reg_mutex);
416
417	return t;
418	}
419
420	static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
421	{
422	u32 t;
423
424	mutex_lock(&reg_mutex);
425	t = __ar7240sw_reg_read(mii, reg);
426	t \|= val;
427	__ar7240sw_reg_write(mii, reg, t);
428	mutex_unlock(&reg_mutex);
429	}
430
431	static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
432	unsigned timeout)
433	{
434	int i;
435
436	for (i = 0; i < timeout; i++) {
437	u32 t;
438
439	t = __ar7240sw_reg_read(mii, reg);
440	if ((t & mask) == val)
441	return 0;
442
443	msleep(1);
444	}
445
446	return -ETIMEDOUT;
447	}
448
449	static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
450	unsigned timeout)
451	{
452	int ret;
453
454	mutex_lock(&reg_mutex);
455	ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
456	mutex_unlock(&reg_mutex);
457	return ret;
458	}
459
460	u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
461	unsigned reg_addr)
462	{
463	u32 t, val = 0xffff;
464	int err;
465
466	if (phy_addr >= AR7240_NUM_PHYS)
467	return 0xffff;
468
469	mutex_lock(&reg_mutex);
470	t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) \|
471	(phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) \|
472	AR7240_MDIO_CTRL_MASTER_EN \|
473	AR7240_MDIO_CTRL_BUSY \|
474	AR7240_MDIO_CTRL_CMD_READ;
475
476	__ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
477	err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
478	AR7240_MDIO_CTRL_BUSY, 0, 5);
479	if (!err)
480	val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
481	mutex_unlock(&reg_mutex);
482
483	return val & AR7240_MDIO_CTRL_DATA_M;
484	}
485
486	int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
487	unsigned reg_addr, u16 reg_val)
488	{
489	u32 t;
490	int ret;
491
492	if (phy_addr >= AR7240_NUM_PHYS)
493	return -EINVAL;
494
495	mutex_lock(&reg_mutex);
496	t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) \|
497	(reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) \|
498	AR7240_MDIO_CTRL_MASTER_EN \|
499	AR7240_MDIO_CTRL_BUSY \|
500	AR7240_MDIO_CTRL_CMD_WRITE \|
501	reg_val;
502
503	__ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
504	ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
505	AR7240_MDIO_CTRL_BUSY, 0, 5);
506	mutex_unlock(&reg_mutex);
507
508	return ret;
509	}
510
511	static int ar7240sw_capture_stats(struct ar7240sw *as)
512	{
513	struct mii_bus *mii = as->mii_bus;
514	int port;
515	int ret;
516
517	write_lock(&as->stats_lock);
518
519	/* Capture the hardware statistics for all ports */
520	ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
521	(AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
522
523	/* Wait for the capturing to complete. */
524	ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
525	AR7240_MIB_BUSY, 0, 10);
526
527	if (ret)
528	goto unlock;
529
530	for (port = 0; port < AR7240_NUM_PORTS; port++) {
531	unsigned int base;
532	struct ar7240sw_port_stat *stats;
533
534	base = AR7240_REG_STATS_BASE(port);
535	stats = &as->port_stats[port];
536
537	#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
538
539	stats->rx_good_byte += READ_STAT(RXGOODBYTE);
540	stats->tx_byte += READ_STAT(TXBYTE);
541
542	#undef READ_STAT
543	}
544
545	ret = 0;
546
547	unlock:
548	write_unlock(&as->stats_lock);
549	return ret;
550	}
551
552	static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
553	{
554	ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
555	AR7240_PORT_CTRL_STATE_DISABLED);
556	}
557
558	static void ar7240sw_setup(struct ar7240sw *as)
559	{
560	struct mii_bus *mii = as->mii_bus;
561
562	/* Enable CPU port, and disable mirror port */
563	ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
564	AR7240_CPU_PORT_EN \|
565	(15 << AR7240_MIRROR_PORT_S));
566
567	/* Setup TAG priority mapping */
568	ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
569
570	if (sw_is_ar934x(as)) {
571	/* Enable aging, MAC replacing */
572	ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
573	0x2b /* 5 min age time */ \|
574	AR934X_AT_CTRL_AGE_EN \|
575	AR934X_AT_CTRL_LEARN_CHANGE);
576	/* Enable ARP frame acknowledge */
577	ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
578	AR934X_QM_CTRL_ARP_EN);
579	/* Enable Broadcast frames transmitted to the CPU */
580	ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
581	AR934X_FLOOD_MASK_BC_DP(0));
582	} else {
583	/* Enable ARP frame acknowledge, aging, MAC replacing */
584	ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
585	AR7240_AT_CTRL_RESERVED \|
586	0x2b /* 5 min age time */ \|
587	AR7240_AT_CTRL_AGE_EN \|
588	AR7240_AT_CTRL_ARP_EN \|
589	AR7240_AT_CTRL_LEARN_CHANGE);
590	/* Enable Broadcast frames transmitted to the CPU */
591	ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
592	AR7240_FLOOD_MASK_BROAD_TO_CPU);
593	}
594
595	/* setup MTU */
596	ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
597	1536);
598
599	/* setup Service TAG */
600	ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
601	}
602
603	static int ar7240sw_reset(struct ar7240sw *as)
604	{
605	struct mii_bus *mii = as->mii_bus;
606	int ret;
607	int i;
608
609	/* Set all ports to disabled state. */
610	for (i = 0; i < AR7240_NUM_PORTS; i++)
611	ar7240sw_disable_port(as, i);
612
613	/* Wait for transmit queues to drain. */
614	msleep(2);
615
616	/* Reset the switch. */
617	ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
618	AR7240_MASK_CTRL_SOFT_RESET);
619
620	ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
621	AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
622
623	/* setup PHYs */
624	for (i = 0; i < AR7240_NUM_PHYS; i++) {
625	ar7240sw_phy_write(mii, i, MII_ADVERTISE,
626	ADVERTISE_ALL \| ADVERTISE_PAUSE_CAP \|
627	ADVERTISE_PAUSE_ASYM);
628	ar7240sw_phy_write(mii, i, MII_BMCR,
629	BMCR_RESET \| BMCR_ANENABLE);
630	}
631	msleep(1000);
632
633	ar7240sw_setup(as);
634	return ret;
635	}
636
637	static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
638	{
639	struct mii_bus *mii = as->mii_bus;
640	u32 ctrl;
641	u32 vid, mode;
642
643	ctrl = AR7240_PORT_CTRL_STATE_FORWARD \| AR7240_PORT_CTRL_LEARN \|
644	AR7240_PORT_CTRL_SINGLE_VLAN;
645
646	if (port == AR7240_PORT_CPU) {
647	ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
648	AR7240_PORT_STATUS_SPEED_1000 \|
649	AR7240_PORT_STATUS_TXFLOW \|
650	AR7240_PORT_STATUS_RXFLOW \|
651	AR7240_PORT_STATUS_TXMAC \|
652	AR7240_PORT_STATUS_RXMAC \|
653	AR7240_PORT_STATUS_DUPLEX);
654	} else {
655	ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
656	AR7240_PORT_STATUS_LINK_AUTO);
657	}
658
659	/* Set the default VID for this port */
660	if (as->vlan) {
661	vid = as->vlan_id[as->pvid[port]];
662	mode = AR7240_PORT_VLAN_MODE_SECURE;
663	} else {
664	vid = port;
665	mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
666	}
667
668	if (as->vlan) {
669	if (as->vlan_tagged & BIT(port))
670	ctrl \|= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
671	AR7240_PORT_CTRL_VLAN_MODE_S;
672	else
673	ctrl \|= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
674	AR7240_PORT_CTRL_VLAN_MODE_S;
675	} else {
676	ctrl \|= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
677	AR7240_PORT_CTRL_VLAN_MODE_S;
678	}
679
680	if (!portmask) {
681	if (port == AR7240_PORT_CPU)
682	portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
683	else
684	portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
685	}
686
687	/* allow the port to talk to all other ports, but exclude its
688	* own ID to prevent frames from being reflected back to the
689	* port that they came from */
690	portmask &= ar7240sw_port_mask_but(as, port);
691
692	ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
693	if (sw_is_ar934x(as)) {
694	u32 vlan1, vlan2;
695
696	vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
697	vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) \|
698	(mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
699	ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
700	ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
701	} else {
702	u32 vlan;
703
704	vlan = vid \| (mode << AR7240_PORT_VLAN_MODE_S) \|
705	(portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
706
707	ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
708	}
709	}
710
711	static int ar7240_set_addr(struct ar7240sw as, u8 addr)
712	{
713	struct mii_bus *mii = as->mii_bus;
714	u32 t;
715
716	t = (addr[4] << 8) \| addr[5];
717	ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
718
719	t = (addr[0] << 24) \| (addr[1] << 16) \| (addr[2] << 8) \| addr[3];
720	ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
721
722	return 0;
723	}
724
725	static int
726	ar7240_set_vid(struct switch_dev dev, const struct switch_attr attr,
727	struct switch_val *val)
728	{
729	struct ar7240sw *as = sw_to_ar7240(dev);
730	as->vlan_id[val->port_vlan] = val->value.i;
731	return 0;
732	}
733
734	static int
735	ar7240_get_vid(struct switch_dev dev, const struct switch_attr attr,
736	struct switch_val *val)
737	{
738	struct ar7240sw *as = sw_to_ar7240(dev);
739	val->value.i = as->vlan_id[val->port_vlan];
740	return 0;
741	}
742
743	static int
744	ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
745	{
746	struct ar7240sw *as = sw_to_ar7240(dev);
747
748	/* make sure no invalid PVIDs get set */
749
750	if (vlan >= dev->vlans)
751	return -EINVAL;
752
753	as->pvid[port] = vlan;
754	return 0;
755	}
756
757	static int
758	ar7240_get_pvid(struct switch_dev dev, int port, int vlan)
759	{
760	struct ar7240sw *as = sw_to_ar7240(dev);
761	*vlan = as->pvid[port];
762	return 0;
763	}
764
765	static int
766	ar7240_get_ports(struct switch_dev dev, struct switch_val val)
767	{
768	struct ar7240sw *as = sw_to_ar7240(dev);
769	u8 ports = as->vlan_table[val->port_vlan];
770	int i;
771
772	val->len = 0;
773	for (i = 0; i < as->swdev.ports; i++) {
774	struct switch_port *p;
775
776	if (!(ports & (1 << i)))
777	continue;
778
779	p = &val->value.ports[val->len++];
780	p->id = i;
781	if (as->vlan_tagged & (1 << i))
782	p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
783	else
784	p->flags = 0;
785	}
786	return 0;
787	}
788
789	static int
790	ar7240_set_ports(struct switch_dev dev, struct switch_val val)
791	{
792	struct ar7240sw *as = sw_to_ar7240(dev);
793	u8 *vt = &as->vlan_table[val->port_vlan];
794	int i, j;
795
796	*vt = 0;
797	for (i = 0; i < val->len; i++) {
798	struct switch_port *p = &val->value.ports[i];
799
800	if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
801	as->vlan_tagged \|= (1 << p->id);
802	else {
803	as->vlan_tagged &= ~(1 << p->id);
804	as->pvid[p->id] = val->port_vlan;
805
806	/* make sure that an untagged port does not
807	* appear in other vlans */
808	for (j = 0; j < AR7240_MAX_VLANS; j++) {
809	if (j == val->port_vlan)
810	continue;
811	as->vlan_table[j] &= ~(1 << p->id);
812	}
813	}
814
815	*vt \|= 1 << p->id;
816	}
817	return 0;
818	}
819
820	static int
821	ar7240_set_vlan(struct switch_dev dev, const struct switch_attr attr,
822	struct switch_val *val)
823	{
824	struct ar7240sw *as = sw_to_ar7240(dev);
825	as->vlan = !!val->value.i;
826	return 0;
827	}
828
829	static int
830	ar7240_get_vlan(struct switch_dev dev, const struct switch_attr attr,
831	struct switch_val *val)
832	{
833	struct ar7240sw *as = sw_to_ar7240(dev);
834	val->value.i = as->vlan;
835	return 0;
836	}
837
838	static void
839	ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
840	{
841	struct mii_bus *mii = as->mii_bus;
842
843	if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
844	return;
845
846	if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
847	val &= AR7240_VTUDATA_MEMBER;
848	val \|= AR7240_VTUDATA_VALID;
849	ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
850	}
851	op \|= AR7240_VTU_ACTIVE;
852	ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
853	}
854
855	static int
856	ar7240_hw_apply(struct switch_dev *dev)
857	{
858	struct ar7240sw *as = sw_to_ar7240(dev);
859	u8 portmask[AR7240_NUM_PORTS];
860	int i, j;
861
862	/* flush all vlan translation unit entries */
863	ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
864
865	memset(portmask, 0, sizeof(portmask));
866	if (as->vlan) {
867	/* calculate the port destination masks and load vlans
868	* into the vlan translation unit */
869	for (j = 0; j < AR7240_MAX_VLANS; j++) {
870	u8 vp = as->vlan_table[j];
871
872	if (!vp)
873	continue;
874
875	for (i = 0; i < as->swdev.ports; i++) {
876	u8 mask = (1 << i);
877	if (vp & mask)
878	portmask[i] \|= vp & ~mask;
879	}
880
881	ar7240_vtu_op(as,
882	AR7240_VTU_OP_LOAD \|
883	(as->vlan_id[j] << AR7240_VTU_VID_S),
884	as->vlan_table[j]);
885	}
886	} else {
887	/* vlan disabled:
888	* isolate all ports, but connect them to the cpu port */
889	for (i = 0; i < as->swdev.ports; i++) {
890	if (i == AR7240_PORT_CPU)
891	continue;
892
893	portmask[i] = 1 << AR7240_PORT_CPU;
894	portmask[AR7240_PORT_CPU] \|= (1 << i);
895	}
896	}
897
898	/* update the port destination mask registers and tag settings */
899	for (i = 0; i < as->swdev.ports; i++)
900	ar7240sw_setup_port(as, i, portmask[i]);
901
902	return 0;
903	}
904
905	static int
906	ar7240_reset_switch(struct switch_dev *dev)
907	{
908	struct ar7240sw *as = sw_to_ar7240(dev);
909	ar7240sw_reset(as);
910	return 0;
911	}
912
913	static int
914	ar7240_get_port_link(struct switch_dev *dev, int port,
915	struct switch_port_link *link)
916	{
917	struct ar7240sw *as = sw_to_ar7240(dev);
918	struct mii_bus *mii = as->mii_bus;
919	u32 status;
920
921	if (port > AR7240_NUM_PORTS)
922	return -EINVAL;
923
924	status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
925	link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
926	if (link->aneg) {
927	link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
928	if (!link->link)
929	return 0;
930	} else {
931	link->link = true;
932	}
933
934	link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
935	link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
936	link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
937	switch (status & AR7240_PORT_STATUS_SPEED_M) {
938	case AR7240_PORT_STATUS_SPEED_10:
939	link->speed = SWITCH_PORT_SPEED_10;
940	break;
941	case AR7240_PORT_STATUS_SPEED_100:
942	link->speed = SWITCH_PORT_SPEED_100;
943	break;
944	case AR7240_PORT_STATUS_SPEED_1000:
945	link->speed = SWITCH_PORT_SPEED_1000;
946	break;
947	}
948
949	return 0;
950	}
951
952	static int
953	ar7240_get_port_stats(struct switch_dev *dev, int port,
954	struct switch_port_stats *stats)
955	{
956	struct ar7240sw *as = sw_to_ar7240(dev);
957
958	if (port > AR7240_NUM_PORTS)
959	return -EINVAL;
960
961	ar7240sw_capture_stats(as);
962
963	read_lock(&as->stats_lock);
964	stats->rx_bytes = as->port_stats[port].rx_good_byte;
965	stats->tx_bytes = as->port_stats[port].tx_byte;
966	read_unlock(&as->stats_lock);
967
968	return 0;
969	}
970
971	static struct switch_attr ar7240_globals[] = {
972	{
973	.type = SWITCH_TYPE_INT,
974	.name = "enable_vlan",
975	.description = "Enable VLAN mode",
976	.set = ar7240_set_vlan,
977	.get = ar7240_get_vlan,
978	.max = 1
979	},
980	};
981
982	static struct switch_attr ar7240_port[] = {
983	};
984
985	static struct switch_attr ar7240_vlan[] = {
986	{
987	.type = SWITCH_TYPE_INT,
988	.name = "vid",
989	.description = "VLAN ID",
990	.set = ar7240_set_vid,
991	.get = ar7240_get_vid,
992	.max = 4094,
993	},
994	};
995
996	static const struct switch_dev_ops ar7240_ops = {
997	.attr_global = {
998	.attr = ar7240_globals,
999	.n_attr = ARRAY_SIZE(ar7240_globals),
1000	},
1001	.attr_port = {
1002	.attr = ar7240_port,
1003	.n_attr = ARRAY_SIZE(ar7240_port),
1004	},
1005	.attr_vlan = {
1006	.attr = ar7240_vlan,
1007	.n_attr = ARRAY_SIZE(ar7240_vlan),
1008	},
1009	.get_port_pvid = ar7240_get_pvid,
1010	.set_port_pvid = ar7240_set_pvid,
1011	.get_vlan_ports = ar7240_get_ports,
1012	.set_vlan_ports = ar7240_set_ports,
1013	.apply_config = ar7240_hw_apply,
1014	.reset_switch = ar7240_reset_switch,
1015	.get_port_link = ar7240_get_port_link,
1016	.get_port_stats = ar7240_get_port_stats,
1017	};
1018
1019	static struct ar7240sw ar7240_probe(struct ag71xx ag)
1020	{
1021	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1022	struct mii_bus *mii = ag->mii_bus;
1023	struct ar7240sw *as;
1024	struct switch_dev *swdev;
1025	u32 ctrl;
1026	u16 phy_id1;
1027	u16 phy_id2;
1028	int i;
1029
1030	phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1031	phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1032	if ((phy_id1 != AR7240_PHY_ID1 \|\| phy_id2 != AR7240_PHY_ID2) &&
1033	(phy_id1 != AR934X_PHY_ID1 \|\| phy_id2 != AR934X_PHY_ID2)) {
1034	pr_err("%s: unknown phy id '%04x:%04x'\n",
1035	ag->dev->name, phy_id1, phy_id2);
1036	return NULL;
1037	}
1038
1039	as = kzalloc(sizeof(*as), GFP_KERNEL);
1040	if (!as)
1041	return NULL;
1042
1043	as->mii_bus = mii;
1044	as->swdata = pdata->switch_data;
1045
1046	swdev = &as->swdev;
1047
1048	ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1049	as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1050	AR7240_MASK_CTRL_VERSION_M;
1051
1052	if (sw_is_ar7240(as)) {
1053	swdev->name = "AR7240/AR9330 built-in switch";
1054	swdev->ports = AR7240_NUM_PORTS - 1;
1055	} else if (sw_is_ar934x(as)) {
1056	swdev->name = "AR934X built-in switch";
1057
1058	if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1059	ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1060	AR934X_OPER_MODE0_MAC_GMII_EN);
1061	} else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1062	ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1063	AR934X_OPER_MODE0_PHY_MII_EN);
1064	} else {
1065	pr_err("%s: invalid PHY interface mode\n",
1066	ag->dev->name);
1067	goto err_free;
1068	}
1069
1070	if (as->swdata->phy4_mii_en) {
1071	ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1072	AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1073	swdev->ports = AR7240_NUM_PORTS - 1;
1074	} else {
1075	swdev->ports = AR7240_NUM_PORTS;
1076	}
1077	} else {
1078	pr_err("%s: unsupported chip, ctrl=%08x\n",
1079	ag->dev->name, ctrl);
1080	goto err_free;
1081	}
1082
1083	swdev->cpu_port = AR7240_PORT_CPU;
1084	swdev->vlans = AR7240_MAX_VLANS;
1085	swdev->ops = &ar7240_ops;
1086
1087	if (register_switch(&as->swdev, ag->dev) < 0)
1088	goto err_free;
1089
1090	pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
1091
1092	/* initialize defaults */
1093	for (i = 0; i < AR7240_MAX_VLANS; i++)
1094	as->vlan_id[i] = i;
1095
1096	as->vlan_table[0] = ar7240sw_port_mask_all(as);
1097
1098	return as;
1099
1100	err_free:
1101	kfree(as);
1102	return NULL;
1103	}
1104
1105	static void link_function(struct work_struct *work) {
1106	struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1107	struct ar7240sw *as = ag->phy_priv;
1108	unsigned long flags;
1109	int i;
1110	int status = 0;
1111
1112	for (i = 0; i < as->swdev.ports; i++) {
1113	int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1114	if(link & BMSR_LSTATUS) {
1115	status = 1;
1116	break;
1117	}
1118	}
1119
1120	spin_lock_irqsave(&ag->lock, flags);
1121	if(status != ag->link) {
1122	ag->link = status;
1123	ag71xx_link_adjust(ag);
1124	}
1125	spin_unlock_irqrestore(&ag->lock, flags);
1126
1127	schedule_delayed_work(&ag->link_work, HZ / 2);
1128	}
1129
1130	void ag71xx_ar7240_start(struct ag71xx *ag)
1131	{
1132	struct ar7240sw *as = ag->phy_priv;
1133
1134	ar7240sw_reset(as);
1135
1136	ag->speed = SPEED_1000;
1137	ag->duplex = 1;
1138
1139	ar7240_set_addr(as, ag->dev->dev_addr);
1140	ar7240_hw_apply(&as->swdev);
1141
1142	schedule_delayed_work(&ag->link_work, HZ / 10);
1143	}
1144
1145	void ag71xx_ar7240_stop(struct ag71xx *ag)
1146	{
1147	cancel_delayed_work_sync(&ag->link_work);
1148	}
1149
1150	int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
1151	{
1152	struct ar7240sw *as;
1153
1154	as = ar7240_probe(ag);
1155	if (!as)
1156	return -ENODEV;
1157
1158	ag->phy_priv = as;
1159	ar7240sw_reset(as);
1160
1161	rwlock_init(&as->stats_lock);
1162	INIT_DELAYED_WORK(&ag->link_work, link_function);
1163
1164	return 0;
1165	}
1166
1167	void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1168	{
1169	struct ar7240sw *as = ag->phy_priv;
1170
1171	if (!as)
1172	return;
1173
1174	unregister_switch(&as->swdev);
1175	kfree(as);
1176	ag->phy_priv = NULL;
1177	}

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