source: src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/ra2882ethreg.h @ 18352

Last change on this file since 18352 was 18352, checked in by BrainSlayer, 16 months ago

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File size: 24.2 KB
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1#ifndef RA2882ETHREG_H
2#define RA2882ETHREG_H
3
4#include <linux/mii.h>          // for struct mii_if_info in ra2882ethreg.h
5#include <linux/version.h>      /* check linux version for 2.4 and 2.6 compatibility */
6#include <linux/interrupt.h>    /* check linux version for 2.4 and 2.6 compatibility */
7
8#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
9#include <asm/rt2880/rt_mmap.h>
10#endif
11#include "raether.h"
12
13#ifdef WORKQUEUE_BH
14#include <linux/workqueue.h>
15#endif // WORKQUEUE_BH //
16
17#define MAX_PACKET_SIZE 1514
18#define MIN_PACKET_SIZE 60
19
20#define phys_to_bus(a) (a & 0x1FFFFFFF)
21
22#define BIT(x)  ((1 << x))
23#define ETHER_ADDR_LEN  6
24
25/*  Phy Vender ID list */
26
27#define EV_MARVELL_PHY_ID0 0x0141 
28#define EV_MARVELL_PHY_ID1 0x0CC2 
29#define EV_VTSS_PHY_ID0 0x0007
30#define EV_VTSS_PHY_ID1 0x0421
31
32/*
33     FE_INT_STATUS
34*/
35#if defined (CONFIG_RALINK_RT5350)
36
37#define RX_COHERENT      BIT(31)
38#define RX_DLY_INT       BIT(30)
39#define TX_COHERENT      BIT(29)
40#define TX_DLY_INT       BIT(28)
41
42#define RX_DONE_INT1     BIT(17)
43#define RX_DONE_INT0     BIT(16)
44
45#define TX_DONE_INT3     BIT(3)
46#define TX_DONE_INT2     BIT(2)
47#define TX_DONE_INT1     BIT(1)
48#define TX_DONE_INT0     BIT(0)
49#else
50//#define CNT_PPE_AF       BIT(31)     
51//#define CNT_GDM_AF       BIT(29)
52#define PSE_P2_FC        BIT(26)
53#define GDM_CRC_DROP     BIT(25)
54#define PSE_BUF_DROP     BIT(24)
55#define GDM_OTHER_DROP   BIT(23)
56#define PSE_P1_FC        BIT(22)
57#define PSE_P0_FC        BIT(21)
58#define PSE_FQ_EMPTY     BIT(20)
59#define GE1_STA_CHG      BIT(18)
60#define TX_COHERENT      BIT(17)
61#define RX_COHERENT      BIT(16)
62
63#define TX_DONE_INT3     BIT(11)
64#define TX_DONE_INT2     BIT(10)
65#define TX_DONE_INT1     BIT(9)
66#define TX_DONE_INT0     BIT(8)
67#define RX_DONE_INT1     RX_DONE_INT0
68#define RX_DONE_INT0     BIT(2)
69#define TX_DLY_INT       BIT(1)
70#define RX_DLY_INT       BIT(0)
71#endif
72
73#define FE_INT_ALL              (TX_DONE_INT3 | TX_DONE_INT2 | \
74                                 TX_DONE_INT1 | TX_DONE_INT0 | \
75                                 RX_DONE_INT0 )
76/*
77 * SW_INT_STATUS
78 */
79#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
80#define PORT0_QUEUE_FULL        BIT(14) //port0 queue full
81#define PORT1_QUEUE_FULL        BIT(15) //port1 queue full
82#define PORT2_QUEUE_FULL        BIT(16) //port2 queue full
83#define PORT3_QUEUE_FULL        BIT(17) //port3 queue full
84#define PORT4_QUEUE_FULL        BIT(18) //port4 queue full
85#define PORT5_QUEUE_FULL        BIT(19) //port5 queue full
86#define PORT6_QUEUE_FULL        BIT(20) //port6 queue full
87#define SHARED_QUEUE_FULL       BIT(23) //shared queue full
88#define QUEUE_EXHAUSTED         BIT(24) //global queue is used up and all packets are dropped
89#define BC_STROM                BIT(25) //the device is undergoing broadcast storm
90#define PORT_ST_CHG             BIT(26) //Port status change
91#define UNSECURED_ALERT         BIT(27) //Intruder alert
92#define ABNORMAL_ALERT          BIT(28) //Abnormal
93
94#define ESW_INT_ALL             (PORT_ST_CHG)
95
96#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 //
97
98#define RX_BUF_ALLOC_SIZE       2000
99#define FASTPATH_HEADROOM       64
100
101#define ETHER_BUFFER_ALIGN      32              ///// Align on a cache line
102
103#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
104        ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
105        ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
106
107#ifdef CONFIG_PSEUDO_SUPPORT
108typedef struct _PSEUDO_ADAPTER {
109    struct net_device *RaethDev;
110    struct net_device *PseudoDev;
111    struct net_device_stats stat;
112#if defined (CONFIG_ETHTOOL)
113        struct mii_if_info      mii_info;
114#endif
115
116} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
117
118#define MAX_PSEUDO_ENTRY               1
119#endif
120
121
122
123/* Register Categories Definition */
124#define RAFRAMEENGINE_OFFSET    0x0000
125#define RAGDMA_OFFSET           0x0020
126#define RAPSE_OFFSET            0x0040
127#define RAGDMA2_OFFSET          0x0060
128#define RACDMA_OFFSET           0x0080
129#if defined (CONFIG_RALINK_RT5350)
130#define RAPDMA_OFFSET           0x0800
131#define SDM_OFFSET              0x0C00
132#else
133#define RAPDMA_OFFSET           0x0100
134#endif
135#define RAPPE_OFFSET            0x0200
136#define RACMTABLE_OFFSET        0x0400
137#define RAPOLICYTABLE_OFFSET    0x1000
138
139
140/* Register Map Detail */
141/* RT3883 */
142#define SYSCFG1                 (RALINK_SYSCTL_BASE + 0x14)
143
144#if defined (CONFIG_RALINK_RT5350)
145
146/* 1. PDMA */
147#define TX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
148#define TX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
149#define TX_CTX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
150#define TX_DTX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
151
152#define TX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
153#define TX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
154#define TX_CTX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
155#define TX_DTX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
156
157#define TX_BASE_PTR2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
158#define TX_MAX_CNT2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
159#define TX_CTX_IDX2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
160#define TX_DTX_IDX2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
161
162#define TX_BASE_PTR3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
163#define TX_MAX_CNT3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
164#define TX_CTX_IDX3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
165#define TX_DTX_IDX3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
166
167#define RX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
168#define RX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
169#define RX_CALC_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
170#define RX_DRX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
171
172#define RX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
173#define RX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
174#define RX_CALC_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
175#define RX_DRX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
176
177#define PDMA_INFO               (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
178#define PDMA_GLO_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
179#define PDMA_RST_IDX            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
180#define PDMA_RST_CFG            (PDMA_RST_IDX)
181#define DLY_INT_CFG             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
182#define FREEQ_THRES             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
183#define INT_STATUS              (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
184#define FE_INT_STATUS           (INT_STATUS)
185#define INT_MASK                (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
186#define FE_INT_ENABLE           (INT_MASK)
187#define PDMA_WRR                (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
188#define PDMA_SCH_CFG            (PDMA_WRR)
189
190#define SDM_CON                 (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00)  //Switch DMA configuration
191#define SDM_RRING               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04)  //Switch DMA Rx Ring
192#define SDM_TRING               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08)  //Switch DMA Tx Ring
193#define SDM_MAC_ADRL            (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C)  //Switch MAC address LSB
194#define SDM_MAC_ADRH            (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10)  //Switch MAC Address MSB
195#define SDM_TPCNT               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
196#define SDM_TBCNT               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
197#define SDM_RPCNT               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
198#define SDM_RBCNT               (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
199#define SDM_CS_ERR              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
200
201#else
202
203/* 1. Frame Engine Global Registers */
204#define MDIO_ACCESS             (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
205#define MDIO_CFG                (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
206#define MDIO_CFG2               (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18)
207#define FE_GLO_CFG              (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
208#define FE_RST_GL               (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
209#define FE_INT_STATUS           (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
210#define FE_INT_ENABLE           (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
211#define MDIO_CFG2               (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
212#define FOC_TS_T                (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
213
214
215/* 2. GDMA Registers */
216#define GDMA1_FWD_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
217#define GDMA1_SCH_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
218#define GDMA1_SHPR_CFG          (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
219#define GDMA1_MAC_ADRL          (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
220#define GDMA1_MAC_ADRH          (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
221
222#define GDMA2_FWD_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
223#define GDMA2_SCH_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
224#define GDMA2_SHPR_CFG          (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
225#define GDMA2_MAC_ADRL          (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
226#define GDMA2_MAC_ADRH          (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
227
228/* 3. PSE */
229#define PSE_FQ_CFG              (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
230#define CDMA_FC_CFG             (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
231#define GDMA1_FC_CFG            (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
232#define GDMA2_FC_CFG            (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
233#define PDMA_FC_CFG             (RALINK_FRAME_ENGINE_BASE+0x1f0)
234
235/* 4. CDMA */
236#define CDMA_CSG_CFG            (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
237#define CDMA_SCH_CFG            (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
238/* skip ppoe sid and vlan id definition */
239
240
241/* 5. PDMA */
242#define PDMA_GLO_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
243#define PDMA_RST_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
244#define PDMA_SCH_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
245
246#define DLY_INT_CFG             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
247
248#define TX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
249#define TX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
250#define TX_CTX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
251#define TX_DTX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
252
253#define TX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
254#define TX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
255#define TX_CTX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
256#define TX_DTX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
257
258#define TX_BASE_PTR2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
259#define TX_MAX_CNT2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
260#define TX_CTX_IDX2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
261#define TX_DTX_IDX2             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
262
263#define TX_BASE_PTR3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
264#define TX_MAX_CNT3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
265#define TX_CTX_IDX3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
266#define TX_DTX_IDX3             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
267
268#define RX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
269#define RX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
270#define RX_CALC_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
271#define RX_DRX_IDX0             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
272
273#define RX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
274#define RX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
275#define RX_CALC_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
276#define RX_DRX_IDX1             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
277
278#endif
279
280#define DELAY_INT_INIT          0x84048404
281#define FE_INT_DLY_INIT         (TX_DLY_INT | RX_DLY_INT)
282
283
284#if !defined (CONFIG_RALINK_RT5350)
285
286/* 6. Counter and Meter Table */
287#define PPE_AC_BCNT0            (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
288#define PPE_AC_PCNT0            (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
289/* 0 ~ 63 */
290
291#define PPE_MTR_CNT0            (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
292/* skip... */
293#define PPE_MTR_CNT63           (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
294
295#define GDMA_TX_GBCNT0          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
296#define GDMA_TX_GPCNT0          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
297#define GDMA_TX_SKIPCNT0        (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
298#define GDMA_TX_COLCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
299
300/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
301#define GDMA_RX_GBCNT0          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
302#define GDMA_RX_GPCNT0          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
303#define GDMA_RX_OERCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
304#define GDMA_RX_FERCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
305#define GDMA_RX_SERCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
306#define GDMA_RX_LERCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
307#define GDMA_RX_CERCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
308#define GDMA_RX_FCCNT1          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
309
310#endif
311
312
313/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
314#define PORT0_PKCOUNT           (0xb01100e8)
315#define PORT1_PKCOUNT           (0xb01100ec)
316#define PORT2_PKCOUNT           (0xb01100f0)
317#define PORT3_PKCOUNT           (0xb01100f4)
318#define PORT4_PKCOUNT           (0xb01100f8)
319#define PORT5_PKCOUNT           (0xb01100fc)
320
321
322// PHYS_TO_K1
323#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
324
325
326#define sysRegRead(phys)        \
327        (*(volatile unsigned int *)PHYS_TO_K1(phys))
328
329#define sysRegWrite(phys, val)  \
330        ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
331
332#define u_long  unsigned long
333#define u32     unsigned int
334#define u16     unsigned short
335
336
337/* ====================================== */
338#define GDM1_DISPAD       BIT(18)
339#define GDM1_DISCRC       BIT(17)
340
341//GDMA1 uni-cast frames destination port
342#define GDM1_ICS_EN        (0x1 << 22)
343#define GDM1_TCS_EN        (0x1 << 21)
344#define GDM1_UCS_EN        (0x1 << 20)
345#define GDM1_JMB_EN        (0x1 << 19)
346#define GDM1_STRPCRC       (0x1 << 16)
347#define GDM1_UFRC_P_CPU     (0 << 12)
348#define GDM1_UFRC_P_GDMA1   (1 << 12)
349#define GDM1_UFRC_P_PPE     (6 << 12)
350
351//GDMA1 broad-cast MAC address frames
352#define GDM1_BFRC_P_CPU     (0 << 8)
353#define GDM1_BFRC_P_GDMA1   (1 << 8)
354#define GDM1_BFRC_P_PPE     (6 << 8)
355
356//GDMA1 multi-cast MAC address frames
357#define GDM1_MFRC_P_CPU     (0 << 4)
358#define GDM1_MFRC_P_GDMA1   (1 << 4)
359#define GDM1_MFRC_P_PPE     (6 << 4)
360
361//GDMA1 other MAC address frames destination port
362#define GDM1_OFRC_P_CPU     (0 << 0)
363#define GDM1_OFRC_P_GDMA1   (1 << 0)
364#define GDM1_OFRC_P_PPE     (6 << 0)
365
366#define ICS_GEN_EN          (1 << 2)
367#define UCS_GEN_EN          (1 << 1)
368#define TCS_GEN_EN          (1 << 0)
369
370// MDIO_CFG     bit
371#define MDIO_CFG_GP1_FC_TX      (1 << 11)
372#define MDIO_CFG_GP1_FC_RX      (1 << 10)
373
374/* ====================================== */
375/* ====================================== */
376#define GP1_LNK_DWN     BIT(9)
377#define GP1_AN_FAIL     BIT(8)
378/* ====================================== */
379/* ====================================== */
380#define PSE_RESET       BIT(0)
381/* ====================================== */
382#define PST_DRX_IDX1       BIT(17)
383#define PST_DRX_IDX0       BIT(16)
384#define PST_DTX_IDX3       BIT(3)
385#define PST_DTX_IDX2       BIT(2)
386#define PST_DTX_IDX1       BIT(1)
387#define PST_DTX_IDX0       BIT(0)
388
389#define TX_WB_DDONE       BIT(6)
390#define RX_DMA_BUSY       BIT(3)
391#define TX_DMA_BUSY       BIT(1)
392#define RX_DMA_EN         BIT(2)
393#define TX_DMA_EN         BIT(0)
394
395#define PDMA_BT_SIZE_4DWORDS     (0<<4)
396#define PDMA_BT_SIZE_8DWORDS     (1<<4)
397#define PDMA_BT_SIZE_16DWORDS    (2<<4)
398
399/* Register bits.
400 */
401
402#define MACCFG_RXEN             (1<<2)
403#define MACCFG_TXEN             (1<<3)
404#define MACCFG_PROMISC          (1<<18)
405#define MACCFG_RXMCAST          (1<<19)
406#define MACCFG_FDUPLEX          (1<<20)
407#define MACCFG_PORTSEL          (1<<27)
408#define MACCFG_HBEATDIS         (1<<28)
409
410
411#define DMACTL_SR               (1<<1)  /* Start/Stop Receive */
412#define DMACTL_ST               (1<<13) /* Start/Stop Transmission Command */
413
414#define DMACFG_SWR              (1<<0)  /* Software Reset */
415#define DMACFG_BURST32          (32<<8)
416
417#define DMASTAT_TS              0x00700000      /* Transmit Process State */
418#define DMASTAT_RS              0x000e0000      /* Receive Process State */
419
420#define MACCFG_INIT             0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
421
422
423
424/* Descriptor bits.
425 */
426#define R_OWN           0x80000000      /* Own Bit */
427#define RD_RER          0x02000000      /* Receive End Of Ring */
428#define RD_LS           0x00000100      /* Last Descriptor */
429#define RD_ES           0x00008000      /* Error Summary */
430#define RD_CHAIN        0x01000000      /* Chained */
431
432/* Word 0 */
433#define T_OWN           0x80000000      /* Own Bit */
434#define TD_ES           0x00008000      /* Error Summary */
435
436/* Word 1 */
437#define TD_LS           0x40000000      /* Last Segment */
438#define TD_FS           0x20000000      /* First Segment */
439#define TD_TER          0x08000000      /* Transmit End Of Ring */
440#define TD_CHAIN        0x01000000      /* Chained */
441
442
443#define TD_SET          0x08000000      /* Setup Packet */
444
445
446#define POLL_DEMAND 1
447
448#define RSTCTL  (0x34)
449#define RSTCTL_RSTENET1 (1<<19)
450#define RSTCTL_RSTENET2 (1<<20)
451
452#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG         0xff908000
453#define INIT_VALUE_OF_PSE_FQFC_CFG              0x80504000
454#define INIT_VALUE_OF_FORCE_100_FD              0x1001BC01
455#define INIT_VALUE_OF_FORCE_1000_FD             0x1F01DC01
456
457// Define Whole FE Reset Register
458#define RSTCTRL         (RALINK_SYSCTL_BASE + 0x34)
459
460/*=========================================
461      PDMA RX Descriptor Format define
462=========================================*/
463
464//-------------------------------------------------
465typedef struct _PDMA_RXD_INFO1_  PDMA_RXD_INFO1_T;
466
467struct _PDMA_RXD_INFO1_
468{
469    unsigned int    PDP0;
470};
471//-------------------------------------------------
472typedef struct _PDMA_RXD_INFO2_    PDMA_RXD_INFO2_T;
473
474struct _PDMA_RXD_INFO2_
475{
476    unsigned int    PLEN1                 : 14;
477    unsigned int    LS1                   : 1;
478    unsigned int    UN_USED               : 1;
479    unsigned int    PLEN0                 : 14;
480    unsigned int    LS0                   : 1;
481    unsigned int    DDONE_bit             : 1;
482};
483//-------------------------------------------------
484typedef struct _PDMA_RXD_INFO3_  PDMA_RXD_INFO3_T;
485
486struct _PDMA_RXD_INFO3_
487{
488    unsigned int    UN_USE1;
489};
490//-------------------------------------------------
491typedef struct _PDMA_RXD_INFO4_    PDMA_RXD_INFO4_T;
492
493struct _PDMA_RXD_INFO4_
494{
495
496    unsigned int    FOE_Entry           : 14;
497    unsigned int    FVLD                : 1;
498    unsigned int    UN_USE1             : 1;
499    unsigned int    AI                  : 8;
500    unsigned int    SP                  : 3;
501    unsigned int    AIS                 : 1;
502    unsigned int    L4F                 : 1;
503    unsigned int    IPF                  : 1;
504    unsigned int    L4FVLD_bit           : 1;
505    unsigned int    IPFVLD_bit           : 1;
506};
507
508
509struct PDMA_rxdesc {
510        PDMA_RXD_INFO1_T rxd_info1;
511        PDMA_RXD_INFO2_T rxd_info2;
512        PDMA_RXD_INFO3_T rxd_info3;
513        PDMA_RXD_INFO4_T rxd_info4;
514};
515
516/*=========================================
517      PDMA TX Descriptor Format define
518=========================================*/
519//-------------------------------------------------
520typedef struct _PDMA_TXD_INFO1_  PDMA_TXD_INFO1_T;
521
522struct _PDMA_TXD_INFO1_
523{
524    unsigned int    SDP0;
525};
526//-------------------------------------------------
527typedef struct _PDMA_TXD_INFO2_    PDMA_TXD_INFO2_T;
528
529struct _PDMA_TXD_INFO2_
530{
531    unsigned int    SDL1                  : 14;
532    unsigned int    LS1_bit               : 1;
533    unsigned int    BURST_bit             : 1;
534    unsigned int    SDL0                  : 14;
535    unsigned int    LS0_bit               : 1;
536    unsigned int    DDONE_bit             : 1;
537};
538//-------------------------------------------------
539typedef struct _PDMA_TXD_INFO3_  PDMA_TXD_INFO3_T;
540
541struct _PDMA_TXD_INFO3_
542{
543    unsigned int    SDP1;
544};
545//-------------------------------------------------
546typedef struct _PDMA_TXD_INFO4_    PDMA_TXD_INFO4_T;
547
548struct _PDMA_TXD_INFO4_
549{
550
551    unsigned int    VIDX                : 4;
552    unsigned int    VPRI                : 3;
553    unsigned int    INSV                : 1;
554    unsigned int    SIDX                : 4;
555    unsigned int    INSP                : 1;
556    unsigned int    RESV                : 1;
557    unsigned int    UN_USE3             : 2;
558    unsigned int    QN                  : 3;
559    unsigned int    UN_USE2             : 1;
560    unsigned int    UDF                 : 4;
561    unsigned int    PN                  : 3;
562    unsigned int    UN_USE1             : 2;
563    unsigned int    TCO                 : 1;
564    unsigned int    UCO                 : 1;
565    unsigned int    ICO                 : 1;
566};
567
568
569struct PDMA_txdesc {
570        PDMA_TXD_INFO1_T txd_info1;
571        PDMA_TXD_INFO2_T txd_info2;
572        PDMA_TXD_INFO3_T txd_info3;
573        PDMA_TXD_INFO4_T txd_info4;
574};
575
576#define phys_to_bus(a) (a & 0x1FFFFFFF)
577
578#define PHY_Enable_Auto_Nego            0x1000
579#define PHY_Restart_Auto_Nego           0x0200
580
581/* PHY_STAT_REG = 1; */
582#define PHY_Auto_Neco_Comp      0x0020
583#define PHY_Link_Status         0x0004
584
585/* PHY_AUTO_NEGO_REG = 4; */
586#define PHY_Cap_10_Half  0x0020
587#define PHY_Cap_10_Full  0x0040
588#define PHY_Cap_100_Half 0x0080
589#define PHY_Cap_100_Full 0x0100
590
591/* proc definition */
592
593#define CDMA_OQ_STA     (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
594#define GDMA1_OQ_STA    (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
595#define PPE_OQ_STA      (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
596#define PSE_IQ_STA      (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
597
598#define PROCREG_CONTROL_FILE      "/var/run/procreg_control"
599#if defined (CONFIG_RALINK_RT2880)
600#define PROCREG_DIR             "rt2880"
601#elif defined (CONFIG_RALINK_RT3052)
602#define PROCREG_DIR             "rt3052"
603#elif defined (CONFIG_RALINK_RT3352)
604#define PROCREG_DIR             "rt3352"
605#elif defined (CONFIG_RALINK_RT5350)
606#define PROCREG_DIR             "rt5350"
607#elif defined (CONFIG_RALINK_RT2883)
608#define PROCREG_DIR             "rt2883"
609#elif defined (CONFIG_RALINK_RT3883)
610#define PROCREG_DIR             "rt3883"
611#else
612#define PROCREG_DIR             "rt2880"
613#endif
614#define PROCREG_GMAC            "gmac"
615#define PROCREG_CP0             "cp0"
616#define PROCREG_RAQOS           "qos"
617#define PROCREG_READ_VAL        "regread_value"
618#define PROCREG_WRITE_VAL       "regwrite_value"
619#define PROCREG_ADDR            "reg_addr"
620#define PROCREG_CTL             "procreg_control"
621#define PROCREG_RXDONE_INTR     "rxdone_intr_count"
622#define PROCREG_ESW_INTR        "esw_intr_count"
623#define PROCREG_SNMP            "snmp"
624
625struct rt2880_reg_op_data {
626  char  name[64];
627  unsigned int reg_addr;
628  unsigned int op;
629  unsigned int reg_value;
630};       
631
632typedef struct MACInfo_s
633{
634        int ivec;       /* interrupt vector */
635        unsigned char   macaddr[6];
636} MAC_INFO;
637
638typedef struct end_device
639{
640    struct net_device      *mac_dev;
641    struct napi_struct mac_napi;
642    unsigned int        ppeEbl;
643    int                 enetUnit;       /* enet unit number */
644    int                 isLAN;          /* 0-->WAN; 1-->LAN */
645    int                 isRequestedUp;  /* desired state of UP & RUNNING */
646
647    unsigned int        tx_cpu_owner_idx0;
648    unsigned int        rx_cpu_owner_idx0;
649    unsigned int        fe_int_status;
650#if defined (CONFIG_RAETH_QOS)
651    unsigned int        tx0_full, tx1_full, tx2_full, tx3_full, tx_full;
652    unsigned int        phy_tx_ring0, phy_tx_ring1, phy_tx_ring2, phy_tx_ring3;
653#else
654    unsigned int        tx_full;
655    unsigned int        phy_tx_ring0;
656#endif
657
658    unsigned int        phy_rx_ring0, phy_rx_ring1;
659
660#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
661    //send signal to user application to notify link status changed
662    struct work_struct  kill_sig_wq;
663#endif
664
665#ifdef WORKQUEUE_BH
666    struct work_struct  rx_wq;
667    struct work_struct  tx_wq;
668#else
669    struct              tasklet_struct     rx_tasklet;
670    struct              tasklet_struct     tx_tasklet;
671#endif // WORKQUEUE_BH //
672
673#if defined(CONFIG_RAETH_QOS)
674    struct              sk_buff *          skb_free[NUM_TX_RINGS][NUM_TX_DESC];
675    unsigned int        free_idx[NUM_TX_RINGS];
676#else
677    struct              sk_buff*           skb_free[NUM_TX_DESC];
678    unsigned int        free_idx;
679#endif
680
681    struct              MACInfo_s          *MACInfo;
682    struct              net_device_stats stat;  /* The new statistics table. */
683    spinlock_t          page_lock;              /* Page register locks */
684    struct PDMA_txdesc *tx_ring0;
685#if defined(CONFIG_RAETH_QOS)
686    struct PDMA_txdesc *tx_ring1;
687    struct PDMA_txdesc *tx_ring2;
688    struct PDMA_txdesc *tx_ring3;
689#endif
690    struct PDMA_rxdesc *rx_ring0;
691    struct sk_buff     *netrx0_skbuf[NUM_RX_DESC];
692#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
693    struct PDMA_rxdesc *rx_ring1;
694    struct sk_buff     *netrx1_skbuf[NUM_RX_DESC];
695#endif
696
697#ifdef CONFIG_RAETH_NAPI
698    atomic_t irq_sem;
699#endif
700#ifdef CONFIG_PSEUDO_SUPPORT
701    struct net_device *PseudoDev;
702    unsigned int isPseudo;
703#endif
704#if defined (CONFIG_ETHTOOL)
705        struct mii_if_info      mii_info;
706#endif
707} END_DEVICE, *pEND_DEVICE;
708
709#define RAETH_VERSION   "v2.0"
710
711#endif
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