| 1 | #ifndef RA2882ETHREG_H |
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| 2 | #define RA2882ETHREG_H |
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| 3 | |
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| 4 | #include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h |
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| 5 | #include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */ |
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| 6 | #include <linux/interrupt.h> /* check linux version for 2.4 and 2.6 compatibility */ |
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| 7 | |
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| 8 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) |
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| 9 | #include <asm/rt2880/rt_mmap.h> |
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| 10 | #endif |
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| 11 | #include "raether.h" |
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| 12 | |
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| 13 | #ifdef WORKQUEUE_BH |
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| 14 | #include <linux/workqueue.h> |
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| 15 | #endif // WORKQUEUE_BH // |
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| 16 | |
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| 17 | #define MAX_PACKET_SIZE 1514 |
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| 18 | #define MIN_PACKET_SIZE 60 |
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| 19 | |
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| 20 | #define phys_to_bus(a) (a & 0x1FFFFFFF) |
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| 21 | |
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| 22 | #define BIT(x) ((1 << x)) |
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| 23 | #define ETHER_ADDR_LEN 6 |
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| 24 | |
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| 25 | /* Phy Vender ID list */ |
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| 26 | |
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| 27 | #define EV_MARVELL_PHY_ID0 0x0141 |
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| 28 | #define EV_MARVELL_PHY_ID1 0x0CC2 |
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| 29 | #define EV_VTSS_PHY_ID0 0x0007 |
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| 30 | #define EV_VTSS_PHY_ID1 0x0421 |
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| 31 | |
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| 32 | /* |
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| 33 | FE_INT_STATUS |
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| 34 | */ |
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| 35 | #if defined (CONFIG_RALINK_RT5350) |
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| 36 | |
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| 37 | #define RX_COHERENT BIT(31) |
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| 38 | #define RX_DLY_INT BIT(30) |
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| 39 | #define TX_COHERENT BIT(29) |
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| 40 | #define TX_DLY_INT BIT(28) |
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| 41 | |
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| 42 | #define RX_DONE_INT1 BIT(17) |
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| 43 | #define RX_DONE_INT0 BIT(16) |
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| 44 | |
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| 45 | #define TX_DONE_INT3 BIT(3) |
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| 46 | #define TX_DONE_INT2 BIT(2) |
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| 47 | #define TX_DONE_INT1 BIT(1) |
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| 48 | #define TX_DONE_INT0 BIT(0) |
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| 49 | #else |
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| 50 | //#define CNT_PPE_AF BIT(31) |
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| 51 | //#define CNT_GDM_AF BIT(29) |
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| 52 | #define PSE_P2_FC BIT(26) |
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| 53 | #define GDM_CRC_DROP BIT(25) |
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| 54 | #define PSE_BUF_DROP BIT(24) |
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| 55 | #define GDM_OTHER_DROP BIT(23) |
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| 56 | #define PSE_P1_FC BIT(22) |
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| 57 | #define PSE_P0_FC BIT(21) |
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| 58 | #define PSE_FQ_EMPTY BIT(20) |
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| 59 | #define GE1_STA_CHG BIT(18) |
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| 60 | #define TX_COHERENT BIT(17) |
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| 61 | #define RX_COHERENT BIT(16) |
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| 62 | |
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| 63 | #define TX_DONE_INT3 BIT(11) |
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| 64 | #define TX_DONE_INT2 BIT(10) |
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| 65 | #define TX_DONE_INT1 BIT(9) |
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| 66 | #define TX_DONE_INT0 BIT(8) |
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| 67 | #define RX_DONE_INT1 RX_DONE_INT0 |
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| 68 | #define RX_DONE_INT0 BIT(2) |
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| 69 | #define TX_DLY_INT BIT(1) |
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| 70 | #define RX_DLY_INT BIT(0) |
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| 71 | #endif |
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| 72 | |
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| 73 | #define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \ |
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| 74 | TX_DONE_INT1 | TX_DONE_INT0 | \ |
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| 75 | RX_DONE_INT0 ) |
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| 76 | /* |
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| 77 | * SW_INT_STATUS |
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| 78 | */ |
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| 79 | #if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) |
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| 80 | #define PORT0_QUEUE_FULL BIT(14) //port0 queue full |
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| 81 | #define PORT1_QUEUE_FULL BIT(15) //port1 queue full |
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| 82 | #define PORT2_QUEUE_FULL BIT(16) //port2 queue full |
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| 83 | #define PORT3_QUEUE_FULL BIT(17) //port3 queue full |
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| 84 | #define PORT4_QUEUE_FULL BIT(18) //port4 queue full |
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| 85 | #define PORT5_QUEUE_FULL BIT(19) //port5 queue full |
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| 86 | #define PORT6_QUEUE_FULL BIT(20) //port6 queue full |
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| 87 | #define SHARED_QUEUE_FULL BIT(23) //shared queue full |
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| 88 | #define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped |
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| 89 | #define BC_STROM BIT(25) //the device is undergoing broadcast storm |
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| 90 | #define PORT_ST_CHG BIT(26) //Port status change |
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| 91 | #define UNSECURED_ALERT BIT(27) //Intruder alert |
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| 92 | #define ABNORMAL_ALERT BIT(28) //Abnormal |
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| 93 | |
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| 94 | #define ESW_INT_ALL (PORT_ST_CHG) |
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| 95 | |
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| 96 | #endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 // |
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| 97 | |
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| 98 | #define RX_BUF_ALLOC_SIZE 2000 |
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| 99 | #define FASTPATH_HEADROOM 64 |
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| 100 | |
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| 101 | #define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line |
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| 102 | |
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| 103 | #define ETHER_ALIGNED_RX_SKB_ADDR(addr) \ |
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| 104 | ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \ |
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| 105 | ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr)) |
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| 106 | |
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| 107 | #ifdef CONFIG_PSEUDO_SUPPORT |
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| 108 | typedef struct _PSEUDO_ADAPTER { |
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| 109 | struct net_device *RaethDev; |
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| 110 | struct net_device *PseudoDev; |
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| 111 | struct net_device_stats stat; |
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| 112 | #if defined (CONFIG_ETHTOOL) |
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| 113 | struct mii_if_info mii_info; |
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| 114 | #endif |
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| 115 | |
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| 116 | } PSEUDO_ADAPTER, PPSEUDO_ADAPTER; |
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| 117 | |
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| 118 | #define MAX_PSEUDO_ENTRY 1 |
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| 119 | #endif |
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| 120 | |
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| 121 | |
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| 122 | |
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| 123 | /* Register Categories Definition */ |
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| 124 | #define RAFRAMEENGINE_OFFSET 0x0000 |
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| 125 | #define RAGDMA_OFFSET 0x0020 |
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| 126 | #define RAPSE_OFFSET 0x0040 |
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| 127 | #define RAGDMA2_OFFSET 0x0060 |
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| 128 | #define RACDMA_OFFSET 0x0080 |
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| 129 | #if defined (CONFIG_RALINK_RT5350) |
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| 130 | #define RAPDMA_OFFSET 0x0800 |
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| 131 | #define SDM_OFFSET 0x0C00 |
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| 132 | #else |
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| 133 | #define RAPDMA_OFFSET 0x0100 |
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| 134 | #endif |
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| 135 | #define RAPPE_OFFSET 0x0200 |
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| 136 | #define RACMTABLE_OFFSET 0x0400 |
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| 137 | #define RAPOLICYTABLE_OFFSET 0x1000 |
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| 138 | |
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| 139 | |
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| 140 | /* Register Map Detail */ |
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| 141 | /* RT3883 */ |
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| 142 | #define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14) |
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| 143 | |
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| 144 | #if defined (CONFIG_RALINK_RT5350) |
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| 145 | |
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| 146 | /* 1. PDMA */ |
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| 147 | #define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000) |
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| 148 | #define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004) |
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| 149 | #define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008) |
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| 150 | #define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C) |
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| 151 | |
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| 152 | #define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010) |
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| 153 | #define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014) |
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| 154 | #define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018) |
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| 155 | #define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C) |
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| 156 | |
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| 157 | #define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020) |
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| 158 | #define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024) |
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| 159 | #define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028) |
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| 160 | #define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C) |
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| 161 | |
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| 162 | #define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030) |
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| 163 | #define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034) |
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| 164 | #define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038) |
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| 165 | #define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C) |
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| 166 | |
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| 167 | #define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100) |
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| 168 | #define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104) |
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| 169 | #define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108) |
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| 170 | #define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C) |
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| 171 | |
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| 172 | #define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110) |
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| 173 | #define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114) |
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| 174 | #define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118) |
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| 175 | #define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C) |
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| 176 | |
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| 177 | #define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200) |
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| 178 | #define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204) |
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| 179 | #define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208) |
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| 180 | #define PDMA_RST_CFG (PDMA_RST_IDX) |
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| 181 | #define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C) |
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| 182 | #define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210) |
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| 183 | #define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220) |
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| 184 | #define FE_INT_STATUS (INT_STATUS) |
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| 185 | #define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228) |
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| 186 | #define FE_INT_ENABLE (INT_MASK) |
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| 187 | #define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280) |
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| 188 | #define PDMA_SCH_CFG (PDMA_WRR) |
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| 189 | |
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| 190 | #define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration |
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| 191 | #define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring |
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| 192 | #define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring |
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| 193 | #define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB |
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| 194 | #define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB |
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| 195 | #define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count |
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| 196 | #define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count |
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| 197 | #define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count |
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| 198 | #define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count |
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| 199 | #define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count |
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| 200 | |
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| 201 | #else |
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| 202 | |
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| 203 | /* 1. Frame Engine Global Registers */ |
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| 204 | #define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00) |
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| 205 | #define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04) |
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| 206 | #define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) |
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| 207 | #define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08) |
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| 208 | #define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C) |
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| 209 | #define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10) |
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| 210 | #define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14) |
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| 211 | #define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA |
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| 212 | #define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C) |
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| 213 | |
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| 214 | |
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| 215 | /* 2. GDMA Registers */ |
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| 216 | #define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00) |
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| 217 | #define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04) |
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| 218 | #define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08) |
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| 219 | #define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C) |
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| 220 | #define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10) |
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| 221 | |
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| 222 | #define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00) |
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| 223 | #define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04) |
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| 224 | #define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08) |
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| 225 | #define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C) |
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| 226 | #define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10) |
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| 227 | |
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| 228 | /* 3. PSE */ |
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| 229 | #define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00) |
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| 230 | #define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04) |
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| 231 | #define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08) |
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| 232 | #define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C) |
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| 233 | #define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0) |
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| 234 | |
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| 235 | /* 4. CDMA */ |
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| 236 | #define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00) |
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| 237 | #define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04) |
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| 238 | /* skip ppoe sid and vlan id definition */ |
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| 239 | |
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| 240 | |
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| 241 | /* 5. PDMA */ |
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| 242 | #define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00) |
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| 243 | #define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04) |
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| 244 | #define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08) |
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| 245 | |
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| 246 | #define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C) |
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| 247 | |
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| 248 | #define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10) |
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| 249 | #define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14) |
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| 250 | #define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18) |
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| 251 | #define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C) |
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| 252 | |
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| 253 | #define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20) |
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| 254 | #define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24) |
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| 255 | #define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28) |
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| 256 | #define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C) |
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| 257 | |
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| 258 | #define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40) |
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| 259 | #define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44) |
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| 260 | #define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48) |
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| 261 | #define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C) |
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| 262 | |
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| 263 | #define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50) |
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| 264 | #define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54) |
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| 265 | #define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58) |
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| 266 | #define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C) |
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| 267 | |
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| 268 | #define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30) |
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| 269 | #define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34) |
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| 270 | #define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38) |
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| 271 | #define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C) |
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| 272 | |
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| 273 | #define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40) |
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| 274 | #define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44) |
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| 275 | #define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48) |
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| 276 | #define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C) |
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| 277 | |
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| 278 | #endif |
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| 279 | |
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| 280 | #define DELAY_INT_INIT 0x84048404 |
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| 281 | #define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT) |
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| 282 | |
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| 283 | |
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| 284 | #if !defined (CONFIG_RALINK_RT5350) |
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| 285 | |
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| 286 | /* 6. Counter and Meter Table */ |
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| 287 | #define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */ |
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| 288 | #define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */ |
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| 289 | /* 0 ~ 63 */ |
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| 290 | |
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| 291 | #define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */ |
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| 292 | /* skip... */ |
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| 293 | #define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC) |
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| 294 | |
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| 295 | #define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */ |
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| 296 | #define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */ |
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| 297 | #define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */ |
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| 298 | #define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */ |
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| 299 | |
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| 300 | /* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */ |
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| 301 | #define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320) |
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| 302 | #define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324) |
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| 303 | #define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328) |
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| 304 | #define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C) |
|---|
| 305 | #define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330) |
|---|
| 306 | #define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334) |
|---|
| 307 | #define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338) |
|---|
| 308 | #define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C) |
|---|
| 309 | |
|---|
| 310 | #endif |
|---|
| 311 | |
|---|
| 312 | |
|---|
| 313 | /* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */ |
|---|
| 314 | #define PORT0_PKCOUNT (0xb01100e8) |
|---|
| 315 | #define PORT1_PKCOUNT (0xb01100ec) |
|---|
| 316 | #define PORT2_PKCOUNT (0xb01100f0) |
|---|
| 317 | #define PORT3_PKCOUNT (0xb01100f4) |
|---|
| 318 | #define PORT4_PKCOUNT (0xb01100f8) |
|---|
| 319 | #define PORT5_PKCOUNT (0xb01100fc) |
|---|
| 320 | |
|---|
| 321 | |
|---|
| 322 | // PHYS_TO_K1 |
|---|
| 323 | #define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr) |
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| 324 | |
|---|
| 325 | |
|---|
| 326 | #define sysRegRead(phys) \ |
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| 327 | (*(volatile unsigned int *)PHYS_TO_K1(phys)) |
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| 328 | |
|---|
| 329 | #define sysRegWrite(phys, val) \ |
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| 330 | ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val)) |
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| 331 | |
|---|
| 332 | #define u_long unsigned long |
|---|
| 333 | #define u32 unsigned int |
|---|
| 334 | #define u16 unsigned short |
|---|
| 335 | |
|---|
| 336 | |
|---|
| 337 | /* ====================================== */ |
|---|
| 338 | #define GDM1_DISPAD BIT(18) |
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| 339 | #define GDM1_DISCRC BIT(17) |
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| 340 | |
|---|
| 341 | //GDMA1 uni-cast frames destination port |
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| 342 | #define GDM1_ICS_EN (0x1 << 22) |
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| 343 | #define GDM1_TCS_EN (0x1 << 21) |
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| 344 | #define GDM1_UCS_EN (0x1 << 20) |
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| 345 | #define GDM1_JMB_EN (0x1 << 19) |
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| 346 | #define GDM1_STRPCRC (0x1 << 16) |
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| 347 | #define GDM1_UFRC_P_CPU (0 << 12) |
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| 348 | #define GDM1_UFRC_P_GDMA1 (1 << 12) |
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| 349 | #define GDM1_UFRC_P_PPE (6 << 12) |
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| 350 | |
|---|
| 351 | //GDMA1 broad-cast MAC address frames |
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| 352 | #define GDM1_BFRC_P_CPU (0 << 8) |
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| 353 | #define GDM1_BFRC_P_GDMA1 (1 << 8) |
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| 354 | #define GDM1_BFRC_P_PPE (6 << 8) |
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| 355 | |
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| 356 | //GDMA1 multi-cast MAC address frames |
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| 357 | #define GDM1_MFRC_P_CPU (0 << 4) |
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| 358 | #define GDM1_MFRC_P_GDMA1 (1 << 4) |
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| 359 | #define GDM1_MFRC_P_PPE (6 << 4) |
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| 360 | |
|---|
| 361 | //GDMA1 other MAC address frames destination port |
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| 362 | #define GDM1_OFRC_P_CPU (0 << 0) |
|---|
| 363 | #define GDM1_OFRC_P_GDMA1 (1 << 0) |
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| 364 | #define GDM1_OFRC_P_PPE (6 << 0) |
|---|
| 365 | |
|---|
| 366 | #define ICS_GEN_EN (1 << 2) |
|---|
| 367 | #define UCS_GEN_EN (1 << 1) |
|---|
| 368 | #define TCS_GEN_EN (1 << 0) |
|---|
| 369 | |
|---|
| 370 | // MDIO_CFG bit |
|---|
| 371 | #define MDIO_CFG_GP1_FC_TX (1 << 11) |
|---|
| 372 | #define MDIO_CFG_GP1_FC_RX (1 << 10) |
|---|
| 373 | |
|---|
| 374 | /* ====================================== */ |
|---|
| 375 | /* ====================================== */ |
|---|
| 376 | #define GP1_LNK_DWN BIT(9) |
|---|
| 377 | #define GP1_AN_FAIL BIT(8) |
|---|
| 378 | /* ====================================== */ |
|---|
| 379 | /* ====================================== */ |
|---|
| 380 | #define PSE_RESET BIT(0) |
|---|
| 381 | /* ====================================== */ |
|---|
| 382 | #define PST_DRX_IDX1 BIT(17) |
|---|
| 383 | #define PST_DRX_IDX0 BIT(16) |
|---|
| 384 | #define PST_DTX_IDX3 BIT(3) |
|---|
| 385 | #define PST_DTX_IDX2 BIT(2) |
|---|
| 386 | #define PST_DTX_IDX1 BIT(1) |
|---|
| 387 | #define PST_DTX_IDX0 BIT(0) |
|---|
| 388 | |
|---|
| 389 | #define TX_WB_DDONE BIT(6) |
|---|
| 390 | #define RX_DMA_BUSY BIT(3) |
|---|
| 391 | #define TX_DMA_BUSY BIT(1) |
|---|
| 392 | #define RX_DMA_EN BIT(2) |
|---|
| 393 | #define TX_DMA_EN BIT(0) |
|---|
| 394 | |
|---|
| 395 | #define PDMA_BT_SIZE_4DWORDS (0<<4) |
|---|
| 396 | #define PDMA_BT_SIZE_8DWORDS (1<<4) |
|---|
| 397 | #define PDMA_BT_SIZE_16DWORDS (2<<4) |
|---|
| 398 | |
|---|
| 399 | /* Register bits. |
|---|
| 400 | */ |
|---|
| 401 | |
|---|
| 402 | #define MACCFG_RXEN (1<<2) |
|---|
| 403 | #define MACCFG_TXEN (1<<3) |
|---|
| 404 | #define MACCFG_PROMISC (1<<18) |
|---|
| 405 | #define MACCFG_RXMCAST (1<<19) |
|---|
| 406 | #define MACCFG_FDUPLEX (1<<20) |
|---|
| 407 | #define MACCFG_PORTSEL (1<<27) |
|---|
| 408 | #define MACCFG_HBEATDIS (1<<28) |
|---|
| 409 | |
|---|
| 410 | |
|---|
| 411 | #define DMACTL_SR (1<<1) /* Start/Stop Receive */ |
|---|
| 412 | #define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */ |
|---|
| 413 | |
|---|
| 414 | #define DMACFG_SWR (1<<0) /* Software Reset */ |
|---|
| 415 | #define DMACFG_BURST32 (32<<8) |
|---|
| 416 | |
|---|
| 417 | #define DMASTAT_TS 0x00700000 /* Transmit Process State */ |
|---|
| 418 | #define DMASTAT_RS 0x000e0000 /* Receive Process State */ |
|---|
| 419 | |
|---|
| 420 | #define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL) |
|---|
| 421 | |
|---|
| 422 | |
|---|
| 423 | |
|---|
| 424 | /* Descriptor bits. |
|---|
| 425 | */ |
|---|
| 426 | #define R_OWN 0x80000000 /* Own Bit */ |
|---|
| 427 | #define RD_RER 0x02000000 /* Receive End Of Ring */ |
|---|
| 428 | #define RD_LS 0x00000100 /* Last Descriptor */ |
|---|
| 429 | #define RD_ES 0x00008000 /* Error Summary */ |
|---|
| 430 | #define RD_CHAIN 0x01000000 /* Chained */ |
|---|
| 431 | |
|---|
| 432 | /* Word 0 */ |
|---|
| 433 | #define T_OWN 0x80000000 /* Own Bit */ |
|---|
| 434 | #define TD_ES 0x00008000 /* Error Summary */ |
|---|
| 435 | |
|---|
| 436 | /* Word 1 */ |
|---|
| 437 | #define TD_LS 0x40000000 /* Last Segment */ |
|---|
| 438 | #define TD_FS 0x20000000 /* First Segment */ |
|---|
| 439 | #define TD_TER 0x08000000 /* Transmit End Of Ring */ |
|---|
| 440 | #define TD_CHAIN 0x01000000 /* Chained */ |
|---|
| 441 | |
|---|
| 442 | |
|---|
| 443 | #define TD_SET 0x08000000 /* Setup Packet */ |
|---|
| 444 | |
|---|
| 445 | |
|---|
| 446 | #define POLL_DEMAND 1 |
|---|
| 447 | |
|---|
| 448 | #define RSTCTL (0x34) |
|---|
| 449 | #define RSTCTL_RSTENET1 (1<<19) |
|---|
| 450 | #define RSTCTL_RSTENET2 (1<<20) |
|---|
| 451 | |
|---|
| 452 | #define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000 |
|---|
| 453 | #define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000 |
|---|
| 454 | #define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01 |
|---|
| 455 | #define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01 |
|---|
| 456 | |
|---|
| 457 | // Define Whole FE Reset Register |
|---|
| 458 | #define RSTCTRL (RALINK_SYSCTL_BASE + 0x34) |
|---|
| 459 | |
|---|
| 460 | /*========================================= |
|---|
| 461 | PDMA RX Descriptor Format define |
|---|
| 462 | =========================================*/ |
|---|
| 463 | |
|---|
| 464 | //------------------------------------------------- |
|---|
| 465 | typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T; |
|---|
| 466 | |
|---|
| 467 | struct _PDMA_RXD_INFO1_ |
|---|
| 468 | { |
|---|
| 469 | unsigned int PDP0; |
|---|
| 470 | }; |
|---|
| 471 | //------------------------------------------------- |
|---|
| 472 | typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T; |
|---|
| 473 | |
|---|
| 474 | struct _PDMA_RXD_INFO2_ |
|---|
| 475 | { |
|---|
| 476 | unsigned int PLEN1 : 14; |
|---|
| 477 | unsigned int LS1 : 1; |
|---|
| 478 | unsigned int UN_USED : 1; |
|---|
| 479 | unsigned int PLEN0 : 14; |
|---|
| 480 | unsigned int LS0 : 1; |
|---|
| 481 | unsigned int DDONE_bit : 1; |
|---|
| 482 | }; |
|---|
| 483 | //------------------------------------------------- |
|---|
| 484 | typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T; |
|---|
| 485 | |
|---|
| 486 | struct _PDMA_RXD_INFO3_ |
|---|
| 487 | { |
|---|
| 488 | unsigned int UN_USE1; |
|---|
| 489 | }; |
|---|
| 490 | //------------------------------------------------- |
|---|
| 491 | typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T; |
|---|
| 492 | |
|---|
| 493 | struct _PDMA_RXD_INFO4_ |
|---|
| 494 | { |
|---|
| 495 | |
|---|
| 496 | unsigned int FOE_Entry : 14; |
|---|
| 497 | unsigned int FVLD : 1; |
|---|
| 498 | unsigned int UN_USE1 : 1; |
|---|
| 499 | unsigned int AI : 8; |
|---|
| 500 | unsigned int SP : 3; |
|---|
| 501 | unsigned int AIS : 1; |
|---|
| 502 | unsigned int L4F : 1; |
|---|
| 503 | unsigned int IPF : 1; |
|---|
| 504 | unsigned int L4FVLD_bit : 1; |
|---|
| 505 | unsigned int IPFVLD_bit : 1; |
|---|
| 506 | }; |
|---|
| 507 | |
|---|
| 508 | |
|---|
| 509 | struct PDMA_rxdesc { |
|---|
| 510 | PDMA_RXD_INFO1_T rxd_info1; |
|---|
| 511 | PDMA_RXD_INFO2_T rxd_info2; |
|---|
| 512 | PDMA_RXD_INFO3_T rxd_info3; |
|---|
| 513 | PDMA_RXD_INFO4_T rxd_info4; |
|---|
| 514 | }; |
|---|
| 515 | |
|---|
| 516 | /*========================================= |
|---|
| 517 | PDMA TX Descriptor Format define |
|---|
| 518 | =========================================*/ |
|---|
| 519 | //------------------------------------------------- |
|---|
| 520 | typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T; |
|---|
| 521 | |
|---|
| 522 | struct _PDMA_TXD_INFO1_ |
|---|
| 523 | { |
|---|
| 524 | unsigned int SDP0; |
|---|
| 525 | }; |
|---|
| 526 | //------------------------------------------------- |
|---|
| 527 | typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T; |
|---|
| 528 | |
|---|
| 529 | struct _PDMA_TXD_INFO2_ |
|---|
| 530 | { |
|---|
| 531 | unsigned int SDL1 : 14; |
|---|
| 532 | unsigned int LS1_bit : 1; |
|---|
| 533 | unsigned int BURST_bit : 1; |
|---|
| 534 | unsigned int SDL0 : 14; |
|---|
| 535 | unsigned int LS0_bit : 1; |
|---|
| 536 | unsigned int DDONE_bit : 1; |
|---|
| 537 | }; |
|---|
| 538 | //------------------------------------------------- |
|---|
| 539 | typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T; |
|---|
| 540 | |
|---|
| 541 | struct _PDMA_TXD_INFO3_ |
|---|
| 542 | { |
|---|
| 543 | unsigned int SDP1; |
|---|
| 544 | }; |
|---|
| 545 | //------------------------------------------------- |
|---|
| 546 | typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T; |
|---|
| 547 | |
|---|
| 548 | struct _PDMA_TXD_INFO4_ |
|---|
| 549 | { |
|---|
| 550 | |
|---|
| 551 | unsigned int VIDX : 4; |
|---|
| 552 | unsigned int VPRI : 3; |
|---|
| 553 | unsigned int INSV : 1; |
|---|
| 554 | unsigned int SIDX : 4; |
|---|
| 555 | unsigned int INSP : 1; |
|---|
| 556 | unsigned int RESV : 1; |
|---|
| 557 | unsigned int UN_USE3 : 2; |
|---|
| 558 | unsigned int QN : 3; |
|---|
| 559 | unsigned int UN_USE2 : 1; |
|---|
| 560 | unsigned int UDF : 4; |
|---|
| 561 | unsigned int PN : 3; |
|---|
| 562 | unsigned int UN_USE1 : 2; |
|---|
| 563 | unsigned int TCO : 1; |
|---|
| 564 | unsigned int UCO : 1; |
|---|
| 565 | unsigned int ICO : 1; |
|---|
| 566 | }; |
|---|
| 567 | |
|---|
| 568 | |
|---|
| 569 | struct PDMA_txdesc { |
|---|
| 570 | PDMA_TXD_INFO1_T txd_info1; |
|---|
| 571 | PDMA_TXD_INFO2_T txd_info2; |
|---|
| 572 | PDMA_TXD_INFO3_T txd_info3; |
|---|
| 573 | PDMA_TXD_INFO4_T txd_info4; |
|---|
| 574 | }; |
|---|
| 575 | |
|---|
| 576 | #define phys_to_bus(a) (a & 0x1FFFFFFF) |
|---|
| 577 | |
|---|
| 578 | #define PHY_Enable_Auto_Nego 0x1000 |
|---|
| 579 | #define PHY_Restart_Auto_Nego 0x0200 |
|---|
| 580 | |
|---|
| 581 | /* PHY_STAT_REG = 1; */ |
|---|
| 582 | #define PHY_Auto_Neco_Comp 0x0020 |
|---|
| 583 | #define PHY_Link_Status 0x0004 |
|---|
| 584 | |
|---|
| 585 | /* PHY_AUTO_NEGO_REG = 4; */ |
|---|
| 586 | #define PHY_Cap_10_Half 0x0020 |
|---|
| 587 | #define PHY_Cap_10_Full 0x0040 |
|---|
| 588 | #define PHY_Cap_100_Half 0x0080 |
|---|
| 589 | #define PHY_Cap_100_Full 0x0100 |
|---|
| 590 | |
|---|
| 591 | /* proc definition */ |
|---|
| 592 | |
|---|
| 593 | #define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c) |
|---|
| 594 | #define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50) |
|---|
| 595 | #define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54) |
|---|
| 596 | #define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58) |
|---|
| 597 | |
|---|
| 598 | #define PROCREG_CONTROL_FILE "/var/run/procreg_control" |
|---|
| 599 | #if defined (CONFIG_RALINK_RT2880) |
|---|
| 600 | #define PROCREG_DIR "rt2880" |
|---|
| 601 | #elif defined (CONFIG_RALINK_RT3052) |
|---|
| 602 | #define PROCREG_DIR "rt3052" |
|---|
| 603 | #elif defined (CONFIG_RALINK_RT3352) |
|---|
| 604 | #define PROCREG_DIR "rt3352" |
|---|
| 605 | #elif defined (CONFIG_RALINK_RT5350) |
|---|
| 606 | #define PROCREG_DIR "rt5350" |
|---|
| 607 | #elif defined (CONFIG_RALINK_RT2883) |
|---|
| 608 | #define PROCREG_DIR "rt2883" |
|---|
| 609 | #elif defined (CONFIG_RALINK_RT3883) |
|---|
| 610 | #define PROCREG_DIR "rt3883" |
|---|
| 611 | #else |
|---|
| 612 | #define PROCREG_DIR "rt2880" |
|---|
| 613 | #endif |
|---|
| 614 | #define PROCREG_GMAC "gmac" |
|---|
| 615 | #define PROCREG_CP0 "cp0" |
|---|
| 616 | #define PROCREG_RAQOS "qos" |
|---|
| 617 | #define PROCREG_READ_VAL "regread_value" |
|---|
| 618 | #define PROCREG_WRITE_VAL "regwrite_value" |
|---|
| 619 | #define PROCREG_ADDR "reg_addr" |
|---|
| 620 | #define PROCREG_CTL "procreg_control" |
|---|
| 621 | #define PROCREG_RXDONE_INTR "rxdone_intr_count" |
|---|
| 622 | #define PROCREG_ESW_INTR "esw_intr_count" |
|---|
| 623 | #define PROCREG_SNMP "snmp" |
|---|
| 624 | |
|---|
| 625 | struct rt2880_reg_op_data { |
|---|
| 626 | char name[64]; |
|---|
| 627 | unsigned int reg_addr; |
|---|
| 628 | unsigned int op; |
|---|
| 629 | unsigned int reg_value; |
|---|
| 630 | }; |
|---|
| 631 | |
|---|
| 632 | typedef struct MACInfo_s |
|---|
| 633 | { |
|---|
| 634 | int ivec; /* interrupt vector */ |
|---|
| 635 | unsigned char macaddr[6]; |
|---|
| 636 | } MAC_INFO; |
|---|
| 637 | |
|---|
| 638 | typedef struct end_device |
|---|
| 639 | { |
|---|
| 640 | struct net_device *mac_dev; |
|---|
| 641 | unsigned int ppeEbl; |
|---|
| 642 | int enetUnit; /* enet unit number */ |
|---|
| 643 | int isLAN; /* 0-->WAN; 1-->LAN */ |
|---|
| 644 | int isRequestedUp; /* desired state of UP & RUNNING */ |
|---|
| 645 | |
|---|
| 646 | unsigned int tx_cpu_owner_idx0; |
|---|
| 647 | unsigned int rx_cpu_owner_idx0; |
|---|
| 648 | unsigned int fe_int_status; |
|---|
| 649 | #if defined (CONFIG_RAETH_QOS) |
|---|
| 650 | unsigned int tx0_full, tx1_full, tx2_full, tx3_full, tx_full; |
|---|
| 651 | unsigned int phy_tx_ring0, phy_tx_ring1, phy_tx_ring2, phy_tx_ring3; |
|---|
| 652 | #else |
|---|
| 653 | unsigned int tx_full; |
|---|
| 654 | unsigned int phy_tx_ring0; |
|---|
| 655 | #endif |
|---|
| 656 | |
|---|
| 657 | unsigned int phy_rx_ring0, phy_rx_ring1; |
|---|
| 658 | |
|---|
| 659 | #if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) |
|---|
| 660 | //send signal to user application to notify link status changed |
|---|
| 661 | struct work_struct kill_sig_wq; |
|---|
| 662 | #endif |
|---|
| 663 | |
|---|
| 664 | #ifdef WORKQUEUE_BH |
|---|
| 665 | struct work_struct rx_wq; |
|---|
| 666 | struct work_struct tx_wq; |
|---|
| 667 | #else |
|---|
| 668 | struct tasklet_struct rx_tasklet; |
|---|
| 669 | struct tasklet_struct tx_tasklet; |
|---|
| 670 | #endif // WORKQUEUE_BH // |
|---|
| 671 | |
|---|
| 672 | #if defined(CONFIG_RAETH_QOS) |
|---|
| 673 | struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC]; |
|---|
| 674 | unsigned int free_idx[NUM_TX_RINGS]; |
|---|
| 675 | #else |
|---|
| 676 | struct sk_buff* skb_free[NUM_TX_DESC]; |
|---|
| 677 | unsigned int free_idx; |
|---|
| 678 | #endif |
|---|
| 679 | |
|---|
| 680 | struct MACInfo_s *MACInfo; |
|---|
| 681 | struct net_device_stats stat; /* The new statistics table. */ |
|---|
| 682 | spinlock_t page_lock; /* Page register locks */ |
|---|
| 683 | struct PDMA_txdesc *tx_ring0; |
|---|
| 684 | #if defined(CONFIG_RAETH_QOS) |
|---|
| 685 | struct PDMA_txdesc *tx_ring1; |
|---|
| 686 | struct PDMA_txdesc *tx_ring2; |
|---|
| 687 | struct PDMA_txdesc *tx_ring3; |
|---|
| 688 | #endif |
|---|
| 689 | struct PDMA_rxdesc *rx_ring0; |
|---|
| 690 | struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; |
|---|
| 691 | #if defined (CONFIG_RAETH_MULTIPLE_RX_RING) |
|---|
| 692 | struct PDMA_rxdesc *rx_ring1; |
|---|
| 693 | struct sk_buff *netrx1_skbuf[NUM_RX_DESC]; |
|---|
| 694 | #endif |
|---|
| 695 | |
|---|
| 696 | #ifdef CONFIG_RAETH_NAPI |
|---|
| 697 | atomic_t irq_sem; |
|---|
| 698 | #endif |
|---|
| 699 | #ifdef CONFIG_PSEUDO_SUPPORT |
|---|
| 700 | struct net_device *PseudoDev; |
|---|
| 701 | unsigned int isPseudo; |
|---|
| 702 | #endif |
|---|
| 703 | #if defined (CONFIG_ETHTOOL) |
|---|
| 704 | struct mii_if_info mii_info; |
|---|
| 705 | #endif |
|---|
| 706 | struct napi_struct mac_napi; |
|---|
| 707 | } END_DEVICE, *pEND_DEVICE; |
|---|
| 708 | |
|---|
| 709 | #define RAETH_VERSION "v2.0" |
|---|
| 710 | |
|---|
| 711 | #endif |
|---|
