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source: src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/raether.c @ 18367

Last change on this file since 18367 was 18367, checked in by BrainSlayer, 16 months ago
fix crashbug
File size: 77.5 KB

Line
1	#include <linux/module.h>
2	#include <linux/version.h>
3	#include <linux/kernel.h>
4	#include <linux/types.h>
5	#include <linux/pci.h>
6	#include <linux/init.h>
7	#include <linux/skbuff.h>
8	#include <linux/if_vlan.h>
9	#include <linux/if_ether.h>
10	#include <asm/uaccess.h>
11	#include <asm/rt2880/surfboardint.h>
12	#include <linux/delay.h>
13
14	#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
15	#include <asm/rt2880/rt_mmap.h>
16	#else
17	#include <linux/libata-compat.h>
18	#endif
19
20	#include "ra2882ethreg.h"
21	#include "raether.h"
22	#include "ra_mac.h"
23	#include "ra_ioctl.h"
24	#include "ra_rfrw.h"
25	#ifdef CONFIG_RAETH_NETLINK
26	#include "ra_netlink.h"
27	#endif
28	#if defined (CONFIG_RAETH_QOS)
29	#include "ra_qos.h"
30	#endif
31
32	#if defined (CONFIG_RA_HW_NAT) \|\| defined (CONFIG_RA_HW_NAT_MODULE)
33	#include "../../../net/nat/hw_nat/ra_nat.h"
34	#endif
35
36
37	#ifdef CONFIG_RAETH_NAPI
38	static int raeth_clean(struct napi_struct *napi, int budget);
39	static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do);
40	#else
41	static int rt2880_eth_recv(struct net_device* dev);
42	#endif
43
44	#if !defined(CONFIG_RA_NAT_NONE)
45	/* bruce+
46	*/
47	extern int (ra_sw_nat_hook_rx)(struct sk_buff skb);
48	extern int (ra_sw_nat_hook_tx)(struct sk_buff skb, int gmac_no);
49	#endif
50
51	#if defined(CONFIG_RA_CLASSIFIER)\|\|defined(CONFIG_RA_CLASSIFIER_MODULE)
52	/* Qwert+
53	*/
54	#include <asm/mipsregs.h>
55	extern int (ra_classifier_hook_rx)(struct sk_buff skb, unsigned long cur_cycle);
56	#endif /* CONFIG_RA_CLASSIFIER */
57
58	#if defined (CONFIG_RALINK_RT3052_MP2)
59	int32_t mcast_rx(struct sk_buff * skb);
60	int32_t mcast_tx(struct sk_buff * skb);
61	#endif
62	#define RA_MTD_RW_BY_NUM 1
63	#ifdef RA_MTD_RW_BY_NUM
64	int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
65	#else
66	int ra_mtd_read_nm(char name, loff_t from, size_t len, u_char buf);
67	#endif
68
69	/* gmac driver feature set config */
70	#if defined (CONFIG_RAETH_NAPI) \|\| defined (CONFIG_RAETH_QOS)
71	#undef DELAY_INT
72	#else
73	#define DELAY_INT 1
74	#endif
75
76	/* end of config */
77
78	#ifdef CONFIG_RAETH_JUMBOFRAME
79	#define MAX_RX_LENGTH 4096
80	#else
81	#define MAX_RX_LENGTH 1536
82	#endif
83	struct net_device *dev_raether;
84
85	static int rx_dma_owner_idx;
86	static int rx_dma_owner_idx0; /* Point to the next RXD DMA wants to use in RXD Ring#0. */
87	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
88	static int rx_dma_owner_idx1; /* Point to the next RXD DMA wants to use in RXD Ring#1. */
89	#endif
90
91	static struct PDMA_rxdesc *rx_ring;
92	static unsigned long tx_ring_full=0;
93
94	#if defined (CONFIG_ETHTOOL)
95	#include "ra_ethtool.h"
96	extern struct ethtool_ops ra_ethtool_ops;
97	#ifdef CONFIG_PSEUDO_SUPPORT
98	extern struct ethtool_ops ra_virt_ethtool_ops;
99	#endif // CONFIG_PSEUDO_SUPPORT //
100	#endif // (CONFIG_ETHTOOL //
101
102	#ifdef CONFIG_RALINK_VISTA_BASIC
103	int is_switch_175c = 1;
104	#endif
105	#if 0
106	void skb_dump(struct sk_buff* sk) {
107	unsigned int i;
108
109	printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n",
110	sk->dev?sk->dev->name:"ip stack",sk->len,sk->truesize,
111	skb_headroom(sk),skb_tailroom(sk));
112
113	//for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) {
114	for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) {
115	if((i % 20) == 0)
116	printk("\n");
117	if(i==(unsigned int)sk->data) printk("{");
118	if(i==(unsigned int)sk->h.raw) printk("#");
119	if(i==(unsigned int)sk->nh.raw) printk("\|");
120	if(i==(unsigned int)sk->mac.raw) printk("*");
121	printk("%02x",((unsigned char)i));
122	if(i==(unsigned int)sk->tail) printk("}");
123	}
124	printk("\n");
125	}
126	#endif
127
128	#if defined (CONFIG_GIGAPHY) \|\| defined (CONFIG_P5_MAC_TO_PHY_MODE)
129	int isMarvellGigaPHY(int ge)
130	{
131	u32 phy_id0 = 0, phy_id1 = 0;
132
133	#ifdef CONFIG_GE2_RGMII_AN
134	if (ge == 2) {
135	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
136	printk("\n Read PhyID 1 is Fail!!\n");
137	phy_id0 =0;
138	}
139	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
140	printk("\n Read PhyID 1 is Fail!!\n");
141	phy_id1 = 0;
142	}
143	}
144	else
145	#endif
146	#if defined (CONFIG_GE1_RGMII_AN) \|\| defined (CONFIG_P5_MAC_TO_PHY_MODE)
147	{
148	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
149	printk("\n Read PhyID 0 is Fail!!\n");
150	phy_id0 =0;
151	}
152	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
153	printk("\n Read PhyID 0 is Fail!!\n");
154	phy_id1 = 0;
155	}
156	}
157	#endif
158	;
159	if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1))
160	return 1;
161	return 0;
162	}
163
164	int isMarvellGigaPHY2(int ge)
165	{
166	u32 phy_id0 = 0, phy_id1 = 0;
167
168	#ifdef CONFIG_GE2_RGMII_AN
169	if (ge == 2) {
170	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
171	printk("\n Read PhyID 1 is Fail!!\n");
172	phy_id0 =0;
173	}
174	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
175	printk("\n Read PhyID 1 is Fail!!\n");
176	phy_id1 = 0;
177	}
178	}
179	else
180	#endif
181	#if defined (CONFIG_GE1_RGMII_AN) \|\| defined (CONFIG_P5_MAC_TO_PHY_MODE)
182	{
183	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
184	printk("\n Read PhyID 0 is Fail!!\n");
185	phy_id0 =0;
186	}
187	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
188	printk("\n Read PhyID 0 is Fail!!\n");
189	phy_id1 = 0;
190	}
191	}
192	#endif
193	;
194	if((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_SENAO_ID1))
195	return 1;
196	return 0;
197	}
198
199	int isVtssGigaPHY(int ge)
200	{
201	u32 phy_id0 = 0, phy_id1 = 0;
202
203	#ifdef CONFIG_GE2_RGMII_AN
204	if (ge == 2) {
205	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
206	printk("\n Read PhyID 1 is Fail!!\n");
207	phy_id0 =0;
208	}
209	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
210	printk("\n Read PhyID 1 is Fail!!\n");
211	phy_id1 = 0;
212	}
213	}
214	else
215	#endif
216	#if defined (CONFIG_GE1_RGMII_AN) \|\| defined (CONFIG_P5_MAC_TO_PHY_MODE)
217	{
218	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
219	printk("\n Read PhyID 0 is Fail!!\n");
220	phy_id0 =0;
221	}
222	if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
223	printk("\n Read PhyID 0 is Fail!!\n");
224	phy_id1 = 0;
225	}
226	}
227	#endif
228	;
229	if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1))
230	return 1;
231	return 0;
232	}
233	#endif
234
235	/*
236	* Set the hardware MAC address.
237	*/
238	static int ei_set_mac_addr(struct net_device dev, void p)
239	{
240	END_DEVICE *ei_local=netdev_priv(dev);
241	MAC_INFO macinfo = (MAC_INFO)ei_local->MACInfo;
242	struct sockaddr *addr = p;
243
244	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
245
246	if(netif_running(dev))
247	return -EBUSY;
248
249	ra2880MacAddressSet(macinfo, addr->sa_data);
250	return 0;
251	}
252
253	#ifdef CONFIG_PSEUDO_SUPPORT
254	static int ei_set_mac2_addr(struct net_device dev, void p)
255	{
256	END_DEVICE *ei_local=netdev_priv(dev);
257	MAC_INFO macinfo = (MAC_INFO)ei_local->MACInfo;
258	struct sockaddr *addr = p;
259
260	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
261
262	if(netif_running(dev))
263	return -EBUSY;
264
265	ra2880Mac2AddressSet(macinfo, addr->sa_data);
266	return 0;
267	}
268	#endif
269
270	void set_fe_pdma_glo_cfg(void)
271	{
272	int pdma_glo_cfg=0;
273	#if defined (CONFIG_RALINK_RT2880) \|\| defined(CONFIG_RALINK_RT2883) \|\| \
274	defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3883)
275	int fe_glo_cfg=0;
276	#endif
277
278	pdma_glo_cfg = (TX_WB_DDONE \| RX_DMA_EN \| TX_DMA_EN \| PDMA_BT_SIZE_4DWORDS);
279	sysRegWrite(PDMA_GLO_CFG, pdma_glo_cfg);
280
281	/* only the following chipset need to set it */
282	#if defined (CONFIG_RALINK_RT2880) \|\| defined(CONFIG_RALINK_RT2883) \|\| \
283	defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3883)
284	//set 1us timer count in unit of clock cycle
285	fe_glo_cfg = sysRegRead(FE_GLO_CFG);
286	fe_glo_cfg &= ~(0xff << 8); //clear bit8-bit15
287	fe_glo_cfg \|= (((get_surfboard_sysclk()/1000000)) << 8);
288	sysRegWrite(FE_GLO_CFG, fe_glo_cfg);
289	#endif
290	}
291
292	int forward_config(struct net_device *dev)
293	{
294
295	#if defined (CONFIG_RALINK_RT5350)
296
297	/* RT5350: No GDMA, PSE, CDMA, PPE */
298	#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
299	unsigned int sdmVal;
300	sdmVal = sysRegRead(SDM_CON);
301	sdmVal \|= 0x7<<16; // UDPCS, TCPCS, IPCS=1
302	sysRegWrite(SDM_CON, sdmVal);
303	#endif
304
305	#if defined (CONFIG_RAETH_SPECIAL_TAG)
306	unsigned int sdmVal;
307	sdmVal = sysRegRead(SDM_CON);
308	sdmVal \|= 0x1<<20; // TCI_81XX
309	sysRegWrite(SDM_CON, sdmVal);
310	#endif
311
312	#else //Non RT5350 chipset
313
314	unsigned int regVal, regCsg;
315
316	#ifdef CONFIG_PSEUDO_SUPPORT
317	unsigned int regVal2;
318	#endif
319
320	regVal = sysRegRead(GDMA1_FWD_CFG);
321	regCsg = sysRegRead(CDMA_CSG_CFG);
322
323	#ifdef CONFIG_PSEUDO_SUPPORT
324	regVal2 = sysRegRead(GDMA2_FWD_CFG);
325	#endif
326
327	//set unicast/multicast/broadcast frame to cpu
328	regVal &= ~0xFFFF;
329	regCsg &= ~0x7;
330
331	#if defined (CONFIG_RAETH_SPECIAL_TAG)
332	regVal \|= (1 << 24); //GDM1_TCI_81xx
333	#endif
334
335	#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
336	//enable ipv4 header checksum check
337	regVal \|= GDM1_ICS_EN;
338	regCsg \|= ICS_GEN_EN;
339
340	//enable tcp checksum check
341	regVal \|= GDM1_TCS_EN;
342	regCsg \|= TCS_GEN_EN;
343
344	//enable udp checksum check
345	regVal \|= GDM1_UCS_EN;
346	regCsg \|= UCS_GEN_EN;
347
348	#ifdef CONFIG_PSEUDO_SUPPORT
349	regVal2 &= ~0xFFFF;
350	regVal2 \|= GDM1_ICS_EN;
351	regVal2 \|= GDM1_TCS_EN;
352	regVal2 \|= GDM1_UCS_EN;
353	#endif
354
355	dev->features \|= NETIF_F_IP_CSUM;
356
357	#else // Checksum offload disabled
358
359	//disable ipv4 header checksum check
360	regVal &= ~GDM1_ICS_EN;
361	regCsg &= ~ICS_GEN_EN;
362
363	//disable tcp checksum check
364	regVal &= ~GDM1_TCS_EN;
365	regCsg &= ~TCS_GEN_EN;
366
367	//disable udp checksum check
368	regVal &= ~GDM1_UCS_EN;
369	regCsg &= ~UCS_GEN_EN;
370
371	#ifdef CONFIG_PSEUDO_SUPPORT
372	regVal2 &= ~GDM1_ICS_EN;
373	regVal2 &= ~GDM1_TCS_EN;
374	regVal2 &= ~GDM1_UCS_EN;
375	#endif
376	#endif
377
378	#ifdef CONFIG_RAETH_JUMBOFRAME
379	// enable jumbo frame
380	regVal \|= GDM1_JMB_EN;
381	#ifdef CONFIG_PSEUDO_SUPPORT
382	regVal2 \|= GDM1_JMB_EN;
383	#endif
384	#endif
385
386	sysRegWrite(GDMA1_FWD_CFG, regVal);
387	sysRegWrite(CDMA_CSG_CFG, regCsg);
388	#ifdef CONFIG_PSEUDO_SUPPORT
389	sysRegWrite(GDMA2_FWD_CFG, regVal2);
390	#endif
391
392	/*
393	* PSE_FQ_CFG register definition -
394	*
395	* Define max free queue page count in PSE. (31:24)
396	* RT2883/RT3883 - 0xff908000 (255 pages)
397	* RT3052 - 0x80504000 (128 pages)
398	* RT2880 - 0x80504000 (128 pages)
399	*
400	* In each page, there are 128 bytes in each page.
401	*
402	* 23:16 - free queue flow control release threshold
403	* 15:8 - free queue flow control assertion threshold
404	* 7:0 - free queue empty threshold
405	*
406	* The register affects QOS correctness in frame engine!
407	*/
408
409	#if defined(CONFIG_RALINK_RT2883) \|\| defined(CONFIG_RALINK_RT3883)
410	sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_RT2883_PSE_FQ_CFG));
411	#elif defined(CONFIG_RALINK_RT3352) \|\| defined(CONFIG_RALINK_RT5350)
412	/use default value/
413	#else
414	sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_PSE_FQFC_CFG));
415	#endif
416
417	/*
418	*FE_RST_GLO register definition -
419	*Bit 0: PSE Rest
420	*Reset PSE after re-programming PSE_FQ_CFG.
421	*/
422	regVal = 0x1;
423	sysRegWrite(FE_RST_GL, regVal);
424	sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
425
426	regCsg = sysRegRead(CDMA_CSG_CFG);
427	printk("CDMA_CSG_CFG = %0X\n",regCsg);
428	regVal = sysRegRead(GDMA1_FWD_CFG);
429	printk("GDMA1_FWD_CFG = %0X\n",regVal);
430
431	#ifdef CONFIG_PSEUDO_SUPPORT
432	regVal = sysRegRead(GDMA2_FWD_CFG);
433	printk("GDMA2_FWD_CFG = %0X\n",regVal);
434	#endif
435	#endif
436	return 1;
437	}
438
439	static int rt2880_eth_setup(struct net_device *dev)
440	{
441
442	int i;
443	unsigned int regVal;
444	END_DEVICE* ei_local = netdev_priv(dev);
445	#if defined (CONFIG_RAETH_QOS)
446	int j;
447	#endif
448
449	while(1)
450	{
451	regVal = sysRegRead(PDMA_GLO_CFG);
452	if((regVal & RX_DMA_BUSY))
453	{
454	printk("\n RX_DMA_BUSY !!! ");
455	continue;
456	}
457	if((regVal & TX_DMA_BUSY))
458	{
459	printk("\n TX_DMA_BUSY !!! ");
460	continue;
461	}
462	break;
463	}
464
465	#if defined (CONFIG_RAETH_QOS)
466	for (i=0;i<NUM_TX_RINGS;i++){
467	for (j=0;j<NUM_TX_DESC;j++){
468	ei_local->skb_free[i][j]=0;
469	}
470	ei_local->free_idx[i]=0;
471	}
472	/*
473	* RT2880: 2 x TX_Ring, 1 x Rx_Ring
474	* RT2883: 4 x TX_Ring, 1 x Rx_Ring
475	* RT3883: 4 x TX_Ring, 1 x Rx_Ring
476	* RT3052: 4 x TX_Ring, 1 x Rx_Ring
477	*/
478	fe_tx_desc_init(dev, 0, 3, 1);
479	if (ei_local->tx_ring0 == NULL) {
480	printk("RAETH: tx ring0 allocation failed\n");
481	return 0;
482	}
483
484	fe_tx_desc_init(dev, 1, 3, 1);
485	if (ei_local->tx_ring1 == NULL) {
486	printk("RAETH: tx ring1 allocation failed\n");
487	return 0;
488	}
489
490	printk("\nphy_tx_ring0 = %08x, tx_ring0 = %p, size: %d bytes\n", ei_local->phy_tx_ring0, ei_local->tx_ring0, sizeof(struct PDMA_txdesc));
491
492	printk("\nphy_tx_ring1 = %08x, tx_ring1 = %p, size: %d bytes\n", ei_local->phy_tx_ring1, ei_local->tx_ring1, sizeof(struct PDMA_txdesc));
493
494	#if defined (CONFIG_RALINK_RT2883) \|\| defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined(CONFIG_RALINK_RT3883) \|\| defined(CONFIG_RALINK_RT5350)
495	fe_tx_desc_init(dev, 2, 3, 1);
496	if (ei_local->tx_ring2 == NULL) {
497	printk("RAETH: tx ring2 allocation failed\n");
498	return 0;
499	}
500
501	fe_tx_desc_init(dev, 3, 3, 1);
502	if (ei_local->tx_ring3 == NULL) {
503	printk("RAETH: tx ring3 allocation failed\n");
504	return 0;
505	}
506
507	printk("\nphy_tx_ring2 = %08x, tx_ring2 = %p, size: %d bytes\n", ei_local->phy_tx_ring2, ei_local->tx_ring2, sizeof(struct PDMA_txdesc));
508
509	printk("\nphy_tx_ring3 = %08x, tx_ring3 = %p, size: %d bytes\n", ei_local->phy_tx_ring3, ei_local->tx_ring3, sizeof(struct PDMA_txdesc));
510
511	#endif // CONFIG_RALINK_RT2883 \|\| CONFIG_RALINK_RT3052 \|\| CONFIG_RALINK_RT3352 \|\| CONFIG_RALINK_RT3883 \|\| CONFIG_RALINK_RT5350 //
512	#else
513	for (i=0;i<NUM_TX_DESC;i++){
514	ei_local->skb_free[i]=0;
515	}
516	ei_local->free_idx =0;
517	ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
518	printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
519
520	for (i=0; i < NUM_TX_DESC; i++) {
521	memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
522	ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
523	ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
524
525	}
526	#endif // CONFIG_RAETH_QOS
527
528	/* Initial RX Ring 0*/
529	ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
530	for (i = 0; i < NUM_RX_DESC; i++) {
531	memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
532	ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
533	ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
534	ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, skb_put(ei_local->netrx0_skbuf[i], 2), MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
535	}
536	printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
537	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
538	/* Initial RX Ring 1*/
539	ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
540	for (i = 0; i < NUM_RX_DESC; i++) {
541	memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
542	ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
543	ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
544	ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, skb_put(ei_local->netrx1_skbuf[i], 2), MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
545	}
546	printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
547	#endif
548
549	regVal = sysRegRead(PDMA_GLO_CFG);
550	regVal &= 0x000000FF;
551	sysRegWrite(PDMA_GLO_CFG, regVal);
552	regVal=sysRegRead(PDMA_GLO_CFG);
553
554	/* Tell the adapter where the TX/RX rings are located. */
555	#if !defined (CONFIG_RAETH_QOS)
556	sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
557	sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
558	sysRegWrite(TX_CTX_IDX0, 0);
559	sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
560	#endif
561
562	sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
563	sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
564	sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
565	sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
566	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
567	sysRegWrite(RX_BASE_PTR1, phys_to_bus((u32) ei_local->phy_rx_ring1));
568	sysRegWrite(RX_MAX_CNT1, cpu_to_le32((u32) NUM_RX_DESC));
569	sysRegWrite(RX_CALC_IDX1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
570	sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX1);
571	#endif
572	#if defined(CONFIG_RALINK_RT3883)
573	regVal = sysRegRead(RX_DRX_IDX0);
574	regVal = (regVal == 0)? (NUM_RX_DESC - 1) : (regVal - 1);
575	sysRegWrite(RX_CALC_IDX0, cpu_to_le32(regVal));
576	rx_dma_owner_idx0 = regVal;
577	#endif
578
579	#if defined (CONFIG_RAETH_QOS)
580	set_scheduler_weight();
581	set_schedule_pause_condition();
582	set_output_shaper();
583	#endif
584	set_fe_pdma_glo_cfg();
585
586	return 1;
587	}
588
589	#if! defined (CONFIG_RAETH_QOS)
590	static inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
591	{
592	unsigned int length=skb->len;
593	END_DEVICE* ei_local = netdev_priv(dev);
594	unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
595	#ifdef CONFIG_PSEUDO_SUPPORT
596	PSEUDO_ADAPTER *pAd;
597	#endif
598
599	while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
600	{
601	printk(KERN_ERR "%s: TX DMA is Busy !! TX desc is Empty!\n", dev->name);
602	#ifdef CONFIG_PSEUDO_SUPPORT
603	if (gmac_no == 2) {
604	if (ei_local->PseudoDev != NULL) {
605	pAd = netdev_priv(ei_local->PseudoDev);
606	pAd->stat.tx_errors++;
607	}
608	} else
609	#endif
610	ei_local->stat.tx_errors++;
611	}
612
613	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
614	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
615	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = gmac_no;
616	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.QN = 3;
617	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
618
619	#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
620	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TCO = 1;
621	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UCO = 1;
622	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.ICO = 1;
623	#endif
624
625	#if defined (CONFIG_RA_HW_NAT) \|\| defined (CONFIG_RA_HW_NAT_MODULE)
626	if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
627	ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = 6; /* PPE */
628	}
629	#endif
630
631	tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
632	sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
633
634	#ifdef CONFIG_PSEUDO_SUPPORT
635	if (gmac_no == 2) {
636	if (ei_local->PseudoDev != NULL) {
637	pAd = netdev_priv(ei_local->PseudoDev);
638	pAd->stat.tx_packets++;
639	pAd->stat.tx_bytes += length;
640	}
641	} else
642	#endif
643	{
644	ei_local->stat.tx_packets++;
645	ei_local->stat.tx_bytes += length;
646	}
647	#ifdef CONFIG_RAETH_NAPI
648	if ( ei_local->tx_full == 1) {
649	ei_local->tx_full = 0;
650	netif_wake_queue(dev);
651	}
652	#endif
653
654	return length;
655	}
656	#endif
657
658	#ifdef CONFIG_RAETH_NAPI
659	static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do)
660	#else
661	static int rt2880_eth_recv(struct net_device* dev)
662	#endif
663	{
664	struct sk_buff skb, rx_skb;
665	unsigned int length = 0;
666	unsigned long RxProcessed;
667	int bReschedule = 0;
668	END_DEVICE* ei_local = netdev_priv(dev);
669	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
670	int rx_ring_no=0;
671	#endif
672
673	#if defined (CONFIG_RAETH_SPECIAL_TAG)
674	struct vlan_ethhdr *veth=NULL;
675	#endif
676
677	#ifdef CONFIG_PSEUDO_SUPPORT
678	PSEUDO_ADAPTER *pAd;
679	#endif
680
681	RxProcessed = 0;
682
683
684	for ( ; ; ) {
685
686	#ifdef CONFIG_RAETH_NAPI
687	if(*work_done >= work_to_do)
688	break;
689	(*work_done)++;
690	#else
691	if (RxProcessed++ > NUM_RX_MAX_PROCESS)
692	{
693	// need to reschedule rx handle
694	bReschedule = 1;
695	break;
696	}
697	#endif
698
699
700	/* Update to Next packet point that was received.
701	*/
702
703	rx_dma_owner_idx0 = (sysRegRead(RX_CALC_IDX0) + 1) % NUM_RX_DESC;
704	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
705	rx_dma_owner_idx1 = (sysRegRead(RX_CALC_IDX1) + 1) % NUM_RX_DESC;
706
707	if (ei_local->rx_ring1[rx_dma_owner_idx1].rxd_info2.DDONE_bit == 1) {
708	rx_ring = ei_local->rx_ring1;
709	rx_dma_owner_idx = rx_dma_owner_idx1;
710	// printk("rx_dma_owner_idx1=%x\n",rx_dma_owner_idx1);
711	rx_ring_no=1;
712	} else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
713	rx_ring = ei_local->rx_ring0;
714	rx_dma_owner_idx = rx_dma_owner_idx0;
715	// printk("rx_dma_owner_idx0=%x\n",rx_dma_owner_idx0);
716	rx_ring_no=0;
717	} else {
718	break;
719	}
720	#else
721
722	if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
723	rx_ring = ei_local->rx_ring0;
724	rx_dma_owner_idx = rx_dma_owner_idx0;
725	} else {
726	break;
727	}
728	#endif
729
730	/* skb processing */
731	length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
732	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
733	if(rx_ring_no==1) {
734	rx_skb = ei_local->netrx1_skbuf[rx_dma_owner_idx];
735	rx_skb->data = ei_local->netrx1_skbuf[rx_dma_owner_idx]->data;
736	} else {
737	rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
738	rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
739	}
740	#else
741	rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
742	rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
743	#endif
744	rx_skb->len = length;
745	rx_skb->tail = rx_skb->data + length;
746
747	#ifdef CONFIG_PSEUDO_SUPPORT
748	if(rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
749	if(ei_local->PseudoDev!=NULL) {
750	rx_skb->dev = ei_local->PseudoDev;
751	rx_skb->protocol = eth_type_trans(rx_skb,ei_local->PseudoDev);
752	}else {
753	printk("ERROR: PseudoDev is still not initialize but receive packet from GMAC2\n");
754	}
755	}else{
756	rx_skb->dev = dev;
757	rx_skb->protocol = eth_type_trans(rx_skb,dev);
758	}
759	#else
760	rx_skb->dev = dev;
761	rx_skb->protocol = eth_type_trans(rx_skb,dev);
762	#endif
763
764	#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
765	rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
766	#else
767	rx_skb->ip_summed = CHECKSUM_NONE;
768	#endif
769
770	#ifdef CONFIG_RALINK_BRIDGING_ONLY
771	rx_skb->cb[22]=0xa8;
772	#endif
773
774	#if defined(CONFIG_RA_CLASSIFIER)\|\|defined(CONFIG_RA_CLASSIFIER_MODULE)
775	/* Qwert+
776	*/
777	if(ra_classifier_hook_rx!= NULL)
778	{
779	#if defined(CONFIG_RALINK_EXTERNAL_TIMER)
780	ra_classifier_hook_rx(rx_skb, (((volatile u32 )(0xB0000D08))&0x0FFFF));
781	#else
782	ra_classifier_hook_rx(rx_skb, read_c0_count());
783	#endif
784	}
785	#endif /* CONFIG_RA_CLASSIFIER */
786
787	#if defined (CONFIG_RA_HW_NAT) \|\| defined (CONFIG_RA_HW_NAT_MODULE)
788	FOE_MAGIC_TAG(rx_skb)= FOE_MAGIC_GE;
789	memcpy(FOE_INFO_START_ADDR(rx_skb)+2, &rx_ring[rx_dma_owner_idx].rxd_info4, sizeof(PDMA_RXD_INFO4_T));
790	#endif
791
792	/* We have to check the free memory size is big enough
793	* before pass the packet to cpu*/
794	skb = __dev_alloc_skb(MAX_RX_LENGTH, GFP_DMA \| GFP_ATOMIC);
795	if (skb == NULL)
796	{
797	printk(KERN_ERR "skb not available...\n");
798	#ifdef CONFIG_PSEUDO_SUPPORT
799	if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
800	if (ei_local->PseudoDev != NULL) {
801	pAd = netdev_priv(ei_local->PseudoDev);
802	pAd->stat.rx_dropped++;
803	}
804	} else
805	#endif
806	ei_local->stat.rx_dropped++;
807	bReschedule = 1;
808	break;
809	}
810	skb_reserve(skb, 2);
811
812	#if defined (CONFIG_RAETH_SPECIAL_TAG)
813	// port0: 0x8100 => 0x8100 0001
814	// port1: 0x8101 => 0x8100 0002
815	// port2: 0x8102 => 0x8100 0003
816	// port3: 0x8103 => 0x8100 0004
817	// port4: 0x8104 => 0x8100 0005
818	// port5: 0x8105 => 0x8100 0006
819	veth = (struct vlan_ethhdr *)(rx_skb->mac.raw);
820	if((veth->h_vlan_proto & 0xFF) == 0x81) {
821	veth->h_vlan_TCI = htons( (((veth->h_vlan_proto >> 8) & 0xF) + 1) );
822	rx_skb->protocol = veth->h_vlan_proto = htons(ETH_P_8021Q);
823	}
824	#endif
825
826	#if !defined(CONFIG_RA_NAT_NONE)
827	/* bruce+
828	* ra_sw_nat_hook_rx return 1 --> continue
829	* ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
830	*/
831	if(ra_sw_nat_hook_rx!= NULL)
832	{
833	if(ra_sw_nat_hook_rx(rx_skb)) {
834	#if defined (CONFIG_RALINK_RT3052_MP2)
835	if(mcast_rx(rx_skb)==0) {
836	kfree_skb(rx_skb);
837	}else
838	#endif
839	#ifdef CONFIG_RAETH_NAPI
840	netif_receive_skb(rx_skb);
841	#else
842	netif_rx(rx_skb);
843	#endif
844	}
845	} else {
846	#if defined (CONFIG_RALINK_RT3052_MP2)
847	if(mcast_rx(rx_skb)==0) {
848	kfree_skb(rx_skb);
849	}else
850	#endif
851	#ifdef CONFIG_RAETH_NAPI
852	netif_receive_skb(rx_skb);
853	#else
854	netif_rx(rx_skb);
855	#endif // CONFIG_RAETH_NAPI //
856	}
857	#else
858
859	#if defined (CONFIG_RALINK_RT3052_MP2)
860	if(mcast_rx(rx_skb)==0) {
861	kfree_skb(rx_skb);
862	}else
863	#endif // CONFIG_RALINK_RT3052_MP2 //
864	#ifdef CONFIG_RAETH_NAPI
865	netif_receive_skb(rx_skb);
866	#else
867	netif_rx(rx_skb);
868	#endif // CONFIG_RAETH_NAPI //
869
870
871	#endif // CONFIG_RA_NAT_NONE //
872	rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
873	rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
874	dma_cache_sync(NULL, &rx_ring[rx_dma_owner_idx], sizeof(struct PDMA_rxdesc), DMA_FROM_DEVICE);
875
876	/* Move point to next RXD which wants to alloc*/
877	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
878	if(rx_ring_no==0) {
879	sysRegWrite(RX_CALC_IDX0, rx_dma_owner_idx);
880	ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
881	}else {
882	sysRegWrite(RX_CALC_IDX1, rx_dma_owner_idx);
883	ei_local->netrx1_skbuf[rx_dma_owner_idx] = skb;
884	}
885	#else
886	sysRegWrite(RX_CALC_IDX0, rx_dma_owner_idx);
887	ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
888	#endif
889
890	#ifdef CONFIG_PSEUDO_SUPPORT
891	if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
892	if (ei_local->PseudoDev != NULL) {
893	pAd = netdev_priv(ei_local->PseudoDev);
894	pAd->stat.rx_packets++;
895	pAd->stat.rx_bytes += length;
896	}
897	} else
898	#endif
899	{
900	ei_local->stat.rx_packets++;
901	ei_local->stat.rx_bytes += length;
902	}
903	} /* for */
904
905	return bReschedule;
906	}
907
908
909
910	///////////////////////////////////////////////////////////////////
911	/////
912	///// ra_get_stats - gather packet information for management plane
913	/////
914	///// Pass net_device_stats to the upper layer.
915	/////
916	/////
917	///// RETURNS: pointer to net_device_stats
918	///////////////////////////////////////////////////////////////////
919
920	struct net_device_stats ra_get_stats(struct net_device dev)
921	{
922	END_DEVICE *ei_local = netdev_priv(dev);
923	return &ei_local->stat;
924	}
925
926	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
927	void kill_sig_workq(struct work_struct *work)
928	{
929
930	}
931	#endif
932
933	///////////////////////////////////////////////////////////////////
934	/////
935	///// ra2880Recv - process the next incoming packet
936	/////
937	///// Handle one incoming packet. The packet is checked for errors and sent
938	///// to the upper layer.
939	/////
940	///// RETURNS: OK on success or ERROR.
941	///////////////////////////////////////////////////////////////////
942
943	#ifndef CONFIG_RAETH_NAPI
944	#ifdef WORKQUEUE_BH
945	void ei_receive_workq(struct work_struct *work)
946	#else
947	void ei_receive(unsigned long unused) // device structure
948	#endif // WORKQUEUE_BH //
949	{
950	struct net_device *dev = dev_raether;
951	END_DEVICE *ei_local = netdev_priv(dev);
952	unsigned long reg_int_mask=0;
953	int bReschedule=0;
954
955	if(tx_ring_full==0){
956	bReschedule = rt2880_eth_recv(dev);
957	if(bReschedule)
958	{
959	#ifdef WORKQUEUE_BH
960	schedule_work(&ei_local->rx_wq);
961	#else
962	tasklet_hi_schedule(&ei_local->rx_tasklet);
963	#endif // WORKQUEUE_BH //
964	}else{
965	reg_int_mask=sysRegRead(FE_INT_ENABLE);
966	#if defined(DELAY_INT)
967	sysRegWrite(FE_INT_ENABLE, reg_int_mask\| RX_DLY_INT);
968	#else
969	sysRegWrite(FE_INT_ENABLE, (reg_int_mask \| RX_DONE_INT0 \| RX_DONE_INT1));
970	#endif
971	}
972	}else{
973	#ifdef WORKQUEUE_BH
974	schedule_work(&ei_local->rx_wq);
975	#else
976	tasklet_schedule(&ei_local->rx_tasklet);
977	#endif // WORKQUEUE_BH //
978	}
979	}
980	#endif
981
982	#ifdef CONFIG_RAETH_NAPI
983	static int
984	raeth_clean(struct napi_struct *napi, int budget)
985	{
986	END_DEVICE *ei_local = container_of(napi, END_DEVICE, mac_napi);
987	//unsigned int reg_int_val;
988	int work_to_do = budget;
989	struct net_device *netdev = ei_local->mac_dev;
990	//int tx_cleaned;
991	int work_done = 0;
992	unsigned long reg_int_mask=0;
993
994	#ifdef WORKQUEUE_BH
995	schedule_work(&ei_local->tx_wq);
996	#else
997	ei_xmit_housekeeping(0);
998	#endif // WORKQUEUE_BH //
999
1000	rt2880_eth_recv(netdev, &work_done, work_to_do);
1001
1002	/* this could control when to re-enable interrupt, 0-> mean never enable interrupt*/
1003	/* if no Tx and not enough Rx work done, exit the polling mode */
1004	if(( (work_done < work_to_do)) \|\| !netif_running(netdev)) {
1005	napi_complete(napi);
1006	atomic_dec_and_test(&ei_local->irq_sem);
1007
1008	sysRegWrite(FE_INT_STATUS, FE_INT_ALL); // ack all fe interrupts
1009	reg_int_mask=sysRegRead(FE_INT_ENABLE);
1010
1011	#ifdef DELAY_INT
1012	sysRegWrite(FE_INT_ENABLE, reg_int_mask \|FE_INT_DLY_INIT); // init delay interrupt only
1013	#else
1014	sysRegWrite(FE_INT_ENABLE,reg_int_mask\| RX_DONE_INT0 \| RX_DONE_INT1 \
1015	\| TX_DONE_INT0 \| TX_DONE_INT1 \
1016	\| TX_DONE_INT2 \| TX_DONE_INT3);
1017	#endif
1018	}
1019
1020	return work_done;
1021	}
1022
1023	#endif
1024
1025
1026	/**
1027	* ei_interrupt - handle controler interrupt
1028	*
1029	* This routine is called at interrupt level in response to an interrupt from
1030	* the controller.
1031	*
1032	* RETURNS: N/A.
1033	*/
1034	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
1035	static irqreturn_t ei_interrupt(int irq, void *dev_id)
1036	#else
1037	static irqreturn_t ei_interrupt(int irq, void dev_id, struct pt_regs regs)
1038	#endif
1039	{
1040	#if !defined(CONFIG_RAETH_NAPI)
1041	unsigned long reg_int_val;
1042	unsigned long reg_int_mask=0;
1043	unsigned int recv = 0;
1044	unsigned int transmit = 0;
1045	unsigned long flags;
1046	#endif
1047
1048	struct net_device dev = (struct net_device ) dev_id;
1049	END_DEVICE *ei_local = netdev_priv(dev);
1050
1051	//Qwert
1052	/*
1053	unsigned long old,cur,dcycle;
1054	static int cnt = 0;
1055	static unsigned long max_dcycle = 0,tcycle = 0;
1056	old = read_c0_count();
1057	*/
1058	if (dev == NULL)
1059	{
1060	printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
1061	return IRQ_NONE;
1062	}
1063
1064	#ifdef CONFIG_RAETH_NAPI
1065	if(napi_schedule_prep(&ei_local->mac_napi)) {
1066	atomic_inc(&ei_local->irq_sem);
1067	sysRegWrite(FE_INT_ENABLE, 0);
1068	__napi_schedule(&ei_local->mac_napi);
1069	}
1070	#else
1071
1072	spin_lock_irqsave(&(ei_local->page_lock), flags);
1073	reg_int_val = sysRegRead(FE_INT_STATUS);
1074
1075	#if defined (DELAY_INT)
1076	if((reg_int_val & RX_DLY_INT))
1077	recv = 1;
1078
1079	if (reg_int_val & TX_DLY_INT)
1080	transmit = 1;
1081	#else
1082	if((reg_int_val & RX_DONE_INT0))
1083	recv = 1;
1084
1085	#if defined (CONFIG_RALINK_RT5350)
1086	if((reg_int_val & RX_DONE_INT1))
1087	recv = 1;
1088	#endif
1089
1090	if (reg_int_val & TX_DONE_INT0)
1091	transmit \|= TX_DONE_INT0;
1092	#if defined (CONFIG_RAETH_QOS)
1093	if (reg_int_val & TX_DONE_INT1)
1094	transmit \|= TX_DONE_INT1;
1095	if (reg_int_val & TX_DONE_INT2)
1096	transmit \|= TX_DONE_INT2;
1097	if (reg_int_val & TX_DONE_INT3)
1098	transmit \|= TX_DONE_INT3;
1099	#endif //CONFIG_RAETH_QOS
1100
1101	#endif //DELAY_INT
1102
1103	sysRegWrite(FE_INT_STATUS, reg_int_val);
1104
1105	//if ( transmit != 0)
1106	#ifdef WORKQUEUE_BH
1107	schedule_work(&ei_local->tx_wq);
1108	#else
1109	ei_xmit_housekeeping(0);
1110	#endif // WORKQUEUE_BH //
1111
1112	if( recv == 1 && tx_ring_full==0 )
1113	{
1114	reg_int_mask = sysRegRead(FE_INT_ENABLE);
1115	#if defined (DELAY_INT)
1116	sysRegWrite(FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
1117	#else
1118	sysRegWrite(FE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 \| RX_DONE_INT1));
1119	#endif //DELAY_INT
1120	#ifdef WORKQUEUE_BH
1121	schedule_work(&ei_local->rx_wq);
1122	#else
1123	tasklet_hi_schedule(&ei_local->rx_tasklet);
1124	#endif // WORKQUEUE_BH //
1125	}
1126
1127
1128	//Qwert
1129	/*
1130	cur = read_c0_count();
1131
1132	if(cur >= old)
1133	{
1134	dcycle = (cur-old)/192;
1135	}
1136	else
1137	{
1138	dcycle = (0xFFFFFFFF - (old - cur))/192;
1139	}
1140
1141	if(max_dcycle < dcycle)
1142	max_dcycle = dcycle;
1143	tcycle+=dcycle;
1144	cnt++;
1145	if(cnt==10000)
1146	{
1147	printk("avg=%d\n",tcycle/10000);
1148	max_dcycle = 0;
1149	tcycle = 0;
1150	cnt = 0;
1151	}
1152	*/
1153	spin_unlock_irqrestore(&(ei_local->page_lock), flags);
1154	#endif
1155
1156	return IRQ_HANDLED;
1157	}
1158
1159	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
1160
1161	static irqreturn_t esw_interrupt(int irq, void *dev_id)
1162	{
1163	unsigned long flags;
1164	unsigned long reg_int_val;
1165	struct net_device dev = (struct net_device ) dev_id;
1166	static u32 stat;
1167	u32 stat_curr;
1168
1169	END_DEVICE *ei_local = netdev_priv(dev);
1170	spin_lock_irqsave(&(ei_local->page_lock), flags);
1171	reg_int_val = (((volatile u32 )(RALINK_ETH_SW_BASE))); //Interrupt Status Register
1172
1173	if (reg_int_val & PORT_ST_CHG) {
1174	printk("RT305x_ESW: Link Status Changed\n");
1175
1176	stat_curr = ((volatile u32 )(RALINK_ETH_SW_BASE+0x80));
1177	#ifdef CONFIG_WAN_AT_P0
1178	//if Port0 link down --> link up
1179	if ((stat & (1<<25)) \|\| !(stat_curr & (1<<25)))
1180	#else
1181	//if Port4 link down --> link up
1182	if ((stat & (1<<29)) \|\| !(stat_curr & (1<<29)))
1183	#endif
1184	goto out;
1185
1186	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
1187	schedule_work(&ei_local->kill_sig_wq);
1188	#endif
1189	out:
1190	stat = stat_curr;
1191	}
1192	sysRegWrite(RALINK_ETH_SW_BASE, reg_int_val);
1193
1194	spin_unlock_irqrestore(&(ei_local->page_lock), flags);
1195	return IRQ_HANDLED;
1196	}
1197	#endif
1198
1199	static int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
1200	{
1201	END_DEVICE *ei_local = netdev_priv(dev);
1202	unsigned long flags;
1203	unsigned long tx_cpu_owner_idx;
1204	unsigned int tx_cpu_owner_idx_next;
1205	#if !defined(CONFIG_RAETH_QOS)
1206	unsigned int tx_cpu_owner_idx_next2;
1207	struct PDMA_txdesc* tx_desc;
1208	#else
1209	int ring_no, queue_no, port_no;
1210	#endif
1211	#ifdef CONFIG_RALINK_VISTA_BASIC
1212	struct vlan_ethhdr *veth;
1213	#endif
1214	#ifdef CONFIG_PSEUDO_SUPPORT
1215	PSEUDO_ADAPTER *pAd;
1216	#endif
1217
1218	#if !defined(CONFIG_RA_NAT_NONE)
1219	/* bruce+
1220	*/
1221	if(ra_sw_nat_hook_tx!= NULL)
1222	{
1223	spin_lock_irqsave(&ei_local->page_lock, flags);
1224	if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
1225	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1226	}else{
1227	kfree_skb(skb);
1228	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1229	return 0;
1230	}
1231	}
1232	#endif
1233
1234	#if defined (CONFIG_RALINK_RT3052_MP2)
1235	mcast_tx(skb);
1236	#endif
1237
1238	#if defined (CONFIG_RT_3052_ESW) \|\| defined (CONFIG_RALINK_RT2883) \|\| defined (CONFIG_RALINK_RT3883)
1239	#define MIN_PKT_LEN 64
1240	if (skb->len < MIN_PKT_LEN) {
1241	if (skb_padto(skb, MIN_PKT_LEN)) {
1242	printk("raeth: skb_padto failed\n");
1243	return 0;
1244	}
1245	skb_put(skb, MIN_PKT_LEN - skb->len);
1246	}
1247	#endif // CONFIG_RT_3052_ESW \|\| CONFIG_RALINK_RT2883 \|\| CONFIG_RALINK_RT3883
1248
1249	dev->trans_start = jiffies; /* save the timestamp */
1250	spin_lock_irqsave(&ei_local->page_lock, flags);
1251	#if defined( CONFIG_RALINK_ENHANCE) \|\| defined (CONFIG_RALINK_BRIDGING_ONLY)
1252	if ((unsigned char)skb->cb[22] == 0xa9)
1253	dma_cache_sync(dev, skb->data, 60, DMA_TO_DEVICE);
1254	else if ((unsigned char)skb->cb[22] == 0xa8) {
1255	dma_cache_sync(dev, skb->data, 16, DMA_TO_DEVICE);
1256	}
1257	else
1258	dma_cache_sync(dev, skb->data, skb->len, DMA_TO_DEVICE);
1259	#else
1260	dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1261	#endif
1262
1263	#ifdef CONFIG_RALINK_VISTA_BASIC
1264	veth = (struct vlan_ethhdr *)(skb->data);
1265	if (is_switch_175c && veth->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1266	if ((veth->h_vlan_TCI & __constant_htons(VLAN_VID_MASK)) == 0) {
1267	veth->h_vlan_TCI \|= htons(VLAN_DEV_INFO(dev)->vlan_id);
1268	}
1269	}
1270	#endif
1271
1272	#if defined (CONFIG_RAETH_QOS)
1273	if(pkt_classifier(skb, gmac_no, &ring_no, &queue_no, &port_no)) {
1274	get_tx_ctx_idx(ring_no, &tx_cpu_owner_idx);
1275
1276	if(tx_cpu_owner_idx== NUM_TX_DESC-1)
1277	tx_cpu_owner_idx_next = 0;
1278	else
1279	tx_cpu_owner_idx_next = tx_cpu_owner_idx +1;
1280
1281
1282	if(((ei_local->skb_free[ring_no][tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[ring_no][tx_cpu_owner_idx_next]==0)){
1283	fe_qos_packet_send(dev, skb, ring_no, queue_no, port_no);
1284	}else{
1285	ei_local->stat.tx_dropped++;
1286	kfree_skb(skb);
1287	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1288	return 0;
1289	}
1290	}
1291	#else
1292	tx_cpu_owner_idx = (unsigned long)TX_CTX_IDX0;
1293	if(tx_cpu_owner_idx== NUM_TX_DESC-1)
1294	tx_cpu_owner_idx_next = 0;
1295	else
1296	tx_cpu_owner_idx_next = tx_cpu_owner_idx +1;
1297
1298	if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
1299	rt2880_eth_send(dev, skb, gmac_no);
1300
1301	if(tx_cpu_owner_idx_next== NUM_TX_DESC-1)
1302	tx_cpu_owner_idx_next2 = 0;
1303	else
1304	tx_cpu_owner_idx_next2 = tx_cpu_owner_idx_next+1;
1305
1306	if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
1307	netif_stop_queue(dev);
1308	#ifdef CONFIG_PSEUDO_SUPPORT
1309	netif_stop_queue(ei_local->PseudoDev);
1310	#endif
1311	tx_ring_full=1;
1312	}
1313	}else {
1314	#ifdef CONFIG_PSEUDO_SUPPORT
1315	if (gmac_no == 2) {
1316	if (ei_local->PseudoDev != NULL) {
1317	pAd = netdev_priv(ei_local->PseudoDev);
1318	pAd->stat.tx_dropped++;
1319	}
1320	} else
1321	#endif
1322	ei_local->stat.tx_dropped++;
1323	printk("tx_ring_full, drop packet\n");
1324	kfree_skb(skb);
1325	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1326	return 0;
1327	}
1328	tx_desc = ei_local->tx_ring0;
1329	ei_local->skb_free[tx_cpu_owner_idx] = skb;
1330
1331	(unsigned long)TX_CTX_IDX0 = ((tx_cpu_owner_idx+1) % NUM_TX_DESC);
1332	#endif
1333	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1334	return 0;
1335	}
1336
1337	static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
1338	{
1339	return ei_start_xmit(skb, dev, 1);
1340	}
1341
1342
1343	int ei_ioctl(struct net_device dev, struct ifreq ifr, int cmd)
1344	{
1345	#if defined(CONFIG_RT_3052_ESW)
1346	esw_reg reg;
1347	#endif
1348	#if defined(CONFIG_RALINK_RT3352) \|\| defined(CONFIG_RALINK_RT5350)
1349	esw_rate ratelimit;
1350	unsigned int offset = 0;
1351	unsigned int value = 0;
1352	#endif
1353	ra_mii_ioctl_data mii;
1354	switch (cmd) {
1355	case RAETH_MII_READ:
1356	copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
1357	mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
1358	//printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out);
1359	copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
1360	break;
1361
1362	case RAETH_MII_WRITE:
1363	copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
1364	//printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in);
1365	mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
1366	break;
1367	#if defined(CONFIG_RT_3052_ESW)
1368	#define _ESW_REG(x) (((volatile u32 )(RALINK_ETH_SW_BASE + x)))
1369	case RAETH_ESW_REG_READ:
1370	copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
1371	if (reg.off > REG_ESW_MAX)
1372	return -EINVAL;
1373	reg.val = _ESW_REG(reg.off);
1374	//printk("read reg off:%x val:%x\n", reg.off, reg.val);
1375	copy_to_user(ifr->ifr_data, &reg, sizeof(reg));
1376	break;
1377	case RAETH_ESW_REG_WRITE:
1378	copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
1379	if (reg.off > REG_ESW_MAX)
1380	return -EINVAL;
1381	_ESW_REG(reg.off) = reg.val;
1382	//printk("write reg off:%x val:%x\n", reg.off, reg.val);
1383	break;
1384	#endif // CONFIG_RT_3052_ESW
1385	#if defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
1386	#define _ESW_REG(x) (((volatile u32 )(RALINK_ETH_SW_BASE + x)))
1387	case RAETH_ESW_INGRESS_RATE:
1388	copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
1389	offset = 0x11c + (4 * (ratelimit.port / 2));
1390	value = _ESW_REG(offset);
1391
1392	if((ratelimit.port % 2) == 0)
1393	{
1394	value &= 0xffff0000;
1395	if(ratelimit.on_off == 1)
1396	{
1397	value \|= (ratelimit.on_off << 14);
1398	value \|= (0x07 << 10);
1399	value \|= ratelimit.bw;
1400	}
1401	}
1402	else if((ratelimit.port % 2) == 1)
1403	{
1404	value &= 0x0000ffff;
1405	if(ratelimit.on_off == 1)
1406	{
1407	value \|= (ratelimit.on_off << 30);
1408	value \|= (0x07 << 26);
1409	value \|= (ratelimit.bw << 16);
1410	}
1411	}
1412	printk("offset = 0x%4x value=0x%x\n\r", offset, value);
1413	_ESW_REG(offset) = value;
1414	break;
1415
1416	case RAETH_ESW_EGRESS_RATE:
1417	copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
1418	offset = 0x140 + (4 * (ratelimit.port / 2));
1419	value = _ESW_REG(offset);
1420
1421	if((ratelimit.port % 2) == 0)
1422	{
1423	value &= 0xffff0000;
1424	if(ratelimit.on_off == 1)
1425	{
1426	value \|= (ratelimit.on_off << 12);
1427	value \|= (0x03 << 10);
1428	value \|= ratelimit.bw;
1429	}
1430	}
1431	else if((ratelimit.port % 2) == 1)
1432	{
1433	value &= 0x0000ffff;
1434	if(ratelimit.on_off == 1)
1435	{
1436	value \|= (ratelimit.on_off << 28);
1437	value \|= (0x03 << 26);
1438	value \|= (ratelimit.bw << 16);
1439	}
1440	}
1441	printk("offset = 0x%4x value=0x%x\n\r", offset, value);
1442	_ESW_REG(offset) = value;
1443	break;
1444	#endif
1445	default:
1446	return -EOPNOTSUPP;
1447
1448	}
1449
1450	return 0;
1451	}
1452
1453	/*
1454	* Set new MTU size
1455	* Change the mtu of Raeth Ethernet Device
1456	*/
1457	static int ei_change_mtu(struct net_device *dev, int new_mtu)
1458	{
1459	unsigned long flags;
1460	END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
1461
1462	if ( ei_local == NULL ) {
1463	printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
1464	return -ENXIO;
1465	}
1466
1467	spin_lock_irqsave(&ei_local->page_lock, flags);
1468
1469	if ( (new_mtu > 4096) \|\| (new_mtu < 64)) {
1470	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1471	return -EINVAL;
1472	}
1473
1474	#ifndef CONFIG_RAETH_JUMBOFRAME
1475	if ( new_mtu > 1500 ) {
1476	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1477	return -EINVAL;
1478	}
1479	#endif
1480
1481	dev->mtu = new_mtu;
1482
1483	spin_unlock_irqrestore(&ei_local->page_lock, flags);
1484	return 0;
1485	}
1486	static struct net_device_ops mac_net_ops;
1487
1488	void ra2880_setup_dev_fptable(struct net_device *dev)
1489	{
1490	END_DEVICE ei_local = (END_DEVICE )netdev_priv(dev);
1491	memset(ei_local, 0, sizeof(END_DEVICE));
1492	RAETH_PRINT(__FUNCTION__ "is called!\n");
1493	mac_net_ops.ndo_init = rather_probe;
1494	mac_net_ops.ndo_open = ei_open;
1495	mac_net_ops.ndo_stop = ei_close;
1496	mac_net_ops.ndo_start_xmit= ei_start_xmit_fake;
1497	mac_net_ops.ndo_get_stats = ra_get_stats;
1498	mac_net_ops.ndo_tx_timeout= ei_tx_timeout;
1499	mac_net_ops.ndo_do_ioctl = ei_ioctl;
1500	mac_net_ops.ndo_change_mtu = ei_change_mtu;
1501	mac_net_ops.ndo_set_mac_address =ei_set_mac_addr;
1502	mac_net_ops.ndo_validate_addr = eth_validate_addr;
1503	#if defined (CONFIG_ETHTOOL)
1504	mac_net_ops.ndo_ethtool_ops = ra_ethtool_ops;
1505	#endif
1506	dev->netdev_ops = (const struct net_device_ops *)&mac_net_ops;
1507	ei_local->mac_dev = dev;
1508	#ifdef CONFIG_RAETH_NAPI
1509	#if defined (CONFIG_RAETH_ROUTER)
1510	netif_napi_add(dev, &ei_local->mac_napi, raeth_clean, 32);
1511	#elif defined (CONFIG_RT_3052_ESW)
1512	netif_napi_add(dev, &ei_local->mac_napi, raeth_clean, 32);
1513	#else
1514	netif_napi_add(dev, &ei_local->mac_napi, raeth_clean, 128);
1515	#endif
1516	#endif
1517	dev->mtu = 1500;
1518	}
1519
1520
1521	#define TX_TIMEOUT (2*HZ)
1522	void ei_tx_timeout(struct net_device *dev)
1523	{
1524	END_DEVICE* ei_local = netdev_priv(dev);
1525	#ifndef WORKQUEUE_BH
1526	tasklet_schedule(&ei_local->tx_tasklet);
1527	#endif // WORKQUEUE_BH //
1528	return;
1529	}
1530
1531	void setup_statistics(END_DEVICE* ei_local)
1532	{
1533	ei_local->stat.tx_packets = 0;
1534	ei_local->stat.tx_bytes = 0;
1535	ei_local->stat.tx_dropped = 0;
1536	ei_local->stat.tx_errors = 0;
1537	ei_local->stat.tx_aborted_errors= 0;
1538	ei_local->stat.tx_carrier_errors= 0;
1539	ei_local->stat.tx_fifo_errors = 0;
1540	ei_local->stat.tx_heartbeat_errors = 0;
1541	ei_local->stat.tx_window_errors = 0;
1542
1543	ei_local->stat.rx_packets = 0;
1544	ei_local->stat.rx_bytes = 0;
1545	ei_local->stat.rx_dropped = 0;
1546	ei_local->stat.rx_errors = 0;
1547	ei_local->stat.rx_length_errors = 0;
1548	ei_local->stat.rx_over_errors = 0;
1549	ei_local->stat.rx_crc_errors = 0;
1550	ei_local->stat.rx_frame_errors = 0;
1551	ei_local->stat.rx_fifo_errors = 0;
1552	ei_local->stat.rx_missed_errors = 0;
1553
1554	ei_local->stat.collisions = 0;
1555	#if defined (CONFIG_RAETH_QOS)
1556	ei_local->tx3_full = 0;
1557	ei_local->tx2_full = 0;
1558	ei_local->tx1_full = 0;
1559	ei_local->tx0_full = 0;
1560	#else
1561	ei_local->tx_full = 0;
1562	#endif
1563	#ifdef CONFIG_RAETH_NAPI
1564	atomic_set(&ei_local->irq_sem, 1);
1565	#endif
1566
1567	}
1568
1569	/**
1570	* rather_probe - pick up ethernet port at boot time
1571	* @dev: network device to probe
1572	*
1573	* This routine probe the ethernet port at boot time.
1574	*
1575	*
1576	*/
1577
1578	int __init rather_probe(struct net_device *dev)
1579	{
1580	int i;
1581	u32 val;
1582	END_DEVICE *ei_local = netdev_priv(dev);
1583	struct sockaddr addr;
1584	unsigned char zero[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};
1585	/* reset frame engine */
1586	val = sysRegRead(RSTCTRL);
1587
1588	// RT5350 need to reset ESW and FE at the same to avoid PDMA panic //
1589	#if defined (CONFIG_RALINK_RT5350)
1590	val = val \| RALINK_FE_RST \| RALINK_ESW_RST ;
1591	#else
1592	val = val \| RALINK_FE_RST;
1593	#endif
1594	sysRegWrite(RSTCTRL, val);
1595	#if defined (CONFIG_RALINK_RT5350)
1596	val = val & ~(RALINK_FE_RST \| RALINK_ESW_RST);
1597	#else
1598	val = val & ~(RALINK_FE_RST);
1599	#endif
1600	sysRegWrite(RSTCTRL, val);
1601	//Get mac0 address from flash
1602	#ifdef RA_MTD_RW_BY_NUM
1603	i = ra_mtd_read(2, GMAC0_OFFSET, 6, addr.sa_data);
1604	#else
1605	i = ra_mtd_read_nm("Factory", GMAC0_OFFSET, 6, addr.sa_data);
1606	#endif
1607
1608	//If reading mtd failed or mac0 is empty, generate a mac address
1609	if (i < 0 \|\| (memcmp(addr.sa_data, zero, 6) == 0)) {
1610	unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
1611	net_srandom(jiffies);
1612	memcpy(addr.sa_data, mac_addr01234, 5);
1613	addr.sa_data[5] = net_random()&0xFF;
1614	}
1615
1616	ei_set_mac_addr(dev, &addr);
1617	spin_lock_init(&ei_local->page_lock);
1618	ether_setup(dev);
1619
1620	dev->watchdog_timeo = TX_TIMEOUT;
1621
1622	setup_statistics(ei_local);
1623
1624	return 0;
1625	}
1626
1627	#ifdef WORKQUEUE_BH
1628	void ei_xmit_housekeeping_workq(struct work_struct *work)
1629	#else
1630	void ei_xmit_housekeeping(unsigned long unused)
1631	#endif // WORKQUEUE_BH //
1632	{
1633	struct net_device *dev = dev_raether;
1634	END_DEVICE *ei_local = netdev_priv(dev);
1635	struct PDMA_txdesc *tx_desc;
1636	unsigned long skb_free_idx;
1637	unsigned long tx_dtx_idx;
1638	#ifndef CONFIG_RAETH_NAPI
1639	unsigned long reg_int_mask=0;
1640	#endif
1641
1642	#ifdef CONFIG_RAETH_QOS
1643	int i;
1644	for (i=0;i<NUM_TX_RINGS;i++){
1645	skb_free_idx = ei_local->free_idx[i];
1646	if((ei_local->skb_free[i][skb_free_idx])==0){
1647	continue;
1648	}
1649
1650	get_tx_desc_and_dtx_idx(ei_local, i, &tx_dtx_idx, &tx_desc);
1651
1652	while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[i][skb_free_idx])!=0 ){
1653
1654	dev_kfree_skb_irq((ei_local->skb_free[i][skb_free_idx]));
1655	ei_local->skb_free[i][skb_free_idx]=0;
1656	skb_free_idx++;
1657	if(skb_free_idx >= NUM_TX_DESC)
1658	skb_free_idx =0;
1659	}
1660	ei_local->free_idx[i] = skb_free_idx;
1661	}
1662	#else
1663	tx_dtx_idx = (unsigned long)TX_DTX_IDX0;
1664	tx_desc = ei_local->tx_ring0;
1665	skb_free_idx = ei_local->free_idx;
1666	if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
1667	while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
1668	dev_kfree_skb_irq((ei_local->skb_free[skb_free_idx]));
1669	ei_local->skb_free[skb_free_idx]=0;
1670	skb_free_idx++;
1671	if(skb_free_idx >= NUM_TX_DESC)
1672	skb_free_idx =0;
1673	}
1674	netif_wake_queue(dev);
1675	#ifdef CONFIG_PSEUDO_SUPPORT
1676	netif_wake_queue(ei_local->PseudoDev);
1677	#endif
1678	tx_ring_full=0;
1679	ei_local->free_idx = skb_free_idx;
1680	} /* if skb_free != 0 */
1681	#endif
1682
1683	#ifndef CONFIG_RAETH_NAPI
1684	reg_int_mask=sysRegRead(FE_INT_ENABLE);
1685	#if defined (DELAY_INT)
1686	sysRegWrite(FE_INT_ENABLE, reg_int_mask\| TX_DLY_INT);
1687	#else
1688
1689	sysRegWrite(FE_INT_ENABLE, reg_int_mask \| TX_DONE_INT0 \
1690	\| TX_DONE_INT1 \
1691	\| TX_DONE_INT2 \
1692	\| TX_DONE_INT3);
1693	#endif
1694	#endif //CONFIG_RAETH_NAPI//
1695	}
1696
1697
1698	#ifdef CONFIG_PSEUDO_SUPPORT
1699	int VirtualIF_ioctl(struct net_device * net_dev,
1700	struct ifreq * ifr, int cmd)
1701	{
1702	ra_mii_ioctl_data mii;
1703
1704	switch (cmd) {
1705	case RAETH_MII_READ:
1706	copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
1707	mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
1708	//printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out);
1709	copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
1710	break;
1711
1712	case RAETH_MII_WRITE:
1713	copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
1714	//printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in);
1715	mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
1716	break;
1717	default:
1718	return -EOPNOTSUPP;
1719	}
1720
1721	return 0;
1722	}
1723
1724	struct net_device_stats VirtualIF_get_stats(struct net_device dev)
1725	{
1726	PSEUDO_ADAPTER *pAd = netdev_priv(dev);
1727	return &pAd->stat;
1728	}
1729
1730	int VirtualIF_open(struct net_device * dev)
1731	{
1732	PSEUDO_ADAPTER *pPesueoAd = dev->priv;
1733
1734	printk("%s: ===> VirtualIF_open\n", dev->name);
1735
1736	netif_start_queue(pPesueoAd->PseudoDev);
1737
1738	return 0;
1739	}
1740
1741	int VirtualIF_close(struct net_device * dev)
1742	{
1743	PSEUDO_ADAPTER *pPesueoAd = dev->priv;
1744
1745	printk("%s: ===> VirtualIF_close\n", dev->name);
1746
1747	netif_stop_queue(pPesueoAd->PseudoDev);
1748
1749	return 0;
1750	}
1751
1752	int VirtualIFSendPackets(struct sk_buff * pSkb,
1753	struct net_device * dev)
1754	{
1755	PSEUDO_ADAPTER *pPesueoAd = dev->priv;
1756
1757	//printk("VirtualIFSendPackets --->\n");
1758
1759	if (!(pPesueoAd->RaethDev->flags & IFF_UP)) {
1760	dev_kfree_skb_any(pSkb);
1761	return 0;
1762	}
1763	//pSkb->cb[40]=0x5a;
1764	pSkb->dev = pPesueoAd->RaethDev;
1765	ei_start_xmit(pSkb, pPesueoAd->RaethDev, 2);
1766	return 0;
1767	}
1768
1769	void virtif_setup_statistics(PSEUDO_ADAPTER* pAd)
1770	{
1771	pAd->stat.tx_packets = 0;
1772	pAd->stat.tx_bytes = 0;
1773	pAd->stat.tx_dropped = 0;
1774	pAd->stat.tx_errors = 0;
1775	pAd->stat.tx_aborted_errors= 0;
1776	pAd->stat.tx_carrier_errors= 0;
1777	pAd->stat.tx_fifo_errors = 0;
1778	pAd->stat.tx_heartbeat_errors = 0;
1779	pAd->stat.tx_window_errors = 0;
1780
1781	pAd->stat.rx_packets = 0;
1782	pAd->stat.rx_bytes = 0;
1783	pAd->stat.rx_dropped = 0;
1784	pAd->stat.rx_errors = 0;
1785	pAd->stat.rx_length_errors = 0;
1786	pAd->stat.rx_over_errors = 0;
1787	pAd->stat.rx_crc_errors = 0;
1788	pAd->stat.rx_frame_errors = 0;
1789	pAd->stat.rx_fifo_errors = 0;
1790	pAd->stat.rx_missed_errors = 0;
1791
1792	pAd->stat.collisions = 0;
1793	}
1794
1795	// Register pseudo interface
1796	void RAETH_Init_PSEUDO(pEND_DEVICE pAd, struct net_device *net_dev)
1797	{
1798	int index;
1799	struct net_device *dev;
1800	PSEUDO_ADAPTER *pPseudoAd;
1801	int i = 0;
1802	char slot_name[16];
1803	struct net_device *device;
1804	struct sockaddr addr;
1805	unsigned char zero[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};
1806
1807	for (index = 0; index < MAX_PSEUDO_ENTRY; index++) {
1808
1809	dev = alloc_etherdev(sizeof(PSEUDO_ADAPTER));
1810
1811	{ // find available
1812	for (i = 3; i < 32; i++) {
1813	sprintf(slot_name, "eth%d", i);
1814
1815	device = net_device_entry(&dev_base_head);
1816	for_each_netdev_continue(device)
1817	{
1818	if (strncmp(device->name, slot_name, 4) == 0) {
1819	break;
1820	}
1821	}
1822
1823	if (device == NULL)
1824	break;
1825	}
1826
1827	if (i != 32) {
1828	sprintf(dev->name, "eth%d", i);
1829	} else {
1830	printk("Ethernet interface number overflow...\n");
1831	break;
1832	}
1833	}
1834
1835	//Get mac2 address from flash
1836	#ifdef RA_MTD_RW_BY_NUM
1837	i = ra_mtd_read(2, GMAC2_OFFSET, 6, addr.sa_data);
1838	#else
1839	i = ra_mtd_read_nm("Factory", GMAC2_OFFSET, 6, addr.sa_data);
1840	#endif
1841
1842	//If reading mtd failed or mac0 is empty, generate a mac address
1843	if (i < 0 \|\| (memcmp(addr.sa_data, zero, 6) == 0)) {
1844	unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
1845	net_srandom(jiffies);
1846	memcpy(addr.sa_data, mac_addr01234, 5);
1847	addr.sa_data[5] = net_random()&0xFF;
1848	}
1849
1850	ei_set_mac2_addr(dev, &addr);
1851	ether_setup(dev);
1852	pPseudoAd = dev->priv;
1853
1854	pPseudoAd->PseudoDev = dev;
1855	pPseudoAd->RaethDev = net_dev;
1856	virtif_setup_statistics(pPseudoAd);
1857	pAd->PseudoDev = dev;
1858
1859	dev->hard_start_xmit = VirtualIFSendPackets;
1860	dev->stop = VirtualIF_close;
1861	dev->open = VirtualIF_open;
1862	dev->do_ioctl = VirtualIF_ioctl;
1863	dev->set_mac_address = ei_set_mac2_addr;
1864	dev->get_stats = VirtualIF_get_stats;
1865	dev->change_mtu = ei_change_mtu;
1866	dev->mtu = 1500;
1867	#if defined (CONFIG_ETHTOOL)
1868	dev->ethtool_ops = &ra_virt_ethtool_ops;
1869	// init mii structure
1870	pPseudoAd->mii_info.dev = dev;
1871	pPseudoAd->mii_info.mdio_read = mdio_virt_read;
1872	pPseudoAd->mii_info.mdio_write = mdio_virt_write;
1873	pPseudoAd->mii_info.phy_id_mask = 0x1f;
1874	pPseudoAd->mii_info.reg_num_mask = 0x1f;
1875	pPseudoAd->mii_info.phy_id = 0x1e;
1876	pPseudoAd->mii_info.supports_gmii = mii_check_gmii_support(&pPseudoAd->mii_info);
1877	#endif
1878
1879	// Register this device
1880	register_netdevice(dev);
1881	}
1882	}
1883	#endif
1884
1885
1886
1887	/**
1888	* ei_open - Open/Initialize the ethernet port.
1889	* @dev: network device to initialize
1890	*
1891	* This routine goes all-out, setting everything
1892	* up a new at each open, even though many of these registers should only need to be set once at boot.
1893	*/
1894	int ei_open(struct net_device *dev)
1895	{
1896	int i,err;
1897	unsigned long flags;
1898	END_DEVICE *ei_local;
1899	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
1900	if (!try_module_get(THIS_MODULE))
1901	{
1902	printk("%s: Cannot reserve module\n", __FUNCTION__);
1903	return -1;
1904	}
1905	#else
1906	MOD_INC_USE_COUNT;
1907	#endif
1908
1909	ei_local = netdev_priv(dev); // get device pointer from System
1910	// unsigned int flags;
1911
1912	if (ei_local == NULL)
1913	{
1914	printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
1915	return -ENXIO;
1916	}
1917
1918	/* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
1919	for ( i = 0; i < NUM_RX_DESC; i++)
1920	{
1921	ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH);
1922	if (ei_local->netrx0_skbuf[i] == NULL )
1923	printk("rx skbuff buffer allocation failed!");
1924	skb_reserve(ei_local->netrx0_skbuf[i], 2);
1925	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
1926	ei_local->netrx1_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH);
1927	if (ei_local->netrx1_skbuf[i] == NULL )
1928	printk("rx1 skbuff buffer allocation failed!");
1929	skb_reserve(ei_local->netrx1_skbuf[i], 2);
1930	#endif
1931	} // kmalloc
1932
1933	// spin_lock_irqsave(&(ei_local->page_lock), flags);
1934	err = request_irq( dev->irq, ei_interrupt, IRQF_DISABLED, dev->name, dev); // try to fix irq in open
1935	if (err)
1936	{
1937	printk("unable to request ETH irq %d\n",dev->irq);
1938
1939	}
1940	rt2880_eth_setup(dev);
1941
1942	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
1943	//INTENA: Interrupt enabled for ESW
1944	//((volatile u32 )(RALINK_INTCL_BASE + 0x34)) = (1<<17);
1945	//((volatile u32 )(RALINK_INTCL_BASE + 0x38)) = (1<<17);
1946	//((volatile u32 )(RALINK_ETH_SW_BASE + 0x04)) &= ~(ESW_INT_ALL);
1947	//((volatile u32 )(RALINK_ETH_SW_BASE + 0x04)) = 0;
1948
1949	((volatile u32 )(RALINK_INTCL_BASE + 0x34)) = (1<<17);
1950	((volatile u32 )(RALINK_ETH_SW_BASE + 0x04)) &= ~(ESW_INT_ALL);
1951	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
1952	INIT_WORK(&ei_local->kill_sig_wq, kill_sig_workq);
1953	#endif
1954	err = request_irq(SURFBOARDINT_ESW, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
1955	if (err)
1956	{
1957	printk("unable to request ESW irq %d\n",SURFBOARDINT_ESW);
1958
1959	}
1960
1961	#endif // CONFIG_RALINK_RT3052 \|\| CONFIG_RALINK_RT3352 \|\| CONFIG_RALINK_RT5350 //
1962
1963
1964	#ifdef DELAY_INT
1965	sysRegWrite(DLY_INT_CFG, DELAY_INT_INIT);
1966	sysRegWrite(FE_INT_ENABLE, FE_INT_DLY_INIT);
1967	#else
1968	sysRegWrite(FE_INT_ENABLE, FE_INT_ALL);
1969	#endif
1970
1971	#ifdef WORKQUEUE_BH
1972	INIT_WORK(&ei_local->tx_wq, ei_xmit_housekeeping_workq);
1973	#ifndef CONFIG_RAETH_NAPI
1974	INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
1975	#endif // CONFIG_RAETH_NAPI //
1976	#else
1977	tasklet_init(&ei_local->tx_tasklet, ei_xmit_housekeeping , 0);
1978	#ifndef CONFIG_RAETH_NAPI
1979	tasklet_init(&ei_local->rx_tasklet, ei_receive, 0);
1980	#endif // CONFIG_RAETH_NAPI //
1981	#endif // WORKQUEUE_BH //
1982
1983	netif_start_queue(dev);
1984
1985	#ifdef CONFIG_RAETH_NAPI
1986	atomic_dec(&ei_local->irq_sem);
1987	napi_enable(&ei_local->mac_napi);
1988	#endif
1989
1990	// spin_unlock_irqrestore(&(ei_local->page_lock), flags);
1991	#ifdef CONFIG_PSEUDO_SUPPORT
1992	if(ei_local->PseudoDev==NULL) {
1993	RAETH_Init_PSEUDO(ei_local, dev);
1994	}
1995
1996	VirtualIF_open(ei_local->PseudoDev);
1997	#endif
1998	forward_config(dev);
1999	return 0;
2000	}
2001
2002	/**
2003	* ei_close - shut down network device
2004	* @dev: network device to clear
2005	*
2006	* This routine shut down network device.
2007	*
2008	*
2009	*/
2010	int ei_close(struct net_device *dev)
2011	{
2012	int i;
2013	END_DEVICE *ei_local = netdev_priv(dev); // device pointer
2014	unsigned long flags;
2015	spin_lock_irqsave(&(ei_local->page_lock), flags);
2016
2017	#ifdef CONFIG_PSEUDO_SUPPORT
2018	VirtualIF_close(ei_local->PseudoDev);
2019	#endif
2020
2021	netif_stop_queue(dev);
2022	ra2880stop(ei_local);
2023	msleep(10);
2024
2025	#ifndef WORKQUEUE_BH
2026	tasklet_kill(&ei_local->tx_tasklet);
2027	tasklet_kill(&ei_local->rx_tasklet);
2028	#endif // WORKQUEUE_BH //
2029
2030	free_irq(dev->irq, dev);
2031
2032	for ( i = 0; i < NUM_RX_DESC; i++)
2033	{
2034	if (ei_local->netrx0_skbuf[i] != NULL) {
2035	dev_kfree_skb(ei_local->netrx0_skbuf[i]);
2036	ei_local->netrx0_skbuf[i] = NULL;
2037	}
2038	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
2039	if (ei_local->netrx1_skbuf[i] != NULL) {
2040	dev_kfree_skb(ei_local->netrx1_skbuf[i]);
2041	ei_local->netrx1_skbuf[i] = NULL;
2042	}
2043	#endif
2044	}
2045
2046
2047	#if defined (CONFIG_RAETH_QOS)
2048	if (ei_local->tx_ring0 != NULL) {
2049	pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
2050	}
2051
2052	if (ei_local->tx_ring1 != NULL) {
2053	pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring1, ei_local->phy_tx_ring1);
2054	}
2055
2056	#if defined (CONFIG_RALINK_RT2883) \|\| defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined(CONFIG_RALINK_RT3883) \|\| defined(CONFIG_RALINK_RT5350)
2057	if (ei_local->tx_ring2 != NULL) {
2058	pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring2, ei_local->phy_tx_ring2);
2059	}
2060
2061	if (ei_local->tx_ring3 != NULL) {
2062	pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring3, ei_local->phy_tx_ring3);
2063	}
2064	#endif
2065	#else
2066	pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
2067	#endif
2068	pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), rx_ring, ei_local->phy_rx_ring0);
2069	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
2070	pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), rx_ring, ei_local->phy_rx_ring1);
2071	#endif
2072
2073	printk("Free TX/RX Ring Memory!\n");
2074
2075	#ifdef CONFIG_RAETH_NAPI
2076	atomic_inc(&ei_local->irq_sem);
2077	napi_disable(&ei_local->mac_napi);
2078	#endif
2079	spin_unlock_irqrestore(&(ei_local->page_lock), flags);
2080
2081	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2082	module_put(THIS_MODULE);
2083	#else
2084	MOD_DEC_USE_COUNT;
2085	#endif
2086	return 0;
2087	}
2088
2089	#if defined (CONFIG_RALINK_RT3052) \|\| defined (CONFIG_RALINK_RT3352) \|\| defined (CONFIG_RALINK_RT5350)
2090	void rt305x_esw_init(void)
2091	{
2092	int i=0;
2093	u32 phy_val=0, val=0;
2094	#if defined (CONFIG_RT3052_ASIC)
2095	u32 phy_val2;
2096	#endif
2097
2098	#if defined (CONFIG_RT5350_ASIC)
2099	(unsigned long )(0xb0110168) = 0x17;
2100	#endif
2101
2102	/*
2103	* FC_RLS_TH=200, FC_SET_TH=160
2104	* DROP_RLS=120, DROP_SET_TH=80
2105	*/
2106	(unsigned long )(0xb0110008) = 0xC8A07850;
2107	(unsigned long )(0xb01100E4) = 0x00000000;
2108	(unsigned long )(0xb0110014) = 0x00405555;
2109	(unsigned long )(0xb0110050) = 0x00002001;
2110	(unsigned long )(0xb0110090) = 0x00007f7f;
2111	(unsigned long )(0xb0110098) = 0x00007f3f; //disable VLAN
2112	(unsigned long )(0xb01100CC) = 0x0002500c;
2113	(unsigned long )(0xb011009C) = 0x0008a301; //hashing algorithm=XOR48, aging interval=300sec
2114	(unsigned long )(0xb011008C) = 0x02404040;
2115	#if defined (CONFIG_RT3052_ASIC) \|\| defined (CONFIG_RT3352_ASIC) \|\| defined (CONFIG_RT5350_ASIC)
2116	(unsigned long )(0xb01100C8) = 0x3f502b28; //Change polling Ext PHY Addr=0x1F
2117	(unsigned long )(0xb0110084) = 0x00000000;
2118	(unsigned long )(0xb0110110) = 0x7d000000; //1us cycle number=125 (FE's clock=125Mhz)
2119	#elif defined (CONFIG_RT3052_FPGA) \|\| defined (CONFIG_RT3352_FPGA) \|\| defined (CONFIG_RT5350_FPGA)
2120	(unsigned long )(0xb01100C8) = 0x20f02b28; //Change polling Ext PHY Addr=0x0
2121	(unsigned long )(0xb0110084) = 0xffdf1f00;
2122	(unsigned long )(0xb0110110) = 0x0d000000; //1us cycle number=13 (FE's clock=12.5Mhz)
2123
2124	/* In order to use 10M/Full on FPGA board. We configure phy capable to
2125	* 10M Full/Half duplex, so we can use auto-negotiation on PC side */
2126	for(i=0;i<5;i++){
2127	mii_mgr_write(i, 4, 0x0461); //Capable of 10M Full/Half Duplex, flow control on/off
2128	mii_mgr_write(i, 0, 0xB100); //reset all digital logic, except phy_reg
2129	}
2130	#endif
2131
2132	/*
2133	* set port 5 force to 1000M/Full when connecting to switch or iNIC
2134	*/
2135	#if defined (CONFIG_P5_RGMII_TO_MAC_MODE)
2136	(unsigned long )(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
2137	(unsigned long )(0xb01100C8) &= ~(1<<29); //disable port 5 auto-polling
2138	(unsigned long )(0xb01100C8) \|= 0x3fff; //force 1000M full duplex
2139	(unsigned long )(0xb01100C8) &= ~(0xf<<20); //rxclk_skew, txclk_skew = 0
2140	#elif defined (CONFIG_P5_MII_TO_MAC_MODE)
2141	(unsigned long )(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
2142	(unsigned long )(0xb01100C8) &= ~(1<<29); //disable port 5 auto-polling
2143	(unsigned long )(0xb01100C8) &= ~(0x3fff);
2144	(unsigned long )(0xb01100C8) \|= 0x3ffd; //force 100M full duplex
2145	#elif defined (CONFIG_P5_MAC_TO_PHY_MODE)
2146	(unsigned long )(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
2147	(unsigned long )(0xb0000060) &= ~(1 << 7); //set MDIO to Normal mode
2148	enable_auto_negotiate(1);
2149	if (isMarvellGigaPHY2(1)) {
2150	mii_mgr_read(0x14,0, &regValue);
2151	regValue &= ~(1<<11); //power up
2152	mii_mgr_write(0x14,0, regValue);
2153
2154	u32 regValue = sysRegRead(MDIO_CFG);
2155	u32 addr = 0x14;
2156	regValue &= 0xe0ff7fff; // clear auto polling related field:
2157	// (MD_PHY1ADDR & GP1_FRC_EN).
2158	regValue \|= 0x20000000; // force to enable MDC/MDIO auto polling.
2159	regValue \|= (addr << 24); // setup PHY address for auto polling.
2160
2161	sysRegWrite(MDIO_CFG, regValue);
2162
2163	wait_linkup();
2164	wait_an_completed();
2165	rt2880_mdio_cfg(0,15,1);
2166	mii_mgr_write(0x14,22,0x0003);
2167	mii_mgr_write(0x14,16,0x1011);
2168	mii_mgr_write(0x14,22,0x0000);
2169
2170	}
2171	if (isMarvellGigaPHY(1)) {
2172	#if defined (CONFIG_RT3052_FPGA) \|\| defined (CONFIG_RT3352_FPGA) \|\| defined (CONFIG_RT5350_FPGA)
2173	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &phy_val);
2174	phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half)
2175	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, phy_val);
2176	#endif
2177	printk("\n Reset MARVELL phy\n");
2178	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val);
2179	phy_val \|= 1<<7; //Add delay to RX_CLK for RXD Outputs
2180	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val);
2181
2182	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
2183	phy_val \|= 1<<15; //PHY Software Reset
2184	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
2185	}
2186	if (isVtssGigaPHY(1)) {
2187	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page
2188	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val);
2189	printk("Vitesse phy skew: %x --> ", phy_val);
2190	phy_val \|= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
2191	phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns
2192	printk("%x\n", phy_val);
2193	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val);
2194	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers
2195	}
2196
2197	#elif defined (CONFIG_P5_RMII_TO_MAC_MODE)
2198	(unsigned long )(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
2199	(unsigned long )(0xb01100C8) &= ~(1<<29); //disable port 5 auto-polling
2200	(unsigned long )(0xb01100C8) &= ~(0x3fff);
2201	(unsigned long )(0xb01100C8) \|= 0x3ffd; //force 100M full duplex
2202	#else // Port 5 Disabled //
2203	(unsigned long )(0xb01100C8) &= ~(1 << 29); //port5 auto polling disable
2204	(unsigned long )(0xb0000060) \|= (1 << 9); //set RGMII to GPIO mode (GPIO41-GPIO50)
2205	(unsigned long )(0xb0000674) = 0xFFF; //GPIO41-GPIO50 output mode
2206	(unsigned long )(0xb0000670) = 0x0; //GPIO41-GPIO50 output low
2207	#endif // CONFIG_P5_RGMII_TO_MAC_MODE //
2208
2209
2210	#if defined (CONFIG_RT3052_ASIC) \|\| defined (CONFIG_RT3352_ASIC) \|\| defined (CONFIG_RT5350_ASIC)
2211	//
2212	#if defined (CONFIG_RT3052_ASIC)
2213	rw_rf_reg(0, 0, &phy_val);
2214	phy_val = phy_val >> 4;
2215
2216	if(phy_val > 0x5) {
2217
2218	rw_rf_reg(0, 26, &phy_val);
2219	phy_val2 = (phy_val \| (0x3 << 5));
2220	rw_rf_reg(1, 26, &phy_val2);
2221
2222	// reset EPHY
2223	val = sysRegRead(RSTCTRL);
2224	val = val \| RALINK_EPHY_RST;
2225	sysRegWrite(RSTCTRL, val);
2226	val = val & ~(RALINK_EPHY_RST);
2227	sysRegWrite(RSTCTRL, val);
2228
2229	rw_rf_reg(1, 26, &phy_val);
2230
2231	//select local register
2232	mii_mgr_write(0, 31, 0x8000);
2233	for(i=0;i<5;i++){
2234	mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY
2235	mii_mgr_write(i, 29, 0x7015); //TX100/TX10 AD/DA current bias
2236	mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control
2237	}
2238
2239	//select global register
2240	mii_mgr_write(0, 31, 0x0);
2241	mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
2242	mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
2243	mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6
2244	mii_mgr_write(0, 12, 0x7eaa);
2245	mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length
2246	mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
2247	mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
2248	mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
2249	mii_mgr_write(0, 22, 0x252f); //tune TP_IDL tail and head waveform, enable power down slew rate control
2250	mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
2251	mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
2252	mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
2253	mii_mgr_write(0, 31, 0x8000); //select local register
2254
2255	for(i=0;i<5;i++){
2256	//LSB=1 enable PHY
2257	mii_mgr_read(i, 26, &phy_val);
2258	phy_val \|= 0x0001;
2259	mii_mgr_write(i, 26, phy_val);
2260	}
2261	} else {
2262	//select local register
2263	mii_mgr_write(0, 31, 0x8000);
2264	for(i=0;i<5;i++){
2265	mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY
2266	mii_mgr_write(i, 29, 0x7058); //TX100/TX10 AD/DA current bias
2267	mii_mgr_write(i, 30, 0x0018); //TX100 slew rate control
2268	}
2269
2270	//select global register
2271	mii_mgr_write(0, 31, 0x0);
2272	mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
2273	mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
2274	mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6
2275	mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length
2276	mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
2277	mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
2278	mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
2279	mii_mgr_write(0, 22, 0x052f); //tune TP_IDL tail and head waveform
2280	mii_mgr_write(0, 27, 0x2fce); //set PLL/Receive bias current are calibrated
2281	mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
2282	mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
2283	mii_mgr_write(0, 31, 0x8000); //select local register
2284
2285	for(i=0;i<5;i++){
2286	//LSB=1 enable PHY
2287	mii_mgr_read(i, 26, &phy_val);
2288	phy_val \|= 0x0001;
2289	mii_mgr_write(i, 26, phy_val);
2290	}
2291	}
2292	#elif defined (CONFIG_RT3352_ASIC)
2293	//PHY IOT
2294	// reset EPHY
2295	val = sysRegRead(RSTCTRL);
2296	val = val \| RALINK_EPHY_RST;
2297	sysRegWrite(RSTCTRL, val);
2298	val = val & ~(RALINK_EPHY_RST);
2299	sysRegWrite(RSTCTRL, val);
2300
2301	//select local register
2302	mii_mgr_write(0, 31, 0x8000);
2303	for(i=0;i<5;i++){
2304	mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY
2305	mii_mgr_write(i, 29, 0x7016); //TX100/TX10 AD/DA current bias
2306	mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control
2307	}
2308
2309	//select global register
2310	mii_mgr_write(0, 31, 0x0);
2311	mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
2312	mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
2313	mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6
2314	mii_mgr_write(0, 12, 0x7eaa);
2315	mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length
2316	mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
2317	mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
2318	mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
2319	mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control
2320	mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
2321	mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
2322	mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
2323	mii_mgr_write(0, 31, 0x8000); //select local register
2324
2325	for(i=0;i<5;i++){
2326	//LSB=1 enable PHY
2327	mii_mgr_read(i, 26, &phy_val);
2328	phy_val \|= 0x0001;
2329	mii_mgr_write(i, 26, phy_val);
2330	}
2331
2332	#elif defined (CONFIG_RT5350_ASIC)
2333	//PHY IOT
2334	// reset EPHY
2335	val = sysRegRead(RSTCTRL);
2336	val = val \| RALINK_EPHY_RST;
2337	sysRegWrite(RSTCTRL, val);
2338	val = val & ~(RALINK_EPHY_RST);
2339	sysRegWrite(RSTCTRL, val);
2340
2341	//select local register
2342	mii_mgr_write(0, 31, 0x8000);
2343	for(i=0;i<5;i++){
2344	mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY
2345	mii_mgr_write(i, 29, 0x7015); //TX100/TX10 AD/DA current bias
2346	mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control
2347	}
2348
2349	//select global register
2350	mii_mgr_write(0, 31, 0x0);
2351	mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
2352	mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
2353	mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6
2354	mii_mgr_write(0, 12, 0x7eaa);
2355	mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length
2356	mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
2357	mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
2358	mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
2359	mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control
2360	mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
2361	mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
2362	mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
2363	mii_mgr_write(0, 31, 0x8000); //select local register
2364
2365	for(i=0;i<5;i++){
2366	//LSB=1 enable PHY
2367	mii_mgr_read(i, 26, &phy_val);
2368	phy_val \|= 0x0001;
2369	mii_mgr_write(i, 26, phy_val);
2370	}
2371
2372	#else
2373	#error "Chip is not supported"
2374	#endif
2375
2376	#endif /* defined (CONFIG_RT3052_ASIC) \|\| defined (CONFIG_RT3352_ASIC) \|\| defined (CONFIG_RT5350_ASIC) */
2377
2378	}
2379	#endif
2380
2381	/**
2382	* ra2882eth_init - Module Init code
2383	*
2384	* Called by kernel to register net_device
2385	*
2386	*/
2387	int __init ra2882eth_init(void)
2388	{
2389	int ret=0;
2390	struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
2391	#if defined (CONFIG_GIGAPHY) \|\| defined (CONFIG_RAETH_ROUTER) \|\| defined (CONFIG_100PHY)
2392	unsigned int regValue = 0;
2393	#endif
2394	#if defined (CONFIG_RTL8366_SWITCH)
2395	extern int rtl_smi_init(void);
2396	rtl_smi_init();
2397	udelay(500);
2398	#endif
2399	#if defined (CONFIG_RTL8366RB_SWITCH)
2400	extern int rtl_smi_init(void);
2401	rtl_smi_init();
2402	udelay(500);
2403	#endif
2404
2405	#ifdef CONFIG_RALINK_VISTA_BASIC
2406	int sw_id=0;
2407	mii_mgr_read(29, 31, &sw_id);
2408	is_switch_175c = (sw_id == 0x175c) ? 1:0;
2409	#endif
2410
2411	if (!dev)
2412	return -ENOMEM;
2413
2414	strcpy(dev->name, DEV_NAME);
2415	dev->irq = IRQ_ENET0;
2416	dev->addr_len = 6;
2417	dev->base_addr = RALINK_FRAME_ENGINE_BASE;
2418
2419	ra2880_setup_dev_fptable(dev);
2420
2421	/* net_device structure Init */
2422	hard_init(dev);
2423	printk("Ralink APSoC Ethernet Driver Initilization. %s %d rx/tx descriptors allocated, mtu = %d!\n", RAETH_VERSION, NUM_RX_DESC, dev->mtu);
2424	#ifdef CONFIG_RAETH_NAPI
2425	printk("NAPI enable, Tx Ring = %d, Rx Ring = %d\n", NUM_TX_DESC, NUM_RX_DESC);
2426	#endif
2427
2428	/* Register net device for the driver */
2429	if ( register_netdev(dev) != 0) {
2430	printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
2431	return -ENXIO;
2432	}
2433
2434	#ifdef CONFIG_RAETH_NETLINK
2435	csr_netlink_init();
2436	#endif
2437	// ret = debug_proc_init();
2438
2439	// Case1: RT288x/RT3883 GE1 + GigaPhy
2440	#if defined (CONFIG_GE1_RGMII_AN)
2441	enable_auto_negotiate(1);
2442
2443
2444	if (isMarvellGigaPHY2(1)) {
2445	mii_mgr_read(0x14,0, &regValue);
2446	regValue &= ~(1<<11); //power up
2447	mii_mgr_write(0x14,0, regValue);
2448
2449	u32 regValue = sysRegRead(MDIO_CFG);
2450	u32 addr = 0x14;
2451	regValue &= 0xe0ff7fff; // clear auto polling related field:
2452	// (MD_PHY1ADDR & GP1_FRC_EN).
2453	regValue \|= 0x20000000; // force to enable MDC/MDIO auto polling.
2454	regValue \|= (addr << 24); // setup PHY address for auto polling.
2455
2456	sysRegWrite(MDIO_CFG, regValue);
2457
2458	wait_linkup();
2459	wait_an_completed();
2460	rt2880_mdio_cfg(0,15,1);
2461	mii_mgr_write(0x14,22,0x0003);
2462	mii_mgr_write(0x14,16,0x1011);
2463	mii_mgr_write(0x14,22,0x0000);
2464
2465	}
2466
2467	if (isMarvellGigaPHY(1)) {
2468	#if defined (CONFIG_RT3883_FPGA)
2469	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &regValue);
2470	regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half)
2471	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, regValue);
2472	#endif
2473	printk("\n Reset MARVELL phy\n");
2474	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &regValue);
2475	regValue \|= 1<<7; //Add delay to RX_CLK for RXD Outputs
2476	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, regValue);
2477
2478	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &regValue);
2479	regValue \|= 1<<15; //PHY Software Reset
2480	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, regValue);
2481
2482	}
2483	if (isVtssGigaPHY(1)) {
2484	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 1);
2485	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &regValue);
2486	printk("Vitesse phy skew: %x --> ", regValue);
2487	regValue \|= (0x3<<12);
2488	regValue &= ~(0x3<<14);
2489	printk("%x\n", regValue);
2490	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, regValue);
2491	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0);
2492	}
2493	#endif // CONFIG_GE1_RGMII_AN //
2494
2495	// Case2: RT3883 GE2 + GigaPhy
2496	#if defined (CONFIG_GE2_RGMII_AN)
2497	enable_auto_negotiate(2);
2498	if (isMarvellGigaPHY(2)) {
2499	#if defined (CONFIG_RT3883_FPGA)
2500	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, &regValue);
2501	regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half)
2502	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, regValue);
2503	#endif
2504	printk("\n GMAC2 Reset MARVELL phy\n");
2505	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, &regValue);
2506	regValue \|= 1<<7; //Add delay to RX_CLK for RXD Outputs
2507	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, regValue);
2508
2509	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &regValue);
2510	regValue \|= 1<<15; //PHY Software Reset
2511	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, regValue);
2512
2513	}
2514	if (isVtssGigaPHY(2)) {
2515	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 1);
2516	mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, &regValue);
2517	printk("Vitesse phy skew: %x --> ", regValue);
2518	regValue \|= (0x3<<12);
2519	regValue &= ~(0x3<<14);
2520	printk("%x\n", regValue);
2521	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, regValue);
2522	mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0);
2523	}
2524	#endif // CONFIG_GE2_RGMII_AN //
2525
2526	// Case3: RT305x/RT335x + EmbeddedSW
2527	#if defined (CONFIG_GIGAPHY)
2528	#if defined (CONFIG_RT_3052_ESW)
2529	rt305x_esw_init();
2530	// RT2880 + GigaSW
2531	#elif defined (CONFIG_MAC_TO_MAC_MODE)
2532	// force cpu port is 1000F
2533	sysRegWrite(MDIO_CFG, 0x1F01DC01);
2534
2535	// RT2880 + 100PHY
2536	#elif defined (CONFIG_RTL8366_SWITCH)
2537
2538	printk("Rtl8366 Phy Init...\n");
2539	sysRegWrite(MDIO_CFG, 0x0000dc01);
2540	#elif defined (CONFIG_RTL8366RB_SWITCH)
2541
2542	printk("Rtl8366RB Phy Init...\n");
2543	// sysRegWrite(MDIO_CFG, 0x0000dc01);
2544
2545	#elif defined (CONFIG_RAETH_ROUTER) \|\| defined (CONFIG_ICPLUS_PHY)
2546
2547	sysRegWrite(MDIO_CFG, INIT_VALUE_OF_ICPLUS_PHY_INIT_VALUE);
2548
2549	#elif CONFIG_RALINK_VISTA_BASIC
2550	int sw_id=0;
2551	mii_mgr_read(29, 31, &sw_id);
2552	if (sw_id == 0x175c) {
2553	is_switch_175c = 1;
2554	} else {
2555	is_switch_175c = 0;
2556	}
2557	#endif // CONFIG_RALINK_VISTA_BASIC
2558
2559	// due to the flaws of RT2880 GMAC implementation (or IC+ SW ?) we use the
2560	// fixed capability instead of auto-polling.
2561	// force cpu port is 100F
2562	mii_mgr_write(29, 22, 0x8420);
2563	#endif // CONFIG_GIGAPHY //
2564	// Case4: RT288x/RT388x GE1 + GigaSW
2565	#if defined (CONFIG_GE1_RGMII_FORCE_1000)
2566	sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_1000_FD);
2567	#endif
2568
2569	// Case5: RT388x GE2 + GigaSW
2570	#if defined (CONFIG_GE2_RGMII_FORCE_1000)
2571	sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_1000_FD);
2572	#endif
2573
2574
2575	// Case6: RT288x GE1 /RT388x GE1/GE2 + (10/100 Switch or 100PHY)
2576	#if defined (CONFIG_RAETH_ROUTER) \|\| defined (CONFIG_100PHY)
2577
2578	//set GMAC to MII or RvMII mode
2579	#if defined (CONFIG_RALINK_RT3883)
2580	regValue = sysRegRead(SYSCFG1);
2581	#if defined (CONFIG_GE1_MII_FORCE_100) \|\| defined (CONFIG_GE1_MII_AN)
2582	regValue &= ~(0x3 << 12);
2583	regValue \|= 0x1 << 12; // GE1 MII Mode
2584	#elif defined (CONFIG_GE1_RVMII_FORCE_100)
2585	regValue &= ~(0x3 << 12);
2586	regValue \|= 0x2 << 12; // GE1 RvMII Mode
2587	#endif
2588
2589	#if defined (CONFIG_GE2_MII_FORCE_100) \|\| defined (CONFIG_GE2_MII_AN)
2590	regValue &= ~(0x3 << 14);
2591	regValue \|= 0x1 << 14; // GE2 MII Mode
2592	#elif defined (CONFIG_GE2_RVMII_FORCE_100)
2593	regValue &= ~(0x3 << 14);
2594	regValue \|= 0x2 << 14; // GE2 RvMII Mode
2595	#endif
2596	sysRegWrite(SYSCFG1, regValue);
2597	#endif // CONFIG_RALINK_RT3883 //
2598
2599	#if defined (CONFIG_GE1_MII_FORCE_100)
2600	sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_100_FD);
2601	#endif
2602	#if defined (CONFIG_GE2_MII_FORCE_100)
2603	sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_100_FD);
2604	#endif
2605	//add switch configuration here for other switch chips.
2606	#if defined (CONFIG_GE1_MII_FORCE_100) \|\| defined (CONFIG_GE2_MII_FORCE_100)
2607	// IC+ 175x: force IC+ switch cpu port is 100/FD
2608	mii_mgr_write(29, 22, 0x8420);
2609	#endif
2610
2611	#if defined (CONFIG_GE1_MII_AN)
2612	enable_auto_negotiate(1);
2613	#endif
2614	#if defined (CONFIG_GE2_MII_AN)
2615	enable_auto_negotiate(2);
2616	#endif
2617
2618	#endif // defined (CONFIG_RAETH_ROUTER) \|\| defined (CONFIG_100PHY) //
2619
2620
2621	dev_raether = dev;
2622	return ret;
2623	}
2624
2625	/**
2626	* ra2882eth_cleanup_module - Module Exit code
2627	*
2628	* Cmd 'rmmod' will invode the routine to exit the module
2629	*
2630	*/
2631	void ra2882eth_cleanup_module(void)
2632	{
2633	int i;
2634	struct net_device *dev = dev_raether;
2635	END_DEVICE *ei_local;
2636
2637	ei_local = netdev_priv(dev);
2638	if ( ei_local->MACInfo != NULL ) {
2639	RAETH_PRINT("Free MACInfo...\n");
2640	kfree(ei_local->MACInfo);
2641	} else {
2642	RAETH_PRINT("MACInfo is null\n");
2643	}
2644
2645	#ifdef CONFIG_PSEUDO_SUPPORT
2646	kfree(ei_local->PseudoDev->priv);
2647	unregister_netdev(ei_local->PseudoDev);
2648	#endif
2649	kfree(ei_local);
2650	unregister_netdev(dev);
2651	RAETH_PRINT("Free ei_local and unregister netdev...\n");
2652
2653	for ( i = 0; i < NUM_RX_DESC; i++)
2654	{
2655	if (ei_local->netrx0_skbuf[i] != NULL) {
2656	dev_kfree_skb(ei_local->netrx0_skbuf[i]);
2657	ei_local->netrx0_skbuf[i] = NULL;
2658	}
2659	#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
2660	if (ei_local->netrx1_skbuf[i] != NULL) {
2661	dev_kfree_skb(ei_local->netrx1_skbuf[i]);
2662	ei_local->netrx1_skbuf[i] = NULL;
2663	}
2664	#endif
2665	} // dev_kfree_skb
2666
2667	free_netdev(dev);
2668	// debug_proc_exit();
2669	#ifdef CONFIG_RAETH_NETLINK
2670	csr_netlink_end();
2671	#endif
2672	}
2673
2674	late_initcall(ra2882eth_init);
2675	module_exit(ra2882eth_cleanup_module);
2676	MODULE_LICENSE("GPL");

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