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source: src/linux/universal/linux-3.2/drivers/net/wireless/rtlwifi/pci.c @ 18879

Last change on this file since 18879 was 18879, checked in by BrainSlayer, 14 months ago
update kernels
File size: 53.1 KB

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1	/******************************************************************************
2	*
3	* Copyright(c) 2009-2010 Realtek Corporation.
4	*
5	* This program is free software; you can redistribute it and/or modify it
6	* under the terms of version 2 of the GNU General Public License as
7	* published by the Free Software Foundation.
8	*
9	* This program is distributed in the hope that it will be useful, but WITHOUT
10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12	* more details.
13	*
14	* You should have received a copy of the GNU General Public License along with
15	* this program; if not, write to the Free Software Foundation, Inc.,
16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17	*
18	* The full GNU General Public License is included in this distribution in the
19	* file called LICENSE.
20	*
21	* Contact Information:
22	* wlanfae <wlanfae@realtek.com>
23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24	* Hsinchu 300, Taiwan.
25	*
26	* Larry Finger <Larry.Finger@lwfinger.net>
27	*
28	*****************************************************************************/
29
30	#include <linux/export.h>
31	#include "core.h"
32	#include "wifi.h"
33	#include "pci.h"
34	#include "base.h"
35	#include "ps.h"
36	#include "efuse.h"
37
38	static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
39	PCI_VENDOR_ID_INTEL,
40	PCI_VENDOR_ID_ATI,
41	PCI_VENDOR_ID_AMD,
42	PCI_VENDOR_ID_SI
43	};
44
45	static const u8 ac_to_hwq[] = {
46	VO_QUEUE,
47	VI_QUEUE,
48	BE_QUEUE,
49	BK_QUEUE
50	};
51
52	static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
53	struct sk_buff *skb)
54	{
55	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
56	__le16 fc = rtl_get_fc(skb);
57	u8 queue_index = skb_get_queue_mapping(skb);
58
59	if (unlikely(ieee80211_is_beacon(fc)))
60	return BEACON_QUEUE;
61	if (ieee80211_is_mgmt(fc))
62	return MGNT_QUEUE;
63	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64	if (ieee80211_is_nullfunc(fc))
65	return HIGH_QUEUE;
66
67	return ac_to_hwq[queue_index];
68	}
69
70	/* Update PCI dependent default settings*/
71	static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72	{
73	struct rtl_priv *rtlpriv = rtl_priv(hw);
74	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
78	u8 init_aspm;
79
80	ppsc->reg_rfps_level = 0;
81	ppsc->support_aspm = 0;
82
83	/Update PCI ASPM setting /
84	ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85	switch (rtlpci->const_pci_aspm) {
86	case 0:
87	/No ASPM /
88	break;
89
90	case 1:
91	/ASPM dynamically enabled/disable. /
92	ppsc->reg_rfps_level \|= RT_RF_LPS_LEVEL_ASPM;
93	break;
94
95	case 2:
96	/ASPM with Clock Req dynamically enabled/disable. /
97	ppsc->reg_rfps_level \|= (RT_RF_LPS_LEVEL_ASPM \|
98	RT_RF_OFF_LEVL_CLK_REQ);
99	break;
100
101	case 3:
102	/*
103	* Always enable ASPM and Clock Req
104	* from initialization to halt.
105	* */
106	ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107	ppsc->reg_rfps_level \|= (RT_RF_PS_LEVEL_ALWAYS_ASPM \|
108	RT_RF_OFF_LEVL_CLK_REQ);
109	break;
110
111	case 4:
112	/*
113	* Always enable ASPM without Clock Req
114	* from initialization to halt.
115	* */
116	ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM \|
117	RT_RF_OFF_LEVL_CLK_REQ);
118	ppsc->reg_rfps_level \|= RT_RF_PS_LEVEL_ALWAYS_ASPM;
119	break;
120	}
121
122	ppsc->reg_rfps_level \|= RT_RF_OFF_LEVL_HALT_NIC;
123
124	/Update Radio OFF setting /
125	switch (rtlpci->const_hwsw_rfoff_d3) {
126	case 1:
127	if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128	ppsc->reg_rfps_level \|= RT_RF_OFF_LEVL_ASPM;
129	break;
130
131	case 2:
132	if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133	ppsc->reg_rfps_level \|= RT_RF_OFF_LEVL_ASPM;
134	ppsc->reg_rfps_level \|= RT_RF_OFF_LEVL_HALT_NIC;
135	break;
136
137	case 3:
138	ppsc->reg_rfps_level \|= RT_RF_OFF_LEVL_PCI_D3;
139	break;
140	}
141
142	/Set HW definition to determine if it supports ASPM. /
143	switch (rtlpci->const_support_pciaspm) {
144	case 0:{
145	/Not support ASPM. /
146	bool support_aspm = false;
147	ppsc->support_aspm = support_aspm;
148	break;
149	}
150	case 1:{
151	/Support ASPM. /
152	bool support_aspm = true;
153	bool support_backdoor = true;
154	ppsc->support_aspm = support_aspm;
155
156	/*if (priv->oem_id == RT_CID_TOSHIBA &&
157	!priv->ndis_adapter.amd_l1_patch)
158	support_backdoor = false; */
159
160	ppsc->support_backdoor = support_backdoor;
161
162	break;
163	}
164	case 2:
165	/ASPM value set by chipset. /
166	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167	bool support_aspm = true;
168	ppsc->support_aspm = support_aspm;
169	}
170	break;
171	default:
172	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
173	("switch case not process\n"));
174	break;
175	}
176
177	/* toshiba aspm issue, toshiba will set aspm selfly
178	* so we should not set aspm in driver */
179	pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180	if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181	init_aspm == 0x43)
182	ppsc->support_aspm = false;
183	}
184
185	static bool _rtl_pci_platform_switch_device_pci_aspm(
186	struct ieee80211_hw *hw,
187	u8 value)
188	{
189	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191
192	if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
193	value \|= 0x40;
194
195	pci_write_config_byte(rtlpci->pdev, 0x80, value);
196
197	return false;
198	}
199
200	/When we set 0x01 to enable clk request. Set 0x0 to disable clk req./
201	static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
202	{
203	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
204	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
205
206	pci_write_config_byte(rtlpci->pdev, 0x81, value);
207
208	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
209	udelay(100);
210
211	return true;
212	}
213
214	/Disable RTL8192SE ASPM & Disable Pci Bridge ASPM/
215	static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
216	{
217	struct rtl_priv *rtlpriv = rtl_priv(hw);
218	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
219	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
220	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
221	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
222	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223	/Retrieve original configuration settings. /
224	u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225	u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226	pcibridge_linkctrlreg;
227	u16 aspmlevel = 0;
228	u8 tmp_u1b = 0;
229
230	if (!ppsc->support_aspm)
231	return;
232
233	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234	RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235	("PCI(Bridge) UNKNOWN.\n"));
236
237	return;
238	}
239
240	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241	RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242	_rtl_pci_switch_clk_req(hw, 0x0);
243	}
244
245	/for promising device will in L0 state after an I/O. /
246	pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
247
248	/Set corresponding value. /
249	aspmlevel \|= BIT(0) \| BIT(1);
250	linkctrl_reg &= ~aspmlevel;
251	pcibridge_linkctrlreg &= ~(BIT(0) \| BIT(1));
252
253	_rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254	udelay(50);
255
256	/4 Disable Pci Bridge ASPM /
257	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
258	pcibridge_linkctrlreg);
259
260	udelay(50);
261	}
262
263	/*
264	*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
265	*power saving We should follow the sequence to enable
266	*RTL8192SE first then enable Pci Bridge ASPM
267	*or the system will show bluescreen.
268	*/
269	static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
270	{
271	struct rtl_priv *rtlpriv = rtl_priv(hw);
272	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
273	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
275	u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
276	u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
277	u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
278	u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
279	u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280	u16 aspmlevel;
281	u8 u_pcibridge_aspmsetting;
282	u8 u_device_aspmsetting;
283
284	if (!ppsc->support_aspm)
285	return;
286
287	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288	RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
289	("PCI(Bridge) UNKNOWN.\n"));
290	return;
291	}
292
293	/4 Enable Pci Bridge ASPM /
294
295	u_pcibridge_aspmsetting =
296	pcipriv->ndis_adapter.pcibridge_linkctrlreg \|
297	rtlpci->const_hostpci_aspm_setting;
298
299	if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300	u_pcibridge_aspmsetting &= ~BIT(0);
301
302	pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303	u_pcibridge_aspmsetting);
304
305	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
306	("PlatformEnableASPM():PciBridge busnumber[%x], "
307	"DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
308	pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
309	(pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
310	u_pcibridge_aspmsetting));
311
312	udelay(50);
313
314	/Get ASPM level (with/without Clock Req) /
315	aspmlevel = rtlpci->const_devicepci_aspm_setting;
316	u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
317
318	/_rtl_pci_platform_switch_device_pci_aspm(dev,/
319	/(priv->ndis_adapter.linkctrl_reg \| ASPMLevel)); /
320
321	u_device_aspmsetting \|= aspmlevel;
322
323	_rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
324
325	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
326	_rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
327	RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
328	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
329	}
330	udelay(100);
331	}
332
333	static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
334	{
335	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
336
337	bool status = false;
338	u8 offset_e0;
339	unsigned offset_e4;
340
341	pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
342
343	pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
344
345	if (offset_e0 == 0xA0) {
346	pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
347	if (offset_e4 & BIT(23))
348	status = true;
349	}
350
351	return status;
352	}
353
354	static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
355	{
356	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
357	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
358	u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
359	u8 linkctrl_reg;
360	u8 num4bbytes;
361
362	num4bbytes = (capabilityoffset + 0x10) / 4;
363
364	/Read Link Control Register /
365	pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
366
367	pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
368	}
369
370	static void rtl_pci_parse_configuration(struct pci_dev *pdev,
371	struct ieee80211_hw *hw)
372	{
373	struct rtl_priv *rtlpriv = rtl_priv(hw);
374	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
375
376	u8 tmp;
377	int pos;
378	u8 linkctrl_reg;
379
380	/Link Control Register /
381	pos = pci_pcie_cap(pdev);
382	pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
383	pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
384
385	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
386	("Link Control Register =%x\n",
387	pcipriv->ndis_adapter.linkctrl_reg));
388
389	pci_read_config_byte(pdev, 0x98, &tmp);
390	tmp \|= BIT(4);
391	pci_write_config_byte(pdev, 0x98, tmp);
392
393	tmp = 0x17;
394	pci_write_config_byte(pdev, 0x70f, tmp);
395	}
396
397	static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
398	{
399	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
400
401	_rtl_pci_update_default_setting(hw);
402
403	if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
404	/Always enable ASPM & Clock Req. /
405	rtl_pci_enable_aspm(hw);
406	RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
407	}
408
409	}
410
411	static void _rtl_pci_io_handler_init(struct device *dev,
412	struct ieee80211_hw *hw)
413	{
414	struct rtl_priv *rtlpriv = rtl_priv(hw);
415
416	rtlpriv->io.dev = dev;
417
418	rtlpriv->io.write8_async = pci_write8_async;
419	rtlpriv->io.write16_async = pci_write16_async;
420	rtlpriv->io.write32_async = pci_write32_async;
421
422	rtlpriv->io.read8_sync = pci_read8_sync;
423	rtlpriv->io.read16_sync = pci_read16_sync;
424	rtlpriv->io.read32_sync = pci_read32_sync;
425
426	}
427
428	static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
429	{
430	}
431
432	static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
433	struct sk_buff skb, struct rtl_tcb_desc tcb_desc, u8 tid)
434	{
435	struct rtl_priv *rtlpriv = rtl_priv(hw);
436	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437	u8 additionlen = FCS_LEN;
438	struct sk_buff *next_skb;
439
440	/* here open is 4, wep/tkip is 8, aes is 12*/
441	if (info->control.hw_key)
442	additionlen += info->control.hw_key->icv_len;
443
444	/* The most skb num is 6 */
445	tcb_desc->empkt_num = 0;
446	spin_lock_bh(&rtlpriv->locks.waitq_lock);
447	skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
448	struct ieee80211_tx_info *next_info;
449
450	next_info = IEEE80211_SKB_CB(next_skb);
451	if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
452	tcb_desc->empkt_len[tcb_desc->empkt_num] =
453	next_skb->len + additionlen;
454	tcb_desc->empkt_num++;
455	} else {
456	break;
457	}
458
459	if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
460	next_skb))
461	break;
462
463	if (tcb_desc->empkt_num >= 5)
464	break;
465	}
466	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
467
468	return true;
469	}
470
471	/* just for early mode now */
472	static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
473	{
474	struct rtl_priv *rtlpriv = rtl_priv(hw);
475	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
476	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
477	struct sk_buff *skb = NULL;
478	struct ieee80211_tx_info *info = NULL;
479	int tid;
480
481	if (!rtlpriv->rtlhal.earlymode_enable)
482	return;
483
484	/* we juse use em for BE/BK/VI/VO */
485	for (tid = 7; tid >= 0; tid--) {
486	u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
487	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
488	while (!mac->act_scanning &&
489	rtlpriv->psc.rfpwr_state == ERFON) {
490	struct rtl_tcb_desc tcb_desc;
491	memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
492
493	spin_lock_bh(&rtlpriv->locks.waitq_lock);
494	if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
495	(ring->entries - skb_queue_len(&ring->queue) > 5)) {
496	skb = skb_dequeue(&mac->skb_waitq[tid]);
497	} else {
498	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
499	break;
500	}
501	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
502
503	/* Some macaddr can't do early mode. like
504	* multicast/broadcast/no_qos data */
505	info = IEEE80211_SKB_CB(skb);
506	if (info->flags & IEEE80211_TX_CTL_AMPDU)
507	_rtl_update_earlymode_info(hw, skb,
508	&tcb_desc, tid);
509
510	rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
511	}
512	}
513	}
514
515
516	static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
517	{
518	struct rtl_priv *rtlpriv = rtl_priv(hw);
519	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
520
521	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
522
523	while (skb_queue_len(&ring->queue)) {
524	struct rtl_tx_desc *entry = &ring->desc[ring->idx];
525	struct sk_buff *skb;
526	struct ieee80211_tx_info *info;
527	__le16 fc;
528	u8 tid;
529
530	u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
531	HW_DESC_OWN);
532
533	/*
534	*beacon packet will only use the first
535	*descriptor defautly,and the own may not
536	*be cleared by the hardware
537	*/
538	if (own)
539	return;
540	ring->idx = (ring->idx + 1) % ring->entries;
541
542	skb = __skb_dequeue(&ring->queue);
543	pci_unmap_single(rtlpci->pdev,
544	rtlpriv->cfg->ops->
545	get_desc((u8 *) entry, true,
546	HW_DESC_TXBUFF_ADDR),
547	skb->len, PCI_DMA_TODEVICE);
548
549	/* remove early mode header */
550	if (rtlpriv->rtlhal.earlymode_enable)
551	skb_pull(skb, EM_HDR_LEN);
552
553	RT_TRACE(rtlpriv, (COMP_INTR \| COMP_SEND), DBG_TRACE,
554	("new ring->idx:%d, "
555	"free: skb_queue_len:%d, free: seq:%x\n",
556	ring->idx,
557	skb_queue_len(&ring->queue),
558	(u16 ) (skb->data + 22)));
559
560	if (prio == TXCMD_QUEUE) {
561	dev_kfree_skb(skb);
562	goto tx_status_ok;
563
564	}
565
566	/* for sw LPS, just after NULL skb send out, we can
567	* sure AP kown we are sleeped, our we should not let
568	* rf to sleep*/
569	fc = rtl_get_fc(skb);
570	if (ieee80211_is_nullfunc(fc)) {
571	if (ieee80211_has_pm(fc)) {
572	rtlpriv->mac80211.offchan_delay = true;
573	rtlpriv->psc.state_inap = 1;
574	} else {
575	rtlpriv->psc.state_inap = 0;
576	}
577	}
578
579	/* update tid tx pkt num */
580	tid = rtl_get_tid(skb);
581	if (tid <= 7)
582	rtlpriv->link_info.tidtx_inperiod[tid]++;
583
584	info = IEEE80211_SKB_CB(skb);
585	ieee80211_tx_info_clear_status(info);
586
587	info->flags \|= IEEE80211_TX_STAT_ACK;
588	/info->status.rates[0].count = 1; /
589
590	ieee80211_tx_status_irqsafe(hw, skb);
591
592	if ((ring->entries - skb_queue_len(&ring->queue))
593	== 2) {
594
595	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
596	("more desc left, wake"
597	"skb_queue@%d,ring->idx = %d,"
598	"skb_queue_len = 0x%d\n",
599	prio, ring->idx,
600	skb_queue_len(&ring->queue)));
601
602	ieee80211_wake_queue(hw,
603	skb_get_queue_mapping
604	(skb));
605	}
606	tx_status_ok:
607	skb = NULL;
608	}
609
610	if (((rtlpriv->link_info.num_rx_inperiod +
611	rtlpriv->link_info.num_tx_inperiod) > 8) \|\|
612	(rtlpriv->link_info.num_rx_inperiod > 2)) {
613	tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
614	}
615	}
616
617	static void _rtl_receive_one(struct ieee80211_hw hw, struct sk_buff skb,
618	struct ieee80211_rx_status rx_status)
619	{
620	struct rtl_priv *rtlpriv = rtl_priv(hw);
621	struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
622	__le16 fc = rtl_get_fc(skb);
623	bool unicast = false;
624	struct sk_buff *uskb = NULL;
625	u8 *pdata;
626
627
628	memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
629
630	if (is_broadcast_ether_addr(hdr->addr1)) {
631	;/TODO/
632	} else if (is_multicast_ether_addr(hdr->addr1)) {
633	;/TODO/
634	} else {
635	unicast = true;
636	rtlpriv->stats.rxbytesunicast += skb->len;
637	}
638
639	rtl_is_special_data(hw, skb, false);
640
641	if (ieee80211_is_data(fc)) {
642	rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
643
644	if (unicast)
645	rtlpriv->link_info.num_rx_inperiod++;
646	}
647
648	/* for sw lps */
649	rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
650	rtl_recognize_peer(hw, (void *)skb->data, skb->len);
651	if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
652	(rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
653	(ieee80211_is_beacon(fc) \|\| ieee80211_is_probe_resp(fc)))
654	return;
655
656	if (unlikely(!rtl_action_proc(hw, skb, false)))
657	return;
658
659	uskb = dev_alloc_skb(skb->len + 128);
660	if (!uskb)
661	return; /* exit if allocation failed */
662	memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
663	pdata = (u8 *)skb_put(uskb, skb->len);
664	memcpy(pdata, skb->data, skb->len);
665
666	ieee80211_rx_irqsafe(hw, uskb);
667	}
668
669	static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
670	{
671	struct rtl_priv *rtlpriv = rtl_priv(hw);
672	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
673	int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
674
675	struct ieee80211_rx_status rx_status = { 0 };
676	unsigned int count = rtlpci->rxringcount;
677	u8 own;
678	u8 tmp_one;
679	u32 bufferaddress;
680
681	struct rtl_stats stats = {
682	.signal = 0,
683	.noise = -98,
684	.rate = 0,
685	};
686	int index = rtlpci->rx_ring[rx_queue_idx].idx;
687
688	/RX NORMAL PKT /
689	while (count--) {
690	/rx descriptor /
691	struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
692	index];
693	/rx pkt /
694	struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
695	index];
696	struct sk_buff *new_skb = NULL;
697
698	own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
699	false, HW_DESC_OWN);
700
701	/wait data to be filled by hardware /
702	if (own)
703	break;
704
705	rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
706	&rx_status,
707	(u8 *) pdesc, skb);
708
709	if (stats.crc \|\| stats.hwerror)
710	goto done;
711
712	new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
713	if (unlikely(!new_skb)) {
714	RT_TRACE(rtlpriv, (COMP_INTR \| COMP_RECV),
715	DBG_DMESG,
716	("can't alloc skb for rx\n"));
717	goto done;
718	}
719
720	pci_unmap_single(rtlpci->pdev,
721	((dma_addr_t ) skb->cb),
722	rtlpci->rxbuffersize,
723	PCI_DMA_FROMDEVICE);
724
725	skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
726	HW_DESC_RXPKT_LEN));
727	skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
728
729	/*
730	* NOTICE This can not be use for mac80211,
731	* this is done in mac80211 code,
732	* if you done here sec DHCP will fail
733	* skb_trim(skb, skb->len - 4);
734	*/
735
736	_rtl_receive_one(hw, skb, rx_status);
737
738	if (((rtlpriv->link_info.num_rx_inperiod +
739	rtlpriv->link_info.num_tx_inperiod) > 8) \|\|
740	(rtlpriv->link_info.num_rx_inperiod > 2)) {
741	tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
742	}
743
744	dev_kfree_skb_any(skb);
745	skb = new_skb;
746
747	rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
748	((dma_addr_t ) skb->cb) =
749	pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
750	rtlpci->rxbuffersize,
751	PCI_DMA_FROMDEVICE);
752
753	done:
754	bufferaddress = (((dma_addr_t )skb->cb));
755	tmp_one = 1;
756	rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
757	HW_DESC_RXBUFF_ADDR,
758	(u8 *)&bufferaddress);
759	rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
760	HW_DESC_RXPKT_LEN,
761	(u8 *)&rtlpci->rxbuffersize);
762
763	if (index == rtlpci->rxringcount - 1)
764	rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
765	HW_DESC_RXERO,
766	(u8 *)&tmp_one);
767
768	rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
769	(u8 *)&tmp_one);
770
771	index = (index + 1) % rtlpci->rxringcount;
772	}
773
774	rtlpci->rx_ring[rx_queue_idx].idx = index;
775	}
776
777	static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
778	{
779	struct ieee80211_hw *hw = dev_id;
780	struct rtl_priv *rtlpriv = rtl_priv(hw);
781	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
782	unsigned long flags;
783	u32 inta = 0;
784	u32 intb = 0;
785
786	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
787
788	/read ISR: 4/8bytes /
789	rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
790
791	/Shared IRQ or HW disappared /
792	if (!inta \|\| inta == 0xffff)
793	goto done;
794
795	/<1> beacon related /
796	if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
797	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
798	("beacon ok interrupt!\n"));
799	}
800
801	if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
802	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
803	("beacon err interrupt!\n"));
804	}
805
806	if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
807	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
808	("beacon interrupt!\n"));
809	}
810
811	if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
812	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
813	("prepare beacon for interrupt!\n"));
814	tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
815	}
816
817	/<3> Tx related /
818	if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
819	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
820
821	if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
822	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
823	("Manage ok interrupt!\n"));
824	_rtl_pci_tx_isr(hw, MGNT_QUEUE);
825	}
826
827	if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
828	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
829	("HIGH_QUEUE ok interrupt!\n"));
830	_rtl_pci_tx_isr(hw, HIGH_QUEUE);
831	}
832
833	if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
834	rtlpriv->link_info.num_tx_inperiod++;
835
836	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
837	("BK Tx OK interrupt!\n"));
838	_rtl_pci_tx_isr(hw, BK_QUEUE);
839	}
840
841	if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
842	rtlpriv->link_info.num_tx_inperiod++;
843
844	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
845	("BE TX OK interrupt!\n"));
846	_rtl_pci_tx_isr(hw, BE_QUEUE);
847	}
848
849	if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
850	rtlpriv->link_info.num_tx_inperiod++;
851
852	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
853	("VI TX OK interrupt!\n"));
854	_rtl_pci_tx_isr(hw, VI_QUEUE);
855	}
856
857	if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
858	rtlpriv->link_info.num_tx_inperiod++;
859
860	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
861	("Vo TX OK interrupt!\n"));
862	_rtl_pci_tx_isr(hw, VO_QUEUE);
863	}
864
865	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
866	if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
867	rtlpriv->link_info.num_tx_inperiod++;
868
869	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
870	("CMD TX OK interrupt!\n"));
871	_rtl_pci_tx_isr(hw, TXCMD_QUEUE);
872	}
873	}
874
875	/<2> Rx related /
876	if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
877	RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
878	_rtl_pci_rx_interrupt(hw);
879	}
880
881	if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
882	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
883	("rx descriptor unavailable!\n"));
884	_rtl_pci_rx_interrupt(hw);
885	}
886
887	if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
888	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
889	_rtl_pci_rx_interrupt(hw);
890	}
891
892	if (rtlpriv->rtlhal.earlymode_enable)
893	tasklet_schedule(&rtlpriv->works.irq_tasklet);
894
895	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
896	return IRQ_HANDLED;
897
898	done:
899	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
900	return IRQ_HANDLED;
901	}
902
903	static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
904	{
905	_rtl_pci_tx_chk_waitq(hw);
906	}
907
908	static void _rtl_pci_ips_leave_tasklet(struct ieee80211_hw *hw)
909	{
910	rtl_lps_leave(hw);
911	}
912
913	static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
914	{
915	struct rtl_priv *rtlpriv = rtl_priv(hw);
916	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
917	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
918	struct rtl8192_tx_ring *ring = NULL;
919	struct ieee80211_hdr *hdr = NULL;
920	struct ieee80211_tx_info *info = NULL;
921	struct sk_buff *pskb = NULL;
922	struct rtl_tx_desc *pdesc = NULL;
923	struct rtl_tcb_desc tcb_desc;
924	u8 temp_one = 1;
925
926	memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
927	ring = &rtlpci->tx_ring[BEACON_QUEUE];
928	pskb = __skb_dequeue(&ring->queue);
929	if (pskb)
930	kfree_skb(pskb);
931
932	/NB: the beacon data buffer must be 32-bit aligned. /
933	pskb = ieee80211_beacon_get(hw, mac->vif);
934	if (pskb == NULL)
935	return;
936	hdr = rtl_get_hdr(pskb);
937	info = IEEE80211_SKB_CB(pskb);
938	pdesc = &ring->desc[0];
939	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
940	info, pskb, BEACON_QUEUE, &tcb_desc);
941
942	__skb_queue_tail(&ring->queue, pskb);
943
944	rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
945	(u8 *)&temp_one);
946
947	return;
948	}
949
950	static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
951	{
952	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
953	u8 i;
954
955	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
956	rtlpci->txringcount[i] = RT_TXDESC_NUM;
957
958	/*
959	*we just alloc 2 desc for beacon queue,
960	*because we just need first desc in hw beacon.
961	*/
962	rtlpci->txringcount[BEACON_QUEUE] = 2;
963
964	/*
965	*BE queue need more descriptor for performance
966	*consideration or, No more tx desc will happen,
967	*and may cause mac80211 mem leakage.
968	*/
969	rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
970
971	rtlpci->rxbuffersize = 9100; /2048/1024; /
972	rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /64; /
973	}
974
975	static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
976	struct pci_dev *pdev)
977	{
978	struct rtl_priv *rtlpriv = rtl_priv(hw);
979	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
980	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
981	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
982
983	rtlpci->up_first_time = true;
984	rtlpci->being_init_adapter = false;
985
986	rtlhal->hw = hw;
987	rtlpci->pdev = pdev;
988
989	/Tx/Rx related var /
990	_rtl_pci_init_trx_var(hw);
991
992	/IBSS/ mac->beacon_interval = 100;
993
994	/AMPDU/
995	mac->min_space_cfg = 0;
996	mac->max_mss_density = 0;
997	/set sane AMPDU defaults /
998	mac->current_ampdu_density = 7;
999	mac->current_ampdu_factor = 3;
1000
1001	/QOS/
1002	rtlpci->acm_method = eAcmWay2_SW;
1003
1004	/task /
1005	tasklet_init(&rtlpriv->works.irq_tasklet,
1006	(void (*)(unsigned long))_rtl_pci_irq_tasklet,
1007	(unsigned long)hw);
1008	tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1009	(void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1010	(unsigned long)hw);
1011	tasklet_init(&rtlpriv->works.ips_leave_tasklet,
1012	(void (*)(unsigned long))_rtl_pci_ips_leave_tasklet,
1013	(unsigned long)hw);
1014	}
1015
1016	static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1017	unsigned int prio, unsigned int entries)
1018	{
1019	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1020	struct rtl_priv *rtlpriv = rtl_priv(hw);
1021	struct rtl_tx_desc *ring;
1022	dma_addr_t dma;
1023	u32 nextdescaddress;
1024	int i;
1025
1026	ring = pci_alloc_consistent(rtlpci->pdev,
1027	sizeof(ring) entries, &dma);
1028
1029	if (!ring \|\| (unsigned long)ring & 0xFF) {
1030	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1031	("Cannot allocate TX ring (prio = %d)\n", prio));
1032	return -ENOMEM;
1033	}
1034
1035	memset(ring, 0, sizeof(ring) entries);
1036	rtlpci->tx_ring[prio].desc = ring;
1037	rtlpci->tx_ring[prio].dma = dma;
1038	rtlpci->tx_ring[prio].idx = 0;
1039	rtlpci->tx_ring[prio].entries = entries;
1040	skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1041
1042	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1043	("queue:%d, ring_addr:%p\n", prio, ring));
1044
1045	for (i = 0; i < entries; i++) {
1046	nextdescaddress = (u32) dma +
1047	((i + 1) % entries) *
1048	sizeof(*ring);
1049
1050	rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1051	true, HW_DESC_TX_NEXTDESC_ADDR,
1052	(u8 *)&nextdescaddress);
1053	}
1054
1055	return 0;
1056	}
1057
1058	static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1059	{
1060	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1061	struct rtl_priv *rtlpriv = rtl_priv(hw);
1062	struct rtl_rx_desc *entry = NULL;
1063	int i, rx_queue_idx;
1064	u8 tmp_one = 1;
1065
1066	/*
1067	*rx_queue_idx 0:RX_MPDU_QUEUE
1068	*rx_queue_idx 1:RX_CMD_QUEUE
1069	*/
1070	for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1071	rx_queue_idx++) {
1072	rtlpci->rx_ring[rx_queue_idx].desc =
1073	pci_alloc_consistent(rtlpci->pdev,
1074	sizeof(*rtlpci->rx_ring[rx_queue_idx].
1075	desc) * rtlpci->rxringcount,
1076	&rtlpci->rx_ring[rx_queue_idx].dma);
1077
1078	if (!rtlpci->rx_ring[rx_queue_idx].desc \|\|
1079	(unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1080	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1081	("Cannot allocate RX ring\n"));
1082	return -ENOMEM;
1083	}
1084
1085	memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1086	sizeof(rtlpci->rx_ring[rx_queue_idx].desc)
1087	rtlpci->rxringcount);
1088
1089	rtlpci->rx_ring[rx_queue_idx].idx = 0;
1090
1091	/* If amsdu_8k is disabled, set buffersize to 4096. This
1092	* change will reduce memory fragmentation.
1093	*/
1094	if (rtlpci->rxbuffersize > 4096 &&
1095	rtlpriv->rtlhal.disable_amsdu_8k)
1096	rtlpci->rxbuffersize = 4096;
1097
1098	for (i = 0; i < rtlpci->rxringcount; i++) {
1099	struct sk_buff *skb =
1100	dev_alloc_skb(rtlpci->rxbuffersize);
1101	u32 bufferaddress;
1102	if (!skb)
1103	return 0;
1104	entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1105
1106	/skb->dev = dev; /
1107
1108	rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1109
1110	/*
1111	*just set skb->cb to mapping addr
1112	*for pci_unmap_single use
1113	*/
1114	((dma_addr_t ) skb->cb) =
1115	pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1116	rtlpci->rxbuffersize,
1117	PCI_DMA_FROMDEVICE);
1118
1119	bufferaddress = (((dma_addr_t )skb->cb));
1120	rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1121	HW_DESC_RXBUFF_ADDR,
1122	(u8 *)&bufferaddress);
1123	rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1124	HW_DESC_RXPKT_LEN,
1125	(u8 *)&rtlpci->
1126	rxbuffersize);
1127	rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1128	HW_DESC_RXOWN,
1129	(u8 *)&tmp_one);
1130	}
1131
1132	rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1133	HW_DESC_RXERO, (u8 *)&tmp_one);
1134	}
1135	return 0;
1136	}
1137
1138	static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1139	unsigned int prio)
1140	{
1141	struct rtl_priv *rtlpriv = rtl_priv(hw);
1142	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1143	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1144
1145	while (skb_queue_len(&ring->queue)) {
1146	struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1147	struct sk_buff *skb = __skb_dequeue(&ring->queue);
1148
1149	pci_unmap_single(rtlpci->pdev,
1150	rtlpriv->cfg->
1151	ops->get_desc((u8 *) entry, true,
1152	HW_DESC_TXBUFF_ADDR),
1153	skb->len, PCI_DMA_TODEVICE);
1154	kfree_skb(skb);
1155	ring->idx = (ring->idx + 1) % ring->entries;
1156	}
1157
1158	if (ring->desc) {
1159	pci_free_consistent(rtlpci->pdev,
1160	sizeof(ring->desc) ring->entries,
1161	ring->desc, ring->dma);
1162	ring->desc = NULL;
1163	}
1164	}
1165
1166	static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1167	{
1168	int i, rx_queue_idx;
1169
1170	/rx_queue_idx 0:RX_MPDU_QUEUE /
1171	/rx_queue_idx 1:RX_CMD_QUEUE /
1172	for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1173	rx_queue_idx++) {
1174	for (i = 0; i < rtlpci->rxringcount; i++) {
1175	struct sk_buff *skb =
1176	rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1177	if (!skb)
1178	continue;
1179
1180	pci_unmap_single(rtlpci->pdev,
1181	((dma_addr_t ) skb->cb),
1182	rtlpci->rxbuffersize,
1183	PCI_DMA_FROMDEVICE);
1184	kfree_skb(skb);
1185	}
1186
1187	if (rtlpci->rx_ring[rx_queue_idx].desc) {
1188	pci_free_consistent(rtlpci->pdev,
1189	sizeof(*rtlpci->rx_ring[rx_queue_idx].
1190	desc) * rtlpci->rxringcount,
1191	rtlpci->rx_ring[rx_queue_idx].desc,
1192	rtlpci->rx_ring[rx_queue_idx].dma);
1193	rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1194	}
1195	}
1196	}
1197
1198	static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1199	{
1200	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1201	int ret;
1202	int i;
1203
1204	ret = _rtl_pci_init_rx_ring(hw);
1205	if (ret)
1206	return ret;
1207
1208	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1209	ret = _rtl_pci_init_tx_ring(hw, i,
1210	rtlpci->txringcount[i]);
1211	if (ret)
1212	goto err_free_rings;
1213	}
1214
1215	return 0;
1216
1217	err_free_rings:
1218	_rtl_pci_free_rx_ring(rtlpci);
1219
1220	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1221	if (rtlpci->tx_ring[i].desc)
1222	_rtl_pci_free_tx_ring(hw, i);
1223
1224	return 1;
1225	}
1226
1227	static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1228	{
1229	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1230	u32 i;
1231
1232	/free rx rings /
1233	_rtl_pci_free_rx_ring(rtlpci);
1234
1235	/free tx rings /
1236	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1237	_rtl_pci_free_tx_ring(hw, i);
1238
1239	return 0;
1240	}
1241
1242	int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1243	{
1244	struct rtl_priv *rtlpriv = rtl_priv(hw);
1245	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1246	int i, rx_queue_idx;
1247	unsigned long flags;
1248	u8 tmp_one = 1;
1249
1250	/rx_queue_idx 0:RX_MPDU_QUEUE /
1251	/rx_queue_idx 1:RX_CMD_QUEUE /
1252	for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1253	rx_queue_idx++) {
1254	/*
1255	*force the rx_ring[RX_MPDU_QUEUE/
1256	*RX_CMD_QUEUE].idx to the first one
1257	*/
1258	if (rtlpci->rx_ring[rx_queue_idx].desc) {
1259	struct rtl_rx_desc *entry = NULL;
1260
1261	for (i = 0; i < rtlpci->rxringcount; i++) {
1262	entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1263	rtlpriv->cfg->ops->set_desc((u8 *) entry,
1264	false,
1265	HW_DESC_RXOWN,
1266	(u8 *)&tmp_one);
1267	}
1268	rtlpci->rx_ring[rx_queue_idx].idx = 0;
1269	}
1270	}
1271
1272	/*
1273	*after reset, release previous pending packet,
1274	*and force the tx idx to the first one
1275	*/
1276	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1277	for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1278	if (rtlpci->tx_ring[i].desc) {
1279	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1280
1281	while (skb_queue_len(&ring->queue)) {
1282	struct rtl_tx_desc *entry =
1283	&ring->desc[ring->idx];
1284	struct sk_buff *skb =
1285	__skb_dequeue(&ring->queue);
1286
1287	pci_unmap_single(rtlpci->pdev,
1288	rtlpriv->cfg->ops->
1289	get_desc((u8 *)
1290	entry,
1291	true,
1292	HW_DESC_TXBUFF_ADDR),
1293	skb->len, PCI_DMA_TODEVICE);
1294	kfree_skb(skb);
1295	ring->idx = (ring->idx + 1) % ring->entries;
1296	}
1297	ring->idx = 0;
1298	}
1299	}
1300
1301	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1302
1303	return 0;
1304	}
1305
1306	static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1307	struct sk_buff *skb)
1308	{
1309	struct rtl_priv *rtlpriv = rtl_priv(hw);
1310	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1311	struct ieee80211_sta *sta = info->control.sta;
1312	struct rtl_sta_info *sta_entry = NULL;
1313	u8 tid = rtl_get_tid(skb);
1314
1315	if (!sta)
1316	return false;
1317	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1318
1319	if (!rtlpriv->rtlhal.earlymode_enable)
1320	return false;
1321	if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1322	return false;
1323	if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1324	return false;
1325	if (tid > 7)
1326	return false;
1327
1328	/* maybe every tid should be checked */
1329	if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1330	return false;
1331
1332	spin_lock_bh(&rtlpriv->locks.waitq_lock);
1333	skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1334	spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1335
1336	return true;
1337	}
1338
1339	static int rtl_pci_tx(struct ieee80211_hw hw, struct sk_buff skb,
1340	struct rtl_tcb_desc *ptcb_desc)
1341	{
1342	struct rtl_priv *rtlpriv = rtl_priv(hw);
1343	struct rtl_sta_info *sta_entry = NULL;
1344	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1345	struct ieee80211_sta *sta = info->control.sta;
1346	struct rtl8192_tx_ring *ring;
1347	struct rtl_tx_desc *pdesc;
1348	u8 idx;
1349	u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1350	unsigned long flags;
1351	struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1352	__le16 fc = rtl_get_fc(skb);
1353	u8 *pda_addr = hdr->addr1;
1354	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1355	/ssn /
1356	u8 tid = 0;
1357	u16 seq_number = 0;
1358	u8 own;
1359	u8 temp_one = 1;
1360
1361	if (ieee80211_is_auth(fc)) {
1362	RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1363	rtl_ips_nic_on(hw);
1364	}
1365
1366	if (rtlpriv->psc.sw_ps_enabled) {
1367	if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1368	!ieee80211_has_pm(fc))
1369	hdr->frame_control \|= cpu_to_le16(IEEE80211_FCTL_PM);
1370	}
1371
1372	rtl_action_proc(hw, skb, true);
1373
1374	if (is_multicast_ether_addr(pda_addr))
1375	rtlpriv->stats.txbytesmulticast += skb->len;
1376	else if (is_broadcast_ether_addr(pda_addr))
1377	rtlpriv->stats.txbytesbroadcast += skb->len;
1378	else
1379	rtlpriv->stats.txbytesunicast += skb->len;
1380
1381	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1382	ring = &rtlpci->tx_ring[hw_queue];
1383	if (hw_queue != BEACON_QUEUE)
1384	idx = (ring->idx + skb_queue_len(&ring->queue)) %
1385	ring->entries;
1386	else
1387	idx = 0;
1388
1389	pdesc = &ring->desc[idx];
1390	own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1391	true, HW_DESC_OWN);
1392
1393	if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1394	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395	("No more TX desc@%d, ring->idx = %d,"
1396	"idx = %d, skb_queue_len = 0x%d\n",
1397	hw_queue, ring->idx, idx,
1398	skb_queue_len(&ring->queue)));
1399
1400	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1401	return skb->len;
1402	}
1403
1404	if (ieee80211_is_data_qos(fc)) {
1405	tid = rtl_get_tid(skb);
1406	if (sta) {
1407	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1408	seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1409	IEEE80211_SCTL_SEQ) >> 4;
1410	seq_number += 1;
1411
1412	if (!ieee80211_has_morefrags(hdr->frame_control))
1413	sta_entry->tids[tid].seq_number = seq_number;
1414	}
1415	}
1416
1417	if (ieee80211_is_data(fc))
1418	rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1419
1420	rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1421	info, skb, hw_queue, ptcb_desc);
1422
1423	__skb_queue_tail(&ring->queue, skb);
1424
1425	rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1426	HW_DESC_OWN, (u8 *)&temp_one);
1427
1428
1429	if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1430	hw_queue != BEACON_QUEUE) {
1431
1432	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1433	("less desc left, stop skb_queue@%d, "
1434	"ring->idx = %d,"
1435	"idx = %d, skb_queue_len = 0x%d\n",
1436	hw_queue, ring->idx, idx,
1437	skb_queue_len(&ring->queue)));
1438
1439	ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1440	}
1441
1442	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1443
1444	rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1445
1446	return 0;
1447	}
1448
1449	static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1450	{
1451	struct rtl_priv *rtlpriv = rtl_priv(hw);
1452	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1453	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1454	u16 i = 0;
1455	int queue_id;
1456	struct rtl8192_tx_ring *ring;
1457
1458	for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1459	u32 queue_len;
1460	ring = &pcipriv->dev.tx_ring[queue_id];
1461	queue_len = skb_queue_len(&ring->queue);
1462	if (queue_len == 0 \|\| queue_id == BEACON_QUEUE \|\|
1463	queue_id == TXCMD_QUEUE) {
1464	queue_id--;
1465	continue;
1466	} else {
1467	msleep(20);
1468	i++;
1469	}
1470
1471	/* we just wait 1s for all queues */
1472	if (rtlpriv->psc.rfpwr_state == ERFOFF \|\|
1473	is_hal_stop(rtlhal) \|\| i >= 200)
1474	return;
1475	}
1476	}
1477
1478	static void rtl_pci_deinit(struct ieee80211_hw *hw)
1479	{
1480	struct rtl_priv *rtlpriv = rtl_priv(hw);
1481	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1482
1483	_rtl_pci_deinit_trx_ring(hw);
1484
1485	synchronize_irq(rtlpci->pdev->irq);
1486	tasklet_kill(&rtlpriv->works.irq_tasklet);
1487	tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1488
1489	flush_workqueue(rtlpriv->works.rtl_wq);
1490	destroy_workqueue(rtlpriv->works.rtl_wq);
1491
1492	}
1493
1494	static int rtl_pci_init(struct ieee80211_hw hw, struct pci_dev pdev)
1495	{
1496	struct rtl_priv *rtlpriv = rtl_priv(hw);
1497	int err;
1498
1499	_rtl_pci_init_struct(hw, pdev);
1500
1501	err = _rtl_pci_init_trx_ring(hw);
1502	if (err) {
1503	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1504	("tx ring initialization failed"));
1505	return err;
1506	}
1507
1508	return 1;
1509	}
1510
1511	static int rtl_pci_start(struct ieee80211_hw *hw)
1512	{
1513	struct rtl_priv *rtlpriv = rtl_priv(hw);
1514	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1515	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1516	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1517
1518	int err;
1519
1520	rtl_pci_reset_trx_ring(hw);
1521
1522	rtlpci->driver_is_goingto_unload = false;
1523	err = rtlpriv->cfg->ops->hw_init(hw);
1524	if (err) {
1525	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1526	("Failed to config hardware!\n"));
1527	return err;
1528	}
1529
1530	rtlpriv->cfg->ops->enable_interrupt(hw);
1531	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1532
1533	rtl_init_rx_config(hw);
1534
1535	/should be after adapter start and interrupt enable. /
1536	set_hal_start(rtlhal);
1537
1538	RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1539
1540	rtlpci->up_first_time = false;
1541
1542	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1543	return 0;
1544	}
1545
1546	static void rtl_pci_stop(struct ieee80211_hw *hw)
1547	{
1548	struct rtl_priv *rtlpriv = rtl_priv(hw);
1549	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1550	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1551	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1552	unsigned long flags;
1553	u8 RFInProgressTimeOut = 0;
1554
1555	/*
1556	*should be before disable interrupt&adapter
1557	*and will do it immediately.
1558	*/
1559	set_hal_stop(rtlhal);
1560
1561	rtlpriv->cfg->ops->disable_interrupt(hw);
1562	tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1563
1564	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1565	while (ppsc->rfchange_inprogress) {
1566	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1567	if (RFInProgressTimeOut > 100) {
1568	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1569	break;
1570	}
1571	mdelay(1);
1572	RFInProgressTimeOut++;
1573	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1574	}
1575	ppsc->rfchange_inprogress = true;
1576	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1577
1578	rtlpci->driver_is_goingto_unload = true;
1579	rtlpriv->cfg->ops->hw_disable(hw);
1580	rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1581
1582	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1583	ppsc->rfchange_inprogress = false;
1584	spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1585
1586	rtl_pci_enable_aspm(hw);
1587	}
1588
1589	static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1590	struct ieee80211_hw *hw)
1591	{
1592	struct rtl_priv *rtlpriv = rtl_priv(hw);
1593	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1594	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1595	struct pci_dev *bridge_pdev = pdev->bus->self;
1596	u16 venderid;
1597	u16 deviceid;
1598	u8 revisionid;
1599	u16 irqline;
1600	u8 tmp;
1601
1602	pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1603	venderid = pdev->vendor;
1604	deviceid = pdev->device;
1605	pci_read_config_byte(pdev, 0x8, &revisionid);
1606	pci_read_config_word(pdev, 0x3C, &irqline);
1607
1608	/* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1609	* r8192e_pci, and RTL8192SE, which uses this driver. If the
1610	* revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1611	* the correct driver is r8192e_pci, thus this routine should
1612	* return false.
1613	*/
1614	if (deviceid == RTL_PCI_8192SE_DID &&
1615	revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1616	return false;
1617
1618	if (deviceid == RTL_PCI_8192_DID \|\|
1619	deviceid == RTL_PCI_0044_DID \|\|
1620	deviceid == RTL_PCI_0047_DID \|\|
1621	deviceid == RTL_PCI_8192SE_DID \|\|
1622	deviceid == RTL_PCI_8174_DID \|\|
1623	deviceid == RTL_PCI_8173_DID \|\|
1624	deviceid == RTL_PCI_8172_DID \|\|
1625	deviceid == RTL_PCI_8171_DID) {
1626	switch (revisionid) {
1627	case RTL_PCI_REVISION_ID_8192PCIE:
1628	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1629	("8192 PCI-E is found - "
1630	"vid/did=%x/%x\n", venderid, deviceid));
1631	rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1632	break;
1633	case RTL_PCI_REVISION_ID_8192SE:
1634	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1635	("8192SE is found - "
1636	"vid/did=%x/%x\n", venderid, deviceid));
1637	rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1638	break;
1639	default:
1640	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1641	("Err: Unknown device - "
1642	"vid/did=%x/%x\n", venderid, deviceid));
1643	rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1644	break;
1645
1646	}
1647	} else if (deviceid == RTL_PCI_8192CET_DID \|\|
1648	deviceid == RTL_PCI_8192CE_DID \|\|
1649	deviceid == RTL_PCI_8191CE_DID \|\|
1650	deviceid == RTL_PCI_8188CE_DID) {
1651	rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1652	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1653	("8192C PCI-E is found - "
1654	"vid/did=%x/%x\n", venderid, deviceid));
1655	} else if (deviceid == RTL_PCI_8192DE_DID \|\|
1656	deviceid == RTL_PCI_8192DE_DID2) {
1657	rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1658	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1659	("8192D PCI-E is found - "
1660	"vid/did=%x/%x\n", venderid, deviceid));
1661	} else {
1662	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1663	("Err: Unknown device -"
1664	" vid/did=%x/%x\n", venderid, deviceid));
1665
1666	rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1667	}
1668
1669	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1670	if (revisionid == 0 \|\| revisionid == 1) {
1671	if (revisionid == 0) {
1672	RT_TRACE(rtlpriv, COMP_INIT,
1673	DBG_LOUD, ("Find 92DE MAC0.\n"));
1674	rtlhal->interfaceindex = 0;
1675	} else if (revisionid == 1) {
1676	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1677	("Find 92DE MAC1.\n"));
1678	rtlhal->interfaceindex = 1;
1679	}
1680	} else {
1681	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1682	("Unknown device - "
1683	"VendorID/DeviceID=%x/%x, Revision=%x\n",
1684	venderid, deviceid, revisionid));
1685	rtlhal->interfaceindex = 0;
1686	}
1687	}
1688	/find bus info /
1689	pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1690	pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1691	pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1692
1693	if (bridge_pdev) {
1694	/find bridge info if available /
1695	pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1696	for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1697	if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1698	pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1699	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1700	("Pci Bridge Vendor is found index:"
1701	" %d\n", tmp));
1702	break;
1703	}
1704	}
1705	}
1706
1707	if (pcipriv->ndis_adapter.pcibridge_vendor !=
1708	PCI_BRIDGE_VENDOR_UNKNOWN) {
1709	pcipriv->ndis_adapter.pcibridge_busnum =
1710	bridge_pdev->bus->number;
1711	pcipriv->ndis_adapter.pcibridge_devnum =
1712	PCI_SLOT(bridge_pdev->devfn);
1713	pcipriv->ndis_adapter.pcibridge_funcnum =
1714	PCI_FUNC(bridge_pdev->devfn);
1715	pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1716	pci_pcie_cap(bridge_pdev);
1717	pcipriv->ndis_adapter.num4bytes =
1718	(pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1719
1720	rtl_pci_get_linkcontrol_field(hw);
1721
1722	if (pcipriv->ndis_adapter.pcibridge_vendor ==
1723	PCI_BRIDGE_VENDOR_AMD) {
1724	pcipriv->ndis_adapter.amd_l1_patch =
1725	rtl_pci_get_amd_l1_patch(hw);
1726	}
1727	}
1728
1729	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1730	("pcidev busnumber:devnumber:funcnumber:"
1731	"vendor:link_ctl %d:%d:%d:%x:%x\n",
1732	pcipriv->ndis_adapter.busnumber,
1733	pcipriv->ndis_adapter.devnumber,
1734	pcipriv->ndis_adapter.funcnumber,
1735	pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1736
1737	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1738	("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1739	"pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1740	pcipriv->ndis_adapter.pcibridge_busnum,
1741	pcipriv->ndis_adapter.pcibridge_devnum,
1742	pcipriv->ndis_adapter.pcibridge_funcnum,
1743	pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1744	pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1745	pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1746	pcipriv->ndis_adapter.amd_l1_patch));
1747
1748	rtl_pci_parse_configuration(pdev, hw);
1749
1750	return true;
1751	}
1752
1753	int __devinit rtl_pci_probe(struct pci_dev *pdev,
1754	const struct pci_device_id *id)
1755	{
1756	struct ieee80211_hw *hw = NULL;
1757
1758	struct rtl_priv *rtlpriv = NULL;
1759	struct rtl_pci_priv *pcipriv = NULL;
1760	struct rtl_pci *rtlpci;
1761	unsigned long pmem_start, pmem_len, pmem_flags;
1762	int err;
1763
1764	err = pci_enable_device(pdev);
1765	if (err) {
1766	RT_ASSERT(false,
1767	("%s : Cannot enable new PCI device\n",
1768	pci_name(pdev)));
1769	return err;
1770	}
1771
1772	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1773	if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1774	RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1775	"for consistent allocations\n"));
1776	pci_disable_device(pdev);
1777	return -ENOMEM;
1778	}
1779	}
1780
1781	pci_set_master(pdev);
1782
1783	hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1784	sizeof(struct rtl_priv), &rtl_ops);
1785	if (!hw) {
1786	RT_ASSERT(false,
1787	("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1788	err = -ENOMEM;
1789	goto fail1;
1790	}
1791
1792	SET_IEEE80211_DEV(hw, &pdev->dev);
1793	pci_set_drvdata(pdev, hw);
1794
1795	rtlpriv = hw->priv;
1796	pcipriv = (void *)rtlpriv->priv;
1797	pcipriv->dev.pdev = pdev;
1798
1799	/* init cfg & intf_ops */
1800	rtlpriv->rtlhal.interface = INTF_PCI;
1801	rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1802	rtlpriv->intf_ops = &rtl_pci_ops;
1803
1804	/*
1805	*init dbgp flags before all
1806	*other functions, because we will
1807	*use it in other funtions like
1808	*RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1809	*you can not use these macro
1810	*before this
1811	*/
1812	rtl_dbgp_flag_init(hw);
1813
1814	/* MEM map */
1815	err = pci_request_regions(pdev, KBUILD_MODNAME);
1816	if (err) {
1817	RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1818	return err;
1819	}
1820
1821	pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1822	pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1823	pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1824
1825	/shared mem start /
1826	rtlpriv->io.pci_mem_start =
1827	(unsigned long)pci_iomap(pdev,
1828	rtlpriv->cfg->bar_id, pmem_len);
1829	if (rtlpriv->io.pci_mem_start == 0) {
1830	RT_ASSERT(false, ("Can't map PCI mem\n"));
1831	goto fail2;
1832	}
1833
1834	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1835	("mem mapped space: start: 0x%08lx len:%08lx "
1836	"flags:%08lx, after map:0x%08lx\n",
1837	pmem_start, pmem_len, pmem_flags,
1838	rtlpriv->io.pci_mem_start));
1839
1840	/* Disable Clk Request */
1841	pci_write_config_byte(pdev, 0x81, 0);
1842	/* leave D3 mode */
1843	pci_write_config_byte(pdev, 0x44, 0);
1844	pci_write_config_byte(pdev, 0x04, 0x06);
1845	pci_write_config_byte(pdev, 0x04, 0x07);
1846
1847	/* find adapter */
1848	if (!_rtl_pci_find_adapter(pdev, hw))
1849	goto fail3;
1850
1851	/* Init IO handler */
1852	_rtl_pci_io_handler_init(&pdev->dev, hw);
1853
1854	/like read eeprom and so on /
1855	rtlpriv->cfg->ops->read_eeprom_info(hw);
1856
1857	if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1858	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1859	("Can't init_sw_vars.\n"));
1860	goto fail3;
1861	}
1862
1863	rtlpriv->cfg->ops->init_sw_leds(hw);
1864
1865	/aspm /
1866	rtl_pci_init_aspm(hw);
1867
1868	/* Init mac80211 sw */
1869	err = rtl_init_core(hw);
1870	if (err) {
1871	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1872	("Can't allocate sw for mac80211.\n"));
1873	goto fail3;
1874	}
1875
1876	/* Init PCI sw */
1877	err = !rtl_pci_init(hw, pdev);
1878	if (err) {
1879	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1880	("Failed to init PCI.\n"));
1881	goto fail3;
1882	}
1883
1884	err = ieee80211_register_hw(hw);
1885	if (err) {
1886	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1887	("Can't register mac80211 hw.\n"));
1888	goto fail3;
1889	} else {
1890	rtlpriv->mac80211.mac80211_registered = 1;
1891	}
1892
1893	err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1894	if (err) {
1895	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1896	("failed to create sysfs device attributes\n"));
1897	goto fail3;
1898	}
1899
1900	/init rfkill /
1901	rtl_init_rfkill(hw);
1902
1903	rtlpci = rtl_pcidev(pcipriv);
1904	err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1905	IRQF_SHARED, KBUILD_MODNAME, hw);
1906	if (err) {
1907	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1908	("%s: failed to register IRQ handler\n",
1909	wiphy_name(hw->wiphy)));
1910	goto fail3;
1911	} else {
1912	rtlpci->irq_alloc = 1;
1913	}
1914
1915	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1916	return 0;
1917
1918	fail3:
1919	pci_set_drvdata(pdev, NULL);
1920	rtl_deinit_core(hw);
1921	_rtl_pci_io_handler_release(hw);
1922	ieee80211_free_hw(hw);
1923
1924	if (rtlpriv->io.pci_mem_start != 0)
1925	pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1926
1927	fail2:
1928	pci_release_regions(pdev);
1929
1930	fail1:
1931
1932	pci_disable_device(pdev);
1933
1934	return -ENODEV;
1935
1936	}
1937	EXPORT_SYMBOL(rtl_pci_probe);
1938
1939	void rtl_pci_disconnect(struct pci_dev *pdev)
1940	{
1941	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1942	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1943	struct rtl_priv *rtlpriv = rtl_priv(hw);
1944	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1945	struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1946
1947	clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1948
1949	sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1950
1951	/ieee80211_unregister_hw will call ops_stop /
1952	if (rtlmac->mac80211_registered == 1) {
1953	ieee80211_unregister_hw(hw);
1954	rtlmac->mac80211_registered = 0;
1955	} else {
1956	rtl_deinit_deferred_work(hw);
1957	rtlpriv->intf_ops->adapter_stop(hw);
1958	}
1959
1960	/deinit rfkill /
1961	rtl_deinit_rfkill(hw);
1962
1963	rtl_pci_deinit(hw);
1964	rtl_deinit_core(hw);
1965	_rtl_pci_io_handler_release(hw);
1966	rtlpriv->cfg->ops->deinit_sw_vars(hw);
1967
1968	if (rtlpci->irq_alloc) {
1969	free_irq(rtlpci->pdev->irq, hw);
1970	rtlpci->irq_alloc = 0;
1971	}
1972
1973	if (rtlpriv->io.pci_mem_start != 0) {
1974	pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1975	pci_release_regions(pdev);
1976	}
1977
1978	pci_disable_device(pdev);
1979
1980	rtl_pci_disable_aspm(hw);
1981
1982	pci_set_drvdata(pdev, NULL);
1983
1984	ieee80211_free_hw(hw);
1985	}
1986	EXPORT_SYMBOL(rtl_pci_disconnect);
1987
1988	/***************************************
1989	kernel pci power state define:
1990	PCI_D0 ((pci_power_t __force) 0)
1991	PCI_D1 ((pci_power_t __force) 1)
1992	PCI_D2 ((pci_power_t __force) 2)
1993	PCI_D3hot ((pci_power_t __force) 3)
1994	PCI_D3cold ((pci_power_t __force) 4)
1995	PCI_UNKNOWN ((pci_power_t __force) 5)
1996
1997	This function is called when system
1998	goes into suspend state mac80211 will
1999	call rtl_mac_stop() from the mac80211
2000	suspend function first, So there is
2001	no need to call hw_disable here.
2002	****************************************/
2003	int rtl_pci_suspend(struct device *dev)
2004	{
2005	struct pci_dev *pdev = to_pci_dev(dev);
2006	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2007	struct rtl_priv *rtlpriv = rtl_priv(hw);
2008
2009	rtlpriv->cfg->ops->hw_suspend(hw);
2010	rtl_deinit_rfkill(hw);
2011
2012	return 0;
2013	}
2014	EXPORT_SYMBOL(rtl_pci_suspend);
2015
2016	int rtl_pci_resume(struct device *dev)
2017	{
2018	struct pci_dev *pdev = to_pci_dev(dev);
2019	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2020	struct rtl_priv *rtlpriv = rtl_priv(hw);
2021
2022	rtlpriv->cfg->ops->hw_resume(hw);
2023	rtl_init_rfkill(hw);
2024	return 0;
2025	}
2026	EXPORT_SYMBOL(rtl_pci_resume);
2027
2028	struct rtl_intf_ops rtl_pci_ops = {
2029	.read_efuse_byte = read_efuse_byte,
2030	.adapter_start = rtl_pci_start,
2031	.adapter_stop = rtl_pci_stop,
2032	.adapter_tx = rtl_pci_tx,
2033	.flush = rtl_pci_flush,
2034	.reset_trx_ring = rtl_pci_reset_trx_ring,
2035	.waitq_insert = rtl_pci_tx_chk_waitq_insert,
2036
2037	.disable_aspm = rtl_pci_disable_aspm,
2038	.enable_aspm = rtl_pci_enable_aspm,
2039	};

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