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source: src/linux/universal/linux-3.2/drivers/tty/serial/8250.c @ 18368

Last change on this file since 18368 was 18368, checked in by BrainSlayer, 16 months ago
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File size: 84.9 KB

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1	/*
2	* Driver for 8250/16550-type serial ports
3	*
4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5	*
6	* Copyright (C) 2001 Russell King.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License as published by
10	* the Free Software Foundation; either version 2 of the License, or
11	* (at your option) any later version.
12	*
13	* A note about mapbase / membase
14	*
15	* mapbase is the physical address of the IO port.
16	* membase is an 'ioremapped' cookie.
17	*/
18
19	#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20	#define SUPPORT_SYSRQ
21	#endif
22
23	#include <linux/module.h>
24	#include <linux/moduleparam.h>
25	#include <linux/ioport.h>
26	#include <linux/init.h>
27	#include <linux/console.h>
28	#include <linux/sysrq.h>
29	#include <linux/delay.h>
30	#include <linux/platform_device.h>
31	#include <linux/tty.h>
32	#include <linux/ratelimit.h>
33	#include <linux/tty_flip.h>
34	#include <linux/serial_reg.h>
35	#include <linux/serial_core.h>
36	#include <linux/serial.h>
37	#include <linux/serial_8250.h>
38	#include <linux/nmi.h>
39	#include <linux/mutex.h>
40	#include <linux/slab.h>
41
42	#include <asm/io.h>
43	#include <asm/irq.h>
44
45	#include "8250.h"
46
47	#ifdef CONFIG_SPARC
48	#include "suncore.h"
49	#endif
50
51	/*
52	* Configuration:
53	* share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54	* is unsafe when used on edge-triggered interrupts.
55	*/
56	static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58	static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60	static struct uart_driver serial8250_reg;
61
62	static int serial_index(struct uart_port *port)
63	{
64	return (serial8250_reg.minor - 64) + port->line;
65	}
66
67	static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69	/*
70	* Debugging.
71	*/
72	#if 0
73	#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74	#else
75	#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76	#endif
77
78	#if 0
79	#define DEBUG_INTR(fmt...) printk(fmt)
80	#else
81	#define DEBUG_INTR(fmt...) do { } while (0)
82	#endif
83
84	#define PASS_LIMIT 512
85
86	#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)
87
88
89	/*
90	* We default to IRQ0 for the "no irq" hack. Some
91	* machine types want others as well - they're free
92	* to redefine this in their header file.
93	*/
94	#define is_real_interrupt(irq) ((irq) != 0)
95
96	#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97	#define CONFIG_SERIAL_DETECT_IRQ 1
98	#endif
99	#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100	#define CONFIG_SERIAL_MANY_PORTS 1
101	#endif
102
103	/*
104	* HUB6 is always on. This will be removed once the header
105	* files have been cleaned.
106	*/
107	#define CONFIG_HUB6 1
108
109	#include <asm/serial.h>
110	/*
111	* SERIAL_PORT_DFNS tells us about built-in ports that have no
112	* standard enumeration mechanism. Platforms that can find all
113	* serial ports via mechanisms like ACPI or PCI need not supply it.
114	*/
115	#ifndef SERIAL_PORT_DFNS
116	#define SERIAL_PORT_DFNS
117	#endif
118
119	static const struct old_serial_port old_serial_port[] = {
120	SERIAL_PORT_DFNS /* defined in asm/serial.h */
121	};
122
123	#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125	#ifdef CONFIG_SERIAL_8250_RSA
126
127	#define PORT_RSA_MAX 4
128	static unsigned long probe_rsa[PORT_RSA_MAX];
129	static unsigned int probe_rsa_count;
130	#endif /* CONFIG_SERIAL_8250_RSA */
131
132	struct uart_8250_port {
133	struct uart_port port;
134	struct timer_list timer; /* "no irq" timer */
135	struct list_head list; /* ports on this IRQ */
136	unsigned short capabilities; /* port capabilities */
137	unsigned short bugs; /* port bugs */
138	unsigned int tx_loadsz; /* transmit fifo load size */
139	unsigned char acr;
140	unsigned char ier;
141	unsigned char lcr;
142	unsigned char mcr;
143	unsigned char mcr_mask; /* mask of user bits */
144	unsigned char mcr_force; /* mask of forced bits */
145	unsigned char cur_iotype; /* Running I/O type */
146
147	/*
148	* Some bits in registers are cleared on a read, so they must
149	* be saved whenever the register is read but the bits will not
150	* be immediately processed.
151	*/
152	#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153	unsigned char lsr_saved_flags;
154	#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155	unsigned char msr_saved_flags;
156	};
157
158	struct irq_info {
159	struct hlist_node node;
160	int irq;
161	spinlock_t lock; /* Protects list not the hash */
162	struct list_head *head;
163	};
164
165	#define NR_IRQ_HASH 32 /* Can be adjusted later */
166	static struct hlist_head irq_lists[NR_IRQ_HASH];
167	static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169	/*
170	* Here we define the default xmit fifo size used for each type of UART.
171	*/
172	static const struct serial8250_config uart_config[] = {
173	[PORT_UNKNOWN] = {
174	.name = "unknown",
175	.fifo_size = 1,
176	.tx_loadsz = 1,
177	},
178	[PORT_8250] = {
179	.name = "8250",
180	.fifo_size = 1,
181	.tx_loadsz = 1,
182	},
183	[PORT_16450] = {
184	.name = "16450",
185	.fifo_size = 1,
186	.tx_loadsz = 1,
187	},
188	[PORT_16550] = {
189	.name = "16550",
190	.fifo_size = 1,
191	.tx_loadsz = 1,
192	},
193	[PORT_16550A] = {
194	.name = "16550A",
195	.fifo_size = 16,
196	.tx_loadsz = 16,
197	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
198	.flags = UART_CAP_FIFO,
199	},
200	[PORT_CIRRUS] = {
201	.name = "Cirrus",
202	.fifo_size = 1,
203	.tx_loadsz = 1,
204	},
205	[PORT_16650] = {
206	.name = "ST16650",
207	.fifo_size = 1,
208	.tx_loadsz = 1,
209	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
210	},
211	[PORT_16650V2] = {
212	.name = "ST16650V2",
213	.fifo_size = 32,
214	.tx_loadsz = 16,
215	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
216	UART_FCR_T_TRIG_00,
217	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
218	},
219	[PORT_16750] = {
220	.name = "TI16750",
221	.fifo_size = 64,
222	.tx_loadsz = 64,
223	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10 \|
224	UART_FCR7_64BYTE,
225	.flags = UART_CAP_FIFO \| UART_CAP_SLEEP \| UART_CAP_AFE,
226	},
227	[PORT_STARTECH] = {
228	.name = "Startech",
229	.fifo_size = 1,
230	.tx_loadsz = 1,
231	},
232	[PORT_16C950] = {
233	.name = "16C950/954",
234	.fifo_size = 128,
235	.tx_loadsz = 128,
236	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
237	/* UART_CAP_EFR breaks billionon CF bluetooth card. */
238	.flags = UART_CAP_FIFO \| UART_CAP_SLEEP,
239	},
240	[PORT_16654] = {
241	.name = "ST16654",
242	.fifo_size = 64,
243	.tx_loadsz = 32,
244	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
245	UART_FCR_T_TRIG_10,
246	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
247	},
248	[PORT_16850] = {
249	.name = "XR16850",
250	.fifo_size = 128,
251	.tx_loadsz = 128,
252	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
253	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
254	},
255	[PORT_RSA] = {
256	.name = "RSA",
257	.fifo_size = 2048,
258	.tx_loadsz = 2048,
259	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_11,
260	.flags = UART_CAP_FIFO,
261	},
262	[PORT_NS16550A] = {
263	.name = "NS16550A",
264	.fifo_size = 16,
265	.tx_loadsz = 16,
266	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
267	.flags = UART_CAP_FIFO \| UART_NATSEMI,
268	},
269	[PORT_XSCALE] = {
270	.name = "XScale",
271	.fifo_size = 32,
272	.tx_loadsz = 32,
273	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
274	.flags = UART_CAP_FIFO \| UART_CAP_UUE \| UART_CAP_RTOIE,
275	},
276	[PORT_RM9000] = {
277	.name = "RM9000",
278	.fifo_size = 16,
279	.tx_loadsz = 16,
280	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
281	.flags = UART_CAP_FIFO,
282	},
283	[PORT_OCTEON] = {
284	.name = "OCTEON",
285	.fifo_size = 64,
286	.tx_loadsz = 64,
287	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
288	.flags = UART_CAP_FIFO,
289	},
290	[PORT_AR7] = {
291	.name = "AR7",
292	.fifo_size = 16,
293	.tx_loadsz = 16,
294	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_00,
295	.flags = UART_CAP_FIFO \| UART_CAP_AFE,
296	},
297	[PORT_U6_16550A] = {
298	.name = "U6_16550A",
299	.fifo_size = 64,
300	.tx_loadsz = 64,
301	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
302	.flags = UART_CAP_FIFO \| UART_CAP_AFE,
303	},
304	[PORT_TEGRA] = {
305	.name = "Tegra",
306	.fifo_size = 32,
307	.tx_loadsz = 8,
308	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
309	UART_FCR_T_TRIG_01,
310	.flags = UART_CAP_FIFO \| UART_CAP_RTOIE,
311	},
312	[PORT_XR17D15X] = {
313	.name = "XR17D15X",
314	.fifo_size = 64,
315	.tx_loadsz = 64,
316	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
317	.flags = UART_CAP_FIFO \| UART_CAP_AFE \| UART_CAP_EFR,
318	},
319	};
320
321	#if defined(CONFIG_MIPS_ALCHEMY) \|\| defined (CONFIG_SERIAL_8250_RT288X)
322
323	/* Au1x00 and RT288x UART hardware has a weird register layout */
324	static const u8 au_io_in_map[] = {
325	[UART_RX] = 0,
326	[UART_IER] = 2,
327	[UART_IIR] = 3,
328	[UART_LCR] = 5,
329	[UART_MCR] = 6,
330	[UART_LSR] = 7,
331	[UART_MSR] = 8,
332	};
333
334	static const u8 au_io_out_map[] = {
335	[UART_TX] = 1,
336	[UART_IER] = 2,
337	[UART_FCR] = 4,
338	[UART_LCR] = 5,
339	[UART_MCR] = 6,
340	};
341
342	/* sane hardware needs no mapping */
343	static inline int map_8250_in_reg(struct uart_port *p, int offset)
344	{
345	if (p->iotype != UPIO_AU)
346	return offset;
347	return au_io_in_map[offset];
348	}
349
350	static inline int map_8250_out_reg(struct uart_port *p, int offset)
351	{
352	if (p->iotype != UPIO_AU)
353	return offset;
354	return au_io_out_map[offset];
355	}
356
357	#elif defined(CONFIG_SERIAL_8250_RM9K)
358
359	static const u8
360	regmap_in[8] = {
361	[UART_RX] = 0x00,
362	[UART_IER] = 0x0c,
363	[UART_IIR] = 0x14,
364	[UART_LCR] = 0x1c,
365	[UART_MCR] = 0x20,
366	[UART_LSR] = 0x24,
367	[UART_MSR] = 0x28,
368	[UART_SCR] = 0x2c
369	},
370	regmap_out[8] = {
371	[UART_TX] = 0x04,
372	[UART_IER] = 0x0c,
373	[UART_FCR] = 0x18,
374	[UART_LCR] = 0x1c,
375	[UART_MCR] = 0x20,
376	[UART_LSR] = 0x24,
377	[UART_MSR] = 0x28,
378	[UART_SCR] = 0x2c
379	};
380
381	static inline int map_8250_in_reg(struct uart_port *p, int offset)
382	{
383	if (p->iotype != UPIO_RM9000)
384	return offset;
385	return regmap_in[offset];
386	}
387
388	static inline int map_8250_out_reg(struct uart_port *p, int offset)
389	{
390	if (p->iotype != UPIO_RM9000)
391	return offset;
392	return regmap_out[offset];
393	}
394
395	#else
396
397	/* sane hardware needs no mapping */
398	#define map_8250_in_reg(up, offset) (offset)
399	#define map_8250_out_reg(up, offset) (offset)
400
401	#endif
402
403	static unsigned int hub6_serial_in(struct uart_port *p, int offset)
404	{
405	offset = map_8250_in_reg(p, offset) << p->regshift;
406	outb(p->hub6 - 1 + offset, p->iobase);
407	return inb(p->iobase + 1);
408	}
409
410	static void hub6_serial_out(struct uart_port *p, int offset, int value)
411	{
412	offset = map_8250_out_reg(p, offset) << p->regshift;
413	outb(p->hub6 - 1 + offset, p->iobase);
414	outb(value, p->iobase + 1);
415	}
416
417	static unsigned int mem_serial_in(struct uart_port *p, int offset)
418	{
419	offset = map_8250_in_reg(p, offset) << p->regshift;
420	return readb(p->membase + offset);
421	}
422
423	static void mem_serial_out(struct uart_port *p, int offset, int value)
424	{
425	offset = map_8250_out_reg(p, offset) << p->regshift;
426	writeb(value, p->membase + offset);
427	}
428
429	static unsigned int memdelay_serial_in(struct uart_port *p, int offset)
430	{
431	struct uart_8250_port up = (struct uart_8250_port )p;
432	udelay(up->port.rw_delay);
433	return mem_serial_in(p, offset);
434	}
435
436	static void memdelay_serial_out(struct uart_port *p, int offset, int value)
437	{
438	struct uart_8250_port up = (struct uart_8250_port )p;
439	udelay(up->port.rw_delay);
440	mem_serial_out(p, offset, value);
441	}
442
443	static void mem32_serial_out(struct uart_port *p, int offset, int value)
444	{
445	offset = map_8250_out_reg(p, offset) << p->regshift;
446	writel(value, p->membase + offset);
447	}
448
449	static unsigned int mem32_serial_in(struct uart_port *p, int offset)
450	{
451	offset = map_8250_in_reg(p, offset) << p->regshift;
452	return readl(p->membase + offset);
453	}
454
455	static unsigned int au_serial_in(struct uart_port *p, int offset)
456	{
457	offset = map_8250_in_reg(p, offset) << p->regshift;
458	return __raw_readl(p->membase + offset);
459	}
460
461	static void au_serial_out(struct uart_port *p, int offset, int value)
462	{
463	offset = map_8250_out_reg(p, offset) << p->regshift;
464	__raw_writel(value, p->membase + offset);
465	}
466
467	static unsigned int io_serial_in(struct uart_port *p, int offset)
468	{
469	offset = map_8250_in_reg(p, offset) << p->regshift;
470	return inb(p->iobase + offset);
471	}
472
473	static void io_serial_out(struct uart_port *p, int offset, int value)
474	{
475	offset = map_8250_out_reg(p, offset) << p->regshift;
476	outb(value, p->iobase + offset);
477	}
478
479	static int serial8250_default_handle_irq(struct uart_port *port);
480
481	static void set_io_from_upio(struct uart_port *p)
482	{
483	struct uart_8250_port *up =
484	container_of(p, struct uart_8250_port, port);
485	switch (p->iotype) {
486	case UPIO_HUB6:
487	p->serial_in = hub6_serial_in;
488	p->serial_out = hub6_serial_out;
489	break;
490
491	case UPIO_MEM:
492	p->serial_in = mem_serial_in;
493	p->serial_out = mem_serial_out;
494	break;
495
496	case UPIO_RM9000:
497	case UPIO_MEM32:
498	p->serial_in = mem32_serial_in;
499	p->serial_out = mem32_serial_out;
500	break;
501
502	case UPIO_MEM_DELAY:
503	p->serial_in = memdelay_serial_in;
504	p->serial_out = memdelay_serial_out;
505	break;
506
507	case UPIO_AU:
508	p->serial_in = au_serial_in;
509	p->serial_out = au_serial_out;
510	break;
511
512	default:
513	p->serial_in = io_serial_in;
514	p->serial_out = io_serial_out;
515	break;
516	}
517	/* Remember loaded iotype */
518	up->cur_iotype = p->iotype;
519	p->handle_irq = serial8250_default_handle_irq;
520	}
521
522	static void
523	serial_out_sync(struct uart_8250_port *up, int offset, int value)
524	{
525	struct uart_port *p = &up->port;
526	switch (p->iotype) {
527	case UPIO_MEM:
528	case UPIO_MEM32:
529	case UPIO_MEM_DELAY:
530	case UPIO_AU:
531	p->serial_out(p, offset, value);
532	p->serial_in(p, UART_LCR); /* safe, no side-effects */
533	break;
534	default:
535	p->serial_out(p, offset, value);
536	}
537	}
538
539	#define serial_in(up, offset) \
540	(up->port.serial_in(&(up)->port, (offset)))
541	#define serial_out(up, offset, value) \
542	(up->port.serial_out(&(up)->port, (offset), (value)))
543	/*
544	* We used to support using pause I/O for certain machines. We
545	* haven't supported this for a while, but just in case it's badly
546	* needed for certain old 386 machines, I've left these #define's
547	* in....
548	*/
549	#define serial_inp(up, offset) serial_in(up, offset)
550	#define serial_outp(up, offset, value) serial_out(up, offset, value)
551
552	/* Uart divisor latch read */
553	static inline int _serial_dl_read(struct uart_8250_port *up)
554	{
555	return serial_inp(up, UART_DLL) \| serial_inp(up, UART_DLM) << 8;
556	}
557
558	/* Uart divisor latch write */
559	static inline void _serial_dl_write(struct uart_8250_port *up, int value)
560	{
561	serial_outp(up, UART_DLL, value & 0xff);
562	serial_outp(up, UART_DLM, value >> 8 & 0xff);
563	}
564
565	#if defined(CONFIG_MIPS_ALCHEMY) \|\| defined (CONFIG_SERIAL_8250_RT288X)
566	/* Au1x00 and RT288x haven't got a standard divisor latch */
567	static int serial_dl_read(struct uart_8250_port *up)
568	{
569	if (up->port.iotype == UPIO_AU)
570	return __raw_readl(up->port.membase + 0x28);
571	else
572	return _serial_dl_read(up);
573	}
574
575	static void serial_dl_write(struct uart_8250_port *up, int value)
576	{
577	if (up->port.iotype == UPIO_AU)
578	__raw_writel(value, up->port.membase + 0x28);
579	else
580	_serial_dl_write(up, value);
581	}
582	#elif defined(CONFIG_SERIAL_8250_RM9K)
583	static int serial_dl_read(struct uart_8250_port *up)
584	{
585	return (up->port.iotype == UPIO_RM9000) ?
586	(((__raw_readl(up->port.membase + 0x10) << 8) \|
587	(__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
588	_serial_dl_read(up);
589	}
590
591	static void serial_dl_write(struct uart_8250_port *up, int value)
592	{
593	if (up->port.iotype == UPIO_RM9000) {
594	__raw_writel(value, up->port.membase + 0x08);
595	__raw_writel(value >> 8, up->port.membase + 0x10);
596	} else {
597	_serial_dl_write(up, value);
598	}
599	}
600	#else
601	#define serial_dl_read(up) _serial_dl_read(up)
602	#define serial_dl_write(up, value) _serial_dl_write(up, value)
603	#endif
604
605	/*
606	* For the 16C950
607	*/
608	static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
609	{
610	serial_out(up, UART_SCR, offset);
611	serial_out(up, UART_ICR, value);
612	}
613
614	static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
615	{
616	unsigned int value;
617
618	serial_icr_write(up, UART_ACR, up->acr \| UART_ACR_ICRRD);
619	serial_out(up, UART_SCR, offset);
620	value = serial_in(up, UART_ICR);
621	serial_icr_write(up, UART_ACR, up->acr);
622
623	return value;
624	}
625
626	/*
627	* FIFO support.
628	*/
629	static void serial8250_clear_fifos(struct uart_8250_port *p)
630	{
631	if (p->capabilities & UART_CAP_FIFO) {
632	serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
633	serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO \|
634	UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
635	serial_outp(p, UART_FCR, 0);
636	}
637	}
638
639	/*
640	* IER sleep support. UARTs which have EFRs need the "extended
641	* capability" bit enabled. Note that on XR16C850s, we need to
642	* reset LCR to write to IER.
643	*/
644	static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
645	{
646	if (p->capabilities & UART_CAP_SLEEP) {
647	if (p->capabilities & UART_CAP_EFR) {
648	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
649	serial_outp(p, UART_EFR, UART_EFR_ECB);
650	serial_outp(p, UART_LCR, 0);
651	}
652	serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
653	if (p->capabilities & UART_CAP_EFR) {
654	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
655	serial_outp(p, UART_EFR, 0);
656	serial_outp(p, UART_LCR, 0);
657	}
658	}
659	}
660
661	#ifdef CONFIG_SERIAL_8250_RSA
662	/*
663	* Attempts to turn on the RSA FIFO. Returns zero on failure.
664	* We set the port uart clock rate if we succeed.
665	*/
666	static int __enable_rsa(struct uart_8250_port *up)
667	{
668	unsigned char mode;
669	int result;
670
671	mode = serial_inp(up, UART_RSA_MSR);
672	result = mode & UART_RSA_MSR_FIFO;
673
674	if (!result) {
675	serial_outp(up, UART_RSA_MSR, mode \| UART_RSA_MSR_FIFO);
676	mode = serial_inp(up, UART_RSA_MSR);
677	result = mode & UART_RSA_MSR_FIFO;
678	}
679
680	if (result)
681	up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
682
683	return result;
684	}
685
686	static void enable_rsa(struct uart_8250_port *up)
687	{
688	if (up->port.type == PORT_RSA) {
689	if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
690	spin_lock_irq(&up->port.lock);
691	__enable_rsa(up);
692	spin_unlock_irq(&up->port.lock);
693	}
694	if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
695	serial_outp(up, UART_RSA_FRR, 0);
696	}
697	}
698
699	/*
700	* Attempts to turn off the RSA FIFO. Returns zero on failure.
701	* It is unknown why interrupts were disabled in here. However,
702	* the caller is expected to preserve this behaviour by grabbing
703	* the spinlock before calling this function.
704	*/
705	static void disable_rsa(struct uart_8250_port *up)
706	{
707	unsigned char mode;
708	int result;
709
710	if (up->port.type == PORT_RSA &&
711	up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
712	spin_lock_irq(&up->port.lock);
713
714	mode = serial_inp(up, UART_RSA_MSR);
715	result = !(mode & UART_RSA_MSR_FIFO);
716
717	if (!result) {
718	serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
719	mode = serial_inp(up, UART_RSA_MSR);
720	result = !(mode & UART_RSA_MSR_FIFO);
721	}
722
723	if (result)
724	up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
725	spin_unlock_irq(&up->port.lock);
726	}
727	}
728	#endif /* CONFIG_SERIAL_8250_RSA */
729
730	/*
731	* This is a quickie test to see how big the FIFO is.
732	* It doesn't work at all the time, more's the pity.
733	*/
734	static int size_fifo(struct uart_8250_port *up)
735	{
736	unsigned char old_fcr, old_mcr, old_lcr;
737	unsigned short old_dl;
738	int count;
739
740	old_lcr = serial_inp(up, UART_LCR);
741	serial_outp(up, UART_LCR, 0);
742	old_fcr = serial_inp(up, UART_FCR);
743	old_mcr = serial_inp(up, UART_MCR);
744	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \|
745	UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
746	serial_outp(up, UART_MCR, UART_MCR_LOOP);
747	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
748	old_dl = serial_dl_read(up);
749	serial_dl_write(up, 0x0001);
750	serial_outp(up, UART_LCR, 0x03);
751	for (count = 0; count < 256; count++)
752	serial_outp(up, UART_TX, count);
753	mdelay(20);/* FIXME - schedule_timeout */
754	for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
755	(count < 256); count++)
756	serial_inp(up, UART_RX);
757	serial_outp(up, UART_FCR, old_fcr);
758	serial_outp(up, UART_MCR, old_mcr);
759	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
760	serial_dl_write(up, old_dl);
761	serial_outp(up, UART_LCR, old_lcr);
762
763	return count;
764	}
765
766	/*
767	* Read UART ID using the divisor method - set DLL and DLM to zero
768	* and the revision will be in DLL and device type in DLM. We
769	* preserve the device state across this.
770	*/
771	static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
772	{
773	unsigned char old_lcr;
774	unsigned int old_dl;
775	unsigned int id;
776
777	old_lcr = serial_inp(p, UART_LCR);
778	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
779
780	old_dl = serial_dl_read(p);
781
782	serial_dl_write(p, 0);
783	id = serial_dl_read(p);
784
785	serial_dl_write(p, old_dl);
786	serial_outp(p, UART_LCR, old_lcr);
787
788	return id;
789	}
790
791	/*
792	* This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
793	* When this function is called we know it is at least a StarTech
794	* 16650 V2, but it might be one of several StarTech UARTs, or one of
795	* its clones. (We treat the broken original StarTech 16650 V1 as a
796	* 16550, and why not? Startech doesn't seem to even acknowledge its
797	* existence.)
798	*
799	* What evil have men's minds wrought...
800	*/
801	static void autoconfig_has_efr(struct uart_8250_port *up)
802	{
803	unsigned int id1, id2, id3, rev;
804
805	/*
806	* Everything with an EFR has SLEEP
807	*/
808	up->capabilities \|= UART_CAP_EFR \| UART_CAP_SLEEP;
809
810	/*
811	* First we check to see if it's an Oxford Semiconductor UART.
812	*
813	* If we have to do this here because some non-National
814	* Semiconductor clone chips lock up if you try writing to the
815	* LSR register (which serial_icr_read does)
816	*/
817
818	/*
819	* Check for Oxford Semiconductor 16C950.
820	*
821	* EFR [4] must be set else this test fails.
822	*
823	* This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
824	* claims that it's needed for 952 dual UART's (which are not
825	* recommended for new designs).
826	*/
827	up->acr = 0;
828	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
829	serial_out(up, UART_EFR, UART_EFR_ECB);
830	serial_out(up, UART_LCR, 0x00);
831	id1 = serial_icr_read(up, UART_ID1);
832	id2 = serial_icr_read(up, UART_ID2);
833	id3 = serial_icr_read(up, UART_ID3);
834	rev = serial_icr_read(up, UART_REV);
835
836	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
837
838	if (id1 == 0x16 && id2 == 0xC9 &&
839	(id3 == 0x50 \|\| id3 == 0x52 \|\| id3 == 0x54)) {
840	up->port.type = PORT_16C950;
841
842	/*
843	* Enable work around for the Oxford Semiconductor 952 rev B
844	* chip which causes it to seriously miscalculate baud rates
845	* when DLL is 0.
846	*/
847	if (id3 == 0x52 && rev == 0x01)
848	up->bugs \|= UART_BUG_QUOT;
849	return;
850	}
851
852	/*
853	* We check for a XR16C850 by setting DLL and DLM to 0, and then
854	* reading back DLL and DLM. The chip type depends on the DLM
855	* value read back:
856	* 0x10 - XR16C850 and the DLL contains the chip revision.
857	* 0x12 - XR16C2850.
858	* 0x14 - XR16C854.
859	*/
860	id1 = autoconfig_read_divisor_id(up);
861	DEBUG_AUTOCONF("850id=%04x ", id1);
862
863	id2 = id1 >> 8;
864	if (id2 == 0x10 \|\| id2 == 0x12 \|\| id2 == 0x14) {
865	up->port.type = PORT_16850;
866	return;
867	}
868
869	/*
870	* It wasn't an XR16C850.
871	*
872	* We distinguish between the '654 and the '650 by counting
873	* how many bytes are in the FIFO. I'm using this for now,
874	* since that's the technique that was sent to me in the
875	* serial driver update, but I'm not convinced this works.
876	* I've had problems doing this in the past. -TYT
877	*/
878	if (size_fifo(up) == 64)
879	up->port.type = PORT_16654;
880	else
881	up->port.type = PORT_16650V2;
882	}
883
884	/*
885	* We detected a chip without a FIFO. Only two fall into
886	* this category - the original 8250 and the 16450. The
887	* 16450 has a scratch register (accessible with LCR=0)
888	*/
889	static void autoconfig_8250(struct uart_8250_port *up)
890	{
891	unsigned char scratch, status1, status2;
892
893	up->port.type = PORT_8250;
894
895	scratch = serial_in(up, UART_SCR);
896	serial_outp(up, UART_SCR, 0xa5);
897	status1 = serial_in(up, UART_SCR);
898	serial_outp(up, UART_SCR, 0x5a);
899	status2 = serial_in(up, UART_SCR);
900	serial_outp(up, UART_SCR, scratch);
901
902	if (status1 == 0xa5 && status2 == 0x5a)
903	up->port.type = PORT_16450;
904	}
905
906	static int broken_efr(struct uart_8250_port *up)
907	{
908	/*
909	* Exar ST16C2550 "A2" devices incorrectly detect as
910	* having an EFR, and report an ID of 0x0201. See
911	* http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
912	*/
913	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
914	return 1;
915
916	return 0;
917	}
918
919	static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
920	{
921	unsigned char status;
922
923	status = serial_in(up, 0x04); /* EXCR2 */
924	#define PRESL(x) ((x) & 0x30)
925	if (PRESL(status) == 0x10) {
926	/* already in high speed mode */
927	return 0;
928	} else {
929	status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
930	status \|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
931	serial_outp(up, 0x04, status);
932	}
933	return 1;
934	}
935
936	/*
937	* We know that the chip has FIFOs. Does it have an EFR? The
938	* EFR is located in the same register position as the IIR and
939	* we know the top two bits of the IIR are currently set. The
940	* EFR should contain zero. Try to read the EFR.
941	*/
942	static void autoconfig_16550a(struct uart_8250_port *up)
943	{
944	unsigned char status1, status2;
945	unsigned int iersave;
946
947	up->port.type = PORT_16550A;
948	up->capabilities \|= UART_CAP_FIFO;
949
950	/*
951	* Check for presence of the EFR when DLAB is set.
952	* Only ST16C650V1 UARTs pass this test.
953	*/
954	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
955	if (serial_in(up, UART_EFR) == 0) {
956	serial_outp(up, UART_EFR, 0xA8);
957	if (serial_in(up, UART_EFR) != 0) {
958	DEBUG_AUTOCONF("EFRv1 ");
959	up->port.type = PORT_16650;
960	up->capabilities \|= UART_CAP_EFR \| UART_CAP_SLEEP;
961	} else {
962	DEBUG_AUTOCONF("Motorola 8xxx DUART ");
963	}
964	serial_outp(up, UART_EFR, 0);
965	return;
966	}
967
968	/*
969	* Maybe it requires 0xbf to be written to the LCR.
970	* (other ST16C650V2 UARTs, TI16C752A, etc)
971	*/
972	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
973	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
974	DEBUG_AUTOCONF("EFRv2 ");
975	autoconfig_has_efr(up);
976	return;
977	}
978
979	/*
980	* Check for a National Semiconductor SuperIO chip.
981	* Attempt to switch to bank 2, read the value of the LOOP bit
982	* from EXCR1. Switch back to bank 0, change it in MCR. Then
983	* switch back to bank 2, read it from EXCR1 again and check
984	* it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
985	*/
986	serial_outp(up, UART_LCR, 0);
987	status1 = serial_in(up, UART_MCR);
988	serial_outp(up, UART_LCR, 0xE0);
989	status2 = serial_in(up, 0x02); /* EXCR1 */
990
991	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
992	serial_outp(up, UART_LCR, 0);
993	serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
994	serial_outp(up, UART_LCR, 0xE0);
995	status2 = serial_in(up, 0x02); /* EXCR1 */
996	serial_outp(up, UART_LCR, 0);
997	serial_outp(up, UART_MCR, status1);
998
999	if ((status2 ^ status1) & UART_MCR_LOOP) {
1000	unsigned short quot;
1001
1002	serial_outp(up, UART_LCR, 0xE0);
1003
1004	quot = serial_dl_read(up);
1005	quot <<= 3;
1006
1007	if (ns16550a_goto_highspeed(up))
1008	serial_dl_write(up, quot);
1009
1010	serial_outp(up, UART_LCR, 0);
1011
1012	up->port.uartclk = 921600*16;
1013	up->port.type = PORT_NS16550A;
1014	up->capabilities \|= UART_NATSEMI;
1015	return;
1016	}
1017	}
1018
1019	/*
1020	* No EFR. Try to detect a TI16750, which only sets bit 5 of
1021	* the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1022	* Try setting it with and without DLAB set. Cheap clones
1023	* set bit 5 without DLAB set.
1024	*/
1025	serial_outp(up, UART_LCR, 0);
1026	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR7_64BYTE);
1027	status1 = serial_in(up, UART_IIR) >> 5;
1028	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1029	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1030	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR7_64BYTE);
1031	status2 = serial_in(up, UART_IIR) >> 5;
1032	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1033	serial_outp(up, UART_LCR, 0);
1034
1035	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1036
1037	if (status1 == 6 && status2 == 7) {
1038	up->port.type = PORT_16750;
1039	up->capabilities \|= UART_CAP_AFE \| UART_CAP_SLEEP;
1040	return;
1041	}
1042
1043	/*
1044	* Try writing and reading the UART_IER_UUE bit (b6).
1045	* If it works, this is probably one of the Xscale platform's
1046	* internal UARTs.
1047	* We're going to explicitly set the UUE bit to 0 before
1048	* trying to write and read a 1 just to make sure it's not
1049	* already a 1 and maybe locked there before we even start start.
1050	*/
1051	iersave = serial_in(up, UART_IER);
1052	serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1053	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1054	/*
1055	* OK it's in a known zero state, try writing and reading
1056	* without disturbing the current state of the other bits.
1057	*/
1058	serial_outp(up, UART_IER, iersave \| UART_IER_UUE);
1059	if (serial_in(up, UART_IER) & UART_IER_UUE) {
1060	/*
1061	* It's an Xscale.
1062	* We'll leave the UART_IER_UUE bit set to 1 (enabled).
1063	*/
1064	DEBUG_AUTOCONF("Xscale ");
1065	up->port.type = PORT_XSCALE;
1066	up->capabilities \|= UART_CAP_UUE \| UART_CAP_RTOIE;
1067	return;
1068	}
1069	} else {
1070	/*
1071	* If we got here we couldn't force the IER_UUE bit to 0.
1072	* Log it and continue.
1073	*/
1074	DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1075	}
1076	serial_outp(up, UART_IER, iersave);
1077
1078	/*
1079	* Exar uarts have EFR in a weird location
1080	*/
1081	if (up->port.flags & UPF_EXAR_EFR) {
1082	up->port.type = PORT_XR17D15X;
1083	up->capabilities \|= UART_CAP_AFE \| UART_CAP_EFR;
1084	}
1085
1086	/*
1087	* We distinguish between 16550A and U6 16550A by counting
1088	* how many bytes are in the FIFO.
1089	*/
1090	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1091	up->port.type = PORT_U6_16550A;
1092	up->capabilities \|= UART_CAP_AFE;
1093	}
1094	}
1095
1096	/*
1097	* This routine is called by rs_init() to initialize a specific serial
1098	* port. It determines what type of UART chip this serial port is
1099	* using: 8250, 16450, 16550, 16550A. The important question is
1100	* whether or not this UART is a 16550A or not, since this will
1101	* determine whether or not we can use its FIFO features or not.
1102	*/
1103	static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1104	{
1105	unsigned char status1, scratch, scratch2, scratch3;
1106	unsigned char save_lcr, save_mcr;
1107	unsigned long flags;
1108
1109	if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1110	return;
1111
1112	DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1113	serial_index(&up->port), up->port.iobase, up->port.membase);
1114
1115	/*
1116	* We really do need global IRQs disabled here - we're going to
1117	* be frobbing the chips IRQ enable register to see if it exists.
1118	*/
1119	spin_lock_irqsave(&up->port.lock, flags);
1120
1121	up->capabilities = 0;
1122	up->bugs = 0;
1123
1124	if (!(up->port.flags & UPF_BUGGY_UART)) {
1125	/*
1126	* Do a simple existence test first; if we fail this,
1127	* there's no point trying anything else.
1128	*
1129	* 0x80 is used as a nonsense port to prevent against
1130	* false positives due to ISA bus float. The
1131	* assumption is that 0x80 is a non-existent port;
1132	* which should be safe since include/asm/io.h also
1133	* makes this assumption.
1134	*
1135	* Note: this is safe as long as MCR bit 4 is clear
1136	* and the device is in "PC" mode.
1137	*/
1138	scratch = serial_inp(up, UART_IER);
1139	serial_outp(up, UART_IER, 0);
1140	#ifdef __i386__
1141	outb(0xff, 0x080);
1142	#endif
1143	/*
1144	* Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1145	* 16C754B) allow only to modify them if an EFR bit is set.
1146	*/
1147	scratch2 = serial_inp(up, UART_IER) & 0x0f;
1148	serial_outp(up, UART_IER, 0x0F);
1149	#ifdef __i386__
1150	outb(0, 0x080);
1151	#endif
1152	scratch3 = serial_inp(up, UART_IER) & 0x0f;
1153	serial_outp(up, UART_IER, scratch);
1154	if (scratch2 != 0 \|\| scratch3 != 0x0F) {
1155	/*
1156	* We failed; there's nothing here
1157	*/
1158	DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1159	scratch2, scratch3);
1160	goto out;
1161	}
1162	}
1163
1164	save_mcr = serial_in(up, UART_MCR);
1165	save_lcr = serial_in(up, UART_LCR);
1166
1167	/*
1168	* Check to see if a UART is really there. Certain broken
1169	* internal modems based on the Rockwell chipset fail this
1170	* test, because they apparently don't implement the loopback
1171	* test mode. So this test is skipped on the COM 1 through
1172	* COM 4 ports. This should be safe, since no board
1173	* manufacturer would be stupid enough to design a board
1174	* that conflicts with COM 1-4 --- we hope!
1175	*/
1176	if (!(up->port.flags & UPF_SKIP_TEST)) {
1177	serial_outp(up, UART_MCR, UART_MCR_LOOP \| 0x0A);
1178	status1 = serial_inp(up, UART_MSR) & 0xF0;
1179	serial_outp(up, UART_MCR, save_mcr);
1180	if (status1 != 0x90) {
1181	DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1182	status1);
1183	goto out;
1184	}
1185	}
1186
1187	/*
1188	* We're pretty sure there's a port here. Lets find out what
1189	* type of port it is. The IIR top two bits allows us to find
1190	* out if it's 8250 or 16450, 16550, 16550A or later. This
1191	* determines what we test for next.
1192	*
1193	* We also initialise the EFR (if any) to zero for later. The
1194	* EFR occupies the same register location as the FCR and IIR.
1195	*/
1196	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1197	serial_outp(up, UART_EFR, 0);
1198	serial_outp(up, UART_LCR, 0);
1199
1200	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1201	scratch = serial_in(up, UART_IIR) >> 6;
1202
1203	DEBUG_AUTOCONF("iir=%d ", scratch);
1204
1205	switch (scratch) {
1206	case 0:
1207	autoconfig_8250(up);
1208	break;
1209	case 1:
1210	up->port.type = PORT_UNKNOWN;
1211	break;
1212	case 2:
1213	up->port.type = PORT_16550;
1214	break;
1215	case 3:
1216	autoconfig_16550a(up);
1217	break;
1218	}
1219
1220	#ifdef CONFIG_SERIAL_8250_RSA
1221	/*
1222	* Only probe for RSA ports if we got the region.
1223	*/
1224	if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1225	int i;
1226
1227	for (i = 0 ; i < probe_rsa_count; ++i) {
1228	if (probe_rsa[i] == up->port.iobase &&
1229	__enable_rsa(up)) {
1230	up->port.type = PORT_RSA;
1231	break;
1232	}
1233	}
1234	}
1235	#endif
1236
1237	serial_outp(up, UART_LCR, save_lcr);
1238
1239	if (up->capabilities != uart_config[up->port.type].flags) {
1240	printk(KERN_WARNING
1241	"ttyS%d: detected caps %08x should be %08x\n",
1242	serial_index(&up->port), up->capabilities,
1243	uart_config[up->port.type].flags);
1244	}
1245
1246	up->port.fifosize = uart_config[up->port.type].fifo_size;
1247	up->capabilities = uart_config[up->port.type].flags;
1248	up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1249
1250	if (up->port.type == PORT_UNKNOWN)
1251	goto out;
1252
1253	/*
1254	* Reset the UART.
1255	*/
1256	#ifdef CONFIG_SERIAL_8250_RSA
1257	if (up->port.type == PORT_RSA)
1258	serial_outp(up, UART_RSA_FRR, 0);
1259	#endif
1260	serial_outp(up, UART_MCR, save_mcr);
1261	serial8250_clear_fifos(up);
1262	serial_in(up, UART_RX);
1263	if (up->capabilities & UART_CAP_UUE)
1264	serial_outp(up, UART_IER, UART_IER_UUE);
1265	else
1266	serial_outp(up, UART_IER, 0);
1267
1268	out:
1269	spin_unlock_irqrestore(&up->port.lock, flags);
1270	DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1271	}
1272
1273	static void autoconfig_irq(struct uart_8250_port *up)
1274	{
1275	unsigned char save_mcr, save_ier;
1276	unsigned char save_ICP = 0;
1277	unsigned int ICP = 0;
1278	unsigned long irqs;
1279	int irq;
1280
1281	if (up->port.flags & UPF_FOURPORT) {
1282	ICP = (up->port.iobase & 0xfe0) \| 0x1f;
1283	save_ICP = inb_p(ICP);
1284	outb_p(0x80, ICP);
1285	(void) inb_p(ICP);
1286	}
1287
1288	/* forget possible initially masked and pending IRQ */
1289	probe_irq_off(probe_irq_on());
1290	save_mcr = serial_inp(up, UART_MCR);
1291	save_ier = serial_inp(up, UART_IER);
1292	serial_outp(up, UART_MCR, UART_MCR_OUT1 \| UART_MCR_OUT2);
1293
1294	irqs = probe_irq_on();
1295	serial_outp(up, UART_MCR, 0);
1296	udelay(10);
1297	if (up->port.flags & UPF_FOURPORT) {
1298	serial_outp(up, UART_MCR,
1299	UART_MCR_DTR \| UART_MCR_RTS);
1300	} else {
1301	serial_outp(up, UART_MCR,
1302	UART_MCR_DTR \| UART_MCR_RTS \| UART_MCR_OUT2);
1303	}
1304	serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1305	(void)serial_inp(up, UART_LSR);
1306	(void)serial_inp(up, UART_RX);
1307	(void)serial_inp(up, UART_IIR);
1308	(void)serial_inp(up, UART_MSR);
1309	serial_outp(up, UART_TX, 0xFF);
1310	udelay(20);
1311	irq = probe_irq_off(irqs);
1312
1313	serial_outp(up, UART_MCR, save_mcr);
1314	serial_outp(up, UART_IER, save_ier);
1315
1316	if (up->port.flags & UPF_FOURPORT)
1317	outb_p(save_ICP, ICP);
1318
1319	up->port.irq = (irq > 0) ? irq : 0;
1320	}
1321
1322	static inline void __stop_tx(struct uart_8250_port *p)
1323	{
1324	if (p->ier & UART_IER_THRI) {
1325	p->ier &= ~UART_IER_THRI;
1326	serial_out(p, UART_IER, p->ier);
1327	}
1328	}
1329
1330	static void serial8250_stop_tx(struct uart_port *port)
1331	{
1332	struct uart_8250_port *up =
1333	container_of(port, struct uart_8250_port, port);
1334
1335	__stop_tx(up);
1336
1337	/*
1338	* We really want to stop the transmitter from sending.
1339	*/
1340	if (up->port.type == PORT_16C950) {
1341	up->acr \|= UART_ACR_TXDIS;
1342	serial_icr_write(up, UART_ACR, up->acr);
1343	}
1344	}
1345
1346	static void transmit_chars(struct uart_8250_port *up);
1347
1348	static void serial8250_start_tx(struct uart_port *port)
1349	{
1350	struct uart_8250_port *up =
1351	container_of(port, struct uart_8250_port, port);
1352
1353	if (!(up->ier & UART_IER_THRI)) {
1354	up->ier \|= UART_IER_THRI;
1355	serial_out(up, UART_IER, up->ier);
1356
1357	if (up->bugs & UART_BUG_TXEN) {
1358	unsigned char lsr;
1359	lsr = serial_in(up, UART_LSR);
1360	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1361	if ((up->port.type == PORT_RM9000) ?
1362	(lsr & UART_LSR_THRE) :
1363	(lsr & UART_LSR_TEMT))
1364	transmit_chars(up);
1365	}
1366	}
1367
1368	/*
1369	* Re-enable the transmitter if we disabled it.
1370	*/
1371	if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1372	up->acr &= ~UART_ACR_TXDIS;
1373	serial_icr_write(up, UART_ACR, up->acr);
1374	}
1375	}
1376
1377	static void serial8250_stop_rx(struct uart_port *port)
1378	{
1379	struct uart_8250_port *up =
1380	container_of(port, struct uart_8250_port, port);
1381
1382	up->ier &= ~UART_IER_RLSI;
1383	up->port.read_status_mask &= ~UART_LSR_DR;
1384	serial_out(up, UART_IER, up->ier);
1385	}
1386
1387	static void serial8250_enable_ms(struct uart_port *port)
1388	{
1389	struct uart_8250_port *up =
1390	container_of(port, struct uart_8250_port, port);
1391
1392	/* no MSR capabilities */
1393	if (up->bugs & UART_BUG_NOMSR)
1394	return;
1395
1396	up->ier \|= UART_IER_MSI;
1397	serial_out(up, UART_IER, up->ier);
1398	}
1399
1400	/*
1401	* Clear the Tegra rx fifo after a break
1402	*
1403	* FIXME: This needs to become a port specific callback once we have a
1404	* framework for this
1405	*/
1406	static void clear_rx_fifo(struct uart_8250_port *up)
1407	{
1408	unsigned int status, tmout = 10000;
1409	do {
1410	status = serial_in(up, UART_LSR);
1411	if (status & (UART_LSR_FIFOE \| UART_LSR_BRK_ERROR_BITS))
1412	status = serial_in(up, UART_RX);
1413	else
1414	break;
1415	if (--tmout == 0)
1416	break;
1417	udelay(1);
1418	} while (1);
1419	}
1420
1421	static void
1422	receive_chars(struct uart_8250_port up, unsigned int status)
1423	{
1424	struct tty_struct *tty = up->port.state->port.tty;
1425	unsigned char ch, lsr = *status;
1426	int max_count = 256;
1427	char flag;
1428
1429	do {
1430	if (likely(lsr & UART_LSR_DR))
1431	ch = serial_inp(up, UART_RX);
1432	else
1433	/*
1434	* Intel 82571 has a Serial Over Lan device that will
1435	* set UART_LSR_BI without setting UART_LSR_DR when
1436	* it receives a break. To avoid reading from the
1437	* receive buffer without UART_LSR_DR bit set, we
1438	* just force the read character to be 0
1439	*/
1440	ch = 0;
1441
1442	flag = TTY_NORMAL;
1443	up->port.icount.rx++;
1444
1445	lsr \|= up->lsr_saved_flags;
1446	up->lsr_saved_flags = 0;
1447
1448	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1449	/*
1450	* For statistics only
1451	*/
1452	if (lsr & UART_LSR_BI) {
1453	lsr &= ~(UART_LSR_FE \| UART_LSR_PE);
1454	up->port.icount.brk++;
1455	/*
1456	* If tegra port then clear the rx fifo to
1457	* accept another break/character.
1458	*/
1459	if (up->port.type == PORT_TEGRA)
1460	clear_rx_fifo(up);
1461
1462	/*
1463	* We do the SysRQ and SAK checking
1464	* here because otherwise the break
1465	* may get masked by ignore_status_mask
1466	* or read_status_mask.
1467	*/
1468	if (uart_handle_break(&up->port))
1469	goto ignore_char;
1470	} else if (lsr & UART_LSR_PE)
1471	up->port.icount.parity++;
1472	else if (lsr & UART_LSR_FE)
1473	up->port.icount.frame++;
1474	if (lsr & UART_LSR_OE)
1475	up->port.icount.overrun++;
1476
1477	/*
1478	* Mask off conditions which should be ignored.
1479	*/
1480	lsr &= up->port.read_status_mask;
1481
1482	if (lsr & UART_LSR_BI) {
1483	DEBUG_INTR("handling break....");
1484	flag = TTY_BREAK;
1485	} else if (lsr & UART_LSR_PE)
1486	flag = TTY_PARITY;
1487	else if (lsr & UART_LSR_FE)
1488	flag = TTY_FRAME;
1489	}
1490	if (uart_handle_sysrq_char(&up->port, ch))
1491	goto ignore_char;
1492
1493	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1494
1495	ignore_char:
1496	lsr = serial_inp(up, UART_LSR);
1497	} while ((lsr & (UART_LSR_DR \| UART_LSR_BI)) && (max_count-- > 0));
1498	spin_unlock(&up->port.lock);
1499	tty_flip_buffer_push(tty);
1500	spin_lock(&up->port.lock);
1501	*status = lsr;
1502	}
1503
1504	static void transmit_chars(struct uart_8250_port *up)
1505	{
1506	struct circ_buf *xmit = &up->port.state->xmit;
1507	int count;
1508
1509	if (up->port.x_char) {
1510	serial_outp(up, UART_TX, up->port.x_char);
1511	up->port.icount.tx++;
1512	up->port.x_char = 0;
1513	return;
1514	}
1515	if (uart_tx_stopped(&up->port)) {
1516	serial8250_stop_tx(&up->port);
1517	return;
1518	}
1519	if (uart_circ_empty(xmit)) {
1520	__stop_tx(up);
1521	return;
1522	}
1523
1524	count = up->tx_loadsz;
1525	do {
1526	serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1527	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1528	up->port.icount.tx++;
1529	if (uart_circ_empty(xmit))
1530	break;
1531	} while (--count > 0);
1532
1533	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1534	uart_write_wakeup(&up->port);
1535
1536	DEBUG_INTR("THRE...");
1537
1538	if (uart_circ_empty(xmit))
1539	__stop_tx(up);
1540	}
1541
1542	static unsigned int check_modem_status(struct uart_8250_port *up)
1543	{
1544	unsigned int status = serial_in(up, UART_MSR);
1545
1546	status \|= up->msr_saved_flags;
1547	up->msr_saved_flags = 0;
1548	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1549	up->port.state != NULL) {
1550	if (status & UART_MSR_TERI)
1551	up->port.icount.rng++;
1552	if (status & UART_MSR_DDSR)
1553	up->port.icount.dsr++;
1554	if (status & UART_MSR_DDCD)
1555	uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1556	if (status & UART_MSR_DCTS)
1557	uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1558
1559	wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1560	}
1561
1562	return status;
1563	}
1564
1565	/*
1566	* This handles the interrupt from one port.
1567	*/
1568	static void serial8250_handle_port(struct uart_8250_port *up)
1569	{
1570	unsigned int status;
1571	unsigned long flags;
1572
1573	spin_lock_irqsave(&up->port.lock, flags);
1574
1575	status = serial_inp(up, UART_LSR);
1576
1577	DEBUG_INTR("status = %x...", status);
1578
1579	if (status & (UART_LSR_DR \| UART_LSR_BI))
1580	receive_chars(up, &status);
1581	check_modem_status(up);
1582	if (status & UART_LSR_THRE)
1583	transmit_chars(up);
1584
1585	spin_unlock_irqrestore(&up->port.lock, flags);
1586	}
1587
1588	int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1589	{
1590	struct uart_8250_port *up =
1591	container_of(port, struct uart_8250_port, port);
1592
1593	if (!(iir & UART_IIR_NO_INT)) {
1594	serial8250_handle_port(up);
1595	return 1;
1596	}
1597
1598	return 0;
1599	}
1600	EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1601
1602	static int serial8250_default_handle_irq(struct uart_port *port)
1603	{
1604	struct uart_8250_port *up =
1605	container_of(port, struct uart_8250_port, port);
1606	unsigned int iir = serial_in(up, UART_IIR);
1607
1608	return serial8250_handle_irq(port, iir);
1609	}
1610
1611	/*
1612	* This is the serial driver's interrupt routine.
1613	*
1614	* Arjan thinks the old way was overly complex, so it got simplified.
1615	* Alan disagrees, saying that need the complexity to handle the weird
1616	* nature of ISA shared interrupts. (This is a special exception.)
1617	*
1618	* In order to handle ISA shared interrupts properly, we need to check
1619	* that all ports have been serviced, and therefore the ISA interrupt
1620	* line has been de-asserted.
1621	*
1622	* This means we need to loop through all ports. checking that they
1623	* don't have an interrupt pending.
1624	*/
1625	static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1626	{
1627	struct irq_info *i = dev_id;
1628	struct list_head l, end = NULL;
1629	int pass_counter = 0, handled = 0;
1630
1631	DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1632
1633	spin_lock(&i->lock);
1634
1635	l = i->head;
1636	do {
1637	struct uart_8250_port *up;
1638	struct uart_port *port;
1639
1640	up = list_entry(l, struct uart_8250_port, list);
1641	port = &up->port;
1642
1643	if (port->handle_irq(port)) {
1644	handled = 1;
1645	end = NULL;
1646	} else if (end == NULL)
1647	end = l;
1648
1649	l = l->next;
1650
1651	if (l == i->head && pass_counter++ > PASS_LIMIT) {
1652	/* If we hit this, we're dead. */
1653	printk_ratelimited(KERN_ERR
1654	"serial8250: too much work for irq%d\n", irq);
1655	break;
1656	}
1657	} while (l != end);
1658
1659	spin_unlock(&i->lock);
1660
1661	DEBUG_INTR("end.\n");
1662
1663	return IRQ_RETVAL(handled);
1664	}
1665
1666	/*
1667	* To support ISA shared interrupts, we need to have one interrupt
1668	* handler that ensures that the IRQ line has been deasserted
1669	* before returning. Failing to do this will result in the IRQ
1670	* line being stuck active, and, since ISA irqs are edge triggered,
1671	* no more IRQs will be seen.
1672	*/
1673	static void serial_do_unlink(struct irq_info i, struct uart_8250_port up)
1674	{
1675	spin_lock_irq(&i->lock);
1676
1677	if (!list_empty(i->head)) {
1678	if (i->head == &up->list)
1679	i->head = i->head->next;
1680	list_del(&up->list);
1681	} else {
1682	BUG_ON(i->head != &up->list);
1683	i->head = NULL;
1684	}
1685	spin_unlock_irq(&i->lock);
1686	/* List empty so throw away the hash node */
1687	if (i->head == NULL) {
1688	hlist_del(&i->node);
1689	kfree(i);
1690	}
1691	}
1692
1693	static int serial_link_irq_chain(struct uart_8250_port *up)
1694	{
1695	struct hlist_head *h;
1696	struct hlist_node *n;
1697	struct irq_info *i;
1698	int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1699
1700	mutex_lock(&hash_mutex);
1701
1702	h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703
1704	hlist_for_each(n, h) {
1705	i = hlist_entry(n, struct irq_info, node);
1706	if (i->irq == up->port.irq)
1707	break;
1708	}
1709
1710	if (n == NULL) {
1711	i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1712	if (i == NULL) {
1713	mutex_unlock(&hash_mutex);
1714	return -ENOMEM;
1715	}
1716	spin_lock_init(&i->lock);
1717	i->irq = up->port.irq;
1718	hlist_add_head(&i->node, h);
1719	}
1720	mutex_unlock(&hash_mutex);
1721
1722	spin_lock_irq(&i->lock);
1723
1724	if (i->head) {
1725	list_add(&up->list, i->head);
1726	spin_unlock_irq(&i->lock);
1727
1728	ret = 0;
1729	} else {
1730	INIT_LIST_HEAD(&up->list);
1731	i->head = &up->list;
1732	spin_unlock_irq(&i->lock);
1733	irq_flags \|= up->port.irqflags;
1734	ret = request_irq(up->port.irq, serial8250_interrupt,
1735	irq_flags, "serial", i);
1736	if (ret < 0)
1737	serial_do_unlink(i, up);
1738	}
1739
1740	return ret;
1741	}
1742
1743	static void serial_unlink_irq_chain(struct uart_8250_port *up)
1744	{
1745	struct irq_info *i;
1746	struct hlist_node *n;
1747	struct hlist_head *h;
1748
1749	mutex_lock(&hash_mutex);
1750
1751	h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1752
1753	hlist_for_each(n, h) {
1754	i = hlist_entry(n, struct irq_info, node);
1755	if (i->irq == up->port.irq)
1756	break;
1757	}
1758
1759	BUG_ON(n == NULL);
1760	BUG_ON(i->head == NULL);
1761
1762	if (list_empty(i->head))
1763	free_irq(up->port.irq, i);
1764
1765	serial_do_unlink(i, up);
1766	mutex_unlock(&hash_mutex);
1767	}
1768
1769	/*
1770	* This function is used to handle ports that do not have an
1771	* interrupt. This doesn't work very well for 16450's, but gives
1772	* barely passable results for a 16550A. (Although at the expense
1773	* of much CPU overhead).
1774	*/
1775	static void serial8250_timeout(unsigned long data)
1776	{
1777	struct uart_8250_port up = (struct uart_8250_port )data;
1778	unsigned int iir;
1779
1780	iir = serial_in(up, UART_IIR);
1781	if (!(iir & UART_IIR_NO_INT))
1782	serial8250_handle_port(up);
1783	mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1784	}
1785
1786	static void serial8250_backup_timeout(unsigned long data)
1787	{
1788	struct uart_8250_port up = (struct uart_8250_port )data;
1789	unsigned int iir, ier = 0, lsr;
1790	unsigned long flags;
1791
1792	spin_lock_irqsave(&up->port.lock, flags);
1793
1794	/*
1795	* Must disable interrupts or else we risk racing with the interrupt
1796	* based handler.
1797	*/
1798	if (is_real_interrupt(up->port.irq)) {
1799	ier = serial_in(up, UART_IER);
1800	serial_out(up, UART_IER, 0);
1801	}
1802
1803	iir = serial_in(up, UART_IIR);
1804
1805	/*
1806	* This should be a safe test for anyone who doesn't trust the
1807	* IIR bits on their UART, but it's specifically designed for
1808	* the "Diva" UART used on the management processor on many HP
1809	* ia64 and parisc boxes.
1810	*/
1811	lsr = serial_in(up, UART_LSR);
1812	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1813	if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1814	(!uart_circ_empty(&up->port.state->xmit) \|\| up->port.x_char) &&
1815	(lsr & UART_LSR_THRE)) {
1816	iir &= ~(UART_IIR_ID \| UART_IIR_NO_INT);
1817	iir \|= UART_IIR_THRI;
1818	}
1819
1820	if (!(iir & UART_IIR_NO_INT))
1821	transmit_chars(up);
1822
1823
1824	if (is_real_interrupt(up->port.irq))
1825	serial_out(up, UART_IER, ier);
1826
1827	spin_unlock_irqrestore(&up->port.lock, flags);
1828
1829
1830	/* Standard timer interval plus 0.2s to keep the port running */
1831	mod_timer(&up->timer,
1832	jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1833	}
1834
1835	static unsigned int serial8250_tx_empty(struct uart_port *port)
1836	{
1837	struct uart_8250_port *up =
1838	container_of(port, struct uart_8250_port, port);
1839	unsigned long flags;
1840	unsigned int lsr;
1841
1842	spin_lock_irqsave(&up->port.lock, flags);
1843	lsr = serial_in(up, UART_LSR);
1844	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1845	spin_unlock_irqrestore(&up->port.lock, flags);
1846
1847	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1848	}
1849
1850	static unsigned int serial8250_get_mctrl(struct uart_port *port)
1851	{
1852	struct uart_8250_port *up =
1853	container_of(port, struct uart_8250_port, port);
1854	unsigned int status;
1855	unsigned int ret;
1856
1857	status = check_modem_status(up);
1858
1859	ret = 0;
1860	if (status & UART_MSR_DCD)
1861	ret \|= TIOCM_CAR;
1862	if (status & UART_MSR_RI)
1863	ret \|= TIOCM_RNG;
1864	if (status & UART_MSR_DSR)
1865	ret \|= TIOCM_DSR;
1866	if (status & UART_MSR_CTS)
1867	ret \|= TIOCM_CTS;
1868	return ret;
1869	}
1870
1871	static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1872	{
1873	struct uart_8250_port *up =
1874	container_of(port, struct uart_8250_port, port);
1875	unsigned char mcr = 0;
1876
1877	if (mctrl & TIOCM_RTS)
1878	mcr \|= UART_MCR_RTS;
1879	if (mctrl & TIOCM_DTR)
1880	mcr \|= UART_MCR_DTR;
1881	if (mctrl & TIOCM_OUT1)
1882	mcr \|= UART_MCR_OUT1;
1883	if (mctrl & TIOCM_OUT2)
1884	mcr \|= UART_MCR_OUT2;
1885	if (mctrl & TIOCM_LOOP)
1886	mcr \|= UART_MCR_LOOP;
1887
1888	mcr = (mcr & up->mcr_mask) \| up->mcr_force \| up->mcr;
1889
1890	serial_out(up, UART_MCR, mcr);
1891	}
1892
1893	static void serial8250_break_ctl(struct uart_port *port, int break_state)
1894	{
1895	struct uart_8250_port *up =
1896	container_of(port, struct uart_8250_port, port);
1897	unsigned long flags;
1898
1899	spin_lock_irqsave(&up->port.lock, flags);
1900	if (break_state == -1)
1901	up->lcr \|= UART_LCR_SBC;
1902	else
1903	up->lcr &= ~UART_LCR_SBC;
1904	serial_out(up, UART_LCR, up->lcr);
1905	spin_unlock_irqrestore(&up->port.lock, flags);
1906	}
1907
1908	/*
1909	* Wait for transmitter & holding register to empty
1910	*/
1911	static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1912	{
1913	unsigned int status, tmout = 10000;
1914
1915	/* Wait up to 10ms for the character(s) to be sent. */
1916	for (;;) {
1917	status = serial_in(up, UART_LSR);
1918
1919	up->lsr_saved_flags \|= status & LSR_SAVE_FLAGS;
1920
1921	if ((status & bits) == bits)
1922	break;
1923	if (--tmout == 0)
1924	break;
1925	udelay(1);
1926	}
1927
1928	/* Wait up to 1s for flow control if necessary */
1929	if (up->port.flags & UPF_CONS_FLOW) {
1930	unsigned int tmout;
1931	for (tmout = 1000000; tmout; tmout--) {
1932	unsigned int msr = serial_in(up, UART_MSR);
1933	up->msr_saved_flags \|= msr & MSR_SAVE_FLAGS;
1934	if (msr & UART_MSR_CTS)
1935	break;
1936	udelay(1);
1937	touch_nmi_watchdog();
1938	}
1939	}
1940	}
1941
1942	#ifdef CONFIG_CONSOLE_POLL
1943	/*
1944	* Console polling routines for writing and reading from the uart while
1945	* in an interrupt or debug context.
1946	*/
1947
1948	static int serial8250_get_poll_char(struct uart_port *port)
1949	{
1950	struct uart_8250_port *up =
1951	container_of(port, struct uart_8250_port, port);
1952	unsigned char lsr = serial_inp(up, UART_LSR);
1953
1954	if (!(lsr & UART_LSR_DR))
1955	return NO_POLL_CHAR;
1956
1957	return serial_inp(up, UART_RX);
1958	}
1959
1960
1961	static void serial8250_put_poll_char(struct uart_port *port,
1962	unsigned char c)
1963	{
1964	unsigned int ier;
1965	struct uart_8250_port *up =
1966	container_of(port, struct uart_8250_port, port);
1967
1968	/*
1969	* First save the IER then disable the interrupts
1970	*/
1971	ier = serial_in(up, UART_IER);
1972	if (up->capabilities & UART_CAP_UUE)
1973	serial_out(up, UART_IER, UART_IER_UUE);
1974	else
1975	serial_out(up, UART_IER, 0);
1976
1977	wait_for_xmitr(up, BOTH_EMPTY);
1978	/*
1979	* Send the character out.
1980	* If a LF, also do CR...
1981	*/
1982	serial_out(up, UART_TX, c);
1983	if (c == 10) {
1984	wait_for_xmitr(up, BOTH_EMPTY);
1985	serial_out(up, UART_TX, 13);
1986	}
1987
1988	/*
1989	* Finally, wait for transmitter to become empty
1990	* and restore the IER
1991	*/
1992	wait_for_xmitr(up, BOTH_EMPTY);
1993	serial_out(up, UART_IER, ier);
1994	}
1995
1996	#endif /* CONFIG_CONSOLE_POLL */
1997
1998	static int serial8250_startup(struct uart_port *port)
1999	{
2000	struct uart_8250_port *up =
2001	container_of(port, struct uart_8250_port, port);
2002	unsigned long flags;
2003	unsigned char lsr, iir;
2004	int retval;
2005
2006	up->port.fifosize = uart_config[up->port.type].fifo_size;
2007	up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2008	up->capabilities = uart_config[up->port.type].flags;
2009	up->mcr = 0;
2010
2011	if (up->port.iotype != up->cur_iotype)
2012	set_io_from_upio(port);
2013
2014	if (up->port.type == PORT_16C950) {
2015	/* Wake up and initialize UART */
2016	up->acr = 0;
2017	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2018	serial_outp(up, UART_EFR, UART_EFR_ECB);
2019	serial_outp(up, UART_IER, 0);
2020	serial_outp(up, UART_LCR, 0);
2021	serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2022	serial_outp(up, UART_LCR, 0xBF);
2023	serial_outp(up, UART_EFR, UART_EFR_ECB);
2024	serial_outp(up, UART_LCR, 0);
2025	}
2026
2027	#ifdef CONFIG_SERIAL_8250_RSA
2028	/*
2029	* If this is an RSA port, see if we can kick it up to the
2030	* higher speed clock.
2031	*/
2032	enable_rsa(up);
2033	#endif
2034
2035	/*
2036	* Clear the FIFO buffers and disable them.
2037	* (they will be reenabled in set_termios())
2038	*/
2039	serial8250_clear_fifos(up);
2040
2041	/*
2042	* Clear the interrupt registers.
2043	*/
2044	(void) serial_inp(up, UART_LSR);
2045	(void) serial_inp(up, UART_RX);
2046	(void) serial_inp(up, UART_IIR);
2047	(void) serial_inp(up, UART_MSR);
2048
2049	/*
2050	* At this point, there's no way the LSR could still be 0xff;
2051	* if it is, then bail out, because there's likely no UART
2052	* here.
2053	*/
2054	if (!(up->port.flags & UPF_BUGGY_UART) &&
2055	(serial_inp(up, UART_LSR) == 0xff)) {
2056	printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2057	serial_index(&up->port));
2058	return -ENODEV;
2059	}
2060
2061	/*
2062	* For a XR16C850, we need to set the trigger levels
2063	*/
2064	if (up->port.type == PORT_16850) {
2065	unsigned char fctr;
2066
2067	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2068
2069	fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX\|UART_FCTR_TX);
2070	serial_outp(up, UART_FCTR, fctr \| UART_FCTR_TRGD \| UART_FCTR_RX);
2071	serial_outp(up, UART_TRG, UART_TRG_96);
2072	serial_outp(up, UART_FCTR, fctr \| UART_FCTR_TRGD \| UART_FCTR_TX);
2073	serial_outp(up, UART_TRG, UART_TRG_96);
2074
2075	serial_outp(up, UART_LCR, 0);
2076	}
2077
2078	if (is_real_interrupt(up->port.irq)) {
2079	unsigned char iir1;
2080	/*
2081	* Test for UARTs that do not reassert THRE when the
2082	* transmitter is idle and the interrupt has already
2083	* been cleared. Real 16550s should always reassert
2084	* this interrupt whenever the transmitter is idle and
2085	* the interrupt is enabled. Delays are necessary to
2086	* allow register changes to become visible.
2087	*/
2088	spin_lock_irqsave(&up->port.lock, flags);
2089	if (up->port.irqflags & IRQF_SHARED)
2090	disable_irq_nosync(up->port.irq);
2091
2092	wait_for_xmitr(up, UART_LSR_THRE);
2093	serial_out_sync(up, UART_IER, UART_IER_THRI);
2094	udelay(1); /* allow THRE to set */
2095	iir1 = serial_in(up, UART_IIR);
2096	serial_out(up, UART_IER, 0);
2097	serial_out_sync(up, UART_IER, UART_IER_THRI);
2098	udelay(1); /* allow a working UART time to re-assert THRE */
2099	iir = serial_in(up, UART_IIR);
2100	serial_out(up, UART_IER, 0);
2101
2102	if (up->port.irqflags & IRQF_SHARED)
2103	enable_irq(up->port.irq);
2104	spin_unlock_irqrestore(&up->port.lock, flags);
2105
2106	/*
2107	* If the interrupt is not reasserted, setup a timer to
2108	* kick the UART on a regular basis.
2109	*/
2110	if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2111	up->bugs \|= UART_BUG_THRE;
2112	pr_debug("ttyS%d - using backup timer\n",
2113	serial_index(port));
2114	}
2115	}
2116
2117	/*
2118	* The above check will only give an accurate result the first time
2119	* the port is opened so this value needs to be preserved.
2120	*/
2121	if (up->bugs & UART_BUG_THRE) {
2122	up->timer.function = serial8250_backup_timeout;
2123	up->timer.data = (unsigned long)up;
2124	mod_timer(&up->timer, jiffies +
2125	uart_poll_timeout(port) + HZ / 5);
2126	}
2127
2128	/*
2129	* If the "interrupt" for this port doesn't correspond with any
2130	* hardware interrupt, we use a timer-based system. The original
2131	* driver used to do this with IRQ0.
2132	*/
2133	if (!is_real_interrupt(up->port.irq)) {
2134	up->timer.data = (unsigned long)up;
2135	mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2136	} else {
2137	retval = serial_link_irq_chain(up);
2138	if (retval)
2139	return retval;
2140	}
2141
2142	/*
2143	* Now, initialize the UART
2144	*/
2145	serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2146
2147	spin_lock_irqsave(&up->port.lock, flags);
2148	if (up->port.flags & UPF_FOURPORT) {
2149	if (!is_real_interrupt(up->port.irq))
2150	up->port.mctrl \|= TIOCM_OUT1;
2151	} else
2152	/*
2153	* Most PC uarts need OUT2 raised to enable interrupts.
2154	*/
2155	if (is_real_interrupt(up->port.irq))
2156	up->port.mctrl \|= TIOCM_OUT2;
2157
2158	serial8250_set_mctrl(&up->port, up->port.mctrl);
2159
2160	/* Serial over Lan (SoL) hack:
2161	Intel 8257x Gigabit ethernet chips have a
2162	16550 emulation, to be used for Serial Over Lan.
2163	Those chips take a longer time than a normal
2164	serial device to signalize that a transmission
2165	data was queued. Due to that, the above test generally
2166	fails. One solution would be to delay the reading of
2167	iir. However, this is not reliable, since the timeout
2168	is variable. So, let's just don't test if we receive
2169	TX irq. This way, we'll never enable UART_BUG_TXEN.
2170	*/
2171	if (skip_txen_test \|\| up->port.flags & UPF_NO_TXEN_TEST)
2172	goto dont_test_tx_en;
2173
2174	/*
2175	* Do a quick test to see if we receive an
2176	* interrupt when we enable the TX irq.
2177	*/
2178	serial_outp(up, UART_IER, UART_IER_THRI);
2179	lsr = serial_in(up, UART_LSR);
2180	iir = serial_in(up, UART_IIR);
2181	serial_outp(up, UART_IER, 0);
2182
2183	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2184	if (!(up->bugs & UART_BUG_TXEN)) {
2185	up->bugs \|= UART_BUG_TXEN;
2186	pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2187	serial_index(port));
2188	}
2189	} else {
2190	up->bugs &= ~UART_BUG_TXEN;
2191	}
2192
2193	dont_test_tx_en:
2194	spin_unlock_irqrestore(&up->port.lock, flags);
2195
2196	/*
2197	* Clear the interrupt registers again for luck, and clear the
2198	* saved flags to avoid getting false values from polling
2199	* routines or the previous session.
2200	*/
2201	serial_inp(up, UART_LSR);
2202	serial_inp(up, UART_RX);
2203	serial_inp(up, UART_IIR);
2204	serial_inp(up, UART_MSR);
2205	up->lsr_saved_flags = 0;
2206	up->msr_saved_flags = 0;
2207
2208	/*
2209	* Finally, enable interrupts. Note: Modem status interrupts
2210	* are set via set_termios(), which will be occurring imminently
2211	* anyway, so we don't enable them here.
2212	*/
2213	up->ier = UART_IER_RLSI \| UART_IER_RDI;
2214	serial_outp(up, UART_IER, up->ier);
2215
2216	if (up->port.flags & UPF_FOURPORT) {
2217	unsigned int icp;
2218	/*
2219	* Enable interrupts on the AST Fourport board
2220	*/
2221	icp = (up->port.iobase & 0xfe0) \| 0x01f;
2222	outb_p(0x80, icp);
2223	(void) inb_p(icp);
2224	}
2225
2226	return 0;
2227	}
2228
2229	static void serial8250_shutdown(struct uart_port *port)
2230	{
2231	struct uart_8250_port *up =
2232	container_of(port, struct uart_8250_port, port);
2233	unsigned long flags;
2234
2235	/*
2236	* Disable interrupts from this port
2237	*/
2238	up->ier = 0;
2239	serial_outp(up, UART_IER, 0);
2240
2241	spin_lock_irqsave(&up->port.lock, flags);
2242	if (up->port.flags & UPF_FOURPORT) {
2243	/* reset interrupts on the AST Fourport board */
2244	inb((up->port.iobase & 0xfe0) \| 0x1f);
2245	up->port.mctrl \|= TIOCM_OUT1;
2246	} else
2247	up->port.mctrl &= ~TIOCM_OUT2;
2248
2249	serial8250_set_mctrl(&up->port, up->port.mctrl);
2250	spin_unlock_irqrestore(&up->port.lock, flags);
2251
2252	/*
2253	* Disable break condition and FIFOs
2254	*/
2255	serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2256	serial8250_clear_fifos(up);
2257
2258	#ifdef CONFIG_SERIAL_8250_RSA
2259	/*
2260	* Reset the RSA board back to 115kbps compat mode.
2261	*/
2262	disable_rsa(up);
2263	#endif
2264
2265	/*
2266	* Read data port to reset things, and then unlink from
2267	* the IRQ chain.
2268	*/
2269	(void) serial_in(up, UART_RX);
2270
2271	del_timer_sync(&up->timer);
2272	up->timer.function = serial8250_timeout;
2273	if (is_real_interrupt(up->port.irq))
2274	serial_unlink_irq_chain(up);
2275	}
2276
2277	static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2278	{
2279	unsigned int quot;
2280
2281	/*
2282	* Handle magic divisors for baud rates above baud_base on
2283	* SMSC SuperIO chips.
2284	*/
2285	if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2286	baud == (port->uartclk/4))
2287	quot = 0x8001;
2288	else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2289	baud == (port->uartclk/8))
2290	quot = 0x8002;
2291	else
2292	quot = uart_get_divisor(port, baud);
2293
2294	return quot;
2295	}
2296
2297	void
2298	serial8250_do_set_termios(struct uart_port port, struct ktermios termios,
2299	struct ktermios *old)
2300	{
2301	struct uart_8250_port *up =
2302	container_of(port, struct uart_8250_port, port);
2303	unsigned char cval, fcr = 0;
2304	unsigned long flags;
2305	unsigned int baud, quot;
2306
2307	switch (termios->c_cflag & CSIZE) {
2308	case CS5:
2309	cval = UART_LCR_WLEN5;
2310	break;
2311	case CS6:
2312	cval = UART_LCR_WLEN6;
2313	break;
2314	case CS7:
2315	cval = UART_LCR_WLEN7;
2316	break;
2317	default:
2318	case CS8:
2319	cval = UART_LCR_WLEN8;
2320	break;
2321	}
2322
2323	if (termios->c_cflag & CSTOPB)
2324	cval \|= UART_LCR_STOP;
2325	if (termios->c_cflag & PARENB)
2326	cval \|= UART_LCR_PARITY;
2327	if (!(termios->c_cflag & PARODD))
2328	cval \|= UART_LCR_EPAR;
2329	#ifdef CMSPAR
2330	if (termios->c_cflag & CMSPAR)
2331	cval \|= UART_LCR_SPAR;
2332	#endif
2333
2334	/*
2335	* Ask the core to calculate the divisor for us.
2336	*/
2337	baud = uart_get_baud_rate(port, termios, old,
2338	port->uartclk / 16 / 0xffff,
2339	port->uartclk / 16);
2340	quot = serial8250_get_divisor(port, baud);
2341
2342	/*
2343	* Oxford Semi 952 rev B workaround
2344	*/
2345	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2346	quot++;
2347
2348	if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2349	if (baud < 2400)
2350	fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_TRIGGER_1;
2351	else
2352	fcr = uart_config[up->port.type].fcr;
2353	}
2354
2355	/*
2356	* MCR-based auto flow control. When AFE is enabled, RTS will be
2357	* deasserted when the receive FIFO contains more characters than
2358	* the trigger, or the MCR RTS bit is cleared. In the case where
2359	* the remote UART is not using CTS auto flow control, we must
2360	* have sufficient FIFO entries for the latency of the remote
2361	* UART to respond. IOW, at least 32 bytes of FIFO.
2362	*/
2363	if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2364	up->mcr &= ~UART_MCR_AFE;
2365	if (termios->c_cflag & CRTSCTS)
2366	up->mcr \|= UART_MCR_AFE;
2367	}
2368
2369	/*
2370	* Ok, we're now changing the port state. Do it with
2371	* interrupts disabled.
2372	*/
2373	spin_lock_irqsave(&up->port.lock, flags);
2374
2375	/*
2376	* Update the per-port timeout.
2377	*/
2378	uart_update_timeout(port, termios->c_cflag, baud);
2379
2380	up->port.read_status_mask = UART_LSR_OE \| UART_LSR_THRE \| UART_LSR_DR;
2381	if (termios->c_iflag & INPCK)
2382	up->port.read_status_mask \|= UART_LSR_FE \| UART_LSR_PE;
2383	if (termios->c_iflag & (BRKINT \| PARMRK))
2384	up->port.read_status_mask \|= UART_LSR_BI;
2385
2386	/*
2387	* Characteres to ignore
2388	*/
2389	up->port.ignore_status_mask = 0;
2390	if (termios->c_iflag & IGNPAR)
2391	up->port.ignore_status_mask \|= UART_LSR_PE \| UART_LSR_FE;
2392	if (termios->c_iflag & IGNBRK) {
2393	up->port.ignore_status_mask \|= UART_LSR_BI;
2394	/*
2395	* If we're ignoring parity and break indicators,
2396	* ignore overruns too (for real raw support).
2397	*/
2398	if (termios->c_iflag & IGNPAR)
2399	up->port.ignore_status_mask \|= UART_LSR_OE;
2400	}
2401
2402	/*
2403	* ignore all characters if CREAD is not set
2404	*/
2405	if ((termios->c_cflag & CREAD) == 0)
2406	up->port.ignore_status_mask \|= UART_LSR_DR;
2407
2408	/*
2409	* CTS flow control flag and modem status interrupts
2410	*/
2411	up->ier &= ~UART_IER_MSI;
2412	if (!(up->bugs & UART_BUG_NOMSR) &&
2413	UART_ENABLE_MS(&up->port, termios->c_cflag))
2414	up->ier \|= UART_IER_MSI;
2415	if (up->capabilities & UART_CAP_UUE)
2416	up->ier \|= UART_IER_UUE;
2417	if (up->capabilities & UART_CAP_RTOIE)
2418	up->ier \|= UART_IER_RTOIE;
2419
2420	serial_out(up, UART_IER, up->ier);
2421
2422	if (up->capabilities & UART_CAP_EFR) {
2423	unsigned char efr = 0;
2424	/*
2425	* TI16C752/Startech hardware flow control. FIXME:
2426	* - TI16C752 requires control thresholds to be set.
2427	* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2428	*/
2429	if (termios->c_cflag & CRTSCTS)
2430	efr \|= UART_EFR_CTS;
2431
2432	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2433	if (up->port.flags & UPF_EXAR_EFR)
2434	serial_outp(up, UART_XR_EFR, efr);
2435	else
2436	serial_outp(up, UART_EFR, efr);
2437	}
2438
2439	#ifdef CONFIG_ARCH_OMAP
2440	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2441	if (cpu_is_omap1510() && is_omap_port(up)) {
2442	if (baud == 115200) {
2443	quot = 1;
2444	serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2445	} else
2446	serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2447	}
2448	#endif
2449
2450	if (up->capabilities & UART_NATSEMI) {
2451	/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2452	serial_outp(up, UART_LCR, 0xe0);
2453	} else {
2454	serial_outp(up, UART_LCR, cval \| UART_LCR_DLAB);/* set DLAB */
2455	}
2456
2457	serial_dl_write(up, quot);
2458
2459	/*
2460	* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2461	* is written without DLAB set, this mode will be disabled.
2462	*/
2463	if (up->port.type == PORT_16750)
2464	serial_outp(up, UART_FCR, fcr);
2465
2466	serial_outp(up, UART_LCR, cval); /* reset DLAB */
2467	up->lcr = cval; /* Save LCR */
2468	if (up->port.type != PORT_16750) {
2469	if (fcr & UART_FCR_ENABLE_FIFO) {
2470	/* emulated UARTs (Lucent Venus 167x) need two steps */
2471	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2472	}
2473	serial_outp(up, UART_FCR, fcr); /* set fcr */
2474	}
2475	serial8250_set_mctrl(&up->port, up->port.mctrl);
2476	spin_unlock_irqrestore(&up->port.lock, flags);
2477	/* Don't rewrite B0 */
2478	if (tty_termios_baud_rate(termios))
2479	tty_termios_encode_baud_rate(termios, baud, baud);
2480	}
2481	EXPORT_SYMBOL(serial8250_do_set_termios);
2482
2483	static void
2484	serial8250_set_termios(struct uart_port port, struct ktermios termios,
2485	struct ktermios *old)
2486	{
2487	if (port->set_termios)
2488	port->set_termios(port, termios, old);
2489	else
2490	serial8250_do_set_termios(port, termios, old);
2491	}
2492
2493	static void
2494	serial8250_set_ldisc(struct uart_port *port, int new)
2495	{
2496	if (new == N_PPS) {
2497	port->flags \|= UPF_HARDPPS_CD;
2498	serial8250_enable_ms(port);
2499	} else
2500	port->flags &= ~UPF_HARDPPS_CD;
2501	}
2502
2503
2504	void serial8250_do_pm(struct uart_port *port, unsigned int state,
2505	unsigned int oldstate)
2506	{
2507	struct uart_8250_port *p =
2508	container_of(port, struct uart_8250_port, port);
2509
2510	serial8250_set_sleep(p, state != 0);
2511	}
2512	EXPORT_SYMBOL(serial8250_do_pm);
2513
2514	static void
2515	serial8250_pm(struct uart_port *port, unsigned int state,
2516	unsigned int oldstate)
2517	{
2518	if (port->pm)
2519	port->pm(port, state, oldstate);
2520	else
2521	serial8250_do_pm(port, state, oldstate);
2522	}
2523
2524	static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2525	{
2526	if (pt->port.iotype == UPIO_AU)
2527	return 0x1000;
2528	#ifdef CONFIG_ARCH_OMAP
2529	if (is_omap_port(pt))
2530	return 0x16 << pt->port.regshift;
2531	#endif
2532	return 8 << pt->port.regshift;
2533	}
2534
2535	/*
2536	* Resource handling.
2537	*/
2538	static int serial8250_request_std_resource(struct uart_8250_port *up)
2539	{
2540	unsigned int size = serial8250_port_size(up);
2541	int ret = 0;
2542
2543	switch (up->port.iotype) {
2544	case UPIO_AU:
2545	case UPIO_TSI:
2546	case UPIO_MEM32:
2547	case UPIO_MEM:
2548	case UPIO_MEM_DELAY:
2549	if (!up->port.mapbase)
2550	break;
2551
2552	if (!request_mem_region(up->port.mapbase, size, "serial")) {
2553	ret = -EBUSY;
2554	break;
2555	}
2556
2557	if (up->port.flags & UPF_IOREMAP) {
2558	up->port.membase = ioremap_nocache(up->port.mapbase,
2559	size);
2560	if (!up->port.membase) {
2561	release_mem_region(up->port.mapbase, size);
2562	ret = -ENOMEM;
2563	}
2564	}
2565	break;
2566
2567	case UPIO_HUB6:
2568	case UPIO_PORT:
2569	if (!request_region(up->port.iobase, size, "serial"))
2570	ret = -EBUSY;
2571	break;
2572	}
2573	return ret;
2574	}
2575
2576	static void serial8250_release_std_resource(struct uart_8250_port *up)
2577	{
2578	unsigned int size = serial8250_port_size(up);
2579
2580	switch (up->port.iotype) {
2581	case UPIO_AU:
2582	case UPIO_TSI:
2583	case UPIO_MEM32:
2584	case UPIO_MEM:
2585	case UPIO_MEM_DELAY:
2586	if (!up->port.mapbase)
2587	break;
2588
2589	if (up->port.flags & UPF_IOREMAP) {
2590	iounmap(up->port.membase);
2591	up->port.membase = NULL;
2592	}
2593
2594	release_mem_region(up->port.mapbase, size);
2595	break;
2596
2597	case UPIO_HUB6:
2598	case UPIO_PORT:
2599	release_region(up->port.iobase, size);
2600	break;
2601	}
2602	}
2603
2604	static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2605	{
2606	unsigned long start = UART_RSA_BASE << up->port.regshift;
2607	unsigned int size = 8 << up->port.regshift;
2608	int ret = -EINVAL;
2609
2610	switch (up->port.iotype) {
2611	case UPIO_HUB6:
2612	case UPIO_PORT:
2613	start += up->port.iobase;
2614	if (request_region(start, size, "serial-rsa"))
2615	ret = 0;
2616	else
2617	ret = -EBUSY;
2618	break;
2619	}
2620
2621	return ret;
2622	}
2623
2624	static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2625	{
2626	unsigned long offset = UART_RSA_BASE << up->port.regshift;
2627	unsigned int size = 8 << up->port.regshift;
2628
2629	switch (up->port.iotype) {
2630	case UPIO_HUB6:
2631	case UPIO_PORT:
2632	release_region(up->port.iobase + offset, size);
2633	break;
2634	}
2635	}
2636
2637	static void serial8250_release_port(struct uart_port *port)
2638	{
2639	struct uart_8250_port *up =
2640	container_of(port, struct uart_8250_port, port);
2641
2642	serial8250_release_std_resource(up);
2643	if (up->port.type == PORT_RSA)
2644	serial8250_release_rsa_resource(up);
2645	}
2646
2647	static int serial8250_request_port(struct uart_port *port)
2648	{
2649	struct uart_8250_port *up =
2650	container_of(port, struct uart_8250_port, port);
2651	int ret = 0;
2652
2653	ret = serial8250_request_std_resource(up);
2654	if (ret == 0 && up->port.type == PORT_RSA) {
2655	ret = serial8250_request_rsa_resource(up);
2656	if (ret < 0)
2657	serial8250_release_std_resource(up);
2658	}
2659
2660	return ret;
2661	}
2662
2663	static void serial8250_config_port(struct uart_port *port, int flags)
2664	{
2665	struct uart_8250_port *up =
2666	container_of(port, struct uart_8250_port, port);
2667	int probeflags = PROBE_ANY;
2668	int ret;
2669
2670	/*
2671	* Find the region that we can probe for. This in turn
2672	* tells us whether we can probe for the type of port.
2673	*/
2674	ret = serial8250_request_std_resource(up);
2675	if (ret < 0)
2676	return;
2677
2678	ret = serial8250_request_rsa_resource(up);
2679	if (ret < 0)
2680	probeflags &= ~PROBE_RSA;
2681
2682	if (up->port.iotype != up->cur_iotype)
2683	set_io_from_upio(port);
2684
2685	if (flags & UART_CONFIG_TYPE)
2686	autoconfig(up, probeflags);
2687
2688	/* if access method is AU, it is a 16550 with a quirk */
2689	if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2690	up->bugs \|= UART_BUG_NOMSR;
2691
2692	if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2693	autoconfig_irq(up);
2694
2695	if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2696	serial8250_release_rsa_resource(up);
2697	if (up->port.type == PORT_UNKNOWN)
2698	serial8250_release_std_resource(up);
2699	}
2700
2701	static int
2702	serial8250_verify_port(struct uart_port port, struct serial_struct ser)
2703	{
2704	if (ser->irq >= nr_irqs \|\| ser->irq < 0 \|\|
2705	ser->baud_base < 9600 \|\| ser->type < PORT_UNKNOWN \|\|
2706	ser->type >= ARRAY_SIZE(uart_config) \|\| ser->type == PORT_CIRRUS \|\|
2707	ser->type == PORT_STARTECH)
2708	return -EINVAL;
2709	return 0;
2710	}
2711
2712	static const char *
2713	serial8250_type(struct uart_port *port)
2714	{
2715	int type = port->type;
2716
2717	if (type >= ARRAY_SIZE(uart_config))
2718	type = 0;
2719	return uart_config[type].name;
2720	}
2721
2722	static struct uart_ops serial8250_pops = {
2723	.tx_empty = serial8250_tx_empty,
2724	.set_mctrl = serial8250_set_mctrl,
2725	.get_mctrl = serial8250_get_mctrl,
2726	.stop_tx = serial8250_stop_tx,
2727	.start_tx = serial8250_start_tx,
2728	.stop_rx = serial8250_stop_rx,
2729	.enable_ms = serial8250_enable_ms,
2730	.break_ctl = serial8250_break_ctl,
2731	.startup = serial8250_startup,
2732	.shutdown = serial8250_shutdown,
2733	.set_termios = serial8250_set_termios,
2734	.set_ldisc = serial8250_set_ldisc,
2735	.pm = serial8250_pm,
2736	.type = serial8250_type,
2737	.release_port = serial8250_release_port,
2738	.request_port = serial8250_request_port,
2739	.config_port = serial8250_config_port,
2740	.verify_port = serial8250_verify_port,
2741	#ifdef CONFIG_CONSOLE_POLL
2742	.poll_get_char = serial8250_get_poll_char,
2743	.poll_put_char = serial8250_put_poll_char,
2744	#endif
2745	};
2746
2747	static struct uart_8250_port serial8250_ports[UART_NR];
2748
2749	static void (serial8250_isa_config)(int port, struct uart_port up,
2750	unsigned short *capabilities);
2751
2752	void serial8250_set_isa_configurator(
2753	void (v)(int port, struct uart_port up, unsigned short *capabilities))
2754	{
2755	serial8250_isa_config = v;
2756	}
2757	EXPORT_SYMBOL(serial8250_set_isa_configurator);
2758
2759	static void __init serial8250_isa_init_ports(void)
2760	{
2761	struct uart_8250_port *up;
2762	static int first = 1;
2763	int i, irqflag = 0;
2764
2765	if (!first)
2766	return;
2767	first = 0;
2768
2769	for (i = 0; i < nr_uarts; i++) {
2770	struct uart_8250_port *up = &serial8250_ports[i];
2771
2772	up->port.line = i;
2773	spin_lock_init(&up->port.lock);
2774
2775	init_timer(&up->timer);
2776	up->timer.function = serial8250_timeout;
2777
2778	/*
2779	* ALPHA_KLUDGE_MCR needs to be killed.
2780	*/
2781	up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2782	up->mcr_force = ALPHA_KLUDGE_MCR;
2783
2784	up->port.ops = &serial8250_pops;
2785	}
2786
2787	if (share_irqs)
2788	irqflag = IRQF_SHARED;
2789
2790	for (i = 0, up = serial8250_ports;
2791	i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2792	i++, up++) {
2793	up->port.iobase = old_serial_port[i].port;
2794	up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2795	up->port.irqflags = old_serial_port[i].irqflags;
2796	up->port.uartclk = old_serial_port[i].baud_base * 16;
2797	up->port.flags = old_serial_port[i].flags;
2798	up->port.hub6 = old_serial_port[i].hub6;
2799	up->port.membase = old_serial_port[i].iomem_base;
2800	up->port.iotype = old_serial_port[i].io_type;
2801	up->port.regshift = old_serial_port[i].iomem_reg_shift;
2802	set_io_from_upio(&up->port);
2803	up->port.irqflags \|= irqflag;
2804	if (serial8250_isa_config != NULL)
2805	serial8250_isa_config(i, &up->port, &up->capabilities);
2806
2807	}
2808	}
2809
2810	static void
2811	serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2812	{
2813	up->port.type = type;
2814	up->port.fifosize = uart_config[type].fifo_size;
2815	up->capabilities = uart_config[type].flags;
2816	up->tx_loadsz = uart_config[type].tx_loadsz;
2817	}
2818
2819	static void __init
2820	serial8250_register_ports(struct uart_driver drv, struct device dev)
2821	{
2822	int i;
2823
2824	for (i = 0; i < nr_uarts; i++) {
2825	struct uart_8250_port *up = &serial8250_ports[i];
2826	up->cur_iotype = 0xFF;
2827	}
2828
2829	serial8250_isa_init_ports();
2830
2831	for (i = 0; i < nr_uarts; i++) {
2832	struct uart_8250_port *up = &serial8250_ports[i];
2833
2834	up->port.dev = dev;
2835
2836	if (up->port.flags & UPF_FIXED_TYPE)
2837	serial8250_init_fixed_type_port(up, up->port.type);
2838
2839	uart_add_one_port(drv, &up->port);
2840	}
2841	}
2842
2843	#ifdef CONFIG_SERIAL_8250_CONSOLE
2844
2845	static void serial8250_console_putchar(struct uart_port *port, int ch)
2846	{
2847	struct uart_8250_port *up =
2848	container_of(port, struct uart_8250_port, port);
2849
2850	wait_for_xmitr(up, UART_LSR_THRE);
2851	serial_out(up, UART_TX, ch);
2852	}
2853
2854	/*
2855	* Print a string to the serial port trying not to disturb
2856	* any possible real use of the port...
2857	*
2858	* The console_lock must be held when we get here.
2859	*/
2860	static void
2861	serial8250_console_write(struct console co, const char s, unsigned int count)
2862	{
2863	struct uart_8250_port *up = &serial8250_ports[co->index];
2864	unsigned long flags;
2865	unsigned int ier;
2866	int locked = 1;
2867
2868	touch_nmi_watchdog();
2869
2870	local_irq_save(flags);
2871	if (up->port.sysrq) {
2872	/* serial8250_handle_port() already took the lock */
2873	locked = 0;
2874	} else if (oops_in_progress) {
2875	locked = spin_trylock(&up->port.lock);
2876	} else
2877	spin_lock(&up->port.lock);
2878
2879	/*
2880	* First save the IER then disable the interrupts
2881	*/
2882	ier = serial_in(up, UART_IER);
2883
2884	if (up->capabilities & UART_CAP_UUE)
2885	serial_out(up, UART_IER, UART_IER_UUE);
2886	else
2887	serial_out(up, UART_IER, 0);
2888
2889	uart_console_write(&up->port, s, count, serial8250_console_putchar);
2890
2891	/*
2892	* Finally, wait for transmitter to become empty
2893	* and restore the IER
2894	*/
2895	wait_for_xmitr(up, BOTH_EMPTY);
2896	serial_out(up, UART_IER, ier);
2897
2898	/*
2899	* The receive handling will happen properly because the
2900	* receive ready bit will still be set; it is not cleared
2901	* on read. However, modem control will not, we must
2902	* call it if we have saved something in the saved flags
2903	* while processing with interrupts off.
2904	*/
2905	if (up->msr_saved_flags)
2906	check_modem_status(up);
2907
2908	if (locked)
2909	spin_unlock(&up->port.lock);
2910	local_irq_restore(flags);
2911	}
2912
2913	static int __init serial8250_console_setup(struct console co, char options)
2914	{
2915	struct uart_port *port;
2916	int baud = 9600;
2917	int bits = 8;
2918	int parity = 'n';
2919	int flow = 'n';
2920
2921	/*
2922	* Check whether an invalid uart number has been specified, and
2923	* if so, search for the first available port that does have
2924	* console support.
2925	*/
2926	if (co->index >= nr_uarts)
2927	co->index = 0;
2928	port = &serial8250_ports[co->index].port;
2929	if (!port->iobase && !port->membase)
2930	return -ENODEV;
2931
2932	if (options)
2933	uart_parse_options(options, &baud, &parity, &bits, &flow);
2934
2935	return uart_set_options(port, co, baud, parity, bits, flow);
2936	}
2937
2938	static int serial8250_console_early_setup(void)
2939	{
2940	return serial8250_find_port_for_earlycon();
2941	}
2942
2943	static struct console serial8250_console = {
2944	.name = "ttyS",
2945	.write = serial8250_console_write,
2946	.device = uart_console_device,
2947	.setup = serial8250_console_setup,
2948	.early_setup = serial8250_console_early_setup,
2949	.flags = CON_PRINTBUFFER \| CON_ANYTIME,
2950	.index = -1,
2951	.data = &serial8250_reg,
2952	};
2953
2954	static int __init serial8250_console_init(void)
2955	{
2956	if (nr_uarts > UART_NR)
2957	nr_uarts = UART_NR;
2958
2959	serial8250_isa_init_ports();
2960	register_console(&serial8250_console);
2961	return 0;
2962	}
2963	console_initcall(serial8250_console_init);
2964
2965	int serial8250_find_port(struct uart_port *p)
2966	{
2967	int line;
2968	struct uart_port *port;
2969
2970	for (line = 0; line < nr_uarts; line++) {
2971	port = &serial8250_ports[line].port;
2972	if (uart_match_port(p, port))
2973	return line;
2974	}
2975	return -ENODEV;
2976	}
2977
2978	#define SERIAL8250_CONSOLE &serial8250_console
2979	#else
2980	#define SERIAL8250_CONSOLE NULL
2981	#endif
2982
2983	static struct uart_driver serial8250_reg = {
2984	.owner = THIS_MODULE,
2985	.driver_name = "serial",
2986	.dev_name = "ttyS",
2987	.major = TTY_MAJOR,
2988	.minor = 64,
2989	.cons = SERIAL8250_CONSOLE,
2990	};
2991
2992	/*
2993	* early_serial_setup - early registration for 8250 ports
2994	*
2995	* Setup an 8250 port structure prior to console initialisation. Use
2996	* after console initialisation will cause undefined behaviour.
2997	*/
2998	int __init early_serial_setup(struct uart_port *port)
2999	{
3000	struct uart_port *p;
3001
3002	if (port->line >= ARRAY_SIZE(serial8250_ports))
3003	return -ENODEV;
3004
3005	serial8250_isa_init_ports();
3006	p = &serial8250_ports[port->line].port;
3007	p->iobase = port->iobase;
3008	p->membase = port->membase;
3009	p->irq = port->irq;
3010	p->irqflags = port->irqflags;
3011	p->uartclk = port->uartclk;
3012	p->fifosize = port->fifosize;
3013	p->regshift = port->regshift;
3014	p->iotype = port->iotype;
3015	p->flags = port->flags;
3016	p->mapbase = port->mapbase;
3017	p->private_data = port->private_data;
3018	p->type = port->type;
3019	p->line = port->line;
3020
3021	set_io_from_upio(p);
3022	if (port->serial_in)
3023	p->serial_in = port->serial_in;
3024	if (port->serial_out)
3025	p->serial_out = port->serial_out;
3026	if (port->handle_irq)
3027	p->handle_irq = port->handle_irq;
3028	else
3029	p->handle_irq = serial8250_default_handle_irq;
3030
3031	return 0;
3032	}
3033
3034	/**
3035	* serial8250_suspend_port - suspend one serial port
3036	* @line: serial line number
3037	*
3038	* Suspend one serial port.
3039	*/
3040	void serial8250_suspend_port(int line)
3041	{
3042	uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3043	}
3044
3045	/**
3046	* serial8250_resume_port - resume one serial port
3047	* @line: serial line number
3048	*
3049	* Resume one serial port.
3050	*/
3051	void serial8250_resume_port(int line)
3052	{
3053	struct uart_8250_port *up = &serial8250_ports[line];
3054
3055	if (up->capabilities & UART_NATSEMI) {
3056	/* Ensure it's still in high speed mode */
3057	serial_outp(up, UART_LCR, 0xE0);
3058
3059	ns16550a_goto_highspeed(up);
3060
3061	serial_outp(up, UART_LCR, 0);
3062	up->port.uartclk = 921600*16;
3063	}
3064	uart_resume_port(&serial8250_reg, &up->port);
3065	}
3066
3067	/*
3068	* Register a set of serial devices attached to a platform device. The
3069	* list is terminated with a zero flags entry, which means we expect
3070	* all entries to have at least UPF_BOOT_AUTOCONF set.
3071	*/
3072	static int __devinit serial8250_probe(struct platform_device *dev)
3073	{
3074	struct plat_serial8250_port *p = dev->dev.platform_data;
3075	struct uart_port port;
3076	int ret, i, irqflag = 0;
3077
3078	memset(&port, 0, sizeof(struct uart_port));
3079
3080	if (share_irqs)
3081	irqflag = IRQF_SHARED;
3082
3083	for (i = 0; p && p->flags != 0; p++, i++) {
3084	port.iobase = p->iobase;
3085	port.membase = p->membase;
3086	port.irq = p->irq;
3087	port.irqflags = p->irqflags;
3088	port.uartclk = p->uartclk;
3089	port.regshift = p->regshift;
3090	port.iotype = p->iotype;
3091	port.flags = p->flags;
3092	port.mapbase = p->mapbase;
3093	port.hub6 = p->hub6;
3094	port.private_data = p->private_data;
3095	port.type = p->type;
3096	port.serial_in = p->serial_in;
3097	port.serial_out = p->serial_out;
3098	port.handle_irq = p->handle_irq;
3099	port.set_termios = p->set_termios;
3100	port.pm = p->pm;
3101	port.dev = &dev->dev;
3102	port.rw_delay = p->rw_delay;
3103	port.irqflags \|= irqflag;
3104	ret = serial8250_register_port(&port);
3105	if (ret < 0) {
3106	dev_err(&dev->dev, "unable to register port at index %d "
3107	"(IO%lx MEM%llx IRQ%d): %d\n", i,
3108	p->iobase, (unsigned long long)p->mapbase,
3109	p->irq, ret);
3110	}
3111	}
3112	return 0;
3113	}
3114
3115	/*
3116	* Remove serial ports registered against a platform device.
3117	*/
3118	static int __devexit serial8250_remove(struct platform_device *dev)
3119	{
3120	int i;
3121
3122	for (i = 0; i < nr_uarts; i++) {
3123	struct uart_8250_port *up = &serial8250_ports[i];
3124
3125	if (up->port.dev == &dev->dev)
3126	serial8250_unregister_port(i);
3127	}
3128	return 0;
3129	}
3130
3131	static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3132	{
3133	int i;
3134
3135	for (i = 0; i < UART_NR; i++) {
3136	struct uart_8250_port *up = &serial8250_ports[i];
3137
3138	if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3139	uart_suspend_port(&serial8250_reg, &up->port);
3140	}
3141
3142	return 0;
3143	}
3144
3145	static int serial8250_resume(struct platform_device *dev)
3146	{
3147	int i;
3148
3149	for (i = 0; i < UART_NR; i++) {
3150	struct uart_8250_port *up = &serial8250_ports[i];
3151
3152	if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3153	serial8250_resume_port(i);
3154	}
3155
3156	return 0;
3157	}
3158
3159	static struct platform_driver serial8250_isa_driver = {
3160	.probe = serial8250_probe,
3161	.remove = __devexit_p(serial8250_remove),
3162	.suspend = serial8250_suspend,
3163	.resume = serial8250_resume,
3164	.driver = {
3165	.name = "serial8250",
3166	.owner = THIS_MODULE,
3167	},
3168	};
3169
3170	/*
3171	* This "device" covers _all_ ISA 8250-compatible serial devices listed
3172	* in the table in include/asm/serial.h
3173	*/
3174	static struct platform_device *serial8250_isa_devs;
3175
3176	/*
3177	* serial8250_register_port and serial8250_unregister_port allows for
3178	* 16x50 serial ports to be configured at run-time, to support PCMCIA
3179	* modems and PCI multiport cards.
3180	*/
3181	static DEFINE_MUTEX(serial_mutex);
3182
3183	static struct uart_8250_port serial8250_find_match_or_unused(struct uart_port port)
3184	{
3185	int i;
3186
3187	/*
3188	* First, find a port entry which matches.
3189	*/
3190	for (i = 0; i < nr_uarts; i++)
3191	if (uart_match_port(&serial8250_ports[i].port, port))
3192	return &serial8250_ports[i];
3193
3194	/*
3195	* We didn't find a matching entry, so look for the first
3196	* free entry. We look for one which hasn't been previously
3197	* used (indicated by zero iobase).
3198	*/
3199	for (i = 0; i < nr_uarts; i++)
3200	if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3201	serial8250_ports[i].port.iobase == 0)
3202	return &serial8250_ports[i];
3203
3204	/*
3205	* That also failed. Last resort is to find any entry which
3206	* doesn't have a real port associated with it.
3207	*/
3208	for (i = 0; i < nr_uarts; i++)
3209	if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3210	return &serial8250_ports[i];
3211
3212	return NULL;
3213	}
3214
3215	/**
3216	* serial8250_register_port - register a serial port
3217	* @port: serial port template
3218	*
3219	* Configure the serial port specified by the request. If the
3220	* port exists and is in use, it is hung up and unregistered
3221	* first.
3222	*
3223	* The port is then probed and if necessary the IRQ is autodetected
3224	* If this fails an error is returned.
3225	*
3226	* On success the port is ready to use and the line number is returned.
3227	*/
3228	int serial8250_register_port(struct uart_port *port)
3229	{
3230	struct uart_8250_port *uart;
3231	int ret = -ENOSPC;
3232
3233	if (port->uartclk == 0)
3234	return -EINVAL;
3235
3236	mutex_lock(&serial_mutex);
3237
3238	uart = serial8250_find_match_or_unused(port);
3239	if (uart) {
3240	uart_remove_one_port(&serial8250_reg, &uart->port);
3241
3242	uart->port.iobase = port->iobase;
3243	uart->port.membase = port->membase;
3244	uart->port.irq = port->irq;
3245	uart->port.irqflags = port->irqflags;
3246	uart->port.uartclk = port->uartclk;
3247	uart->port.fifosize = port->fifosize;
3248	uart->port.regshift = port->regshift;
3249	uart->port.iotype = port->iotype;
3250	uart->port.flags = port->flags \| UPF_BOOT_AUTOCONF;
3251	uart->port.mapbase = port->mapbase;
3252	uart->port.rw_delay = port->rw_delay;
3253	uart->port.private_data = port->private_data;
3254	if (port->dev)
3255	uart->port.dev = port->dev;
3256
3257	if (port->flags & UPF_FIXED_TYPE)
3258	serial8250_init_fixed_type_port(uart, port->type);
3259
3260	set_io_from_upio(&uart->port);
3261	/* Possibly override default I/O functions. */
3262	if (port->serial_in)
3263	uart->port.serial_in = port->serial_in;
3264	if (port->serial_out)
3265	uart->port.serial_out = port->serial_out;
3266	if (port->handle_irq)
3267	uart->port.handle_irq = port->handle_irq;
3268	/* Possibly override set_termios call */
3269	if (port->set_termios)
3270	uart->port.set_termios = port->set_termios;
3271	if (port->pm)
3272	uart->port.pm = port->pm;
3273
3274	if (serial8250_isa_config != NULL)
3275	serial8250_isa_config(0, &uart->port,
3276	&uart->capabilities);
3277
3278	ret = uart_add_one_port(&serial8250_reg, &uart->port);
3279	if (ret == 0)
3280	ret = uart->port.line;
3281	}
3282	mutex_unlock(&serial_mutex);
3283
3284	return ret;
3285	}
3286	EXPORT_SYMBOL(serial8250_register_port);
3287
3288	/**
3289	* serial8250_unregister_port - remove a 16x50 serial port at runtime
3290	* @line: serial line number
3291	*
3292	* Remove one serial port. This may not be called from interrupt
3293	* context. We hand the port back to the our control.
3294	*/
3295	void serial8250_unregister_port(int line)
3296	{
3297	struct uart_8250_port *uart = &serial8250_ports[line];
3298
3299	mutex_lock(&serial_mutex);
3300	uart_remove_one_port(&serial8250_reg, &uart->port);
3301	if (serial8250_isa_devs) {
3302	uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3303	uart->port.type = PORT_UNKNOWN;
3304	uart->port.dev = &serial8250_isa_devs->dev;
3305	uart->capabilities = uart_config[uart->port.type].flags;
3306	uart_add_one_port(&serial8250_reg, &uart->port);
3307	} else {
3308	uart->port.dev = NULL;
3309	}
3310	mutex_unlock(&serial_mutex);
3311	}
3312	EXPORT_SYMBOL(serial8250_unregister_port);
3313
3314	static int __init serial8250_init(void)
3315	{
3316	int ret;
3317
3318	if (nr_uarts > UART_NR)
3319	nr_uarts = UART_NR;
3320
3321	printk(KERN_INFO "Serial: 8250/16550 driver, "
3322	"%d ports, IRQ sharing %sabled\n", nr_uarts,
3323	share_irqs ? "en" : "dis");
3324
3325	#ifdef CONFIG_SPARC
3326	ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3327	#else
3328	serial8250_reg.nr = UART_NR;
3329	ret = uart_register_driver(&serial8250_reg);
3330	#endif
3331	if (ret)
3332	goto out;
3333
3334	serial8250_isa_devs = platform_device_alloc("serial8250",
3335	PLAT8250_DEV_LEGACY);
3336	if (!serial8250_isa_devs) {
3337	ret = -ENOMEM;
3338	goto unreg_uart_drv;
3339	}
3340
3341	ret = platform_device_add(serial8250_isa_devs);
3342	if (ret)
3343	goto put_dev;
3344
3345	serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3346
3347	ret = platform_driver_register(&serial8250_isa_driver);
3348	if (ret == 0)
3349	goto out;
3350
3351	platform_device_del(serial8250_isa_devs);
3352	put_dev:
3353	platform_device_put(serial8250_isa_devs);
3354	unreg_uart_drv:
3355	#ifdef CONFIG_SPARC
3356	sunserial_unregister_minors(&serial8250_reg, UART_NR);
3357	#else
3358	uart_unregister_driver(&serial8250_reg);
3359	#endif
3360	out:
3361	return ret;
3362	}
3363
3364	static void __exit serial8250_exit(void)
3365	{
3366	struct platform_device *isa_dev = serial8250_isa_devs;
3367
3368	/*
3369	* This tells serial8250_unregister_port() not to re-register
3370	* the ports (thereby making serial8250_isa_driver permanently
3371	* in use.)
3372	*/
3373	serial8250_isa_devs = NULL;
3374
3375	platform_driver_unregister(&serial8250_isa_driver);
3376	platform_device_unregister(isa_dev);
3377
3378	#ifdef CONFIG_SPARC
3379	sunserial_unregister_minors(&serial8250_reg, UART_NR);
3380	#else
3381	uart_unregister_driver(&serial8250_reg);
3382	#endif
3383	}
3384
3385	module_init(serial8250_init);
3386	module_exit(serial8250_exit);
3387
3388	EXPORT_SYMBOL(serial8250_suspend_port);
3389	EXPORT_SYMBOL(serial8250_resume_port);
3390
3391	MODULE_LICENSE("GPL");
3392	MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3393
3394	module_param(share_irqs, uint, 0644);
3395	MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3396	" (unsafe)");
3397
3398	module_param(nr_uarts, uint, 0644);
3399	MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3400
3401	module_param(skip_txen_test, uint, 0644);
3402	MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3403
3404	#ifdef CONFIG_SERIAL_8250_RSA
3405	module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3406	MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3407	#endif
3408	MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);

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