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source: src/linux/universal/linux-3.2/drivers/usb/host/ehci-hcd.c @ 18352

Last change on this file since 18352 was 18352, checked in by BrainSlayer, 16 months ago
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File size: 40.6 KB

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1	/*
2	* Enhanced Host Controller Interface (EHCI) driver for USB.
3	*
4	* Maintainer: Alan Stern <stern@rowland.harvard.edu>
5	*
6	* Copyright (c) 2000-2004 by David Brownell
7	*
8	* This program is free software; you can redistribute it and/or modify it
9	* under the terms of the GNU General Public License as published by the
10	* Free Software Foundation; either version 2 of the License, or (at your
11	* option) any later version.
12	*
13	* This program is distributed in the hope that it will be useful, but
14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16	* for more details.
17	*
18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software Foundation,
20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	*/
22
23	#include <linux/module.h>
24	#include <linux/pci.h>
25	#include <linux/dmapool.h>
26	#include <linux/kernel.h>
27	#include <linux/delay.h>
28	#include <linux/ioport.h>
29	#include <linux/sched.h>
30	#include <linux/vmalloc.h>
31	#include <linux/errno.h>
32	#include <linux/init.h>
33	#include <linux/timer.h>
34	#include <linux/ktime.h>
35	#include <linux/list.h>
36	#include <linux/interrupt.h>
37	#include <linux/usb.h>
38	#include <linux/usb/hcd.h>
39	#include <linux/moduleparam.h>
40	#include <linux/dma-mapping.h>
41	#include <linux/debugfs.h>
42	#include <linux/slab.h>
43	#include <linux/uaccess.h>
44
45	#include <asm/byteorder.h>
46	#include <asm/io.h>
47	#include <asm/irq.h>
48	#include <asm/system.h>
49	#include <asm/unaligned.h>
50
51	#if defined(CONFIG_MACH_AR7240) \|\| defined(CONFIG_MACH_HORNET) \|\| defined(CONFIG_WASP_SUPPORT)
52
53	#ifdef CONFIG_WASP_SUPPORT
54	#include "../gadget/ath_defs.h"
55	#else
56	#include "../gadget/ar9130_defs.h"
57	#endif
58	#endif
59
60
61	/-------------------------------------------------------------------------/
62
63	/*
64	* EHCI hc_driver implementation ... experimental, incomplete.
65	* Based on the final 1.0 register interface specification.
66	*
67	* USB 2.0 shows up in upcoming www.pcmcia.org technology.
68	* First was PCMCIA, like ISA; then CardBus, which is PCI.
69	* Next comes "CardBay", using USB 2.0 signals.
70	*
71	* Contains additional contributions by Brad Hards, Rory Bolt, and others.
72	* Special thanks to Intel and VIA for providing host controllers to
73	* test this driver on, and Cypress (including In-System Design) for
74	* providing early devices for those host controllers to talk to!
75	*/
76
77	#define DRIVER_AUTHOR "David Brownell"
78	#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
79
80	static const char hcd_name [] = "ehci_hcd";
81
82
83	#undef VERBOSE_DEBUG
84	#undef EHCI_URB_TRACE
85
86	#ifdef DEBUG
87	#define EHCI_STATS
88	#endif
89
90	/* magic numbers that can affect system performance */
91	#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
92	#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
93	#define EHCI_TUNE_RL_TT 0
94	#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
95	#define EHCI_TUNE_MULT_TT 1
96	/*
97	* Some drivers think it's safe to schedule isochronous transfers more than
98	* 256 ms into the future (partly as a result of an old bug in the scheduling
99	* code). In an attempt to avoid trouble, we will use a minimum scheduling
100	* length of 512 frames instead of 256.
101	*/
102	#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
103
104	#define EHCI_IAA_MSECS 10 /* arbitrary */
105	#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
106	#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
107	#define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
108	/* 5-ms async qh unlink delay */
109
110	/* Initial IRQ latency: faster than hw default */
111	static int log2_irq_thresh = 0; // 0 to 6
112	module_param (log2_irq_thresh, int, S_IRUGO);
113	MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
114
115	/* initial park setting: slower than hw default */
116	static unsigned park = 0;
117	module_param (park, uint, S_IRUGO);
118	MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
119
120	/* for flakey hardware, ignore overcurrent indicators */
121	static int ignore_oc = 0;
122	module_param (ignore_oc, bool, S_IRUGO);
123	MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
124
125	/* for link power management(LPM) feature */
126	static unsigned int hird;
127	module_param(hird, int, S_IRUGO);
128	MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
129
130	#define INTR_MASK (STS_IAA \| STS_FATAL \| STS_PCD \| STS_ERR \| STS_INT)
131
132	/-------------------------------------------------------------------------/
133
134	#include "ehci.h"
135	#include "ehci-dbg.c"
136	#include "pci-quirks.h"
137
138	/-------------------------------------------------------------------------/
139
140	static void
141	timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
142	{
143	/* Don't override timeouts which shrink or (later) disable
144	* the async ring; just the I/O watchdog. Note that if a
145	* SHRINK were pending, OFF would never be requested.
146	*/
147	if (timer_pending(&ehci->watchdog)
148	&& ((BIT(TIMER_ASYNC_SHRINK) \| BIT(TIMER_ASYNC_OFF))
149	& ehci->actions))
150	return;
151
152	if (!test_and_set_bit(action, &ehci->actions)) {
153	unsigned long t;
154
155	switch (action) {
156	case TIMER_IO_WATCHDOG:
157	if (!ehci->need_io_watchdog)
158	return;
159	t = EHCI_IO_JIFFIES;
160	break;
161	case TIMER_ASYNC_OFF:
162	t = EHCI_ASYNC_JIFFIES;
163	break;
164	/* case TIMER_ASYNC_SHRINK: */
165	default:
166	t = EHCI_SHRINK_JIFFIES;
167	break;
168	}
169	mod_timer(&ehci->watchdog, t + jiffies);
170	}
171	}
172
173	/-------------------------------------------------------------------------/
174
175	/*
176	* handshake - spin reading hc until handshake completes or fails
177	* @ptr: address of hc register to be read
178	* @mask: bits to look at in result of read
179	* @done: value of those bits when handshake succeeds
180	* @usec: timeout in microseconds
181	*
182	* Returns negative errno, or zero on success
183	*
184	* Success happens when the "mask" bits have the specified value (hardware
185	* handshake done). There are two failure modes: "usec" have passed (major
186	* hardware flakeout), or the register reads as all-ones (hardware removed).
187	*
188	* That last failure should_only happen in cases like physical cardbus eject
189	* before driver shutdown. But it also seems to be caused by bugs in cardbus
190	* bridge shutdown: shutting down the bridge before the devices using it.
191	*/
192	static int handshake (struct ehci_hcd ehci, void __iomem ptr,
193	u32 mask, u32 done, int usec)
194	{
195	u32 result;
196
197	do {
198	result = ehci_readl(ehci, ptr);
199	if (result == ~(u32)0) /* card removed */
200	return -ENODEV;
201	result &= mask;
202	if (result == done)
203	return 0;
204	udelay (1);
205	usec--;
206	} while (usec > 0);
207	return -ETIMEDOUT;
208	}
209
210	/* check TDI/ARC silicon is in host mode */
211	static int tdi_in_host_mode (struct ehci_hcd *ehci)
212	{
213	u32 __iomem *reg_ptr;
214	u32 tmp;
215
216	reg_ptr = (u32 __iomem )(((u8 __iomem )ehci->regs) + USBMODE);
217	tmp = ehci_readl(ehci, reg_ptr);
218	return (tmp & 3) == USBMODE_CM_HC;
219	}
220
221	/* force HC to halt state from unknown (EHCI spec section 2.3) */
222	static int ehci_halt (struct ehci_hcd *ehci)
223	{
224	u32 temp = ehci_readl(ehci, &ehci->regs->status);
225
226	/* disable any irqs left enabled by previous code */
227	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
228
229	if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
230	return 0;
231	}
232
233	if ((temp & STS_HALT) != 0)
234	return 0;
235
236	temp = ehci_readl(ehci, &ehci->regs->command);
237	temp &= ~CMD_RUN;
238	ehci_writel(ehci, temp, &ehci->regs->command);
239	return handshake (ehci, &ehci->regs->status,
240	STS_HALT, STS_HALT, 16 * 125);
241	}
242
243	static int handshake_on_error_set_halt(struct ehci_hcd ehci, void __iomem ptr,
244	u32 mask, u32 done, int usec)
245	{
246	int error;
247
248	error = handshake(ehci, ptr, mask, done, usec);
249	if (error) {
250	ehci_halt(ehci);
251	ehci->rh_state = EHCI_RH_HALTED;
252	ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
253	ptr, mask, done, error);
254	}
255
256	return error;
257	}
258
259	/* put TDI/ARC silicon into EHCI mode */
260	static void tdi_reset (struct ehci_hcd *ehci)
261	{
262	u32 __iomem *reg_ptr;
263	u32 tmp;
264
265	reg_ptr = (u32 __iomem )(((u8 __iomem )ehci->regs) + USBMODE);
266	tmp = ehci_readl(ehci, reg_ptr);
267	tmp \|= USBMODE_CM_HC;
268	/* The default byte access to MMR space is LE after
269	* controller reset. Set the required endian mode
270	* for transfer buffers to match the host microprocessor
271	*/
272	if (ehci_big_endian_mmio(ehci))
273	tmp \|= USBMODE_BE;
274	ehci_writel(ehci, tmp, reg_ptr);
275	}
276
277	/* reset a non-running (STS_HALT == 1) controller */
278	static int ehci_reset (struct ehci_hcd *ehci)
279	{
280	int retval;
281	u32 command = ehci_readl(ehci, &ehci->regs->command);
282
283	/* If the EHCI debug controller is active, special care must be
284	* taken before and after a host controller reset */
285	if (ehci->debug && !dbgp_reset_prep())
286	ehci->debug = NULL;
287
288	command \|= CMD_RESET;
289	dbg_cmd (ehci, "reset", command);
290	ehci_writel(ehci, command, &ehci->regs->command);
291	#if defined(CONFIG_MACH_AR7240) \|\| defined(CONFIG_MACH_HORNET) \|\| defined(CONFIG_WASP_SUPPORT)
292	#define ath_usb_reg_wr ar7240_reg_wr
293	#define ath_usb_reg_rd ar7240_reg_rd
294	#define ATH_USB_USB_MODE AR9130_USB_MODE
295	udelay(1000);
296	#ifdef CONFIG_WASP_SUPPORT
297	ath_usb_reg_wr(ATH_USB_USB_MODE,
298	(ath_usb_reg_rd(ATH_USB_USB_MODE) \| 0x13));
299	#else
300	ath_usb_reg_wr(ATH_USB_USB_MODE,
301	(ath_usb_reg_rd(ATH_USB_USB_MODE) \| 0x03));
302	#endif
303	printk("%s Intialize USB CONTROLLER in host mode: %x\n",
304	__func__, ath_usb_reg_rd(ATH_USB_USB_MODE));
305
306	udelay(1000);
307	writel((readl(&ehci->regs->port_status[0]) \| (1 << 28) ), &ehci->regs->port_status[0]);
308	printk("%s Port Status %x \n", __func__, readl(&ehci->regs->port_status[0]));
309	#endif
310
311	ehci->rh_state = EHCI_RH_HALTED;
312	ehci->next_statechange = jiffies;
313	retval = handshake (ehci, &ehci->regs->command,
314	CMD_RESET, 0, 250 * 1000);
315
316	if (ehci->has_hostpc) {
317	ehci_writel(ehci, USBMODE_EX_HC \| USBMODE_EX_VBPS,
318	(u32 __iomem )(((u8 )ehci->regs) + USBMODE_EX));
319	ehci_writel(ehci, TXFIFO_DEFAULT,
320	(u32 __iomem )(((u8 )ehci->regs) + TXFILLTUNING));
321	}
322	if (retval)
323	return retval;
324
325	if (ehci_is_TDI(ehci))
326	tdi_reset (ehci);
327
328	if (ehci->debug)
329	dbgp_external_startup();
330
331	return retval;
332	}
333
334	/* idle the controller (from running) */
335	static void ehci_quiesce (struct ehci_hcd *ehci)
336	{
337	u32 temp;
338
339	#ifdef DEBUG
340	if (ehci->rh_state != EHCI_RH_RUNNING)
341	BUG ();
342	#endif
343
344	/* wait for any schedule enables/disables to take effect */
345	temp = ehci_readl(ehci, &ehci->regs->command) << 10;
346	temp &= STS_ASS \| STS_PSS;
347	if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
348	STS_ASS \| STS_PSS, temp, 16 * 125))
349	return;
350
351	/* then disable anything that's still active */
352	temp = ehci_readl(ehci, &ehci->regs->command);
353	temp &= ~(CMD_ASE \| CMD_IAAD \| CMD_PSE);
354	ehci_writel(ehci, temp, &ehci->regs->command);
355
356	/* hardware can take 16 microframes to turn off ... */
357	handshake_on_error_set_halt(ehci, &ehci->regs->status,
358	STS_ASS \| STS_PSS, 0, 16 * 125);
359	}
360
361	/-------------------------------------------------------------------------/
362
363	static void end_unlink_async(struct ehci_hcd *ehci);
364	static void ehci_work(struct ehci_hcd *ehci);
365
366	#include "ehci-hub.c"
367	#include "ehci-lpm.c"
368	#include "ehci-mem.c"
369	#include "ehci-q.c"
370	#include "ehci-sched.c"
371	#include "ehci-sysfs.c"
372
373	/-------------------------------------------------------------------------/
374
375	static void ehci_iaa_watchdog(unsigned long param)
376	{
377	struct ehci_hcd ehci = (struct ehci_hcd ) param;
378	unsigned long flags;
379
380	spin_lock_irqsave (&ehci->lock, flags);
381
382	/* Lost IAA irqs wedge things badly; seen first with a vt8235.
383	* So we need this watchdog, but must protect it against both
384	* (a) SMP races against real IAA firing and retriggering, and
385	* (b) clean HC shutdown, when IAA watchdog was pending.
386	*/
387	if (ehci->reclaim
388	&& !timer_pending(&ehci->iaa_watchdog)
389	&& ehci->rh_state == EHCI_RH_RUNNING) {
390	u32 cmd, status;
391
392	/* If we get here, IAA is REALLY late. It's barely
393	* conceivable that the system is so busy that CMD_IAAD
394	* is still legitimately set, so let's be sure it's
395	* clear before we read STS_IAA. (The HC should clear
396	* CMD_IAAD when it sets STS_IAA.)
397	*/
398	cmd = ehci_readl(ehci, &ehci->regs->command);
399	if (cmd & CMD_IAAD)
400	ehci_writel(ehci, cmd & ~CMD_IAAD,
401	&ehci->regs->command);
402
403	/* If IAA is set here it either legitimately triggered
404	* before we cleared IAAD above (but _way_ late, so we'll
405	* still count it as lost) ... or a silicon erratum:
406	* - VIA seems to set IAA without triggering the IRQ;
407	* - IAAD potentially cleared without setting IAA.
408	*/
409	status = ehci_readl(ehci, &ehci->regs->status);
410	if ((status & STS_IAA) \|\| !(cmd & CMD_IAAD)) {
411	COUNT (ehci->stats.lost_iaa);
412	ehci_writel(ehci, STS_IAA, &ehci->regs->status);
413	}
414
415	ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
416	status, cmd);
417	end_unlink_async(ehci);
418	}
419
420	spin_unlock_irqrestore(&ehci->lock, flags);
421	}
422
423	static void ehci_watchdog(unsigned long param)
424	{
425	struct ehci_hcd ehci = (struct ehci_hcd ) param;
426	unsigned long flags;
427
428	spin_lock_irqsave(&ehci->lock, flags);
429
430	/* stop async processing after it's idled a bit */
431	if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
432	start_unlink_async (ehci, ehci->async);
433
434	/* ehci could run by timer, without IRQs ... */
435	ehci_work (ehci);
436
437	spin_unlock_irqrestore (&ehci->lock, flags);
438	}
439
440	/* On some systems, leaving remote wakeup enabled prevents system shutdown.
441	* The firmware seems to think that powering off is a wakeup event!
442	* This routine turns off remote wakeup and everything else, on all ports.
443	*/
444	static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
445	{
446	int port = HCS_N_PORTS(ehci->hcs_params);
447
448	while (port--)
449	ehci_writel(ehci, PORT_RWC_BITS,
450	&ehci->regs->port_status[port]);
451	}
452
453	/*
454	* Halt HC, turn off all ports, and let the BIOS use the companion controllers.
455	* Should be called with ehci->lock held.
456	*/
457	static void ehci_silence_controller(struct ehci_hcd *ehci)
458	{
459	ehci_halt(ehci);
460	ehci_turn_off_all_ports(ehci);
461
462	/* make BIOS/etc use companion controller during reboot */
463	ehci_writel(ehci, 0, &ehci->regs->configured_flag);
464
465	/* unblock posted writes */
466	ehci_readl(ehci, &ehci->regs->configured_flag);
467	}
468
469	/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
470	* This forcibly disables dma and IRQs, helping kexec and other cases
471	* where the next system software may expect clean state.
472	*/
473	static void ehci_shutdown(struct usb_hcd *hcd)
474	{
475	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
476
477	del_timer_sync(&ehci->watchdog);
478	del_timer_sync(&ehci->iaa_watchdog);
479
480	spin_lock_irq(&ehci->lock);
481	ehci_silence_controller(ehci);
482	spin_unlock_irq(&ehci->lock);
483	}
484
485	static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
486	{
487	unsigned port;
488
489	if (!HCS_PPC (ehci->hcs_params))
490	return;
491
492	ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
493	for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
494	(void) ehci_hub_control(ehci_to_hcd(ehci),
495	is_on ? SetPortFeature : ClearPortFeature,
496	USB_PORT_FEAT_POWER,
497	port--, NULL, 0);
498	/* Flush those writes */
499	ehci_readl(ehci, &ehci->regs->command);
500	msleep(20);
501	}
502
503	/-------------------------------------------------------------------------/
504
505	/*
506	* ehci_work is called from some interrupts, timers, and so on.
507	* it calls driver completion functions, after dropping ehci->lock.
508	*/
509	static void ehci_work (struct ehci_hcd *ehci)
510	{
511	timer_action_done (ehci, TIMER_IO_WATCHDOG);
512
513	/* another CPU may drop ehci->lock during a schedule scan while
514	* it reports urb completions. this flag guards against bogus
515	* attempts at re-entrant schedule scanning.
516	*/
517	if (ehci->scanning)
518	return;
519	ehci->scanning = 1;
520	scan_async (ehci);
521	if (ehci->next_uframe != -1)
522	scan_periodic (ehci);
523	ehci->scanning = 0;
524
525	/* the IO watchdog guards against hardware or driver bugs that
526	* misplace IRQs, and should let us run completely without IRQs.
527	* such lossage has been observed on both VT6202 and VT8235.
528	*/
529	if (ehci->rh_state == EHCI_RH_RUNNING &&
530	(ehci->async->qh_next.ptr != NULL \|\|
531	ehci->periodic_sched != 0))
532	timer_action (ehci, TIMER_IO_WATCHDOG);
533	}
534
535	/*
536	* Called when the ehci_hcd module is removed.
537	*/
538	static void ehci_stop (struct usb_hcd *hcd)
539	{
540	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
541
542	ehci_dbg (ehci, "stop\n");
543
544	/* no more interrupts ... */
545	del_timer_sync (&ehci->watchdog);
546	del_timer_sync(&ehci->iaa_watchdog);
547
548	spin_lock_irq(&ehci->lock);
549	if (ehci->rh_state == EHCI_RH_RUNNING)
550	ehci_quiesce (ehci);
551
552	ehci_silence_controller(ehci);
553	ehci_reset (ehci);
554	spin_unlock_irq(&ehci->lock);
555
556	remove_sysfs_files(ehci);
557	remove_debug_files (ehci);
558
559	/* root hub is shut down separately (first, when possible) */
560	spin_lock_irq (&ehci->lock);
561	if (ehci->async)
562	ehci_work (ehci);
563	spin_unlock_irq (&ehci->lock);
564	ehci_mem_cleanup (ehci);
565
566	if (ehci->amd_pll_fix == 1)
567	usb_amd_dev_put();
568
569	#ifdef EHCI_STATS
570	ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
571	ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
572	ehci->stats.lost_iaa);
573	ehci_dbg (ehci, "complete %ld unlink %ld\n",
574	ehci->stats.complete, ehci->stats.unlink);
575	#endif
576
577	dbg_status (ehci, "ehci_stop completed",
578	ehci_readl(ehci, &ehci->regs->status));
579	}
580
581	/* one-time init, only for memory state */
582	static int ehci_init(struct usb_hcd *hcd)
583	{
584	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
585	u32 temp;
586	int retval;
587	u32 hcc_params;
588	struct ehci_qh_hw *hw;
589
590	spin_lock_init(&ehci->lock);
591
592	/*
593	* keep io watchdog by default, those good HCDs could turn off it later
594	*/
595	ehci->need_io_watchdog = 1;
596	init_timer(&ehci->watchdog);
597	ehci->watchdog.function = ehci_watchdog;
598	ehci->watchdog.data = (unsigned long) ehci;
599
600	init_timer(&ehci->iaa_watchdog);
601	ehci->iaa_watchdog.function = ehci_iaa_watchdog;
602	ehci->iaa_watchdog.data = (unsigned long) ehci;
603
604	hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
605
606	/*
607	* by default set standard 80% (== 100 usec/uframe) max periodic
608	* bandwidth as required by USB 2.0
609	*/
610	ehci->uframe_periodic_max = 100;
611
612	/*
613	* hw default: 1K periodic list heads, one per frame.
614	* periodic_size can shrink by USBCMD update if hcc_params allows.
615	*/
616	ehci->periodic_size = DEFAULT_I_TDPS;
617	INIT_LIST_HEAD(&ehci->cached_itd_list);
618	INIT_LIST_HEAD(&ehci->cached_sitd_list);
619
620	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
621	/* periodic schedule size can be smaller than default */
622	switch (EHCI_TUNE_FLS) {
623	case 0: ehci->periodic_size = 1024; break;
624	case 1: ehci->periodic_size = 512; break;
625	case 2: ehci->periodic_size = 256; break;
626	default: BUG();
627	}
628	}
629	if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
630	return retval;
631
632	/* controllers may cache some of the periodic schedule ... */
633	if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
634	ehci->i_thresh = 2 + 8;
635	else // N microframes cached
636	ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
637
638	ehci->reclaim = NULL;
639	ehci->next_uframe = -1;
640	ehci->clock_frame = -1;
641
642	/*
643	* dedicate a qh for the async ring head, since we couldn't unlink
644	* a 'real' qh without stopping the async schedule [4.8]. use it
645	* as the 'reclamation list head' too.
646	* its dummy is used in hw_alt_next of many tds, to prevent the qh
647	* from automatically advancing to the next td after short reads.
648	*/
649	ehci->async->qh_next.qh = NULL;
650	hw = ehci->async->hw;
651	hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
652	hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
653	hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
654	hw->hw_qtd_next = EHCI_LIST_END(ehci);
655	ehci->async->qh_state = QH_STATE_LINKED;
656	hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
657
658	/* clear interrupt enables, set irq latency */
659	if (log2_irq_thresh < 0 \|\| log2_irq_thresh > 6)
660	log2_irq_thresh = 0;
661	temp = 1 << (16 + log2_irq_thresh);
662	if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
663	ehci->has_ppcd = 1;
664	ehci_dbg(ehci, "enable per-port change event\n");
665	temp \|= CMD_PPCEE;
666	}
667	if (HCC_CANPARK(hcc_params)) {
668	/* HW default park == 3, on hardware that supports it (like
669	* NVidia and ALI silicon), maximizes throughput on the async
670	* schedule by avoiding QH fetches between transfers.
671	*
672	* With fast usb storage devices and NForce2, "park" seems to
673	* make problems: throughput reduction (!), data errors...
674	*/
675	if (park) {
676	park = min(park, (unsigned) 3);
677	temp \|= CMD_PARK;
678	temp \|= park << 8;
679	}
680	ehci_dbg(ehci, "park %d\n", park);
681	}
682	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
683	/* periodic schedule size can be smaller than default */
684	temp &= ~(3 << 2);
685	temp \|= (EHCI_TUNE_FLS << 2);
686	}
687	if (HCC_LPM(hcc_params)) {
688	/* support link power management EHCI 1.1 addendum */
689	ehci_dbg(ehci, "support lpm\n");
690	ehci->has_lpm = 1;
691	if (hird > 0xf) {
692	ehci_dbg(ehci, "hird %d invalid, use default 0",
693	hird);
694	hird = 0;
695	}
696	temp \|= hird << 24;
697	}
698	ehci->command = temp;
699
700	/* Accept arbitrarily long scatter-gather lists */
701	if (!(hcd->driver->flags & HCD_LOCAL_MEM))
702	hcd->self.sg_tablesize = ~0;
703	return 0;
704	}
705
706	/* start HC running; it's halted, ehci_init() has been run (once) */
707	static int ehci_run (struct usb_hcd *hcd)
708	{
709	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
710	int retval;
711	u32 temp;
712	u32 hcc_params;
713
714	hcd->uses_new_polling = 1;
715
716	/* EHCI spec section 4.1 */
717	/*
718	* TDI driver does the ehci_reset in their reset callback.
719	* Don't reset here, because configuration settings will
720	* vanish.
721	*/
722	if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) {
723	ehci_mem_cleanup(ehci);
724	return retval;
725	}
726	ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
727	ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
728
729	/*
730	* hcc_params controls whether ehci->regs->segment must (!!!)
731	* be used; it constrains QH/ITD/SITD and QTD locations.
732	* pci_pool consistent memory always uses segment zero.
733	* streaming mappings for I/O buffers, like pci_map_single(),
734	* can return segments above 4GB, if the device allows.
735	*
736	* NOTE: the dma mask is visible through dma_supported(), so
737	* drivers can pass this info along ... like NETIF_F_HIGHDMA,
738	* Scsi_Host.highmem_io, and so forth. It's readonly to all
739	* host side drivers though.
740	*/
741	hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
742	if (HCC_64BIT_ADDR(hcc_params)) {
743	ehci_writel(ehci, 0, &ehci->regs->segment);
744	#if 0
745	// this is deeply broken on almost all architectures
746	if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
747	ehci_info(ehci, "enabled 64bit DMA\n");
748	#endif
749	}
750
751
752	// Philips, Intel, and maybe others need CMD_RUN before the
753	// root hub will detect new devices (why?); NEC doesn't
754	ehci->command &= ~(CMD_LRESET\|CMD_IAAD\|CMD_PSE\|CMD_ASE\|CMD_RESET);
755	ehci->command \|= CMD_RUN;
756	ehci_writel(ehci, ehci->command, &ehci->regs->command);
757	dbg_cmd (ehci, "init", ehci->command);
758
759	/*
760	* Start, enabling full USB 2.0 functionality ... usb 1.1 devices
761	* are explicitly handed to companion controller(s), so no TT is
762	* involved with the root hub. (Except where one is integrated,
763	* and there's no companion controller unless maybe for USB OTG.)
764	*
765	* Turning on the CF flag will transfer ownership of all ports
766	* from the companions to the EHCI controller. If any of the
767	* companions are in the middle of a port reset at the time, it
768	* could cause trouble. Write-locking ehci_cf_port_reset_rwsem
769	* guarantees that no resets are in progress. After we set CF,
770	* a short delay lets the hardware catch up; new resets shouldn't
771	* be started before the port switching actions could complete.
772	*/
773	down_write(&ehci_cf_port_reset_rwsem);
774	ehci->rh_state = EHCI_RH_RUNNING;
775	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
776	ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
777	msleep(5);
778	up_write(&ehci_cf_port_reset_rwsem);
779	ehci->last_periodic_enable = ktime_get_real();
780
781	temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
782	ehci_info (ehci,
783	"USB %x.%x started, EHCI %x.%02x%s\n",
784	((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
785	temp >> 8, temp & 0xff,
786	ignore_oc ? ", overcurrent ignored" : "");
787
788	ehci_writel(ehci, INTR_MASK,
789	&ehci->regs->intr_enable); /* Turn On Interrupts */
790
791	/* GRR this is run-once init(), being done every time the HC starts.
792	* So long as they're part of class devices, we can't do it init()
793	* since the class device isn't created that early.
794	*/
795	create_debug_files(ehci);
796	create_sysfs_files(ehci);
797
798	return 0;
799	}
800
801	static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
802	{
803	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
804	int retval;
805
806	ehci->regs = (void __iomem *)ehci->caps +
807	HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
808	dbg_hcs_params(ehci, "reset");
809	dbg_hcc_params(ehci, "reset");
810
811	/* cache this readonly data; minimize chip reads */
812	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
813
814	ehci->sbrn = HCD_USB2;
815
816	retval = ehci_halt(ehci);
817	if (retval)
818	return retval;
819
820	/* data structure init */
821	retval = ehci_init(hcd);
822	if (retval)
823	return retval;
824
825	ehci_reset(ehci);
826
827	return 0;
828	}
829
830	/-------------------------------------------------------------------------/
831
832	static irqreturn_t ehci_irq (struct usb_hcd *hcd)
833	{
834	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
835	u32 status, masked_status, pcd_status = 0, cmd;
836	int bh;
837
838	spin_lock (&ehci->lock);
839
840	status = ehci_readl(ehci, &ehci->regs->status);
841
842	/* e.g. cardbus physical eject */
843	if (status == ~(u32) 0) {
844	ehci_dbg (ehci, "device removed\n");
845	goto dead;
846	}
847
848	/* Shared IRQ? */
849	masked_status = status & INTR_MASK;
850	if (!masked_status \|\| unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
851	spin_unlock(&ehci->lock);
852	return IRQ_NONE;
853	}
854
855	/* clear (just) interrupts */
856	ehci_writel(ehci, masked_status, &ehci->regs->status);
857	cmd = ehci_readl(ehci, &ehci->regs->command);
858	bh = 0;
859
860	#ifdef VERBOSE_DEBUG
861	/* unrequested/ignored: Frame List Rollover */
862	dbg_status (ehci, "irq", status);
863	#endif
864
865	/* INT, ERR, and IAA interrupt rates can be throttled */
866
867	/* normal [4.15.1.2] or error [4.15.1.1] completion */
868	if (likely ((status & (STS_INT\|STS_ERR)) != 0)) {
869	if (likely ((status & STS_ERR) == 0))
870	COUNT (ehci->stats.normal);
871	else
872	COUNT (ehci->stats.error);
873	bh = 1;
874	}
875
876	/* complete the unlinking of some qh [4.15.2.3] */
877	if (status & STS_IAA) {
878	/* guard against (alleged) silicon errata */
879	if (cmd & CMD_IAAD) {
880	ehci_writel(ehci, cmd & ~CMD_IAAD,
881	&ehci->regs->command);
882	ehci_dbg(ehci, "IAA with IAAD still set?\n");
883	}
884	if (ehci->reclaim) {
885	COUNT(ehci->stats.reclaim);
886	end_unlink_async(ehci);
887	} else
888	ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
889	}
890
891	/* remote wakeup [4.3.1] */
892	if (status & STS_PCD) {
893	unsigned i = HCS_N_PORTS (ehci->hcs_params);
894	u32 ppcd = 0;
895
896	/* kick root hub later */
897	pcd_status = status;
898
899	#ifdef CONFIG_WASP_SUPPORT
900	#define ath_reg_wr ar7240_reg_wr
901	#define ath_reg_rd ar7240_reg_rd
902
903	#define USB_PHY_CTRL5 0xb8116c94
904	if((ath_reg_rd(&ehci->regs->status) & STS_PCD) && (hcd->state != HC_STATE_SUSPENDED) && \
905	((1<<USB_PORT_STAT_HIGH_SPEED) == ehci_port_speed(ehci, ehci_readl(ehci, &ehci->regs->port_status [0])))) {
906	ath_reg_wr (USB_PHY_CTRL5, (ath_reg_rd(USB_PHY_CTRL5)\|((1<<17) \| (1<<22) \| (1<<23))) & (~((0x3<<18) \| (0x1<<20))));
907	ath_reg_wr (USB_PHY_CTRL5, (ath_reg_rd(USB_PHY_CTRL5)) & (~(1<<17)));
908	}
909	#endif
910
911	/* resume root hub? */
912	if (!(cmd & CMD_RUN))
913	usb_hcd_resume_root_hub(hcd);
914
915	/* get per-port change detect bits */
916	if (ehci->has_ppcd)
917	ppcd = status >> 16;
918
919	while (i--) {
920	int pstatus;
921
922	/* leverage per-port change bits feature */
923	if (ehci->has_ppcd && !(ppcd & (1 << i)))
924	continue;
925	pstatus = ehci_readl(ehci,
926	&ehci->regs->port_status[i]);
927
928	if (pstatus & PORT_OWNER)
929	continue;
930	if (!(test_bit(i, &ehci->suspended_ports) &&
931	((pstatus & PORT_RESUME) \|\|
932	!(pstatus & PORT_SUSPEND)) &&
933	(pstatus & PORT_PE) &&
934	ehci->reset_done[i] == 0))
935	continue;
936
937	/* start 20 msec resume signaling from this port,
938	* and make khubd collect PORT_STAT_C_SUSPEND to
939	* stop that signaling. Use 5 ms extra for safety,
940	* like usb_port_resume() does.
941	*/
942	ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
943	ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
944	mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
945	}
946	}
947
948	/* PCI errors [4.15.2.4] */
949	if (unlikely ((status & STS_FATAL) != 0)) {
950	ehci_err(ehci, "fatal error\n");
951	dbg_cmd(ehci, "fatal", cmd);
952	dbg_status(ehci, "fatal", status);
953	ehci_halt(ehci);
954	dead:
955	ehci_reset(ehci);
956	ehci_writel(ehci, 0, &ehci->regs->configured_flag);
957	usb_hc_died(hcd);
958	/* generic layer kills/unlinks all urbs, then
959	* uses ehci_stop to clean up the rest
960	*/
961	bh = 1;
962	}
963
964	if (bh)
965	ehci_work (ehci);
966	spin_unlock (&ehci->lock);
967	if (pcd_status)
968	usb_hcd_poll_rh_status(hcd);
969	return IRQ_HANDLED;
970	}
971
972	/-------------------------------------------------------------------------/
973
974	/*
975	* non-error returns are a promise to giveback() the urb later
976	* we drop ownership so next owner (or urb unlink) can get it
977	*
978	* urb + dev is in hcd.self.controller.urb_list
979	* we're queueing TDs onto software and hardware lists
980	*
981	* hcd-specific init for hcpriv hasn't been done yet
982	*
983	* NOTE: control, bulk, and interrupt share the same code to append TDs
984	* to a (possibly active) QH, and the same QH scanning code.
985	*/
986	static int ehci_urb_enqueue (
987	struct usb_hcd *hcd,
988	struct urb *urb,
989	gfp_t mem_flags
990	) {
991	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
992	struct list_head qtd_list;
993
994	INIT_LIST_HEAD (&qtd_list);
995
996	switch (usb_pipetype (urb->pipe)) {
997	case PIPE_CONTROL:
998	/* qh_completions() code doesn't handle all the fault cases
999	* in multi-TD control transfers. Even 1KB is rare anyway.
1000	*/
1001	if (urb->transfer_buffer_length > (16 * 1024))
1002	return -EMSGSIZE;
1003	/* FALLTHROUGH */
1004	/* case PIPE_BULK: */
1005	default:
1006	if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1007	return -ENOMEM;
1008	return submit_async(ehci, urb, &qtd_list, mem_flags);
1009
1010	case PIPE_INTERRUPT:
1011	if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1012	return -ENOMEM;
1013	return intr_submit(ehci, urb, &qtd_list, mem_flags);
1014
1015	case PIPE_ISOCHRONOUS:
1016	if (urb->dev->speed == USB_SPEED_HIGH)
1017	return itd_submit (ehci, urb, mem_flags);
1018	else
1019	return sitd_submit (ehci, urb, mem_flags);
1020	}
1021	}
1022
1023	static void unlink_async (struct ehci_hcd ehci, struct ehci_qh qh)
1024	{
1025	/* failfast */
1026	if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1027	end_unlink_async(ehci);
1028
1029	/* If the QH isn't linked then there's nothing we can do
1030	* unless we were called during a giveback, in which case
1031	* qh_completions() has to deal with it.
1032	*/
1033	if (qh->qh_state != QH_STATE_LINKED) {
1034	if (qh->qh_state == QH_STATE_COMPLETING)
1035	qh->needs_rescan = 1;
1036	return;
1037	}
1038
1039	/* defer till later if busy */
1040	if (ehci->reclaim) {
1041	struct ehci_qh *last;
1042
1043	for (last = ehci->reclaim;
1044	last->reclaim;
1045	last = last->reclaim)
1046	continue;
1047	qh->qh_state = QH_STATE_UNLINK_WAIT;
1048	last->reclaim = qh;
1049
1050	/* start IAA cycle */
1051	} else
1052	start_unlink_async (ehci, qh);
1053	}
1054
1055	/* remove from hardware lists
1056	* completions normally happen asynchronously
1057	*/
1058
1059	static int ehci_urb_dequeue(struct usb_hcd hcd, struct urb urb, int status)
1060	{
1061	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1062	struct ehci_qh *qh;
1063	unsigned long flags;
1064	int rc;
1065
1066	spin_lock_irqsave (&ehci->lock, flags);
1067	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1068	if (rc)
1069	goto done;
1070
1071	switch (usb_pipetype (urb->pipe)) {
1072	// case PIPE_CONTROL:
1073	// case PIPE_BULK:
1074	default:
1075	qh = (struct ehci_qh *) urb->hcpriv;
1076	if (!qh)
1077	break;
1078	switch (qh->qh_state) {
1079	case QH_STATE_LINKED:
1080	case QH_STATE_COMPLETING:
1081	unlink_async(ehci, qh);
1082	break;
1083	case QH_STATE_UNLINK:
1084	case QH_STATE_UNLINK_WAIT:
1085	/* already started */
1086	break;
1087	case QH_STATE_IDLE:
1088	/* QH might be waiting for a Clear-TT-Buffer */
1089	qh_completions(ehci, qh);
1090	break;
1091	}
1092	break;
1093
1094	case PIPE_INTERRUPT:
1095	qh = (struct ehci_qh *) urb->hcpriv;
1096	if (!qh)
1097	break;
1098	switch (qh->qh_state) {
1099	case QH_STATE_LINKED:
1100	case QH_STATE_COMPLETING:
1101	intr_deschedule (ehci, qh);
1102	break;
1103	case QH_STATE_IDLE:
1104	qh_completions (ehci, qh);
1105	break;
1106	default:
1107	ehci_dbg (ehci, "bogus qh %p state %d\n",
1108	qh, qh->qh_state);
1109	goto done;
1110	}
1111	break;
1112
1113	case PIPE_ISOCHRONOUS:
1114	// itd or sitd ...
1115
1116	// wait till next completion, do it then.
1117	// completion irqs can wait up to 1024 msec,
1118	break;
1119	}
1120	done:
1121	spin_unlock_irqrestore (&ehci->lock, flags);
1122	return rc;
1123	}
1124
1125	/-------------------------------------------------------------------------/
1126
1127	// bulk qh holds the data toggle
1128
1129	static void
1130	ehci_endpoint_disable (struct usb_hcd hcd, struct usb_host_endpoint ep)
1131	{
1132	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1133	unsigned long flags;
1134	struct ehci_qh qh, tmp;
1135
1136	/* ASSERT: any requests/urbs are being unlinked */
1137	/* ASSERT: nobody can be submitting urbs for this any more */
1138
1139	rescan:
1140	spin_lock_irqsave (&ehci->lock, flags);
1141	qh = ep->hcpriv;
1142	if (!qh)
1143	goto done;
1144
1145	/* endpoints can be iso streams. for now, we don't
1146	* accelerate iso completions ... so spin a while.
1147	*/
1148	if (qh->hw == NULL) {
1149	ehci_vdbg (ehci, "iso delay\n");
1150	goto idle_timeout;
1151	}
1152
1153	if (ehci->rh_state != EHCI_RH_RUNNING)
1154	qh->qh_state = QH_STATE_IDLE;
1155	switch (qh->qh_state) {
1156	case QH_STATE_LINKED:
1157	case QH_STATE_COMPLETING:
1158	for (tmp = ehci->async->qh_next.qh;
1159	tmp && tmp != qh;
1160	tmp = tmp->qh_next.qh)
1161	continue;
1162	/* periodic qh self-unlinks on empty, and a COMPLETING qh
1163	* may already be unlinked.
1164	*/
1165	if (tmp)
1166	unlink_async(ehci, qh);
1167	/* FALL THROUGH */
1168	case QH_STATE_UNLINK: /* wait for hw to finish? */
1169	case QH_STATE_UNLINK_WAIT:
1170	idle_timeout:
1171	spin_unlock_irqrestore (&ehci->lock, flags);
1172	schedule_timeout_uninterruptible(1);
1173	goto rescan;
1174	case QH_STATE_IDLE: /* fully unlinked */
1175	if (qh->clearing_tt)
1176	goto idle_timeout;
1177	if (list_empty (&qh->qtd_list)) {
1178	qh_put (qh);
1179	break;
1180	}
1181	/* else FALL THROUGH */
1182	default:
1183	/* caller was supposed to have unlinked any requests;
1184	* that's not our job. just leak this memory.
1185	*/
1186	ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1187	qh, ep->desc.bEndpointAddress, qh->qh_state,
1188	list_empty (&qh->qtd_list) ? "" : "(has tds)");
1189	break;
1190	}
1191	ep->hcpriv = NULL;
1192	done:
1193	spin_unlock_irqrestore (&ehci->lock, flags);
1194	}
1195
1196	static void
1197	ehci_endpoint_reset(struct usb_hcd hcd, struct usb_host_endpoint ep)
1198	{
1199	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1200	struct ehci_qh *qh;
1201	int eptype = usb_endpoint_type(&ep->desc);
1202	int epnum = usb_endpoint_num(&ep->desc);
1203	int is_out = usb_endpoint_dir_out(&ep->desc);
1204	unsigned long flags;
1205
1206	if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1207	return;
1208
1209	spin_lock_irqsave(&ehci->lock, flags);
1210	qh = ep->hcpriv;
1211
1212	/* For Bulk and Interrupt endpoints we maintain the toggle state
1213	* in the hardware; the toggle bits in udev aren't used at all.
1214	* When an endpoint is reset by usb_clear_halt() we must reset
1215	* the toggle bit in the QH.
1216	*/
1217	if (qh) {
1218	usb_settoggle(qh->dev, epnum, is_out, 0);
1219	if (!list_empty(&qh->qtd_list)) {
1220	WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1221	} else if (qh->qh_state == QH_STATE_LINKED \|\|
1222	qh->qh_state == QH_STATE_COMPLETING) {
1223
1224	/* The toggle value in the QH can't be updated
1225	* while the QH is active. Unlink it now;
1226	* re-linking will call qh_refresh().
1227	*/
1228	if (eptype == USB_ENDPOINT_XFER_BULK)
1229	unlink_async(ehci, qh);
1230	else
1231	intr_deschedule(ehci, qh);
1232	}
1233	}
1234	spin_unlock_irqrestore(&ehci->lock, flags);
1235	}
1236
1237	static int ehci_get_frame (struct usb_hcd *hcd)
1238	{
1239	struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1240	return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1241	}
1242
1243	/-------------------------------------------------------------------------/
1244
1245	MODULE_DESCRIPTION(DRIVER_DESC);
1246	MODULE_AUTHOR (DRIVER_AUTHOR);
1247	MODULE_LICENSE ("GPL");
1248
1249	#ifdef CONFIG_PCI
1250	#include "ehci-pci.c"
1251	#define PCI_DRIVER ehci_pci_driver
1252	#endif
1253
1254	#ifdef CONFIG_USB_EHCI_FSL
1255	#include "ehci-fsl.c"
1256	#define PLATFORM_DRIVER ehci_fsl_driver
1257	#endif
1258
1259	#ifdef CONFIG_USB_EHCI_MXC
1260	#include "ehci-mxc.c"
1261	#define PLATFORM_DRIVER ehci_mxc_driver
1262	#endif
1263
1264	#ifdef CONFIG_USB_EHCI_SH
1265	#include "ehci-sh.c"
1266	#define PLATFORM_DRIVER ehci_hcd_sh_driver
1267	#endif
1268
1269	#ifdef CONFIG_MIPS_ALCHEMY
1270	#include "ehci-au1xxx.c"
1271	#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1272	#endif
1273
1274	#ifdef CONFIG_USB_EHCI_HCD_OMAP
1275	#include "ehci-omap.c"
1276	#define PLATFORM_DRIVER ehci_hcd_omap_driver
1277	#endif
1278
1279	#ifdef CONFIG_PPC_PS3
1280	#include "ehci-ps3.c"
1281	#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1282	#endif
1283
1284	#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1285	#include "ehci-ppc-of.c"
1286	#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1287	#endif
1288
1289	#ifdef CONFIG_XPS_USB_HCD_XILINX
1290	#include "ehci-xilinx-of.c"
1291	#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1292	#endif
1293
1294	#ifdef CONFIG_PLAT_ORION
1295	#include "ehci-orion.c"
1296	#define PLATFORM_DRIVER ehci_orion_driver
1297	#endif
1298
1299	#ifdef CONFIG_ARCH_IXP4XX
1300	#include "ehci-ixp4xx.c"
1301	#define PLATFORM_DRIVER ixp4xx_ehci_driver
1302	#endif
1303
1304	#ifdef CONFIG_USB_W90X900_EHCI
1305	#include "ehci-w90x900.c"
1306	#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1307	#endif
1308
1309	#ifdef CONFIG_ARCH_AT91
1310	#include "ehci-atmel.c"
1311	#define PLATFORM_DRIVER ehci_atmel_driver
1312	#endif
1313
1314	#ifdef CONFIG_USB_OCTEON_EHCI
1315	#include "ehci-octeon.c"
1316	#define PLATFORM_DRIVER ehci_octeon_driver
1317	#endif
1318
1319	#ifdef CONFIG_USB_CNS3XXX_EHCI
1320	#include "ehci-cns3xxx.c"
1321	#define PLATFORM_DRIVER cns3xxx_ehci_driver
1322	#endif
1323
1324	#ifdef CONFIG_ARCH_VT8500
1325	#include "ehci-vt8500.c"
1326	#define PLATFORM_DRIVER vt8500_ehci_driver
1327	#endif
1328
1329	#ifdef CONFIG_PLAT_SPEAR
1330	#include "ehci-spear.c"
1331	#define PLATFORM_DRIVER spear_ehci_hcd_driver
1332	#endif
1333
1334	#ifdef CONFIG_USB_EHCI_MSM
1335	#include "ehci-msm.c"
1336	#define PLATFORM_DRIVER ehci_msm_driver
1337	#endif
1338
1339	#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1340	#include "ehci-pmcmsp.c"
1341	#define PLATFORM_DRIVER ehci_hcd_msp_driver
1342	#endif
1343
1344	#ifdef CONFIG_USB_EHCI_TEGRA
1345	#include "ehci-tegra.c"
1346	#define PLATFORM_DRIVER tegra_ehci_driver
1347	#endif
1348
1349	#ifdef CONFIG_USB_EHCI_S5P
1350	#include "ehci-s5p.c"
1351	#define PLATFORM_DRIVER s5p_ehci_driver
1352	#endif
1353
1354	#ifdef CONFIG_USB_EHCI_ATH79
1355	#include "ehci-ath79.c"
1356	#define PLATFORM_DRIVER ehci_ath79_driver
1357	#endif
1358
1359	#ifdef CONFIG_SPARC_LEON
1360	#include "ehci-grlib.c"
1361	#define PLATFORM_DRIVER ehci_grlib_driver
1362	#endif
1363
1364	#ifdef CONFIG_USB_PXA168_EHCI
1365	#include "ehci-pxa168.c"
1366	#define PLATFORM_DRIVER ehci_pxa168_driver
1367	#endif
1368
1369	#ifdef CONFIG_NLM_XLR
1370	#include "ehci-xls.c"
1371	#define PLATFORM_DRIVER ehci_xls_driver
1372	#endif
1373
1374	#ifdef CONFIG_USB_EHCI_AR9130
1375	#include "ehci-ar71xx.c"
1376	#define PLATFORM_DRIVER ehci_ar71xx_driver
1377	#endif
1378
1379	#ifdef CONFIG_USB_EHCI_AR7100
1380	#include "ehci-ar71xx.c"
1381	#define PLATFORM_DRIVER ehci_ar71xx_driver
1382	#endif
1383
1384	#if defined (CONFIG_RT3XXX_EHCI) \|\| defined (CONFIG_RT3XXX_EHCI_MODULE)
1385	#include "ehci-rt3xxx.c"
1386	#define PLATFORM_DRIVER rt3xxx_ehci_driver
1387	#endif
1388
1389
1390	#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1391	!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1392	!defined(XILINX_OF_PLATFORM_DRIVER)
1393	#error "missing bus glue for ehci-hcd"
1394	#endif
1395
1396	static int __init ehci_hcd_init(void)
1397	{
1398	int retval = 0;
1399
1400	if (usb_disabled())
1401	return -ENODEV;
1402
1403	printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1404	set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1405	if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) \|\|
1406	test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1407	printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1408	" before uhci_hcd and ohci_hcd, not after\n");
1409
1410	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1411	hcd_name,
1412	sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1413	sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1414
1415	#ifdef DEBUG
1416	ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1417	if (!ehci_debug_root) {
1418	retval = -ENOENT;
1419	goto err_debug;
1420	}
1421	#endif
1422
1423	#ifdef PLATFORM_DRIVER
1424	retval = platform_driver_register(&PLATFORM_DRIVER);
1425	if (retval < 0)
1426	goto clean0;
1427	#endif
1428
1429	#ifdef PCI_DRIVER
1430	retval = pci_register_driver(&PCI_DRIVER);
1431	if (retval < 0)
1432	goto clean1;
1433	#endif
1434
1435	#ifdef PS3_SYSTEM_BUS_DRIVER
1436	retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1437	if (retval < 0)
1438	goto clean2;
1439	#endif
1440
1441	#ifdef OF_PLATFORM_DRIVER
1442	retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1443	if (retval < 0)
1444	goto clean3;
1445	#endif
1446
1447	#ifdef XILINX_OF_PLATFORM_DRIVER
1448	retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1449	if (retval < 0)
1450	goto clean4;
1451	#endif
1452	return retval;
1453
1454	#ifdef XILINX_OF_PLATFORM_DRIVER
1455	/* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1456	clean4:
1457	#endif
1458	#ifdef OF_PLATFORM_DRIVER
1459	platform_driver_unregister(&OF_PLATFORM_DRIVER);
1460	clean3:
1461	#endif
1462	#ifdef PS3_SYSTEM_BUS_DRIVER
1463	ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1464	clean2:
1465	#endif
1466	#ifdef PCI_DRIVER
1467	pci_unregister_driver(&PCI_DRIVER);
1468	clean1:
1469	#endif
1470	#ifdef PLATFORM_DRIVER
1471	platform_driver_unregister(&PLATFORM_DRIVER);
1472	clean0:
1473	#endif
1474	#ifdef DEBUG
1475	debugfs_remove(ehci_debug_root);
1476	ehci_debug_root = NULL;
1477	err_debug:
1478	#endif
1479	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1480	return retval;
1481	}
1482	module_init(ehci_hcd_init);
1483
1484	static void __exit ehci_hcd_cleanup(void)
1485	{
1486	#ifdef XILINX_OF_PLATFORM_DRIVER
1487	platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1488	#endif
1489	#ifdef OF_PLATFORM_DRIVER
1490	platform_driver_unregister(&OF_PLATFORM_DRIVER);
1491	#endif
1492	#ifdef PLATFORM_DRIVER
1493	platform_driver_unregister(&PLATFORM_DRIVER);
1494	#endif
1495	#ifdef PCI_DRIVER
1496	pci_unregister_driver(&PCI_DRIVER);
1497	#endif
1498	#ifdef PS3_SYSTEM_BUS_DRIVER
1499	ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1500	#endif
1501	#ifdef DEBUG
1502	debugfs_remove(ehci_debug_root);
1503	#endif
1504	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1505	}
1506	module_exit(ehci_hcd_cleanup);
1507

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