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source: src/linux/universal/linux-3.3/drivers/tty/serial/8250/8250.c @ 19073

Last change on this file since 19073 was 19073, checked in by BrainSlayer, 13 months ago
kernel update
File size: 84.2 KB

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1	/*
2	* Driver for 8250/16550-type serial ports
3	*
4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5	*
6	* Copyright (C) 2001 Russell King.
7	*
8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License as published by
10	* the Free Software Foundation; either version 2 of the License, or
11	* (at your option) any later version.
12	*
13	* A note about mapbase / membase
14	*
15	* mapbase is the physical address of the IO port.
16	* membase is an 'ioremapped' cookie.
17	*/
18
19	#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20	#define SUPPORT_SYSRQ
21	#endif
22
23	#include <linux/module.h>
24	#include <linux/moduleparam.h>
25	#include <linux/ioport.h>
26	#include <linux/init.h>
27	#include <linux/console.h>
28	#include <linux/sysrq.h>
29	#include <linux/delay.h>
30	#include <linux/platform_device.h>
31	#include <linux/tty.h>
32	#include <linux/ratelimit.h>
33	#include <linux/tty_flip.h>
34	#include <linux/serial_reg.h>
35	#include <linux/serial_core.h>
36	#include <linux/serial.h>
37	#include <linux/serial_8250.h>
38	#include <linux/nmi.h>
39	#include <linux/mutex.h>
40	#include <linux/slab.h>
41
42	#include <asm/io.h>
43	#include <asm/irq.h>
44
45	#include "8250.h"
46
47	#ifdef CONFIG_SPARC
48	#include "../suncore.h"
49	#endif
50
51	/*
52	* Configuration:
53	* share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54	* is unsafe when used on edge-triggered interrupts.
55	*/
56	static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58	static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60	static struct uart_driver serial8250_reg;
61
62	static int serial_index(struct uart_port *port)
63	{
64	return (serial8250_reg.minor - 64) + port->line;
65	}
66
67	static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69	/*
70	* Debugging.
71	*/
72	#if 0
73	#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74	#else
75	#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76	#endif
77
78	#if 0
79	#define DEBUG_INTR(fmt...) printk(fmt)
80	#else
81	#define DEBUG_INTR(fmt...) do { } while (0)
82	#endif
83
84	#define PASS_LIMIT 512
85
86	#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)
87
88
89	/*
90	* We default to IRQ0 for the "no irq" hack. Some
91	* machine types want others as well - they're free
92	* to redefine this in their header file.
93	*/
94	#define is_real_interrupt(irq) ((irq) != 0)
95
96	#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97	#define CONFIG_SERIAL_DETECT_IRQ 1
98	#endif
99	#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100	#define CONFIG_SERIAL_MANY_PORTS 1
101	#endif
102
103	/*
104	* HUB6 is always on. This will be removed once the header
105	* files have been cleaned.
106	*/
107	#define CONFIG_HUB6 1
108
109	#include <asm/serial.h>
110	/*
111	* SERIAL_PORT_DFNS tells us about built-in ports that have no
112	* standard enumeration mechanism. Platforms that can find all
113	* serial ports via mechanisms like ACPI or PCI need not supply it.
114	*/
115	#ifndef SERIAL_PORT_DFNS
116	#define SERIAL_PORT_DFNS
117	#endif
118
119	static const struct old_serial_port old_serial_port[] = {
120	SERIAL_PORT_DFNS /* defined in asm/serial.h */
121	};
122
123	#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125	#ifdef CONFIG_SERIAL_8250_RSA
126
127	#define PORT_RSA_MAX 4
128	static unsigned long probe_rsa[PORT_RSA_MAX];
129	static unsigned int probe_rsa_count;
130	#endif /* CONFIG_SERIAL_8250_RSA */
131
132	struct irq_info {
133	struct hlist_node node;
134	int irq;
135	spinlock_t lock; /* Protects list not the hash */
136	struct list_head *head;
137	};
138
139	#define NR_IRQ_HASH 32 /* Can be adjusted later */
140	static struct hlist_head irq_lists[NR_IRQ_HASH];
141	static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
142
143	/*
144	* Here we define the default xmit fifo size used for each type of UART.
145	*/
146	static const struct serial8250_config uart_config[] = {
147	[PORT_UNKNOWN] = {
148	.name = "unknown",
149	.fifo_size = 1,
150	.tx_loadsz = 1,
151	},
152	[PORT_8250] = {
153	.name = "8250",
154	.fifo_size = 1,
155	.tx_loadsz = 1,
156	},
157	[PORT_16450] = {
158	.name = "16450",
159	.fifo_size = 1,
160	.tx_loadsz = 1,
161	},
162	[PORT_16550] = {
163	.name = "16550",
164	.fifo_size = 1,
165	.tx_loadsz = 1,
166	},
167	[PORT_16550A] = {
168	.name = "16550A",
169	.fifo_size = 16,
170	.tx_loadsz = 16,
171	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
172	.flags = UART_CAP_FIFO,
173	},
174	[PORT_CIRRUS] = {
175	.name = "Cirrus",
176	.fifo_size = 1,
177	.tx_loadsz = 1,
178	},
179	[PORT_16650] = {
180	.name = "ST16650",
181	.fifo_size = 1,
182	.tx_loadsz = 1,
183	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
184	},
185	[PORT_16650V2] = {
186	.name = "ST16650V2",
187	.fifo_size = 32,
188	.tx_loadsz = 16,
189	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
190	UART_FCR_T_TRIG_00,
191	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
192	},
193	[PORT_16750] = {
194	.name = "TI16750",
195	.fifo_size = 64,
196	.tx_loadsz = 64,
197	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10 \|
198	UART_FCR7_64BYTE,
199	.flags = UART_CAP_FIFO \| UART_CAP_SLEEP \| UART_CAP_AFE,
200	},
201	[PORT_STARTECH] = {
202	.name = "Startech",
203	.fifo_size = 1,
204	.tx_loadsz = 1,
205	},
206	[PORT_16C950] = {
207	.name = "16C950/954",
208	.fifo_size = 128,
209	.tx_loadsz = 128,
210	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
211	/* UART_CAP_EFR breaks billionon CF bluetooth card. */
212	.flags = UART_CAP_FIFO \| UART_CAP_SLEEP,
213	},
214	[PORT_16654] = {
215	.name = "ST16654",
216	.fifo_size = 64,
217	.tx_loadsz = 32,
218	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
219	UART_FCR_T_TRIG_10,
220	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
221	},
222	[PORT_16850] = {
223	.name = "XR16850",
224	.fifo_size = 128,
225	.tx_loadsz = 128,
226	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
227	.flags = UART_CAP_FIFO \| UART_CAP_EFR \| UART_CAP_SLEEP,
228	},
229	[PORT_RSA] = {
230	.name = "RSA",
231	.fifo_size = 2048,
232	.tx_loadsz = 2048,
233	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_11,
234	.flags = UART_CAP_FIFO,
235	},
236	[PORT_NS16550A] = {
237	.name = "NS16550A",
238	.fifo_size = 16,
239	.tx_loadsz = 16,
240	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
241	.flags = UART_CAP_FIFO \| UART_NATSEMI,
242	},
243	[PORT_XSCALE] = {
244	.name = "XScale",
245	.fifo_size = 32,
246	.tx_loadsz = 32,
247	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
248	.flags = UART_CAP_FIFO \| UART_CAP_UUE \| UART_CAP_RTOIE,
249	},
250	[PORT_RM9000] = {
251	.name = "RM9000",
252	.fifo_size = 16,
253	.tx_loadsz = 16,
254	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
255	.flags = UART_CAP_FIFO,
256	},
257	[PORT_OCTEON] = {
258	.name = "OCTEON",
259	.fifo_size = 64,
260	.tx_loadsz = 64,
261	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
262	.flags = UART_CAP_FIFO,
263	},
264	[PORT_AR7] = {
265	.name = "AR7",
266	.fifo_size = 16,
267	.tx_loadsz = 16,
268	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_00,
269	.flags = UART_CAP_FIFO \| UART_CAP_AFE,
270	},
271	[PORT_U6_16550A] = {
272	.name = "U6_16550A",
273	.fifo_size = 64,
274	.tx_loadsz = 64,
275	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
276	.flags = UART_CAP_FIFO \| UART_CAP_AFE,
277	},
278	[PORT_TEGRA] = {
279	.name = "Tegra",
280	.fifo_size = 32,
281	.tx_loadsz = 8,
282	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_01 \|
283	UART_FCR_T_TRIG_01,
284	.flags = UART_CAP_FIFO \| UART_CAP_RTOIE,
285	},
286	[PORT_XR17D15X] = {
287	.name = "XR17D15X",
288	.fifo_size = 64,
289	.tx_loadsz = 64,
290	.fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_R_TRIG_10,
291	.flags = UART_CAP_FIFO \| UART_CAP_AFE \| UART_CAP_EFR,
292	},
293	};
294
295	#if defined(CONFIG_MIPS_ALCHEMY) \|\| defined (CONFIG_SERIAL_8250_RT288X)
296
297	/* Au1x00 and RT288x UART hardware has a weird register layout */
298	static const u8 au_io_in_map[] = {
299	[UART_RX] = 0,
300	[UART_IER] = 2,
301	[UART_IIR] = 3,
302	[UART_LCR] = 5,
303	[UART_MCR] = 6,
304	[UART_LSR] = 7,
305	[UART_MSR] = 8,
306	};
307
308	static const u8 au_io_out_map[] = {
309	[UART_TX] = 1,
310	[UART_IER] = 2,
311	[UART_FCR] = 4,
312	[UART_LCR] = 5,
313	[UART_MCR] = 6,
314	};
315
316	/* sane hardware needs no mapping */
317	static inline int map_8250_in_reg(struct uart_port *p, int offset)
318	{
319	if (p->iotype != UPIO_AU)
320	return offset;
321	return au_io_in_map[offset];
322	}
323
324	static inline int map_8250_out_reg(struct uart_port *p, int offset)
325	{
326	if (p->iotype != UPIO_AU)
327	return offset;
328	return au_io_out_map[offset];
329	}
330
331	#elif defined(CONFIG_SERIAL_8250_RM9K)
332
333	static const u8
334	regmap_in[8] = {
335	[UART_RX] = 0x00,
336	[UART_IER] = 0x0c,
337	[UART_IIR] = 0x14,
338	[UART_LCR] = 0x1c,
339	[UART_MCR] = 0x20,
340	[UART_LSR] = 0x24,
341	[UART_MSR] = 0x28,
342	[UART_SCR] = 0x2c
343	},
344	regmap_out[8] = {
345	[UART_TX] = 0x04,
346	[UART_IER] = 0x0c,
347	[UART_FCR] = 0x18,
348	[UART_LCR] = 0x1c,
349	[UART_MCR] = 0x20,
350	[UART_LSR] = 0x24,
351	[UART_MSR] = 0x28,
352	[UART_SCR] = 0x2c
353	};
354
355	static inline int map_8250_in_reg(struct uart_port *p, int offset)
356	{
357	if (p->iotype != UPIO_RM9000)
358	return offset;
359	return regmap_in[offset];
360	}
361
362	static inline int map_8250_out_reg(struct uart_port *p, int offset)
363	{
364	if (p->iotype != UPIO_RM9000)
365	return offset;
366	return regmap_out[offset];
367	}
368
369	#else
370
371	/* sane hardware needs no mapping */
372	#define map_8250_in_reg(up, offset) (offset)
373	#define map_8250_out_reg(up, offset) (offset)
374
375	#endif
376
377	static unsigned int hub6_serial_in(struct uart_port *p, int offset)
378	{
379	offset = map_8250_in_reg(p, offset) << p->regshift;
380	outb(p->hub6 - 1 + offset, p->iobase);
381	return inb(p->iobase + 1);
382	}
383
384	static void hub6_serial_out(struct uart_port *p, int offset, int value)
385	{
386	offset = map_8250_out_reg(p, offset) << p->regshift;
387	outb(p->hub6 - 1 + offset, p->iobase);
388	outb(value, p->iobase + 1);
389	}
390
391	static unsigned int mem_serial_in(struct uart_port *p, int offset)
392	{
393	offset = map_8250_in_reg(p, offset) << p->regshift;
394	return readb(p->membase + offset);
395	}
396
397	static void mem_serial_out(struct uart_port *p, int offset, int value)
398	{
399	offset = map_8250_out_reg(p, offset) << p->regshift;
400	writeb(value, p->membase + offset);
401	}
402
403	static unsigned int memdelay_serial_in(struct uart_port *p, int offset)
404	{
405	struct uart_8250_port up = (struct uart_8250_port )p;
406	udelay(up->port.rw_delay);
407	return mem_serial_in(p, offset);
408	}
409
410	static void memdelay_serial_out(struct uart_port *p, int offset, int value)
411	{
412	struct uart_8250_port up = (struct uart_8250_port )p;
413	udelay(up->port.rw_delay);
414	mem_serial_out(p, offset, value);
415	}
416
417	static void mem32_serial_out(struct uart_port *p, int offset, int value)
418	{
419	offset = map_8250_out_reg(p, offset) << p->regshift;
420	writel(value, p->membase + offset);
421	}
422
423	static unsigned int mem32_serial_in(struct uart_port *p, int offset)
424	{
425	offset = map_8250_in_reg(p, offset) << p->regshift;
426	return readl(p->membase + offset);
427	}
428
429	static unsigned int au_serial_in(struct uart_port *p, int offset)
430	{
431	offset = map_8250_in_reg(p, offset) << p->regshift;
432	return __raw_readl(p->membase + offset);
433	}
434
435	static void au_serial_out(struct uart_port *p, int offset, int value)
436	{
437	offset = map_8250_out_reg(p, offset) << p->regshift;
438	__raw_writel(value, p->membase + offset);
439	}
440
441	static unsigned int io_serial_in(struct uart_port *p, int offset)
442	{
443	offset = map_8250_in_reg(p, offset) << p->regshift;
444	return inb(p->iobase + offset);
445	}
446
447	static void io_serial_out(struct uart_port *p, int offset, int value)
448	{
449	offset = map_8250_out_reg(p, offset) << p->regshift;
450	outb(value, p->iobase + offset);
451	}
452
453	static int serial8250_default_handle_irq(struct uart_port *port);
454
455	static void set_io_from_upio(struct uart_port *p)
456	{
457	struct uart_8250_port *up =
458	container_of(p, struct uart_8250_port, port);
459	switch (p->iotype) {
460	case UPIO_HUB6:
461	p->serial_in = hub6_serial_in;
462	p->serial_out = hub6_serial_out;
463	break;
464
465	case UPIO_MEM:
466	p->serial_in = mem_serial_in;
467	p->serial_out = mem_serial_out;
468	break;
469
470	case UPIO_RM9000:
471	case UPIO_MEM32:
472	p->serial_in = mem32_serial_in;
473	p->serial_out = mem32_serial_out;
474	break;
475
476	case UPIO_MEM_DELAY:
477	p->serial_in = memdelay_serial_in;
478	p->serial_out = memdelay_serial_out;
479	break;
480
481	case UPIO_AU:
482	p->serial_in = au_serial_in;
483	p->serial_out = au_serial_out;
484	break;
485
486	default:
487	p->serial_in = io_serial_in;
488	p->serial_out = io_serial_out;
489	break;
490	}
491	/* Remember loaded iotype */
492	up->cur_iotype = p->iotype;
493	p->handle_irq = serial8250_default_handle_irq;
494	}
495
496	static void
497	serial_out_sync(struct uart_8250_port *up, int offset, int value)
498	{
499	struct uart_port *p = &up->port;
500	switch (p->iotype) {
501	case UPIO_MEM:
502	case UPIO_MEM32:
503	case UPIO_MEM_DELAY:
504	case UPIO_AU:
505	p->serial_out(p, offset, value);
506	p->serial_in(p, UART_LCR); /* safe, no side-effects */
507	break;
508	default:
509	p->serial_out(p, offset, value);
510	}
511	}
512
513	#define serial_in(up, offset) \
514	(up->port.serial_in(&(up)->port, (offset)))
515	#define serial_out(up, offset, value) \
516	(up->port.serial_out(&(up)->port, (offset), (value)))
517	/*
518	* We used to support using pause I/O for certain machines. We
519	* haven't supported this for a while, but just in case it's badly
520	* needed for certain old 386 machines, I've left these #define's
521	* in....
522	*/
523	#define serial_inp(up, offset) serial_in(up, offset)
524	#define serial_outp(up, offset, value) serial_out(up, offset, value)
525
526	/* Uart divisor latch read */
527	static inline int _serial_dl_read(struct uart_8250_port *up)
528	{
529	return serial_inp(up, UART_DLL) \| serial_inp(up, UART_DLM) << 8;
530	}
531
532	/* Uart divisor latch write */
533	static inline void _serial_dl_write(struct uart_8250_port *up, int value)
534	{
535	serial_outp(up, UART_DLL, value & 0xff);
536	serial_outp(up, UART_DLM, value >> 8 & 0xff);
537	}
538
539	#if defined(CONFIG_MIPS_ALCHEMY) \|\| defined (CONFIG_SERIAL_8250_RT288X)
540	/* Au1x00 and RT288x haven't got a standard divisor latch */
541	static int serial_dl_read(struct uart_8250_port *up)
542	{
543	if (up->port.iotype == UPIO_AU)
544	return __raw_readl(up->port.membase + 0x28);
545	else
546	return _serial_dl_read(up);
547	}
548
549	static void serial_dl_write(struct uart_8250_port *up, int value)
550	{
551	if (up->port.iotype == UPIO_AU)
552	__raw_writel(value, up->port.membase + 0x28);
553	else
554	_serial_dl_write(up, value);
555	}
556	#elif defined(CONFIG_SERIAL_8250_RM9K)
557	static int serial_dl_read(struct uart_8250_port *up)
558	{
559	return (up->port.iotype == UPIO_RM9000) ?
560	(((__raw_readl(up->port.membase + 0x10) << 8) \|
561	(__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
562	_serial_dl_read(up);
563	}
564
565	static void serial_dl_write(struct uart_8250_port *up, int value)
566	{
567	if (up->port.iotype == UPIO_RM9000) {
568	__raw_writel(value, up->port.membase + 0x08);
569	__raw_writel(value >> 8, up->port.membase + 0x10);
570	} else {
571	_serial_dl_write(up, value);
572	}
573	}
574	#else
575	#define serial_dl_read(up) _serial_dl_read(up)
576	#define serial_dl_write(up, value) _serial_dl_write(up, value)
577	#endif
578
579	/*
580	* For the 16C950
581	*/
582	static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
583	{
584	serial_out(up, UART_SCR, offset);
585	serial_out(up, UART_ICR, value);
586	}
587
588	static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
589	{
590	unsigned int value;
591
592	serial_icr_write(up, UART_ACR, up->acr \| UART_ACR_ICRRD);
593	serial_out(up, UART_SCR, offset);
594	value = serial_in(up, UART_ICR);
595	serial_icr_write(up, UART_ACR, up->acr);
596
597	return value;
598	}
599
600	/*
601	* FIFO support.
602	*/
603	static void serial8250_clear_fifos(struct uart_8250_port *p)
604	{
605	if (p->capabilities & UART_CAP_FIFO) {
606	serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
607	serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO \|
608	UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
609	serial_outp(p, UART_FCR, 0);
610	}
611	}
612
613	/*
614	* IER sleep support. UARTs which have EFRs need the "extended
615	* capability" bit enabled. Note that on XR16C850s, we need to
616	* reset LCR to write to IER.
617	*/
618	static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
619	{
620	if (p->capabilities & UART_CAP_SLEEP) {
621	if (p->capabilities & UART_CAP_EFR) {
622	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
623	serial_outp(p, UART_EFR, UART_EFR_ECB);
624	serial_outp(p, UART_LCR, 0);
625	}
626	serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
627	if (p->capabilities & UART_CAP_EFR) {
628	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
629	serial_outp(p, UART_EFR, 0);
630	serial_outp(p, UART_LCR, 0);
631	}
632	}
633	}
634
635	#ifdef CONFIG_SERIAL_8250_RSA
636	/*
637	* Attempts to turn on the RSA FIFO. Returns zero on failure.
638	* We set the port uart clock rate if we succeed.
639	*/
640	static int __enable_rsa(struct uart_8250_port *up)
641	{
642	unsigned char mode;
643	int result;
644
645	mode = serial_inp(up, UART_RSA_MSR);
646	result = mode & UART_RSA_MSR_FIFO;
647
648	if (!result) {
649	serial_outp(up, UART_RSA_MSR, mode \| UART_RSA_MSR_FIFO);
650	mode = serial_inp(up, UART_RSA_MSR);
651	result = mode & UART_RSA_MSR_FIFO;
652	}
653
654	if (result)
655	up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
656
657	return result;
658	}
659
660	static void enable_rsa(struct uart_8250_port *up)
661	{
662	if (up->port.type == PORT_RSA) {
663	if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
664	spin_lock_irq(&up->port.lock);
665	__enable_rsa(up);
666	spin_unlock_irq(&up->port.lock);
667	}
668	if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
669	serial_outp(up, UART_RSA_FRR, 0);
670	}
671	}
672
673	/*
674	* Attempts to turn off the RSA FIFO. Returns zero on failure.
675	* It is unknown why interrupts were disabled in here. However,
676	* the caller is expected to preserve this behaviour by grabbing
677	* the spinlock before calling this function.
678	*/
679	static void disable_rsa(struct uart_8250_port *up)
680	{
681	unsigned char mode;
682	int result;
683
684	if (up->port.type == PORT_RSA &&
685	up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
686	spin_lock_irq(&up->port.lock);
687
688	mode = serial_inp(up, UART_RSA_MSR);
689	result = !(mode & UART_RSA_MSR_FIFO);
690
691	if (!result) {
692	serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
693	mode = serial_inp(up, UART_RSA_MSR);
694	result = !(mode & UART_RSA_MSR_FIFO);
695	}
696
697	if (result)
698	up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
699	spin_unlock_irq(&up->port.lock);
700	}
701	}
702	#endif /* CONFIG_SERIAL_8250_RSA */
703
704	/*
705	* This is a quickie test to see how big the FIFO is.
706	* It doesn't work at all the time, more's the pity.
707	*/
708	static int size_fifo(struct uart_8250_port *up)
709	{
710	unsigned char old_fcr, old_mcr, old_lcr;
711	unsigned short old_dl;
712	int count;
713
714	old_lcr = serial_inp(up, UART_LCR);
715	serial_outp(up, UART_LCR, 0);
716	old_fcr = serial_inp(up, UART_FCR);
717	old_mcr = serial_inp(up, UART_MCR);
718	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \|
719	UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
720	serial_outp(up, UART_MCR, UART_MCR_LOOP);
721	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
722	old_dl = serial_dl_read(up);
723	serial_dl_write(up, 0x0001);
724	serial_outp(up, UART_LCR, 0x03);
725	for (count = 0; count < 256; count++)
726	serial_outp(up, UART_TX, count);
727	mdelay(20);/* FIXME - schedule_timeout */
728	for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
729	(count < 256); count++)
730	serial_inp(up, UART_RX);
731	serial_outp(up, UART_FCR, old_fcr);
732	serial_outp(up, UART_MCR, old_mcr);
733	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
734	serial_dl_write(up, old_dl);
735	serial_outp(up, UART_LCR, old_lcr);
736
737	return count;
738	}
739
740	/*
741	* Read UART ID using the divisor method - set DLL and DLM to zero
742	* and the revision will be in DLL and device type in DLM. We
743	* preserve the device state across this.
744	*/
745	static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
746	{
747	unsigned char old_lcr;
748	unsigned int old_dl;
749	unsigned int id;
750
751	old_lcr = serial_inp(p, UART_LCR);
752	serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
753
754	old_dl = serial_dl_read(p);
755
756	serial_dl_write(p, 0);
757	id = serial_dl_read(p);
758
759	serial_dl_write(p, old_dl);
760	serial_outp(p, UART_LCR, old_lcr);
761
762	return id;
763	}
764
765	/*
766	* This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
767	* When this function is called we know it is at least a StarTech
768	* 16650 V2, but it might be one of several StarTech UARTs, or one of
769	* its clones. (We treat the broken original StarTech 16650 V1 as a
770	* 16550, and why not? Startech doesn't seem to even acknowledge its
771	* existence.)
772	*
773	* What evil have men's minds wrought...
774	*/
775	static void autoconfig_has_efr(struct uart_8250_port *up)
776	{
777	unsigned int id1, id2, id3, rev;
778
779	/*
780	* Everything with an EFR has SLEEP
781	*/
782	up->capabilities \|= UART_CAP_EFR \| UART_CAP_SLEEP;
783
784	/*
785	* First we check to see if it's an Oxford Semiconductor UART.
786	*
787	* If we have to do this here because some non-National
788	* Semiconductor clone chips lock up if you try writing to the
789	* LSR register (which serial_icr_read does)
790	*/
791
792	/*
793	* Check for Oxford Semiconductor 16C950.
794	*
795	* EFR [4] must be set else this test fails.
796	*
797	* This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
798	* claims that it's needed for 952 dual UART's (which are not
799	* recommended for new designs).
800	*/
801	up->acr = 0;
802	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
803	serial_out(up, UART_EFR, UART_EFR_ECB);
804	serial_out(up, UART_LCR, 0x00);
805	id1 = serial_icr_read(up, UART_ID1);
806	id2 = serial_icr_read(up, UART_ID2);
807	id3 = serial_icr_read(up, UART_ID3);
808	rev = serial_icr_read(up, UART_REV);
809
810	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
811
812	if (id1 == 0x16 && id2 == 0xC9 &&
813	(id3 == 0x50 \|\| id3 == 0x52 \|\| id3 == 0x54)) {
814	up->port.type = PORT_16C950;
815
816	/*
817	* Enable work around for the Oxford Semiconductor 952 rev B
818	* chip which causes it to seriously miscalculate baud rates
819	* when DLL is 0.
820	*/
821	if (id3 == 0x52 && rev == 0x01)
822	up->bugs \|= UART_BUG_QUOT;
823	return;
824	}
825
826	/*
827	* We check for a XR16C850 by setting DLL and DLM to 0, and then
828	* reading back DLL and DLM. The chip type depends on the DLM
829	* value read back:
830	* 0x10 - XR16C850 and the DLL contains the chip revision.
831	* 0x12 - XR16C2850.
832	* 0x14 - XR16C854.
833	*/
834	id1 = autoconfig_read_divisor_id(up);
835	DEBUG_AUTOCONF("850id=%04x ", id1);
836
837	id2 = id1 >> 8;
838	if (id2 == 0x10 \|\| id2 == 0x12 \|\| id2 == 0x14) {
839	up->port.type = PORT_16850;
840	return;
841	}
842
843	/*
844	* It wasn't an XR16C850.
845	*
846	* We distinguish between the '654 and the '650 by counting
847	* how many bytes are in the FIFO. I'm using this for now,
848	* since that's the technique that was sent to me in the
849	* serial driver update, but I'm not convinced this works.
850	* I've had problems doing this in the past. -TYT
851	*/
852	if (size_fifo(up) == 64)
853	up->port.type = PORT_16654;
854	else
855	up->port.type = PORT_16650V2;
856	}
857
858	/*
859	* We detected a chip without a FIFO. Only two fall into
860	* this category - the original 8250 and the 16450. The
861	* 16450 has a scratch register (accessible with LCR=0)
862	*/
863	static void autoconfig_8250(struct uart_8250_port *up)
864	{
865	unsigned char scratch, status1, status2;
866
867	up->port.type = PORT_8250;
868
869	scratch = serial_in(up, UART_SCR);
870	serial_outp(up, UART_SCR, 0xa5);
871	status1 = serial_in(up, UART_SCR);
872	serial_outp(up, UART_SCR, 0x5a);
873	status2 = serial_in(up, UART_SCR);
874	serial_outp(up, UART_SCR, scratch);
875
876	if (status1 == 0xa5 && status2 == 0x5a)
877	up->port.type = PORT_16450;
878	}
879
880	static int broken_efr(struct uart_8250_port *up)
881	{
882	/*
883	* Exar ST16C2550 "A2" devices incorrectly detect as
884	* having an EFR, and report an ID of 0x0201. See
885	* http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
886	*/
887	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
888	return 1;
889
890	return 0;
891	}
892
893	static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
894	{
895	unsigned char status;
896
897	status = serial_in(up, 0x04); /* EXCR2 */
898	#define PRESL(x) ((x) & 0x30)
899	if (PRESL(status) == 0x10) {
900	/* already in high speed mode */
901	return 0;
902	} else {
903	status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
904	status \|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
905	serial_outp(up, 0x04, status);
906	}
907	return 1;
908	}
909
910	/*
911	* We know that the chip has FIFOs. Does it have an EFR? The
912	* EFR is located in the same register position as the IIR and
913	* we know the top two bits of the IIR are currently set. The
914	* EFR should contain zero. Try to read the EFR.
915	*/
916	static void autoconfig_16550a(struct uart_8250_port *up)
917	{
918	unsigned char status1, status2;
919	unsigned int iersave;
920
921	up->port.type = PORT_16550A;
922	up->capabilities \|= UART_CAP_FIFO;
923
924	/*
925	* Check for presence of the EFR when DLAB is set.
926	* Only ST16C650V1 UARTs pass this test.
927	*/
928	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
929	if (serial_in(up, UART_EFR) == 0) {
930	serial_outp(up, UART_EFR, 0xA8);
931	if (serial_in(up, UART_EFR) != 0) {
932	DEBUG_AUTOCONF("EFRv1 ");
933	up->port.type = PORT_16650;
934	up->capabilities \|= UART_CAP_EFR \| UART_CAP_SLEEP;
935	} else {
936	DEBUG_AUTOCONF("Motorola 8xxx DUART ");
937	}
938	serial_outp(up, UART_EFR, 0);
939	return;
940	}
941
942	/*
943	* Maybe it requires 0xbf to be written to the LCR.
944	* (other ST16C650V2 UARTs, TI16C752A, etc)
945	*/
946	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
947	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
948	DEBUG_AUTOCONF("EFRv2 ");
949	autoconfig_has_efr(up);
950	return;
951	}
952
953	/*
954	* Check for a National Semiconductor SuperIO chip.
955	* Attempt to switch to bank 2, read the value of the LOOP bit
956	* from EXCR1. Switch back to bank 0, change it in MCR. Then
957	* switch back to bank 2, read it from EXCR1 again and check
958	* it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
959	*/
960	serial_outp(up, UART_LCR, 0);
961	status1 = serial_in(up, UART_MCR);
962	serial_outp(up, UART_LCR, 0xE0);
963	status2 = serial_in(up, 0x02); /* EXCR1 */
964
965	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
966	serial_outp(up, UART_LCR, 0);
967	serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
968	serial_outp(up, UART_LCR, 0xE0);
969	status2 = serial_in(up, 0x02); /* EXCR1 */
970	serial_outp(up, UART_LCR, 0);
971	serial_outp(up, UART_MCR, status1);
972
973	if ((status2 ^ status1) & UART_MCR_LOOP) {
974	unsigned short quot;
975
976	serial_outp(up, UART_LCR, 0xE0);
977
978	quot = serial_dl_read(up);
979	quot <<= 3;
980
981	if (ns16550a_goto_highspeed(up))
982	serial_dl_write(up, quot);
983
984	serial_outp(up, UART_LCR, 0);
985
986	up->port.uartclk = 921600*16;
987	up->port.type = PORT_NS16550A;
988	up->capabilities \|= UART_NATSEMI;
989	return;
990	}
991	}
992
993	/*
994	* No EFR. Try to detect a TI16750, which only sets bit 5 of
995	* the IIR when 64 byte FIFO mode is enabled when DLAB is set.
996	* Try setting it with and without DLAB set. Cheap clones
997	* set bit 5 without DLAB set.
998	*/
999	serial_outp(up, UART_LCR, 0);
1000	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR7_64BYTE);
1001	status1 = serial_in(up, UART_IIR) >> 5;
1002	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1003	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1004	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR7_64BYTE);
1005	status2 = serial_in(up, UART_IIR) >> 5;
1006	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1007	serial_outp(up, UART_LCR, 0);
1008
1009	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1010
1011	if (status1 == 6 && status2 == 7) {
1012	up->port.type = PORT_16750;
1013	up->capabilities \|= UART_CAP_AFE \| UART_CAP_SLEEP;
1014	return;
1015	}
1016
1017	/*
1018	* Try writing and reading the UART_IER_UUE bit (b6).
1019	* If it works, this is probably one of the Xscale platform's
1020	* internal UARTs.
1021	* We're going to explicitly set the UUE bit to 0 before
1022	* trying to write and read a 1 just to make sure it's not
1023	* already a 1 and maybe locked there before we even start start.
1024	*/
1025	iersave = serial_in(up, UART_IER);
1026	serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1027	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1028	/*
1029	* OK it's in a known zero state, try writing and reading
1030	* without disturbing the current state of the other bits.
1031	*/
1032	serial_outp(up, UART_IER, iersave \| UART_IER_UUE);
1033	if (serial_in(up, UART_IER) & UART_IER_UUE) {
1034	/*
1035	* It's an Xscale.
1036	* We'll leave the UART_IER_UUE bit set to 1 (enabled).
1037	*/
1038	DEBUG_AUTOCONF("Xscale ");
1039	up->port.type = PORT_XSCALE;
1040	up->capabilities \|= UART_CAP_UUE \| UART_CAP_RTOIE;
1041	return;
1042	}
1043	} else {
1044	/*
1045	* If we got here we couldn't force the IER_UUE bit to 0.
1046	* Log it and continue.
1047	*/
1048	DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1049	}
1050	serial_outp(up, UART_IER, iersave);
1051
1052	/*
1053	* Exar uarts have EFR in a weird location
1054	*/
1055	if (up->port.flags & UPF_EXAR_EFR) {
1056	up->port.type = PORT_XR17D15X;
1057	up->capabilities \|= UART_CAP_AFE \| UART_CAP_EFR;
1058	}
1059
1060	/*
1061	* We distinguish between 16550A and U6 16550A by counting
1062	* how many bytes are in the FIFO.
1063	*/
1064	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1065	up->port.type = PORT_U6_16550A;
1066	up->capabilities \|= UART_CAP_AFE;
1067	}
1068	}
1069
1070	/*
1071	* This routine is called by rs_init() to initialize a specific serial
1072	* port. It determines what type of UART chip this serial port is
1073	* using: 8250, 16450, 16550, 16550A. The important question is
1074	* whether or not this UART is a 16550A or not, since this will
1075	* determine whether or not we can use its FIFO features or not.
1076	*/
1077	static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1078	{
1079	unsigned char status1, scratch, scratch2, scratch3;
1080	unsigned char save_lcr, save_mcr;
1081	unsigned long flags;
1082
1083	if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1084	return;
1085
1086	DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1087	serial_index(&up->port), up->port.iobase, up->port.membase);
1088
1089	/*
1090	* We really do need global IRQs disabled here - we're going to
1091	* be frobbing the chips IRQ enable register to see if it exists.
1092	*/
1093	spin_lock_irqsave(&up->port.lock, flags);
1094
1095	up->capabilities = 0;
1096	up->bugs = 0;
1097
1098	if (!(up->port.flags & UPF_BUGGY_UART)) {
1099	/*
1100	* Do a simple existence test first; if we fail this,
1101	* there's no point trying anything else.
1102	*
1103	* 0x80 is used as a nonsense port to prevent against
1104	* false positives due to ISA bus float. The
1105	* assumption is that 0x80 is a non-existent port;
1106	* which should be safe since include/asm/io.h also
1107	* makes this assumption.
1108	*
1109	* Note: this is safe as long as MCR bit 4 is clear
1110	* and the device is in "PC" mode.
1111	*/
1112	scratch = serial_inp(up, UART_IER);
1113	serial_outp(up, UART_IER, 0);
1114	#ifdef __i386__
1115	outb(0xff, 0x080);
1116	#endif
1117	/*
1118	* Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1119	* 16C754B) allow only to modify them if an EFR bit is set.
1120	*/
1121	scratch2 = serial_inp(up, UART_IER) & 0x0f;
1122	serial_outp(up, UART_IER, 0x0F);
1123	#ifdef __i386__
1124	outb(0, 0x080);
1125	#endif
1126	scratch3 = serial_inp(up, UART_IER) & 0x0f;
1127	serial_outp(up, UART_IER, scratch);
1128	if (scratch2 != 0 \|\| scratch3 != 0x0F) {
1129	/*
1130	* We failed; there's nothing here
1131	*/
1132	DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1133	scratch2, scratch3);
1134	goto out;
1135	}
1136	}
1137
1138	save_mcr = serial_in(up, UART_MCR);
1139	save_lcr = serial_in(up, UART_LCR);
1140
1141	/*
1142	* Check to see if a UART is really there. Certain broken
1143	* internal modems based on the Rockwell chipset fail this
1144	* test, because they apparently don't implement the loopback
1145	* test mode. So this test is skipped on the COM 1 through
1146	* COM 4 ports. This should be safe, since no board
1147	* manufacturer would be stupid enough to design a board
1148	* that conflicts with COM 1-4 --- we hope!
1149	*/
1150	if (!(up->port.flags & UPF_SKIP_TEST)) {
1151	serial_outp(up, UART_MCR, UART_MCR_LOOP \| 0x0A);
1152	status1 = serial_inp(up, UART_MSR) & 0xF0;
1153	serial_outp(up, UART_MCR, save_mcr);
1154	if (status1 != 0x90) {
1155	DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1156	status1);
1157	goto out;
1158	}
1159	}
1160
1161	/*
1162	* We're pretty sure there's a port here. Lets find out what
1163	* type of port it is. The IIR top two bits allows us to find
1164	* out if it's 8250 or 16450, 16550, 16550A or later. This
1165	* determines what we test for next.
1166	*
1167	* We also initialise the EFR (if any) to zero for later. The
1168	* EFR occupies the same register location as the FCR and IIR.
1169	*/
1170	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1171	serial_outp(up, UART_EFR, 0);
1172	serial_outp(up, UART_LCR, 0);
1173
1174	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1175	scratch = serial_in(up, UART_IIR) >> 6;
1176
1177	DEBUG_AUTOCONF("iir=%d ", scratch);
1178
1179	switch (scratch) {
1180	case 0:
1181	autoconfig_8250(up);
1182	break;
1183	case 1:
1184	up->port.type = PORT_UNKNOWN;
1185	break;
1186	case 2:
1187	up->port.type = PORT_16550;
1188	break;
1189	case 3:
1190	autoconfig_16550a(up);
1191	break;
1192	}
1193
1194	#ifdef CONFIG_SERIAL_8250_RSA
1195	/*
1196	* Only probe for RSA ports if we got the region.
1197	*/
1198	if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1199	int i;
1200
1201	for (i = 0 ; i < probe_rsa_count; ++i) {
1202	if (probe_rsa[i] == up->port.iobase &&
1203	__enable_rsa(up)) {
1204	up->port.type = PORT_RSA;
1205	break;
1206	}
1207	}
1208	}
1209	#endif
1210
1211	serial_outp(up, UART_LCR, save_lcr);
1212
1213	if (up->capabilities != uart_config[up->port.type].flags) {
1214	printk(KERN_WARNING
1215	"ttyS%d: detected caps %08x should be %08x\n",
1216	serial_index(&up->port), up->capabilities,
1217	uart_config[up->port.type].flags);
1218	}
1219
1220	up->port.fifosize = uart_config[up->port.type].fifo_size;
1221	up->capabilities = uart_config[up->port.type].flags;
1222	up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1223
1224	if (up->port.type == PORT_UNKNOWN)
1225	goto out;
1226
1227	/*
1228	* Reset the UART.
1229	*/
1230	#ifdef CONFIG_SERIAL_8250_RSA
1231	if (up->port.type == PORT_RSA)
1232	serial_outp(up, UART_RSA_FRR, 0);
1233	#endif
1234	serial_outp(up, UART_MCR, save_mcr);
1235	serial8250_clear_fifos(up);
1236	serial_in(up, UART_RX);
1237	if (up->capabilities & UART_CAP_UUE)
1238	serial_outp(up, UART_IER, UART_IER_UUE);
1239	else
1240	serial_outp(up, UART_IER, 0);
1241
1242	out:
1243	spin_unlock_irqrestore(&up->port.lock, flags);
1244	DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1245	}
1246
1247	static void autoconfig_irq(struct uart_8250_port *up)
1248	{
1249	unsigned char save_mcr, save_ier;
1250	unsigned char save_ICP = 0;
1251	unsigned int ICP = 0;
1252	unsigned long irqs;
1253	int irq;
1254
1255	if (up->port.flags & UPF_FOURPORT) {
1256	ICP = (up->port.iobase & 0xfe0) \| 0x1f;
1257	save_ICP = inb_p(ICP);
1258	outb_p(0x80, ICP);
1259	(void) inb_p(ICP);
1260	}
1261
1262	/* forget possible initially masked and pending IRQ */
1263	probe_irq_off(probe_irq_on());
1264	save_mcr = serial_inp(up, UART_MCR);
1265	save_ier = serial_inp(up, UART_IER);
1266	serial_outp(up, UART_MCR, UART_MCR_OUT1 \| UART_MCR_OUT2);
1267
1268	irqs = probe_irq_on();
1269	serial_outp(up, UART_MCR, 0);
1270	udelay(10);
1271	if (up->port.flags & UPF_FOURPORT) {
1272	serial_outp(up, UART_MCR,
1273	UART_MCR_DTR \| UART_MCR_RTS);
1274	} else {
1275	serial_outp(up, UART_MCR,
1276	UART_MCR_DTR \| UART_MCR_RTS \| UART_MCR_OUT2);
1277	}
1278	serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1279	(void)serial_inp(up, UART_LSR);
1280	(void)serial_inp(up, UART_RX);
1281	(void)serial_inp(up, UART_IIR);
1282	(void)serial_inp(up, UART_MSR);
1283	serial_outp(up, UART_TX, 0xFF);
1284	udelay(20);
1285	irq = probe_irq_off(irqs);
1286
1287	serial_outp(up, UART_MCR, save_mcr);
1288	serial_outp(up, UART_IER, save_ier);
1289
1290	if (up->port.flags & UPF_FOURPORT)
1291	outb_p(save_ICP, ICP);
1292
1293	up->port.irq = (irq > 0) ? irq : 0;
1294	}
1295
1296	static inline void __stop_tx(struct uart_8250_port *p)
1297	{
1298	if (p->ier & UART_IER_THRI) {
1299	p->ier &= ~UART_IER_THRI;
1300	serial_out(p, UART_IER, p->ier);
1301	}
1302	}
1303
1304	static void serial8250_stop_tx(struct uart_port *port)
1305	{
1306	struct uart_8250_port *up =
1307	container_of(port, struct uart_8250_port, port);
1308
1309	__stop_tx(up);
1310
1311	/*
1312	* We really want to stop the transmitter from sending.
1313	*/
1314	if (up->port.type == PORT_16C950) {
1315	up->acr \|= UART_ACR_TXDIS;
1316	serial_icr_write(up, UART_ACR, up->acr);
1317	}
1318	}
1319
1320	static void serial8250_start_tx(struct uart_port *port)
1321	{
1322	struct uart_8250_port *up =
1323	container_of(port, struct uart_8250_port, port);
1324
1325	if (!(up->ier & UART_IER_THRI)) {
1326	up->ier \|= UART_IER_THRI;
1327	serial_out(up, UART_IER, up->ier);
1328
1329	if (up->bugs & UART_BUG_TXEN) {
1330	unsigned char lsr;
1331	lsr = serial_in(up, UART_LSR);
1332	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1333	if ((up->port.type == PORT_RM9000) ?
1334	(lsr & UART_LSR_THRE) :
1335	(lsr & UART_LSR_TEMT))
1336	serial8250_tx_chars(up);
1337	}
1338	}
1339
1340	/*
1341	* Re-enable the transmitter if we disabled it.
1342	*/
1343	if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1344	up->acr &= ~UART_ACR_TXDIS;
1345	serial_icr_write(up, UART_ACR, up->acr);
1346	}
1347	}
1348
1349	static void serial8250_stop_rx(struct uart_port *port)
1350	{
1351	struct uart_8250_port *up =
1352	container_of(port, struct uart_8250_port, port);
1353
1354	up->ier &= ~UART_IER_RLSI;
1355	up->port.read_status_mask &= ~UART_LSR_DR;
1356	serial_out(up, UART_IER, up->ier);
1357	}
1358
1359	static void serial8250_enable_ms(struct uart_port *port)
1360	{
1361	struct uart_8250_port *up =
1362	container_of(port, struct uart_8250_port, port);
1363
1364	/* no MSR capabilities */
1365	if (up->bugs & UART_BUG_NOMSR)
1366	return;
1367
1368	up->ier \|= UART_IER_MSI;
1369	serial_out(up, UART_IER, up->ier);
1370	}
1371
1372	/*
1373	* Clear the Tegra rx fifo after a break
1374	*
1375	* FIXME: This needs to become a port specific callback once we have a
1376	* framework for this
1377	*/
1378	static void clear_rx_fifo(struct uart_8250_port *up)
1379	{
1380	unsigned int status, tmout = 10000;
1381	do {
1382	status = serial_in(up, UART_LSR);
1383	if (status & (UART_LSR_FIFOE \| UART_LSR_BRK_ERROR_BITS))
1384	status = serial_in(up, UART_RX);
1385	else
1386	break;
1387	if (--tmout == 0)
1388	break;
1389	udelay(1);
1390	} while (1);
1391	}
1392
1393	/*
1394	* serial8250_rx_chars: processes according to the passed in LSR
1395	* value, and returns the remaining LSR bits not handled
1396	* by this Rx routine.
1397	*/
1398	unsigned char
1399	serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1400	{
1401	struct tty_struct *tty = up->port.state->port.tty;
1402	unsigned char ch;
1403	int max_count = 256;
1404	char flag;
1405
1406	do {
1407	if (likely(lsr & UART_LSR_DR))
1408	ch = serial_inp(up, UART_RX);
1409	else
1410	/*
1411	* Intel 82571 has a Serial Over Lan device that will
1412	* set UART_LSR_BI without setting UART_LSR_DR when
1413	* it receives a break. To avoid reading from the
1414	* receive buffer without UART_LSR_DR bit set, we
1415	* just force the read character to be 0
1416	*/
1417	ch = 0;
1418
1419	flag = TTY_NORMAL;
1420	up->port.icount.rx++;
1421
1422	lsr \|= up->lsr_saved_flags;
1423	up->lsr_saved_flags = 0;
1424
1425	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1426	/*
1427	* For statistics only
1428	*/
1429	if (lsr & UART_LSR_BI) {
1430	lsr &= ~(UART_LSR_FE \| UART_LSR_PE);
1431	up->port.icount.brk++;
1432	/*
1433	* If tegra port then clear the rx fifo to
1434	* accept another break/character.
1435	*/
1436	if (up->port.type == PORT_TEGRA)
1437	clear_rx_fifo(up);
1438
1439	/*
1440	* We do the SysRQ and SAK checking
1441	* here because otherwise the break
1442	* may get masked by ignore_status_mask
1443	* or read_status_mask.
1444	*/
1445	if (uart_handle_break(&up->port))
1446	goto ignore_char;
1447	} else if (lsr & UART_LSR_PE)
1448	up->port.icount.parity++;
1449	else if (lsr & UART_LSR_FE)
1450	up->port.icount.frame++;
1451	if (lsr & UART_LSR_OE)
1452	up->port.icount.overrun++;
1453
1454	/*
1455	* Mask off conditions which should be ignored.
1456	*/
1457	lsr &= up->port.read_status_mask;
1458
1459	if (lsr & UART_LSR_BI) {
1460	DEBUG_INTR("handling break....");
1461	flag = TTY_BREAK;
1462	} else if (lsr & UART_LSR_PE)
1463	flag = TTY_PARITY;
1464	else if (lsr & UART_LSR_FE)
1465	flag = TTY_FRAME;
1466	}
1467	if (uart_handle_sysrq_char(&up->port, ch))
1468	goto ignore_char;
1469
1470	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1471
1472	ignore_char:
1473	lsr = serial_inp(up, UART_LSR);
1474	} while ((lsr & (UART_LSR_DR \| UART_LSR_BI)) && (max_count-- > 0));
1475	spin_unlock(&up->port.lock);
1476	tty_flip_buffer_push(tty);
1477	spin_lock(&up->port.lock);
1478	return lsr;
1479	}
1480	EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1481
1482	void serial8250_tx_chars(struct uart_8250_port *up)
1483	{
1484	struct circ_buf *xmit = &up->port.state->xmit;
1485	int count;
1486
1487	if (up->port.x_char) {
1488	serial_outp(up, UART_TX, up->port.x_char);
1489	up->port.icount.tx++;
1490	up->port.x_char = 0;
1491	return;
1492	}
1493	if (uart_tx_stopped(&up->port)) {
1494	serial8250_stop_tx(&up->port);
1495	return;
1496	}
1497	if (uart_circ_empty(xmit)) {
1498	__stop_tx(up);
1499	return;
1500	}
1501
1502	count = up->tx_loadsz;
1503	do {
1504	serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1505	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1506	up->port.icount.tx++;
1507	if (uart_circ_empty(xmit))
1508	break;
1509	} while (--count > 0);
1510
1511	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1512	uart_write_wakeup(&up->port);
1513
1514	DEBUG_INTR("THRE...");
1515
1516	if (uart_circ_empty(xmit))
1517	__stop_tx(up);
1518	}
1519	EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1520
1521	unsigned int serial8250_modem_status(struct uart_8250_port *up)
1522	{
1523	unsigned int status = serial_in(up, UART_MSR);
1524
1525	status \|= up->msr_saved_flags;
1526	up->msr_saved_flags = 0;
1527	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1528	up->port.state != NULL) {
1529	if (status & UART_MSR_TERI)
1530	up->port.icount.rng++;
1531	if (status & UART_MSR_DDSR)
1532	up->port.icount.dsr++;
1533	if (status & UART_MSR_DDCD)
1534	uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1535	if (status & UART_MSR_DCTS)
1536	uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1537
1538	wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1539	}
1540
1541	return status;
1542	}
1543	EXPORT_SYMBOL_GPL(serial8250_modem_status);
1544
1545	/*
1546	* This handles the interrupt from one port.
1547	*/
1548	int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1549	{
1550	unsigned char status;
1551	unsigned long flags;
1552	struct uart_8250_port *up =
1553	container_of(port, struct uart_8250_port, port);
1554
1555	if (iir & UART_IIR_NO_INT)
1556	return 0;
1557
1558	spin_lock_irqsave(&up->port.lock, flags);
1559
1560	status = serial_inp(up, UART_LSR);
1561
1562	DEBUG_INTR("status = %x...", status);
1563
1564	if (status & (UART_LSR_DR \| UART_LSR_BI))
1565	status = serial8250_rx_chars(up, status);
1566	serial8250_modem_status(up);
1567	if (status & UART_LSR_THRE)
1568	serial8250_tx_chars(up);
1569
1570	spin_unlock_irqrestore(&up->port.lock, flags);
1571	return 1;
1572	}
1573	EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1574
1575	static int serial8250_default_handle_irq(struct uart_port *port)
1576	{
1577	struct uart_8250_port *up =
1578	container_of(port, struct uart_8250_port, port);
1579	unsigned int iir = serial_in(up, UART_IIR);
1580
1581	return serial8250_handle_irq(port, iir);
1582	}
1583
1584	/*
1585	* This is the serial driver's interrupt routine.
1586	*
1587	* Arjan thinks the old way was overly complex, so it got simplified.
1588	* Alan disagrees, saying that need the complexity to handle the weird
1589	* nature of ISA shared interrupts. (This is a special exception.)
1590	*
1591	* In order to handle ISA shared interrupts properly, we need to check
1592	* that all ports have been serviced, and therefore the ISA interrupt
1593	* line has been de-asserted.
1594	*
1595	* This means we need to loop through all ports. checking that they
1596	* don't have an interrupt pending.
1597	*/
1598	static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1599	{
1600	struct irq_info *i = dev_id;
1601	struct list_head l, end = NULL;
1602	int pass_counter = 0, handled = 0;
1603
1604	DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1605
1606	spin_lock(&i->lock);
1607
1608	l = i->head;
1609	do {
1610	struct uart_8250_port *up;
1611	struct uart_port *port;
1612
1613	up = list_entry(l, struct uart_8250_port, list);
1614	port = &up->port;
1615
1616	if (port->handle_irq(port)) {
1617	handled = 1;
1618	end = NULL;
1619	} else if (end == NULL)
1620	end = l;
1621
1622	l = l->next;
1623
1624	if (l == i->head && pass_counter++ > PASS_LIMIT) {
1625	/* If we hit this, we're dead. */
1626	printk_ratelimited(KERN_ERR
1627	"serial8250: too much work for irq%d\n", irq);
1628	break;
1629	}
1630	} while (l != end);
1631
1632	spin_unlock(&i->lock);
1633
1634	DEBUG_INTR("end.\n");
1635
1636	return IRQ_RETVAL(handled);
1637	}
1638
1639	/*
1640	* To support ISA shared interrupts, we need to have one interrupt
1641	* handler that ensures that the IRQ line has been deasserted
1642	* before returning. Failing to do this will result in the IRQ
1643	* line being stuck active, and, since ISA irqs are edge triggered,
1644	* no more IRQs will be seen.
1645	*/
1646	static void serial_do_unlink(struct irq_info i, struct uart_8250_port up)
1647	{
1648	spin_lock_irq(&i->lock);
1649
1650	if (!list_empty(i->head)) {
1651	if (i->head == &up->list)
1652	i->head = i->head->next;
1653	list_del(&up->list);
1654	} else {
1655	BUG_ON(i->head != &up->list);
1656	i->head = NULL;
1657	}
1658	spin_unlock_irq(&i->lock);
1659	/* List empty so throw away the hash node */
1660	if (i->head == NULL) {
1661	hlist_del(&i->node);
1662	kfree(i);
1663	}
1664	}
1665
1666	static int serial_link_irq_chain(struct uart_8250_port *up)
1667	{
1668	struct hlist_head *h;
1669	struct hlist_node *n;
1670	struct irq_info *i;
1671	int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1672
1673	mutex_lock(&hash_mutex);
1674
1675	h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1676
1677	hlist_for_each(n, h) {
1678	i = hlist_entry(n, struct irq_info, node);
1679	if (i->irq == up->port.irq)
1680	break;
1681	}
1682
1683	if (n == NULL) {
1684	i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1685	if (i == NULL) {
1686	mutex_unlock(&hash_mutex);
1687	return -ENOMEM;
1688	}
1689	spin_lock_init(&i->lock);
1690	i->irq = up->port.irq;
1691	hlist_add_head(&i->node, h);
1692	}
1693	mutex_unlock(&hash_mutex);
1694
1695	spin_lock_irq(&i->lock);
1696
1697	if (i->head) {
1698	list_add(&up->list, i->head);
1699	spin_unlock_irq(&i->lock);
1700
1701	ret = 0;
1702	} else {
1703	INIT_LIST_HEAD(&up->list);
1704	i->head = &up->list;
1705	spin_unlock_irq(&i->lock);
1706	irq_flags \|= up->port.irqflags;
1707	ret = request_irq(up->port.irq, serial8250_interrupt,
1708	irq_flags, "serial", i);
1709	if (ret < 0)
1710	serial_do_unlink(i, up);
1711	}
1712
1713	return ret;
1714	}
1715
1716	static void serial_unlink_irq_chain(struct uart_8250_port *up)
1717	{
1718	struct irq_info *i;
1719	struct hlist_node *n;
1720	struct hlist_head *h;
1721
1722	mutex_lock(&hash_mutex);
1723
1724	h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1725
1726	hlist_for_each(n, h) {
1727	i = hlist_entry(n, struct irq_info, node);
1728	if (i->irq == up->port.irq)
1729	break;
1730	}
1731
1732	BUG_ON(n == NULL);
1733	BUG_ON(i->head == NULL);
1734
1735	if (list_empty(i->head))
1736	free_irq(up->port.irq, i);
1737
1738	serial_do_unlink(i, up);
1739	mutex_unlock(&hash_mutex);
1740	}
1741
1742	/*
1743	* This function is used to handle ports that do not have an
1744	* interrupt. This doesn't work very well for 16450's, but gives
1745	* barely passable results for a 16550A. (Although at the expense
1746	* of much CPU overhead).
1747	*/
1748	static void serial8250_timeout(unsigned long data)
1749	{
1750	struct uart_8250_port up = (struct uart_8250_port )data;
1751
1752	up->port.handle_irq(&up->port);
1753	mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1754	}
1755
1756	static void serial8250_backup_timeout(unsigned long data)
1757	{
1758	struct uart_8250_port up = (struct uart_8250_port )data;
1759	unsigned int iir, ier = 0, lsr;
1760	unsigned long flags;
1761
1762	spin_lock_irqsave(&up->port.lock, flags);
1763
1764	/*
1765	* Must disable interrupts or else we risk racing with the interrupt
1766	* based handler.
1767	*/
1768	if (is_real_interrupt(up->port.irq)) {
1769	ier = serial_in(up, UART_IER);
1770	serial_out(up, UART_IER, 0);
1771	}
1772
1773	iir = serial_in(up, UART_IIR);
1774
1775	/*
1776	* This should be a safe test for anyone who doesn't trust the
1777	* IIR bits on their UART, but it's specifically designed for
1778	* the "Diva" UART used on the management processor on many HP
1779	* ia64 and parisc boxes.
1780	*/
1781	lsr = serial_in(up, UART_LSR);
1782	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1783	if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1784	(!uart_circ_empty(&up->port.state->xmit) \|\| up->port.x_char) &&
1785	(lsr & UART_LSR_THRE)) {
1786	iir &= ~(UART_IIR_ID \| UART_IIR_NO_INT);
1787	iir \|= UART_IIR_THRI;
1788	}
1789
1790	if (!(iir & UART_IIR_NO_INT))
1791	serial8250_tx_chars(up);
1792
1793
1794	if (is_real_interrupt(up->port.irq))
1795	serial_out(up, UART_IER, ier);
1796
1797	spin_unlock_irqrestore(&up->port.lock, flags);
1798
1799
1800	/* Standard timer interval plus 0.2s to keep the port running */
1801	mod_timer(&up->timer,
1802	jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1803	}
1804
1805	static unsigned int serial8250_tx_empty(struct uart_port *port)
1806	{
1807	struct uart_8250_port *up =
1808	container_of(port, struct uart_8250_port, port);
1809	unsigned long flags;
1810	unsigned int lsr;
1811
1812	spin_lock_irqsave(&up->port.lock, flags);
1813	lsr = serial_in(up, UART_LSR);
1814	up->lsr_saved_flags \|= lsr & LSR_SAVE_FLAGS;
1815	spin_unlock_irqrestore(&up->port.lock, flags);
1816
1817	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1818	}
1819
1820	static unsigned int serial8250_get_mctrl(struct uart_port *port)
1821	{
1822	struct uart_8250_port *up =
1823	container_of(port, struct uart_8250_port, port);
1824	unsigned int status;
1825	unsigned int ret;
1826
1827	status = serial8250_modem_status(up);
1828
1829	ret = 0;
1830	if (status & UART_MSR_DCD)
1831	ret \|= TIOCM_CAR;
1832	if (status & UART_MSR_RI)
1833	ret \|= TIOCM_RNG;
1834	if (status & UART_MSR_DSR)
1835	ret \|= TIOCM_DSR;
1836	if (status & UART_MSR_CTS)
1837	ret \|= TIOCM_CTS;
1838	return ret;
1839	}
1840
1841	static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1842	{
1843	struct uart_8250_port *up =
1844	container_of(port, struct uart_8250_port, port);
1845	unsigned char mcr = 0;
1846
1847	if (mctrl & TIOCM_RTS)
1848	mcr \|= UART_MCR_RTS;
1849	if (mctrl & TIOCM_DTR)
1850	mcr \|= UART_MCR_DTR;
1851	if (mctrl & TIOCM_OUT1)
1852	mcr \|= UART_MCR_OUT1;
1853	if (mctrl & TIOCM_OUT2)
1854	mcr \|= UART_MCR_OUT2;
1855	if (mctrl & TIOCM_LOOP)
1856	mcr \|= UART_MCR_LOOP;
1857
1858	mcr = (mcr & up->mcr_mask) \| up->mcr_force \| up->mcr;
1859
1860	serial_out(up, UART_MCR, mcr);
1861	}
1862
1863	static void serial8250_break_ctl(struct uart_port *port, int break_state)
1864	{
1865	struct uart_8250_port *up =
1866	container_of(port, struct uart_8250_port, port);
1867	unsigned long flags;
1868
1869	spin_lock_irqsave(&up->port.lock, flags);
1870	if (break_state == -1)
1871	up->lcr \|= UART_LCR_SBC;
1872	else
1873	up->lcr &= ~UART_LCR_SBC;
1874	serial_out(up, UART_LCR, up->lcr);
1875	spin_unlock_irqrestore(&up->port.lock, flags);
1876	}
1877
1878	/*
1879	* Wait for transmitter & holding register to empty
1880	*/
1881	static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1882	{
1883	unsigned int status, tmout = 10000;
1884
1885	/* Wait up to 10ms for the character(s) to be sent. */
1886	for (;;) {
1887	status = serial_in(up, UART_LSR);
1888
1889	up->lsr_saved_flags \|= status & LSR_SAVE_FLAGS;
1890
1891	if ((status & bits) == bits)
1892	break;
1893	if (--tmout == 0)
1894	break;
1895	udelay(1);
1896	}
1897
1898	/* Wait up to 1s for flow control if necessary */
1899	if (up->port.flags & UPF_CONS_FLOW) {
1900	unsigned int tmout;
1901	for (tmout = 1000000; tmout; tmout--) {
1902	unsigned int msr = serial_in(up, UART_MSR);
1903	up->msr_saved_flags \|= msr & MSR_SAVE_FLAGS;
1904	if (msr & UART_MSR_CTS)
1905	break;
1906	udelay(1);
1907	touch_nmi_watchdog();
1908	}
1909	}
1910	}
1911
1912	#ifdef CONFIG_CONSOLE_POLL
1913	/*
1914	* Console polling routines for writing and reading from the uart while
1915	* in an interrupt or debug context.
1916	*/
1917
1918	static int serial8250_get_poll_char(struct uart_port *port)
1919	{
1920	struct uart_8250_port *up =
1921	container_of(port, struct uart_8250_port, port);
1922	unsigned char lsr = serial_inp(up, UART_LSR);
1923
1924	if (!(lsr & UART_LSR_DR))
1925	return NO_POLL_CHAR;
1926
1927	return serial_inp(up, UART_RX);
1928	}
1929
1930
1931	static void serial8250_put_poll_char(struct uart_port *port,
1932	unsigned char c)
1933	{
1934	unsigned int ier;
1935	struct uart_8250_port *up =
1936	container_of(port, struct uart_8250_port, port);
1937
1938	/*
1939	* First save the IER then disable the interrupts
1940	*/
1941	ier = serial_in(up, UART_IER);
1942	if (up->capabilities & UART_CAP_UUE)
1943	serial_out(up, UART_IER, UART_IER_UUE);
1944	else
1945	serial_out(up, UART_IER, 0);
1946
1947	wait_for_xmitr(up, BOTH_EMPTY);
1948	/*
1949	* Send the character out.
1950	* If a LF, also do CR...
1951	*/
1952	serial_out(up, UART_TX, c);
1953	if (c == 10) {
1954	wait_for_xmitr(up, BOTH_EMPTY);
1955	serial_out(up, UART_TX, 13);
1956	}
1957
1958	/*
1959	* Finally, wait for transmitter to become empty
1960	* and restore the IER
1961	*/
1962	wait_for_xmitr(up, BOTH_EMPTY);
1963	serial_out(up, UART_IER, ier);
1964	}
1965
1966	#endif /* CONFIG_CONSOLE_POLL */
1967
1968	static int serial8250_startup(struct uart_port *port)
1969	{
1970	struct uart_8250_port *up =
1971	container_of(port, struct uart_8250_port, port);
1972	unsigned long flags;
1973	unsigned char lsr, iir;
1974	int retval;
1975
1976	up->port.fifosize = uart_config[up->port.type].fifo_size;
1977	up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1978	up->capabilities = uart_config[up->port.type].flags;
1979	up->mcr = 0;
1980
1981	if (up->port.iotype != up->cur_iotype)
1982	set_io_from_upio(port);
1983
1984	if (up->port.type == PORT_16C950) {
1985	/* Wake up and initialize UART */
1986	up->acr = 0;
1987	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1988	serial_outp(up, UART_EFR, UART_EFR_ECB);
1989	serial_outp(up, UART_IER, 0);
1990	serial_outp(up, UART_LCR, 0);
1991	serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1992	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1993	serial_outp(up, UART_EFR, UART_EFR_ECB);
1994	serial_outp(up, UART_LCR, 0);
1995	}
1996
1997	#ifdef CONFIG_SERIAL_8250_RSA
1998	/*
1999	* If this is an RSA port, see if we can kick it up to the
2000	* higher speed clock.
2001	*/
2002	enable_rsa(up);
2003	#endif
2004
2005	/*
2006	* Clear the FIFO buffers and disable them.
2007	* (they will be reenabled in set_termios())
2008	*/
2009	serial8250_clear_fifos(up);
2010
2011	/*
2012	* Clear the interrupt registers.
2013	*/
2014	(void) serial_inp(up, UART_LSR);
2015	(void) serial_inp(up, UART_RX);
2016	(void) serial_inp(up, UART_IIR);
2017	(void) serial_inp(up, UART_MSR);
2018
2019	/*
2020	* At this point, there's no way the LSR could still be 0xff;
2021	* if it is, then bail out, because there's likely no UART
2022	* here.
2023	*/
2024	if (!(up->port.flags & UPF_BUGGY_UART) &&
2025	(serial_inp(up, UART_LSR) == 0xff)) {
2026	printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2027	serial_index(&up->port));
2028	return -ENODEV;
2029	}
2030
2031	/*
2032	* For a XR16C850, we need to set the trigger levels
2033	*/
2034	if (up->port.type == PORT_16850) {
2035	unsigned char fctr;
2036
2037	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2038
2039	fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX\|UART_FCTR_TX);
2040	serial_outp(up, UART_FCTR, fctr \| UART_FCTR_TRGD \| UART_FCTR_RX);
2041	serial_outp(up, UART_TRG, UART_TRG_96);
2042	serial_outp(up, UART_FCTR, fctr \| UART_FCTR_TRGD \| UART_FCTR_TX);
2043	serial_outp(up, UART_TRG, UART_TRG_96);
2044
2045	serial_outp(up, UART_LCR, 0);
2046	}
2047
2048	if (is_real_interrupt(up->port.irq)) {
2049	unsigned char iir1;
2050	/*
2051	* Test for UARTs that do not reassert THRE when the
2052	* transmitter is idle and the interrupt has already
2053	* been cleared. Real 16550s should always reassert
2054	* this interrupt whenever the transmitter is idle and
2055	* the interrupt is enabled. Delays are necessary to
2056	* allow register changes to become visible.
2057	*/
2058	spin_lock_irqsave(&up->port.lock, flags);
2059	if (up->port.irqflags & IRQF_SHARED)
2060	disable_irq_nosync(up->port.irq);
2061
2062	wait_for_xmitr(up, UART_LSR_THRE);
2063	serial_out_sync(up, UART_IER, UART_IER_THRI);
2064	udelay(1); /* allow THRE to set */
2065	iir1 = serial_in(up, UART_IIR);
2066	serial_out(up, UART_IER, 0);
2067	serial_out_sync(up, UART_IER, UART_IER_THRI);
2068	udelay(1); /* allow a working UART time to re-assert THRE */
2069	iir = serial_in(up, UART_IIR);
2070	serial_out(up, UART_IER, 0);
2071
2072	if (up->port.irqflags & IRQF_SHARED)
2073	enable_irq(up->port.irq);
2074	spin_unlock_irqrestore(&up->port.lock, flags);
2075
2076	/*
2077	* If the interrupt is not reasserted, or we otherwise
2078	* don't trust the iir, setup a timer to kick the UART
2079	* on a regular basis.
2080	*/
2081	if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) \|\|
2082	up->port.flags & UPF_BUG_THRE) {
2083	up->bugs \|= UART_BUG_THRE;
2084	pr_debug("ttyS%d - using backup timer\n",
2085	serial_index(port));
2086	}
2087	}
2088
2089	/*
2090	* The above check will only give an accurate result the first time
2091	* the port is opened so this value needs to be preserved.
2092	*/
2093	if (up->bugs & UART_BUG_THRE) {
2094	up->timer.function = serial8250_backup_timeout;
2095	up->timer.data = (unsigned long)up;
2096	mod_timer(&up->timer, jiffies +
2097	uart_poll_timeout(port) + HZ / 5);
2098	}
2099
2100	/*
2101	* If the "interrupt" for this port doesn't correspond with any
2102	* hardware interrupt, we use a timer-based system. The original
2103	* driver used to do this with IRQ0.
2104	*/
2105	if (!is_real_interrupt(up->port.irq)) {
2106	up->timer.data = (unsigned long)up;
2107	mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2108	} else {
2109	retval = serial_link_irq_chain(up);
2110	if (retval)
2111	return retval;
2112	}
2113
2114	/*
2115	* Now, initialize the UART
2116	*/
2117	serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2118
2119	spin_lock_irqsave(&up->port.lock, flags);
2120	if (up->port.flags & UPF_FOURPORT) {
2121	if (!is_real_interrupt(up->port.irq))
2122	up->port.mctrl \|= TIOCM_OUT1;
2123	} else
2124	/*
2125	* Most PC uarts need OUT2 raised to enable interrupts.
2126	*/
2127	if (is_real_interrupt(up->port.irq))
2128	up->port.mctrl \|= TIOCM_OUT2;
2129
2130	serial8250_set_mctrl(&up->port, up->port.mctrl);
2131
2132	/* Serial over Lan (SoL) hack:
2133	Intel 8257x Gigabit ethernet chips have a
2134	16550 emulation, to be used for Serial Over Lan.
2135	Those chips take a longer time than a normal
2136	serial device to signalize that a transmission
2137	data was queued. Due to that, the above test generally
2138	fails. One solution would be to delay the reading of
2139	iir. However, this is not reliable, since the timeout
2140	is variable. So, let's just don't test if we receive
2141	TX irq. This way, we'll never enable UART_BUG_TXEN.
2142	*/
2143	if (skip_txen_test \|\| up->port.flags & UPF_NO_TXEN_TEST)
2144	goto dont_test_tx_en;
2145
2146	/*
2147	* Do a quick test to see if we receive an
2148	* interrupt when we enable the TX irq.
2149	*/
2150	serial_outp(up, UART_IER, UART_IER_THRI);
2151	lsr = serial_in(up, UART_LSR);
2152	iir = serial_in(up, UART_IIR);
2153	serial_outp(up, UART_IER, 0);
2154
2155	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2156	if (!(up->bugs & UART_BUG_TXEN)) {
2157	up->bugs \|= UART_BUG_TXEN;
2158	pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2159	serial_index(port));
2160	}
2161	} else {
2162	up->bugs &= ~UART_BUG_TXEN;
2163	}
2164
2165	dont_test_tx_en:
2166	spin_unlock_irqrestore(&up->port.lock, flags);
2167
2168	/*
2169	* Clear the interrupt registers again for luck, and clear the
2170	* saved flags to avoid getting false values from polling
2171	* routines or the previous session.
2172	*/
2173	serial_inp(up, UART_LSR);
2174	serial_inp(up, UART_RX);
2175	serial_inp(up, UART_IIR);
2176	serial_inp(up, UART_MSR);
2177	up->lsr_saved_flags = 0;
2178	up->msr_saved_flags = 0;
2179
2180	/*
2181	* Finally, enable interrupts. Note: Modem status interrupts
2182	* are set via set_termios(), which will be occurring imminently
2183	* anyway, so we don't enable them here.
2184	*/
2185	up->ier = UART_IER_RLSI \| UART_IER_RDI;
2186	serial_outp(up, UART_IER, up->ier);
2187
2188	if (up->port.flags & UPF_FOURPORT) {
2189	unsigned int icp;
2190	/*
2191	* Enable interrupts on the AST Fourport board
2192	*/
2193	icp = (up->port.iobase & 0xfe0) \| 0x01f;
2194	outb_p(0x80, icp);
2195	(void) inb_p(icp);
2196	}
2197
2198	return 0;
2199	}
2200
2201	static void serial8250_shutdown(struct uart_port *port)
2202	{
2203	struct uart_8250_port *up =
2204	container_of(port, struct uart_8250_port, port);
2205	unsigned long flags;
2206
2207	/*
2208	* Disable interrupts from this port
2209	*/
2210	up->ier = 0;
2211	serial_outp(up, UART_IER, 0);
2212
2213	spin_lock_irqsave(&up->port.lock, flags);
2214	if (up->port.flags & UPF_FOURPORT) {
2215	/* reset interrupts on the AST Fourport board */
2216	inb((up->port.iobase & 0xfe0) \| 0x1f);
2217	up->port.mctrl \|= TIOCM_OUT1;
2218	} else
2219	up->port.mctrl &= ~TIOCM_OUT2;
2220
2221	serial8250_set_mctrl(&up->port, up->port.mctrl);
2222	spin_unlock_irqrestore(&up->port.lock, flags);
2223
2224	/*
2225	* Disable break condition and FIFOs
2226	*/
2227	serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2228	serial8250_clear_fifos(up);
2229
2230	#ifdef CONFIG_SERIAL_8250_RSA
2231	/*
2232	* Reset the RSA board back to 115kbps compat mode.
2233	*/
2234	disable_rsa(up);
2235	#endif
2236
2237	/*
2238	* Read data port to reset things, and then unlink from
2239	* the IRQ chain.
2240	*/
2241	(void) serial_in(up, UART_RX);
2242
2243	del_timer_sync(&up->timer);
2244	up->timer.function = serial8250_timeout;
2245	if (is_real_interrupt(up->port.irq))
2246	serial_unlink_irq_chain(up);
2247	}
2248
2249	static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2250	{
2251	unsigned int quot;
2252
2253	/*
2254	* Handle magic divisors for baud rates above baud_base on
2255	* SMSC SuperIO chips.
2256	*/
2257	if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2258	baud == (port->uartclk/4))
2259	quot = 0x8001;
2260	else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2261	baud == (port->uartclk/8))
2262	quot = 0x8002;
2263	else
2264	quot = uart_get_divisor(port, baud);
2265
2266	return quot;
2267	}
2268
2269	void
2270	serial8250_do_set_termios(struct uart_port port, struct ktermios termios,
2271	struct ktermios *old)
2272	{
2273	struct uart_8250_port *up =
2274	container_of(port, struct uart_8250_port, port);
2275	unsigned char cval, fcr = 0;
2276	unsigned long flags;
2277	unsigned int baud, quot;
2278
2279	switch (termios->c_cflag & CSIZE) {
2280	case CS5:
2281	cval = UART_LCR_WLEN5;
2282	break;
2283	case CS6:
2284	cval = UART_LCR_WLEN6;
2285	break;
2286	case CS7:
2287	cval = UART_LCR_WLEN7;
2288	break;
2289	default:
2290	case CS8:
2291	cval = UART_LCR_WLEN8;
2292	break;
2293	}
2294
2295	if (termios->c_cflag & CSTOPB)
2296	cval \|= UART_LCR_STOP;
2297	if (termios->c_cflag & PARENB)
2298	cval \|= UART_LCR_PARITY;
2299	if (!(termios->c_cflag & PARODD))
2300	cval \|= UART_LCR_EPAR;
2301	#ifdef CMSPAR
2302	if (termios->c_cflag & CMSPAR)
2303	cval \|= UART_LCR_SPAR;
2304	#endif
2305
2306	/*
2307	* Ask the core to calculate the divisor for us.
2308	*/
2309	baud = uart_get_baud_rate(port, termios, old,
2310	port->uartclk / 16 / 0xffff,
2311	port->uartclk / 16);
2312	quot = serial8250_get_divisor(port, baud);
2313
2314	/*
2315	* Oxford Semi 952 rev B workaround
2316	*/
2317	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2318	quot++;
2319
2320	if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2321	if (baud < 2400)
2322	fcr = UART_FCR_ENABLE_FIFO \| UART_FCR_TRIGGER_1;
2323	else
2324	fcr = uart_config[up->port.type].fcr;
2325	}
2326
2327	/*
2328	* MCR-based auto flow control. When AFE is enabled, RTS will be
2329	* deasserted when the receive FIFO contains more characters than
2330	* the trigger, or the MCR RTS bit is cleared. In the case where
2331	* the remote UART is not using CTS auto flow control, we must
2332	* have sufficient FIFO entries for the latency of the remote
2333	* UART to respond. IOW, at least 32 bytes of FIFO.
2334	*/
2335	if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2336	up->mcr &= ~UART_MCR_AFE;
2337	if (termios->c_cflag & CRTSCTS)
2338	up->mcr \|= UART_MCR_AFE;
2339	}
2340
2341	/*
2342	* Ok, we're now changing the port state. Do it with
2343	* interrupts disabled.
2344	*/
2345	spin_lock_irqsave(&up->port.lock, flags);
2346
2347	/*
2348	* Update the per-port timeout.
2349	*/
2350	uart_update_timeout(port, termios->c_cflag, baud);
2351
2352	up->port.read_status_mask = UART_LSR_OE \| UART_LSR_THRE \| UART_LSR_DR;
2353	if (termios->c_iflag & INPCK)
2354	up->port.read_status_mask \|= UART_LSR_FE \| UART_LSR_PE;
2355	if (termios->c_iflag & (BRKINT \| PARMRK))
2356	up->port.read_status_mask \|= UART_LSR_BI;
2357
2358	/*
2359	* Characteres to ignore
2360	*/
2361	up->port.ignore_status_mask = 0;
2362	if (termios->c_iflag & IGNPAR)
2363	up->port.ignore_status_mask \|= UART_LSR_PE \| UART_LSR_FE;
2364	if (termios->c_iflag & IGNBRK) {
2365	up->port.ignore_status_mask \|= UART_LSR_BI;
2366	/*
2367	* If we're ignoring parity and break indicators,
2368	* ignore overruns too (for real raw support).
2369	*/
2370	if (termios->c_iflag & IGNPAR)
2371	up->port.ignore_status_mask \|= UART_LSR_OE;
2372	}
2373
2374	/*
2375	* ignore all characters if CREAD is not set
2376	*/
2377	if ((termios->c_cflag & CREAD) == 0)
2378	up->port.ignore_status_mask \|= UART_LSR_DR;
2379
2380	/*
2381	* CTS flow control flag and modem status interrupts
2382	*/
2383	up->ier &= ~UART_IER_MSI;
2384	if (!(up->bugs & UART_BUG_NOMSR) &&
2385	UART_ENABLE_MS(&up->port, termios->c_cflag))
2386	up->ier \|= UART_IER_MSI;
2387	if (up->capabilities & UART_CAP_UUE)
2388	up->ier \|= UART_IER_UUE;
2389	if (up->capabilities & UART_CAP_RTOIE)
2390	up->ier \|= UART_IER_RTOIE;
2391
2392	serial_out(up, UART_IER, up->ier);
2393
2394	if (up->capabilities & UART_CAP_EFR) {
2395	unsigned char efr = 0;
2396	/*
2397	* TI16C752/Startech hardware flow control. FIXME:
2398	* - TI16C752 requires control thresholds to be set.
2399	* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2400	*/
2401	if (termios->c_cflag & CRTSCTS)
2402	efr \|= UART_EFR_CTS;
2403
2404	serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2405	if (up->port.flags & UPF_EXAR_EFR)
2406	serial_outp(up, UART_XR_EFR, efr);
2407	else
2408	serial_outp(up, UART_EFR, efr);
2409	}
2410
2411	#ifdef CONFIG_ARCH_OMAP
2412	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2413	if (cpu_is_omap1510() && is_omap_port(up)) {
2414	if (baud == 115200) {
2415	quot = 1;
2416	serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2417	} else
2418	serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2419	}
2420	#endif
2421
2422	if (up->capabilities & UART_NATSEMI) {
2423	/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2424	serial_outp(up, UART_LCR, 0xe0);
2425	} else {
2426	serial_outp(up, UART_LCR, cval \| UART_LCR_DLAB);/* set DLAB */
2427	}
2428
2429	serial_dl_write(up, quot);
2430
2431	/*
2432	* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2433	* is written without DLAB set, this mode will be disabled.
2434	*/
2435	if (up->port.type == PORT_16750)
2436	serial_outp(up, UART_FCR, fcr);
2437
2438	serial_outp(up, UART_LCR, cval); /* reset DLAB */
2439	up->lcr = cval; /* Save LCR */
2440	if (up->port.type != PORT_16750) {
2441	if (fcr & UART_FCR_ENABLE_FIFO) {
2442	/* emulated UARTs (Lucent Venus 167x) need two steps */
2443	serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2444	}
2445	serial_outp(up, UART_FCR, fcr); /* set fcr */
2446	}
2447	serial8250_set_mctrl(&up->port, up->port.mctrl);
2448	spin_unlock_irqrestore(&up->port.lock, flags);
2449	/* Don't rewrite B0 */
2450	if (tty_termios_baud_rate(termios))
2451	tty_termios_encode_baud_rate(termios, baud, baud);
2452	}
2453	EXPORT_SYMBOL(serial8250_do_set_termios);
2454
2455	static void
2456	serial8250_set_termios(struct uart_port port, struct ktermios termios,
2457	struct ktermios *old)
2458	{
2459	if (port->set_termios)
2460	port->set_termios(port, termios, old);
2461	else
2462	serial8250_do_set_termios(port, termios, old);
2463	}
2464
2465	static void
2466	serial8250_set_ldisc(struct uart_port *port, int new)
2467	{
2468	if (new == N_PPS) {
2469	port->flags \|= UPF_HARDPPS_CD;
2470	serial8250_enable_ms(port);
2471	} else
2472	port->flags &= ~UPF_HARDPPS_CD;
2473	}
2474
2475
2476	void serial8250_do_pm(struct uart_port *port, unsigned int state,
2477	unsigned int oldstate)
2478	{
2479	struct uart_8250_port *p =
2480	container_of(port, struct uart_8250_port, port);
2481
2482	serial8250_set_sleep(p, state != 0);
2483	}
2484	EXPORT_SYMBOL(serial8250_do_pm);
2485
2486	static void
2487	serial8250_pm(struct uart_port *port, unsigned int state,
2488	unsigned int oldstate)
2489	{
2490	if (port->pm)
2491	port->pm(port, state, oldstate);
2492	else
2493	serial8250_do_pm(port, state, oldstate);
2494	}
2495
2496	static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2497	{
2498	if (pt->port.iotype == UPIO_AU)
2499	return 0x1000;
2500	#ifdef CONFIG_ARCH_OMAP
2501	if (is_omap_port(pt))
2502	return 0x16 << pt->port.regshift;
2503	#endif
2504	return 8 << pt->port.regshift;
2505	}
2506
2507	/*
2508	* Resource handling.
2509	*/
2510	static int serial8250_request_std_resource(struct uart_8250_port *up)
2511	{
2512	unsigned int size = serial8250_port_size(up);
2513	int ret = 0;
2514
2515	switch (up->port.iotype) {
2516	case UPIO_AU:
2517	case UPIO_TSI:
2518	case UPIO_MEM32:
2519	case UPIO_MEM:
2520	case UPIO_MEM_DELAY:
2521	if (!up->port.mapbase)
2522	break;
2523
2524	if (!request_mem_region(up->port.mapbase, size, "serial")) {
2525	ret = -EBUSY;
2526	break;
2527	}
2528
2529	if (up->port.flags & UPF_IOREMAP) {
2530	up->port.membase = ioremap_nocache(up->port.mapbase,
2531	size);
2532	if (!up->port.membase) {
2533	release_mem_region(up->port.mapbase, size);
2534	ret = -ENOMEM;
2535	}
2536	}
2537	break;
2538
2539	case UPIO_HUB6:
2540	case UPIO_PORT:
2541	if (!request_region(up->port.iobase, size, "serial"))
2542	ret = -EBUSY;
2543	break;
2544	}
2545	return ret;
2546	}
2547
2548	static void serial8250_release_std_resource(struct uart_8250_port *up)
2549	{
2550	unsigned int size = serial8250_port_size(up);
2551
2552	switch (up->port.iotype) {
2553	case UPIO_AU:
2554	case UPIO_TSI:
2555	case UPIO_MEM32:
2556	case UPIO_MEM:
2557	case UPIO_MEM_DELAY:
2558	if (!up->port.mapbase)
2559	break;
2560
2561	if (up->port.flags & UPF_IOREMAP) {
2562	iounmap(up->port.membase);
2563	up->port.membase = NULL;
2564	}
2565
2566	release_mem_region(up->port.mapbase, size);
2567	break;
2568
2569	case UPIO_HUB6:
2570	case UPIO_PORT:
2571	release_region(up->port.iobase, size);
2572	break;
2573	}
2574	}
2575
2576	static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2577	{
2578	unsigned long start = UART_RSA_BASE << up->port.regshift;
2579	unsigned int size = 8 << up->port.regshift;
2580	int ret = -EINVAL;
2581
2582	switch (up->port.iotype) {
2583	case UPIO_HUB6:
2584	case UPIO_PORT:
2585	start += up->port.iobase;
2586	if (request_region(start, size, "serial-rsa"))
2587	ret = 0;
2588	else
2589	ret = -EBUSY;
2590	break;
2591	}
2592
2593	return ret;
2594	}
2595
2596	static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2597	{
2598	unsigned long offset = UART_RSA_BASE << up->port.regshift;
2599	unsigned int size = 8 << up->port.regshift;
2600
2601	switch (up->port.iotype) {
2602	case UPIO_HUB6:
2603	case UPIO_PORT:
2604	release_region(up->port.iobase + offset, size);
2605	break;
2606	}
2607	}
2608
2609	static void serial8250_release_port(struct uart_port *port)
2610	{
2611	struct uart_8250_port *up =
2612	container_of(port, struct uart_8250_port, port);
2613
2614	serial8250_release_std_resource(up);
2615	if (up->port.type == PORT_RSA)
2616	serial8250_release_rsa_resource(up);
2617	}
2618
2619	static int serial8250_request_port(struct uart_port *port)
2620	{
2621	struct uart_8250_port *up =
2622	container_of(port, struct uart_8250_port, port);
2623	int ret = 0;
2624
2625	ret = serial8250_request_std_resource(up);
2626	if (ret == 0 && up->port.type == PORT_RSA) {
2627	ret = serial8250_request_rsa_resource(up);
2628	if (ret < 0)
2629	serial8250_release_std_resource(up);
2630	}
2631
2632	return ret;
2633	}
2634
2635	static void serial8250_config_port(struct uart_port *port, int flags)
2636	{
2637	struct uart_8250_port *up =
2638	container_of(port, struct uart_8250_port, port);
2639	int probeflags = PROBE_ANY;
2640	int ret;
2641
2642	/*
2643	* Find the region that we can probe for. This in turn
2644	* tells us whether we can probe for the type of port.
2645	*/
2646	ret = serial8250_request_std_resource(up);
2647	if (ret < 0)
2648	return;
2649
2650	ret = serial8250_request_rsa_resource(up);
2651	if (ret < 0)
2652	probeflags &= ~PROBE_RSA;
2653
2654	if (up->port.iotype != up->cur_iotype)
2655	set_io_from_upio(port);
2656
2657	if (flags & UART_CONFIG_TYPE)
2658	autoconfig(up, probeflags);
2659
2660	/* if access method is AU, it is a 16550 with a quirk */
2661	if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2662	up->bugs \|= UART_BUG_NOMSR;
2663
2664	if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2665	autoconfig_irq(up);
2666
2667	if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2668	serial8250_release_rsa_resource(up);
2669	if (up->port.type == PORT_UNKNOWN)
2670	serial8250_release_std_resource(up);
2671	}
2672
2673	static int
2674	serial8250_verify_port(struct uart_port port, struct serial_struct ser)
2675	{
2676	if (ser->irq >= nr_irqs \|\| ser->irq < 0 \|\|
2677	ser->baud_base < 9600 \|\| ser->type < PORT_UNKNOWN \|\|
2678	ser->type >= ARRAY_SIZE(uart_config) \|\| ser->type == PORT_CIRRUS \|\|
2679	ser->type == PORT_STARTECH)
2680	return -EINVAL;
2681	return 0;
2682	}
2683
2684	static const char *
2685	serial8250_type(struct uart_port *port)
2686	{
2687	int type = port->type;
2688
2689	if (type >= ARRAY_SIZE(uart_config))
2690	type = 0;
2691	return uart_config[type].name;
2692	}
2693
2694	static struct uart_ops serial8250_pops = {
2695	.tx_empty = serial8250_tx_empty,
2696	.set_mctrl = serial8250_set_mctrl,
2697	.get_mctrl = serial8250_get_mctrl,
2698	.stop_tx = serial8250_stop_tx,
2699	.start_tx = serial8250_start_tx,
2700	.stop_rx = serial8250_stop_rx,
2701	.enable_ms = serial8250_enable_ms,
2702	.break_ctl = serial8250_break_ctl,
2703	.startup = serial8250_startup,
2704	.shutdown = serial8250_shutdown,
2705	.set_termios = serial8250_set_termios,
2706	.set_ldisc = serial8250_set_ldisc,
2707	.pm = serial8250_pm,
2708	.type = serial8250_type,
2709	.release_port = serial8250_release_port,
2710	.request_port = serial8250_request_port,
2711	.config_port = serial8250_config_port,
2712	.verify_port = serial8250_verify_port,
2713	#ifdef CONFIG_CONSOLE_POLL
2714	.poll_get_char = serial8250_get_poll_char,
2715	.poll_put_char = serial8250_put_poll_char,
2716	#endif
2717	};
2718
2719	static struct uart_8250_port serial8250_ports[UART_NR];
2720
2721	static void (serial8250_isa_config)(int port, struct uart_port up,
2722	unsigned short *capabilities);
2723
2724	void serial8250_set_isa_configurator(
2725	void (v)(int port, struct uart_port up, unsigned short *capabilities))
2726	{
2727	serial8250_isa_config = v;
2728	}
2729	EXPORT_SYMBOL(serial8250_set_isa_configurator);
2730
2731	static void __init serial8250_isa_init_ports(void)
2732	{
2733	struct uart_8250_port *up;
2734	static int first = 1;
2735	int i, irqflag = 0;
2736
2737	if (!first)
2738	return;
2739	first = 0;
2740
2741	for (i = 0; i < nr_uarts; i++) {
2742	struct uart_8250_port *up = &serial8250_ports[i];
2743
2744	up->port.line = i;
2745	spin_lock_init(&up->port.lock);
2746
2747	init_timer(&up->timer);
2748	up->timer.function = serial8250_timeout;
2749
2750	/*
2751	* ALPHA_KLUDGE_MCR needs to be killed.
2752	*/
2753	up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2754	up->mcr_force = ALPHA_KLUDGE_MCR;
2755
2756	up->port.ops = &serial8250_pops;
2757	}
2758
2759	if (share_irqs)
2760	irqflag = IRQF_SHARED;
2761
2762	for (i = 0, up = serial8250_ports;
2763	i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2764	i++, up++) {
2765	up->port.iobase = old_serial_port[i].port;
2766	up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2767	up->port.irqflags = old_serial_port[i].irqflags;
2768	up->port.uartclk = old_serial_port[i].baud_base * 16;
2769	up->port.flags = old_serial_port[i].flags;
2770	up->port.hub6 = old_serial_port[i].hub6;
2771	up->port.membase = old_serial_port[i].iomem_base;
2772	up->port.iotype = old_serial_port[i].io_type;
2773	up->port.regshift = old_serial_port[i].iomem_reg_shift;
2774	set_io_from_upio(&up->port);
2775	up->port.irqflags \|= irqflag;
2776	if (serial8250_isa_config != NULL)
2777	serial8250_isa_config(i, &up->port, &up->capabilities);
2778
2779	}
2780	}
2781
2782	static void
2783	serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2784	{
2785	up->port.type = type;
2786	up->port.fifosize = uart_config[type].fifo_size;
2787	up->capabilities = uart_config[type].flags;
2788	up->tx_loadsz = uart_config[type].tx_loadsz;
2789	}
2790
2791	static void __init
2792	serial8250_register_ports(struct uart_driver drv, struct device dev)
2793	{
2794	int i;
2795
2796	for (i = 0; i < nr_uarts; i++) {
2797	struct uart_8250_port *up = &serial8250_ports[i];
2798	up->cur_iotype = 0xFF;
2799	}
2800
2801	serial8250_isa_init_ports();
2802
2803	for (i = 0; i < nr_uarts; i++) {
2804	struct uart_8250_port *up = &serial8250_ports[i];
2805
2806	up->port.dev = dev;
2807
2808	if (up->port.flags & UPF_FIXED_TYPE)
2809	serial8250_init_fixed_type_port(up, up->port.type);
2810
2811	uart_add_one_port(drv, &up->port);
2812	}
2813	}
2814
2815	#ifdef CONFIG_SERIAL_8250_CONSOLE
2816
2817	static void serial8250_console_putchar(struct uart_port *port, int ch)
2818	{
2819	struct uart_8250_port *up =
2820	container_of(port, struct uart_8250_port, port);
2821
2822	wait_for_xmitr(up, UART_LSR_THRE);
2823	serial_out(up, UART_TX, ch);
2824	}
2825
2826	/*
2827	* Print a string to the serial port trying not to disturb
2828	* any possible real use of the port...
2829	*
2830	* The console_lock must be held when we get here.
2831	*/
2832	static void
2833	serial8250_console_write(struct console co, const char s, unsigned int count)
2834	{
2835	struct uart_8250_port *up = &serial8250_ports[co->index];
2836	unsigned long flags;
2837	unsigned int ier;
2838	int locked = 1;
2839
2840	touch_nmi_watchdog();
2841
2842	local_irq_save(flags);
2843	if (up->port.sysrq) {
2844	/* serial8250_handle_irq() already took the lock */
2845	locked = 0;
2846	} else if (oops_in_progress) {
2847	locked = spin_trylock(&up->port.lock);
2848	} else
2849	spin_lock(&up->port.lock);
2850
2851	/*
2852	* First save the IER then disable the interrupts
2853	*/
2854	ier = serial_in(up, UART_IER);
2855
2856	if (up->capabilities & UART_CAP_UUE)
2857	serial_out(up, UART_IER, UART_IER_UUE);
2858	else
2859	serial_out(up, UART_IER, 0);
2860
2861	uart_console_write(&up->port, s, count, serial8250_console_putchar);
2862
2863	/*
2864	* Finally, wait for transmitter to become empty
2865	* and restore the IER
2866	*/
2867	wait_for_xmitr(up, BOTH_EMPTY);
2868	serial_out(up, UART_IER, ier);
2869
2870	/*
2871	* The receive handling will happen properly because the
2872	* receive ready bit will still be set; it is not cleared
2873	* on read. However, modem control will not, we must
2874	* call it if we have saved something in the saved flags
2875	* while processing with interrupts off.
2876	*/
2877	if (up->msr_saved_flags)
2878	serial8250_modem_status(up);
2879
2880	if (locked)
2881	spin_unlock(&up->port.lock);
2882	local_irq_restore(flags);
2883	}
2884
2885	static int __init serial8250_console_setup(struct console co, char options)
2886	{
2887	struct uart_port *port;
2888	int baud = 9600;
2889	int bits = 8;
2890	int parity = 'n';
2891	int flow = 'n';
2892
2893	/*
2894	* Check whether an invalid uart number has been specified, and
2895	* if so, search for the first available port that does have
2896	* console support.
2897	*/
2898	if (co->index >= nr_uarts)
2899	co->index = 0;
2900	port = &serial8250_ports[co->index].port;
2901	if (!port->iobase && !port->membase)
2902	return -ENODEV;
2903
2904	if (options)
2905	uart_parse_options(options, &baud, &parity, &bits, &flow);
2906
2907	return uart_set_options(port, co, baud, parity, bits, flow);
2908	}
2909
2910	static int serial8250_console_early_setup(void)
2911	{
2912	return serial8250_find_port_for_earlycon();
2913	}
2914
2915	static struct console serial8250_console = {
2916	.name = "ttyS",
2917	.write = serial8250_console_write,
2918	.device = uart_console_device,
2919	.setup = serial8250_console_setup,
2920	.early_setup = serial8250_console_early_setup,
2921	.flags = CON_PRINTBUFFER \| CON_ANYTIME,
2922	.index = -1,
2923	.data = &serial8250_reg,
2924	};
2925
2926	static int __init serial8250_console_init(void)
2927	{
2928	if (nr_uarts > UART_NR)
2929	nr_uarts = UART_NR;
2930
2931	serial8250_isa_init_ports();
2932	register_console(&serial8250_console);
2933	return 0;
2934	}
2935	console_initcall(serial8250_console_init);
2936
2937	int serial8250_find_port(struct uart_port *p)
2938	{
2939	int line;
2940	struct uart_port *port;
2941
2942	for (line = 0; line < nr_uarts; line++) {
2943	port = &serial8250_ports[line].port;
2944	if (uart_match_port(p, port))
2945	return line;
2946	}
2947	return -ENODEV;
2948	}
2949
2950	#define SERIAL8250_CONSOLE &serial8250_console
2951	#else
2952	#define SERIAL8250_CONSOLE NULL
2953	#endif
2954
2955	static struct uart_driver serial8250_reg = {
2956	.owner = THIS_MODULE,
2957	.driver_name = "serial",
2958	.dev_name = "ttyS",
2959	.major = TTY_MAJOR,
2960	.minor = 64,
2961	.cons = SERIAL8250_CONSOLE,
2962	};
2963
2964	/*
2965	* early_serial_setup - early registration for 8250 ports
2966	*
2967	* Setup an 8250 port structure prior to console initialisation. Use
2968	* after console initialisation will cause undefined behaviour.
2969	*/
2970	int __init early_serial_setup(struct uart_port *port)
2971	{
2972	struct uart_port *p;
2973
2974	if (port->line >= ARRAY_SIZE(serial8250_ports))
2975	return -ENODEV;
2976
2977	serial8250_isa_init_ports();
2978	p = &serial8250_ports[port->line].port;
2979	p->iobase = port->iobase;
2980	p->membase = port->membase;
2981	p->irq = port->irq;
2982	p->irqflags = port->irqflags;
2983	p->uartclk = port->uartclk;
2984	p->fifosize = port->fifosize;
2985	p->regshift = port->regshift;
2986	p->iotype = port->iotype;
2987	p->flags = port->flags;
2988	p->mapbase = port->mapbase;
2989	p->private_data = port->private_data;
2990	p->type = port->type;
2991	p->line = port->line;
2992
2993	set_io_from_upio(p);
2994	if (port->serial_in)
2995	p->serial_in = port->serial_in;
2996	if (port->serial_out)
2997	p->serial_out = port->serial_out;
2998	if (port->handle_irq)
2999	p->handle_irq = port->handle_irq;
3000	else
3001	p->handle_irq = serial8250_default_handle_irq;
3002
3003	return 0;
3004	}
3005
3006	/**
3007	* serial8250_suspend_port - suspend one serial port
3008	* @line: serial line number
3009	*
3010	* Suspend one serial port.
3011	*/
3012	void serial8250_suspend_port(int line)
3013	{
3014	uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3015	}
3016
3017	/**
3018	* serial8250_resume_port - resume one serial port
3019	* @line: serial line number
3020	*
3021	* Resume one serial port.
3022	*/
3023	void serial8250_resume_port(int line)
3024	{
3025	struct uart_8250_port *up = &serial8250_ports[line];
3026
3027	if (up->capabilities & UART_NATSEMI) {
3028	/* Ensure it's still in high speed mode */
3029	serial_outp(up, UART_LCR, 0xE0);
3030
3031	ns16550a_goto_highspeed(up);
3032
3033	serial_outp(up, UART_LCR, 0);
3034	up->port.uartclk = 921600*16;
3035	}
3036	uart_resume_port(&serial8250_reg, &up->port);
3037	}
3038
3039	/*
3040	* Register a set of serial devices attached to a platform device. The
3041	* list is terminated with a zero flags entry, which means we expect
3042	* all entries to have at least UPF_BOOT_AUTOCONF set.
3043	*/
3044	static int __devinit serial8250_probe(struct platform_device *dev)
3045	{
3046	struct plat_serial8250_port *p = dev->dev.platform_data;
3047	struct uart_port port;
3048	int ret, i, irqflag = 0;
3049
3050	memset(&port, 0, sizeof(struct uart_port));
3051
3052	if (share_irqs)
3053	irqflag = IRQF_SHARED;
3054
3055	for (i = 0; p && p->flags != 0; p++, i++) {
3056	port.iobase = p->iobase;
3057	port.membase = p->membase;
3058	port.irq = p->irq;
3059	port.irqflags = p->irqflags;
3060	port.uartclk = p->uartclk;
3061	port.regshift = p->regshift;
3062	port.iotype = p->iotype;
3063	port.flags = p->flags;
3064	port.mapbase = p->mapbase;
3065	port.hub6 = p->hub6;
3066	port.private_data = p->private_data;
3067	port.type = p->type;
3068	port.serial_in = p->serial_in;
3069	port.serial_out = p->serial_out;
3070	port.handle_irq = p->handle_irq;
3071	port.set_termios = p->set_termios;
3072	port.pm = p->pm;
3073	port.dev = &dev->dev;
3074	port.rw_delay = p->rw_delay;
3075	port.irqflags \|= irqflag;
3076	ret = serial8250_register_port(&port);
3077	if (ret < 0) {
3078	dev_err(&dev->dev, "unable to register port at index %d "
3079	"(IO%lx MEM%llx IRQ%d): %d\n", i,
3080	p->iobase, (unsigned long long)p->mapbase,
3081	p->irq, ret);
3082	}
3083	}
3084	return 0;
3085	}
3086
3087	/*
3088	* Remove serial ports registered against a platform device.
3089	*/
3090	static int __devexit serial8250_remove(struct platform_device *dev)
3091	{
3092	int i;
3093
3094	for (i = 0; i < nr_uarts; i++) {
3095	struct uart_8250_port *up = &serial8250_ports[i];
3096
3097	if (up->port.dev == &dev->dev)
3098	serial8250_unregister_port(i);
3099	}
3100	return 0;
3101	}
3102
3103	static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3104	{
3105	int i;
3106
3107	for (i = 0; i < UART_NR; i++) {
3108	struct uart_8250_port *up = &serial8250_ports[i];
3109
3110	if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3111	uart_suspend_port(&serial8250_reg, &up->port);
3112	}
3113
3114	return 0;
3115	}
3116
3117	static int serial8250_resume(struct platform_device *dev)
3118	{
3119	int i;
3120
3121	for (i = 0; i < UART_NR; i++) {
3122	struct uart_8250_port *up = &serial8250_ports[i];
3123
3124	if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3125	serial8250_resume_port(i);
3126	}
3127
3128	return 0;
3129	}
3130
3131	static struct platform_driver serial8250_isa_driver = {
3132	.probe = serial8250_probe,
3133	.remove = __devexit_p(serial8250_remove),
3134	.suspend = serial8250_suspend,
3135	.resume = serial8250_resume,
3136	.driver = {
3137	.name = "serial8250",
3138	.owner = THIS_MODULE,
3139	},
3140	};
3141
3142	/*
3143	* This "device" covers _all_ ISA 8250-compatible serial devices listed
3144	* in the table in include/asm/serial.h
3145	*/
3146	static struct platform_device *serial8250_isa_devs;
3147
3148	/*
3149	* serial8250_register_port and serial8250_unregister_port allows for
3150	* 16x50 serial ports to be configured at run-time, to support PCMCIA
3151	* modems and PCI multiport cards.
3152	*/
3153	static DEFINE_MUTEX(serial_mutex);
3154
3155	static struct uart_8250_port serial8250_find_match_or_unused(struct uart_port port)
3156	{
3157	int i;
3158
3159	/*
3160	* First, find a port entry which matches.
3161	*/
3162	for (i = 0; i < nr_uarts; i++)
3163	if (uart_match_port(&serial8250_ports[i].port, port))
3164	return &serial8250_ports[i];
3165
3166	/*
3167	* We didn't find a matching entry, so look for the first
3168	* free entry. We look for one which hasn't been previously
3169	* used (indicated by zero iobase).
3170	*/
3171	for (i = 0; i < nr_uarts; i++)
3172	if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3173	serial8250_ports[i].port.iobase == 0)
3174	return &serial8250_ports[i];
3175
3176	/*
3177	* That also failed. Last resort is to find any entry which
3178	* doesn't have a real port associated with it.
3179	*/
3180	for (i = 0; i < nr_uarts; i++)
3181	if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3182	return &serial8250_ports[i];
3183
3184	return NULL;
3185	}
3186
3187	/**
3188	* serial8250_register_port - register a serial port
3189	* @port: serial port template
3190	*
3191	* Configure the serial port specified by the request. If the
3192	* port exists and is in use, it is hung up and unregistered
3193	* first.
3194	*
3195	* The port is then probed and if necessary the IRQ is autodetected
3196	* If this fails an error is returned.
3197	*
3198	* On success the port is ready to use and the line number is returned.
3199	*/
3200	int serial8250_register_port(struct uart_port *port)
3201	{
3202	struct uart_8250_port *uart;
3203	int ret = -ENOSPC;
3204
3205	if (port->uartclk == 0)
3206	return -EINVAL;
3207
3208	mutex_lock(&serial_mutex);
3209
3210	uart = serial8250_find_match_or_unused(port);
3211	if (uart) {
3212	uart_remove_one_port(&serial8250_reg, &uart->port);
3213
3214	uart->port.iobase = port->iobase;
3215	uart->port.membase = port->membase;
3216	uart->port.irq = port->irq;
3217	uart->port.irqflags = port->irqflags;
3218	uart->port.uartclk = port->uartclk;
3219	uart->port.fifosize = port->fifosize;
3220	uart->port.regshift = port->regshift;
3221	uart->port.iotype = port->iotype;
3222	uart->port.flags = port->flags \| UPF_BOOT_AUTOCONF;
3223	uart->port.mapbase = port->mapbase;
3224	uart->port.rw_delay = port->rw_delay;
3225	uart->port.private_data = port->private_data;
3226	if (port->dev)
3227	uart->port.dev = port->dev;
3228
3229	if (port->flags & UPF_FIXED_TYPE)
3230	serial8250_init_fixed_type_port(uart, port->type);
3231
3232	set_io_from_upio(&uart->port);
3233	/* Possibly override default I/O functions. */
3234	if (port->serial_in)
3235	uart->port.serial_in = port->serial_in;
3236	if (port->serial_out)
3237	uart->port.serial_out = port->serial_out;
3238	if (port->handle_irq)
3239	uart->port.handle_irq = port->handle_irq;
3240	/* Possibly override set_termios call */
3241	if (port->set_termios)
3242	uart->port.set_termios = port->set_termios;
3243	if (port->pm)
3244	uart->port.pm = port->pm;
3245
3246	if (serial8250_isa_config != NULL)
3247	serial8250_isa_config(0, &uart->port,
3248	&uart->capabilities);
3249
3250	ret = uart_add_one_port(&serial8250_reg, &uart->port);
3251	if (ret == 0)
3252	ret = uart->port.line;
3253	}
3254	mutex_unlock(&serial_mutex);
3255
3256	return ret;
3257	}
3258	EXPORT_SYMBOL(serial8250_register_port);
3259
3260	/**
3261	* serial8250_unregister_port - remove a 16x50 serial port at runtime
3262	* @line: serial line number
3263	*
3264	* Remove one serial port. This may not be called from interrupt
3265	* context. We hand the port back to the our control.
3266	*/
3267	void serial8250_unregister_port(int line)
3268	{
3269	struct uart_8250_port *uart = &serial8250_ports[line];
3270
3271	mutex_lock(&serial_mutex);
3272	uart_remove_one_port(&serial8250_reg, &uart->port);
3273	if (serial8250_isa_devs) {
3274	uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3275	uart->port.type = PORT_UNKNOWN;
3276	uart->port.dev = &serial8250_isa_devs->dev;
3277	uart->capabilities = uart_config[uart->port.type].flags;
3278	uart_add_one_port(&serial8250_reg, &uart->port);
3279	} else {
3280	uart->port.dev = NULL;
3281	}
3282	mutex_unlock(&serial_mutex);
3283	}
3284	EXPORT_SYMBOL(serial8250_unregister_port);
3285
3286	static int __init serial8250_init(void)
3287	{
3288	int ret;
3289
3290	if (nr_uarts > UART_NR)
3291	nr_uarts = UART_NR;
3292
3293	printk(KERN_INFO "Serial: 8250/16550 driver, "
3294	"%d ports, IRQ sharing %sabled\n", nr_uarts,
3295	share_irqs ? "en" : "dis");
3296
3297	#ifdef CONFIG_SPARC
3298	ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3299	#else
3300	serial8250_reg.nr = UART_NR;
3301	ret = uart_register_driver(&serial8250_reg);
3302	#endif
3303	if (ret)
3304	goto out;
3305
3306	serial8250_isa_devs = platform_device_alloc("serial8250",
3307	PLAT8250_DEV_LEGACY);
3308	if (!serial8250_isa_devs) {
3309	ret = -ENOMEM;
3310	goto unreg_uart_drv;
3311	}
3312
3313	ret = platform_device_add(serial8250_isa_devs);
3314	if (ret)
3315	goto put_dev;
3316
3317	serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3318
3319	ret = platform_driver_register(&serial8250_isa_driver);
3320	if (ret == 0)
3321	goto out;
3322
3323	platform_device_del(serial8250_isa_devs);
3324	put_dev:
3325	platform_device_put(serial8250_isa_devs);
3326	unreg_uart_drv:
3327	#ifdef CONFIG_SPARC
3328	sunserial_unregister_minors(&serial8250_reg, UART_NR);
3329	#else
3330	uart_unregister_driver(&serial8250_reg);
3331	#endif
3332	out:
3333	return ret;
3334	}
3335
3336	static void __exit serial8250_exit(void)
3337	{
3338	struct platform_device *isa_dev = serial8250_isa_devs;
3339
3340	/*
3341	* This tells serial8250_unregister_port() not to re-register
3342	* the ports (thereby making serial8250_isa_driver permanently
3343	* in use.)
3344	*/
3345	serial8250_isa_devs = NULL;
3346
3347	platform_driver_unregister(&serial8250_isa_driver);
3348	platform_device_unregister(isa_dev);
3349
3350	#ifdef CONFIG_SPARC
3351	sunserial_unregister_minors(&serial8250_reg, UART_NR);
3352	#else
3353	uart_unregister_driver(&serial8250_reg);
3354	#endif
3355	}
3356
3357	module_init(serial8250_init);
3358	module_exit(serial8250_exit);
3359
3360	EXPORT_SYMBOL(serial8250_suspend_port);
3361	EXPORT_SYMBOL(serial8250_resume_port);
3362
3363	MODULE_LICENSE("GPL");
3364	MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3365
3366	module_param(share_irqs, uint, 0644);
3367	MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3368	" (unsafe)");
3369
3370	module_param(nr_uarts, uint, 0644);
3371	MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3372
3373	module_param(skip_txen_test, uint, 0644);
3374	MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3375
3376	#ifdef CONFIG_SERIAL_8250_RSA
3377	module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3378	MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3379	#endif
3380	MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);

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