source: src/linux/universal/linux-4.4/arch/mips/kernel/asm-offsets.c @ 31884

Last change on this file since 31884 was 31884, checked in by brainslayer, 8 days ago

update kernels

File size: 15.5 KB
Line 
1/*
2 * asm-offsets.c: Calculate pt_regs and task_struct offsets.
3 *
4 * Copyright (C) 1996 David S. Miller
5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 *
8 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 */
11#include <linux/compat.h>
12#include <linux/types.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/kbuild.h>
16#include <linux/suspend.h>
17#include <asm/pm.h>
18#include <asm/ptrace.h>
19#include <asm/processor.h>
20#include <asm/smp-cps.h>
21
22#include <linux/kvm_host.h>
23
24void output_ptreg_defines(void)
25{
26        COMMENT("MIPS pt_regs offsets.");
27        OFFSET(PT_R0, pt_regs, regs[0]);
28        OFFSET(PT_R1, pt_regs, regs[1]);
29        OFFSET(PT_R2, pt_regs, regs[2]);
30        OFFSET(PT_R3, pt_regs, regs[3]);
31        OFFSET(PT_R4, pt_regs, regs[4]);
32        OFFSET(PT_R5, pt_regs, regs[5]);
33        OFFSET(PT_R6, pt_regs, regs[6]);
34        OFFSET(PT_R7, pt_regs, regs[7]);
35        OFFSET(PT_R8, pt_regs, regs[8]);
36        OFFSET(PT_R9, pt_regs, regs[9]);
37        OFFSET(PT_R10, pt_regs, regs[10]);
38        OFFSET(PT_R11, pt_regs, regs[11]);
39        OFFSET(PT_R12, pt_regs, regs[12]);
40        OFFSET(PT_R13, pt_regs, regs[13]);
41        OFFSET(PT_R14, pt_regs, regs[14]);
42        OFFSET(PT_R15, pt_regs, regs[15]);
43        OFFSET(PT_R16, pt_regs, regs[16]);
44        OFFSET(PT_R17, pt_regs, regs[17]);
45        OFFSET(PT_R18, pt_regs, regs[18]);
46        OFFSET(PT_R19, pt_regs, regs[19]);
47        OFFSET(PT_R20, pt_regs, regs[20]);
48        OFFSET(PT_R21, pt_regs, regs[21]);
49        OFFSET(PT_R22, pt_regs, regs[22]);
50        OFFSET(PT_R23, pt_regs, regs[23]);
51        OFFSET(PT_R24, pt_regs, regs[24]);
52        OFFSET(PT_R25, pt_regs, regs[25]);
53        OFFSET(PT_R26, pt_regs, regs[26]);
54        OFFSET(PT_R27, pt_regs, regs[27]);
55        OFFSET(PT_R28, pt_regs, regs[28]);
56        OFFSET(PT_R29, pt_regs, regs[29]);
57        OFFSET(PT_R30, pt_regs, regs[30]);
58        OFFSET(PT_R31, pt_regs, regs[31]);
59        OFFSET(PT_LO, pt_regs, lo);
60        OFFSET(PT_HI, pt_regs, hi);
61#ifdef CONFIG_CPU_HAS_SMARTMIPS
62        OFFSET(PT_ACX, pt_regs, acx);
63#endif
64        OFFSET(PT_EPC, pt_regs, cp0_epc);
65        OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
66        OFFSET(PT_STATUS, pt_regs, cp0_status);
67        OFFSET(PT_CAUSE, pt_regs, cp0_cause);
68#ifdef CONFIG_CPU_CAVIUM_OCTEON
69        OFFSET(PT_MPL, pt_regs, mpl);
70        OFFSET(PT_MTP, pt_regs, mtp);
71#endif /* CONFIG_CPU_CAVIUM_OCTEON */
72        DEFINE(PT_SIZE, sizeof(struct pt_regs));
73        BLANK();
74}
75
76void output_task_defines(void)
77{
78        COMMENT("MIPS task_struct offsets.");
79        OFFSET(TASK_STATE, task_struct, state);
80        OFFSET(TASK_THREAD_INFO, task_struct, stack);
81        OFFSET(TASK_FLAGS, task_struct, flags);
82        OFFSET(TASK_MM, task_struct, mm);
83        OFFSET(TASK_PID, task_struct, pid);
84#if defined(CONFIG_CC_STACKPROTECTOR)
85        OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
86#endif
87        DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
88        BLANK();
89}
90
91void output_thread_info_defines(void)
92{
93        COMMENT("MIPS thread_info offsets.");
94        OFFSET(TI_TASK, thread_info, task);
95        OFFSET(TI_FLAGS, thread_info, flags);
96        OFFSET(TI_TP_VALUE, thread_info, tp_value);
97        OFFSET(TI_CPU, thread_info, cpu);
98        OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
99        OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return);
100        OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
101        OFFSET(TI_REGS, thread_info, regs);
102        DEFINE(_THREAD_SIZE, THREAD_SIZE);
103        DEFINE(_THREAD_MASK, THREAD_MASK);
104        DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
105        BLANK();
106}
107
108void output_thread_defines(void)
109{
110        COMMENT("MIPS specific thread_struct offsets.");
111        OFFSET(THREAD_REG16, task_struct, thread.reg16);
112        OFFSET(THREAD_REG17, task_struct, thread.reg17);
113        OFFSET(THREAD_REG18, task_struct, thread.reg18);
114        OFFSET(THREAD_REG19, task_struct, thread.reg19);
115        OFFSET(THREAD_REG20, task_struct, thread.reg20);
116        OFFSET(THREAD_REG21, task_struct, thread.reg21);
117        OFFSET(THREAD_REG22, task_struct, thread.reg22);
118        OFFSET(THREAD_REG23, task_struct, thread.reg23);
119        OFFSET(THREAD_REG29, task_struct, thread.reg29);
120        OFFSET(THREAD_REG30, task_struct, thread.reg30);
121        OFFSET(THREAD_REG31, task_struct, thread.reg31);
122        OFFSET(THREAD_STATUS, task_struct,
123               thread.cp0_status);
124        OFFSET(THREAD_FPU, task_struct, thread.fpu);
125
126        OFFSET(THREAD_BVADDR, task_struct, \
127               thread.cp0_badvaddr);
128        OFFSET(THREAD_BUADDR, task_struct, \
129               thread.cp0_baduaddr);
130        OFFSET(THREAD_ECODE, task_struct, \
131               thread.error_code);
132        OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
133        BLANK();
134}
135
136void output_thread_fpu_defines(void)
137{
138        OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
139        OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
140        OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
141        OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
142        OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
143        OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
144        OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
145        OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
146        OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
147        OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
148        OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
149        OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
150        OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
151        OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
152        OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
153        OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
154        OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
155        OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
156        OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
157        OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
158        OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
159        OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
160        OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
161        OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
162        OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
163        OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
164        OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
165        OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
166        OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
167        OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
168        OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
169        OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
170
171        OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
172        OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
173        BLANK();
174}
175
176void output_mm_defines(void)
177{
178        COMMENT("Size of struct page");
179        DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
180        BLANK();
181        COMMENT("Linux mm_struct offsets.");
182        OFFSET(MM_USERS, mm_struct, mm_users);
183        OFFSET(MM_PGD, mm_struct, pgd);
184        OFFSET(MM_CONTEXT, mm_struct, context);
185        BLANK();
186        DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
187        DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
188        DEFINE(_PTE_T_SIZE, sizeof(pte_t));
189        BLANK();
190        DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
191#ifndef __PAGETABLE_PMD_FOLDED
192        DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
193#endif
194        DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
195        BLANK();
196        DEFINE(_PGD_ORDER, PGD_ORDER);
197#ifndef __PAGETABLE_PMD_FOLDED
198        DEFINE(_PMD_ORDER, PMD_ORDER);
199#endif
200        DEFINE(_PTE_ORDER, PTE_ORDER);
201        BLANK();
202        DEFINE(_PMD_SHIFT, PMD_SHIFT);
203        DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
204        BLANK();
205        DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
206        DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
207        DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
208        BLANK();
209        DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
210        DEFINE(_PAGE_SIZE, PAGE_SIZE);
211        BLANK();
212}
213
214#ifdef CONFIG_32BIT
215void output_sc_defines(void)
216{
217        COMMENT("Linux sigcontext offsets.");
218        OFFSET(SC_REGS, sigcontext, sc_regs);
219        OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
220        OFFSET(SC_ACX, sigcontext, sc_acx);
221        OFFSET(SC_MDHI, sigcontext, sc_mdhi);
222        OFFSET(SC_MDLO, sigcontext, sc_mdlo);
223        OFFSET(SC_PC, sigcontext, sc_pc);
224        OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
225        OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
226        OFFSET(SC_HI1, sigcontext, sc_hi1);
227        OFFSET(SC_LO1, sigcontext, sc_lo1);
228        OFFSET(SC_HI2, sigcontext, sc_hi2);
229        OFFSET(SC_LO2, sigcontext, sc_lo2);
230        OFFSET(SC_HI3, sigcontext, sc_hi3);
231        OFFSET(SC_LO3, sigcontext, sc_lo3);
232        BLANK();
233}
234#endif
235
236#ifdef CONFIG_64BIT
237void output_sc_defines(void)
238{
239        COMMENT("Linux sigcontext offsets.");
240        OFFSET(SC_REGS, sigcontext, sc_regs);
241        OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
242        OFFSET(SC_MDHI, sigcontext, sc_mdhi);
243        OFFSET(SC_MDLO, sigcontext, sc_mdlo);
244        OFFSET(SC_PC, sigcontext, sc_pc);
245        OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
246        BLANK();
247}
248#endif
249
250void output_signal_defined(void)
251{
252        COMMENT("Linux signal numbers.");
253        DEFINE(_SIGHUP, SIGHUP);
254        DEFINE(_SIGINT, SIGINT);
255        DEFINE(_SIGQUIT, SIGQUIT);
256        DEFINE(_SIGILL, SIGILL);
257        DEFINE(_SIGTRAP, SIGTRAP);
258        DEFINE(_SIGIOT, SIGIOT);
259        DEFINE(_SIGABRT, SIGABRT);
260        DEFINE(_SIGEMT, SIGEMT);
261        DEFINE(_SIGFPE, SIGFPE);
262        DEFINE(_SIGKILL, SIGKILL);
263        DEFINE(_SIGBUS, SIGBUS);
264        DEFINE(_SIGSEGV, SIGSEGV);
265        DEFINE(_SIGSYS, SIGSYS);
266        DEFINE(_SIGPIPE, SIGPIPE);
267        DEFINE(_SIGALRM, SIGALRM);
268        DEFINE(_SIGTERM, SIGTERM);
269        DEFINE(_SIGUSR1, SIGUSR1);
270        DEFINE(_SIGUSR2, SIGUSR2);
271        DEFINE(_SIGCHLD, SIGCHLD);
272        DEFINE(_SIGPWR, SIGPWR);
273        DEFINE(_SIGWINCH, SIGWINCH);
274        DEFINE(_SIGURG, SIGURG);
275        DEFINE(_SIGIO, SIGIO);
276        DEFINE(_SIGSTOP, SIGSTOP);
277        DEFINE(_SIGTSTP, SIGTSTP);
278        DEFINE(_SIGCONT, SIGCONT);
279        DEFINE(_SIGTTIN, SIGTTIN);
280        DEFINE(_SIGTTOU, SIGTTOU);
281        DEFINE(_SIGVTALRM, SIGVTALRM);
282        DEFINE(_SIGPROF, SIGPROF);
283        DEFINE(_SIGXCPU, SIGXCPU);
284        DEFINE(_SIGXFSZ, SIGXFSZ);
285        BLANK();
286}
287
288#ifdef CONFIG_CPU_CAVIUM_OCTEON
289void output_octeon_cop2_state_defines(void)
290{
291        COMMENT("Octeon specific octeon_cop2_state offsets.");
292        OFFSET(OCTEON_CP2_CRC_IV,       octeon_cop2_state, cop2_crc_iv);
293        OFFSET(OCTEON_CP2_CRC_LENGTH,   octeon_cop2_state, cop2_crc_length);
294        OFFSET(OCTEON_CP2_CRC_POLY,     octeon_cop2_state, cop2_crc_poly);
295        OFFSET(OCTEON_CP2_LLM_DAT,      octeon_cop2_state, cop2_llm_dat);
296        OFFSET(OCTEON_CP2_3DES_IV,      octeon_cop2_state, cop2_3des_iv);
297        OFFSET(OCTEON_CP2_3DES_KEY,     octeon_cop2_state, cop2_3des_key);
298        OFFSET(OCTEON_CP2_3DES_RESULT,  octeon_cop2_state, cop2_3des_result);
299        OFFSET(OCTEON_CP2_AES_INP0,     octeon_cop2_state, cop2_aes_inp0);
300        OFFSET(OCTEON_CP2_AES_IV,       octeon_cop2_state, cop2_aes_iv);
301        OFFSET(OCTEON_CP2_AES_KEY,      octeon_cop2_state, cop2_aes_key);
302        OFFSET(OCTEON_CP2_AES_KEYLEN,   octeon_cop2_state, cop2_aes_keylen);
303        OFFSET(OCTEON_CP2_AES_RESULT,   octeon_cop2_state, cop2_aes_result);
304        OFFSET(OCTEON_CP2_GFM_MULT,     octeon_cop2_state, cop2_gfm_mult);
305        OFFSET(OCTEON_CP2_GFM_POLY,     octeon_cop2_state, cop2_gfm_poly);
306        OFFSET(OCTEON_CP2_GFM_RESULT,   octeon_cop2_state, cop2_gfm_result);
307        OFFSET(OCTEON_CP2_HSH_DATW,     octeon_cop2_state, cop2_hsh_datw);
308        OFFSET(OCTEON_CP2_HSH_IVW,      octeon_cop2_state, cop2_hsh_ivw);
309        OFFSET(OCTEON_CP2_SHA3,         octeon_cop2_state, cop2_sha3);
310        OFFSET(THREAD_CP2,      task_struct, thread.cp2);
311        OFFSET(THREAD_CVMSEG,   task_struct, thread.cvmseg.cvmseg);
312        BLANK();
313}
314#endif
315
316#ifdef CONFIG_HIBERNATION
317void output_pbe_defines(void)
318{
319        COMMENT(" Linux struct pbe offsets. ");
320        OFFSET(PBE_ADDRESS, pbe, address);
321        OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
322        OFFSET(PBE_NEXT, pbe, next);
323        DEFINE(PBE_SIZE, sizeof(struct pbe));
324        BLANK();
325}
326#endif
327
328#ifdef CONFIG_CPU_PM
329void output_pm_defines(void)
330{
331        COMMENT(" PM offsets. ");
332#ifdef CONFIG_EVA
333        OFFSET(SSS_SEGCTL0,     mips_static_suspend_state, segctl[0]);
334        OFFSET(SSS_SEGCTL1,     mips_static_suspend_state, segctl[1]);
335        OFFSET(SSS_SEGCTL2,     mips_static_suspend_state, segctl[2]);
336#endif
337        OFFSET(SSS_SP,          mips_static_suspend_state, sp);
338        BLANK();
339}
340#endif
341
342void output_kvm_defines(void)
343{
344        COMMENT(" KVM/MIPS Specfic offsets. ");
345        DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
346        OFFSET(VCPU_RUN, kvm_vcpu, run);
347        OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
348
349        OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
350        OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
351
352        OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
353        OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
354
355        OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
356        OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
357        OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
358        OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
359
360        OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
361
362        OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
363        OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
364        OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
365        OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
366        OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
367        OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
368        OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
369        OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
370        OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
371        OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
372        OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
373        OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
374        OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
375        OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
376        OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
377        OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
378        OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
379        OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
380        OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
381        OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
382        OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
383        OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
384        OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
385        OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
386        OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
387        OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
388        OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
389        OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
390        OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
391        OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
392        OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
393        OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
394        OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
395        OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
396        OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
397        BLANK();
398
399        OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
400        OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
401        OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
402        OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
403        OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
404        OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
405        OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
406        OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
407        OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
408        OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
409        OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
410        OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
411        OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
412        OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
413        OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
414        OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
415        OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
416        OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
417        OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
418        OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
419        OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
420        OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
421        OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
422        OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
423        OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
424        OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
425        OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
426        OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
427        OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
428        OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
429        OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
430        OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
431
432        OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
433        OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
434        BLANK();
435
436        OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
437        OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
438        OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
439
440        OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
441        OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
442        BLANK();
443}
444
445#ifdef CONFIG_MIPS_CPS
446void output_cps_defines(void)
447{
448        COMMENT(" MIPS CPS offsets. ");
449
450        OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
451        OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
452        DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
453
454        OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
455        OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
456        OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
457        DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
458}
459#endif
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