source: src/linux/universal/linux-4.4/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @ 31662

Last change on this file since 31662 was 31662, checked in by brainslayer, 7 weeks ago

use new squashfs in all kernels

File size: 116.3 KB
Line 
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_11_0_d.h"
36#include "dce/dce_11_0_sh_mask.h"
37#include "dce/dce_11_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48        CRTC0_REGISTER_OFFSET,
49        CRTC1_REGISTER_OFFSET,
50        CRTC2_REGISTER_OFFSET,
51        CRTC3_REGISTER_OFFSET,
52        CRTC4_REGISTER_OFFSET,
53        CRTC5_REGISTER_OFFSET,
54        CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59        HPD0_REGISTER_OFFSET,
60        HPD1_REGISTER_OFFSET,
61        HPD2_REGISTER_OFFSET,
62        HPD3_REGISTER_OFFSET,
63        HPD4_REGISTER_OFFSET,
64        HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68        DIG0_REGISTER_OFFSET,
69        DIG1_REGISTER_OFFSET,
70        DIG2_REGISTER_OFFSET,
71        DIG3_REGISTER_OFFSET,
72        DIG4_REGISTER_OFFSET,
73        DIG5_REGISTER_OFFSET,
74        DIG6_REGISTER_OFFSET,
75        DIG7_REGISTER_OFFSET,
76        DIG8_REGISTER_OFFSET
77};
78
79static const struct {
80        uint32_t        reg;
81        uint32_t        vblank;
82        uint32_t        vline;
83        uint32_t        hpd;
84
85} interrupt_status_offsets[] = { {
86        .reg = mmDISP_INTERRUPT_STATUS,
87        .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88        .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89        .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90}, {
91        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92        .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93        .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94        .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95}, {
96        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97        .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98        .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99        .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100}, {
101        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102        .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103        .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104        .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105}, {
106        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107        .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108        .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109        .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110}, {
111        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112        .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113        .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114        .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115} };
116
117static const u32 cz_golden_settings_a11[] =
118{
119        mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120        mmFBC_MISC, 0x1f311fff, 0x14300000,
121};
122
123static const u32 cz_mgcg_cgcg_init[] =
124{
125        mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126        mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
129static const u32 stoney_golden_settings_a11[] =
130{
131        mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132        mmFBC_MISC, 0x1f311fff, 0x14302000,
133};
134
135
136static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
137{
138        switch (adev->asic_type) {
139        case CHIP_CARRIZO:
140                amdgpu_program_register_sequence(adev,
141                                                 cz_mgcg_cgcg_init,
142                                                 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
143                amdgpu_program_register_sequence(adev,
144                                                 cz_golden_settings_a11,
145                                                 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
146                break;
147        case CHIP_STONEY:
148                amdgpu_program_register_sequence(adev,
149                                                 stoney_golden_settings_a11,
150                                                 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
151                break;
152        default:
153                break;
154        }
155}
156
157static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
158                                     u32 block_offset, u32 reg)
159{
160        unsigned long flags;
161        u32 r;
162
163        spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
164        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
165        r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
166        spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
167
168        return r;
169}
170
171static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
172                                      u32 block_offset, u32 reg, u32 v)
173{
174        unsigned long flags;
175
176        spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
177        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
178        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
179        spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
180}
181
182static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
183{
184        if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
185                        CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
186                return true;
187        else
188                return false;
189}
190
191static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
192{
193        u32 pos1, pos2;
194
195        pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
196        pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
197
198        if (pos1 != pos2)
199                return true;
200        else
201                return false;
202}
203
204/**
205 * dce_v11_0_vblank_wait - vblank wait asic callback.
206 *
207 * @adev: amdgpu_device pointer
208 * @crtc: crtc to wait for vblank on
209 *
210 * Wait for vblank on the requested crtc (evergreen+).
211 */
212static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
213{
214        unsigned i = 0;
215
216        if (crtc >= adev->mode_info.num_crtc)
217                return;
218
219        if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
220                return;
221
222        /* depending on when we hit vblank, we may be close to active; if so,
223         * wait for another frame.
224         */
225        while (dce_v11_0_is_in_vblank(adev, crtc)) {
226                if (i++ % 100 == 0) {
227                        if (!dce_v11_0_is_counter_moving(adev, crtc))
228                                break;
229                }
230        }
231
232        while (!dce_v11_0_is_in_vblank(adev, crtc)) {
233                if (i++ % 100 == 0) {
234                        if (!dce_v11_0_is_counter_moving(adev, crtc))
235                                break;
236                }
237        }
238}
239
240static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
241{
242        if (crtc >= adev->mode_info.num_crtc)
243                return 0;
244        else
245                return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
246}
247
248static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
249{
250        unsigned i;
251
252        /* Enable pflip interrupts */
253        for (i = 0; i < adev->mode_info.num_crtc; i++)
254                amdgpu_irq_get(adev, &adev->pageflip_irq, i);
255}
256
257static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
258{
259        unsigned i;
260
261        /* Disable pflip interrupts */
262        for (i = 0; i < adev->mode_info.num_crtc; i++)
263                amdgpu_irq_put(adev, &adev->pageflip_irq, i);
264}
265
266/**
267 * dce_v11_0_page_flip - pageflip callback.
268 *
269 * @adev: amdgpu_device pointer
270 * @crtc_id: crtc to cleanup pageflip on
271 * @crtc_base: new address of the crtc (GPU MC address)
272 *
273 * Triggers the actual pageflip by updating the primary
274 * surface base address.
275 */
276static void dce_v11_0_page_flip(struct amdgpu_device *adev,
277                              int crtc_id, u64 crtc_base)
278{
279        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
280
281        /* update the scanout addresses */
282        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
283               upper_32_bits(crtc_base));
284        /* writing to the low address triggers the update */
285        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
286               lower_32_bits(crtc_base));
287        /* post the write */
288        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
289}
290
291static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
292                                        u32 *vbl, u32 *position)
293{
294        if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
295                return -EINVAL;
296
297        *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
298        *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
299
300        return 0;
301}
302
303/**
304 * dce_v11_0_hpd_sense - hpd sense callback.
305 *
306 * @adev: amdgpu_device pointer
307 * @hpd: hpd (hotplug detect) pin
308 *
309 * Checks if a digital monitor is connected (evergreen+).
310 * Returns true if connected, false if not connected.
311 */
312static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
313                               enum amdgpu_hpd_id hpd)
314{
315        int idx;
316        bool connected = false;
317
318        switch (hpd) {
319        case AMDGPU_HPD_1:
320                idx = 0;
321                break;
322        case AMDGPU_HPD_2:
323                idx = 1;
324                break;
325        case AMDGPU_HPD_3:
326                idx = 2;
327                break;
328        case AMDGPU_HPD_4:
329                idx = 3;
330                break;
331        case AMDGPU_HPD_5:
332                idx = 4;
333                break;
334        case AMDGPU_HPD_6:
335                idx = 5;
336                break;
337        default:
338                return connected;
339        }
340
341        if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
342            DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
343                connected = true;
344
345        return connected;
346}
347
348/**
349 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
350 *
351 * @adev: amdgpu_device pointer
352 * @hpd: hpd (hotplug detect) pin
353 *
354 * Set the polarity of the hpd pin (evergreen+).
355 */
356static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
357                                      enum amdgpu_hpd_id hpd)
358{
359        u32 tmp;
360        bool connected = dce_v11_0_hpd_sense(adev, hpd);
361        int idx;
362
363        switch (hpd) {
364        case AMDGPU_HPD_1:
365                idx = 0;
366                break;
367        case AMDGPU_HPD_2:
368                idx = 1;
369                break;
370        case AMDGPU_HPD_3:
371                idx = 2;
372                break;
373        case AMDGPU_HPD_4:
374                idx = 3;
375                break;
376        case AMDGPU_HPD_5:
377                idx = 4;
378                break;
379        case AMDGPU_HPD_6:
380                idx = 5;
381                break;
382        default:
383                return;
384        }
385
386        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
387        if (connected)
388                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
389        else
390                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
391        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
392}
393
394/**
395 * dce_v11_0_hpd_init - hpd setup callback.
396 *
397 * @adev: amdgpu_device pointer
398 *
399 * Setup the hpd pins used by the card (evergreen+).
400 * Enable the pin, set the polarity, and enable the hpd interrupts.
401 */
402static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
403{
404        struct drm_device *dev = adev->ddev;
405        struct drm_connector *connector;
406        u32 tmp;
407        int idx;
408
409        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
410                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
411
412                switch (amdgpu_connector->hpd.hpd) {
413                case AMDGPU_HPD_1:
414                        idx = 0;
415                        break;
416                case AMDGPU_HPD_2:
417                        idx = 1;
418                        break;
419                case AMDGPU_HPD_3:
420                        idx = 2;
421                        break;
422                case AMDGPU_HPD_4:
423                        idx = 3;
424                        break;
425                case AMDGPU_HPD_5:
426                        idx = 4;
427                        break;
428                case AMDGPU_HPD_6:
429                        idx = 5;
430                        break;
431                default:
432                        continue;
433                }
434
435                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
436                    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
437                        /* don't try to enable hpd on eDP or LVDS avoid breaking the
438                         * aux dp channel on imac and help (but not completely fix)
439                         * https://bugzilla.redhat.com/show_bug.cgi?id=726143
440                         * also avoid interrupt storms during dpms.
441                         */
442                        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
443                        tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
444                        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
445                        continue;
446                }
447
448                tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
449                tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
450                WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
451
452                tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
453                tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
454                                    DC_HPD_CONNECT_INT_DELAY,
455                                    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
456                tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
457                                    DC_HPD_DISCONNECT_INT_DELAY,
458                                    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
459                WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
460
461                dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
462                amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
463        }
464}
465
466/**
467 * dce_v11_0_hpd_fini - hpd tear down callback.
468 *
469 * @adev: amdgpu_device pointer
470 *
471 * Tear down the hpd pins used by the card (evergreen+).
472 * Disable the hpd interrupts.
473 */
474static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
475{
476        struct drm_device *dev = adev->ddev;
477        struct drm_connector *connector;
478        u32 tmp;
479        int idx;
480
481        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
482                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
483
484                switch (amdgpu_connector->hpd.hpd) {
485                case AMDGPU_HPD_1:
486                        idx = 0;
487                        break;
488                case AMDGPU_HPD_2:
489                        idx = 1;
490                        break;
491                case AMDGPU_HPD_3:
492                        idx = 2;
493                        break;
494                case AMDGPU_HPD_4:
495                        idx = 3;
496                        break;
497                case AMDGPU_HPD_5:
498                        idx = 4;
499                        break;
500                case AMDGPU_HPD_6:
501                        idx = 5;
502                        break;
503                default:
504                        continue;
505                }
506
507                tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
508                tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
509                WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
510
511                amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
512        }
513}
514
515static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
516{
517        return mmDC_GPIO_HPD_A;
518}
519
520static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
521{
522        u32 crtc_hung = 0;
523        u32 crtc_status[6];
524        u32 i, j, tmp;
525
526        for (i = 0; i < adev->mode_info.num_crtc; i++) {
527                tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
528                if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
529                        crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
530                        crtc_hung |= (1 << i);
531                }
532        }
533
534        for (j = 0; j < 10; j++) {
535                for (i = 0; i < adev->mode_info.num_crtc; i++) {
536                        if (crtc_hung & (1 << i)) {
537                                tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
538                                if (tmp != crtc_status[i])
539                                        crtc_hung &= ~(1 << i);
540                        }
541                }
542                if (crtc_hung == 0)
543                        return false;
544                udelay(100);
545        }
546
547        return true;
548}
549
550static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
551                                     struct amdgpu_mode_mc_save *save)
552{
553        u32 crtc_enabled, tmp;
554        int i;
555
556        save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
557        save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
558
559        /* disable VGA render */
560        tmp = RREG32(mmVGA_RENDER_CONTROL);
561        tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
562        WREG32(mmVGA_RENDER_CONTROL, tmp);
563
564        /* blank the display controllers */
565        for (i = 0; i < adev->mode_info.num_crtc; i++) {
566                crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
567                                             CRTC_CONTROL, CRTC_MASTER_EN);
568                if (crtc_enabled) {
569#if 0
570                        u32 frame_count;
571                        int j;
572
573                        save->crtc_enabled[i] = true;
574                        tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
575                        if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
576                                amdgpu_display_vblank_wait(adev, i);
577                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
578                                tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
579                                WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
580                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
581                        }
582                        /* wait for the next frame */
583                        frame_count = amdgpu_display_vblank_get_counter(adev, i);
584                        for (j = 0; j < adev->usec_timeout; j++) {
585                                if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
586                                        break;
587                                udelay(1);
588                        }
589                        tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
590                        if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
591                                tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
592                                WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
593                        }
594                        tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
595                        if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
596                                tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
597                                WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
598                        }
599#else
600                        /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
601                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
602                        tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
603                        tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
604                        WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
605                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
606                        save->crtc_enabled[i] = false;
607                        /* ***** */
608#endif
609                } else {
610                        save->crtc_enabled[i] = false;
611                }
612        }
613}
614
615static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
616                                       struct amdgpu_mode_mc_save *save)
617{
618        u32 tmp, frame_count;
619        int i, j;
620
621        /* update crtc base addresses */
622        for (i = 0; i < adev->mode_info.num_crtc; i++) {
623                WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
624                       upper_32_bits(adev->mc.vram_start));
625                WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
626                       upper_32_bits(adev->mc.vram_start));
627                WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
628                       (u32)adev->mc.vram_start);
629                WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
630                       (u32)adev->mc.vram_start);
631
632                if (save->crtc_enabled[i]) {
633                        tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
634                        if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
635                                tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
636                                WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
637                        }
638                        tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
639                        if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
640                                tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
641                                WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
642                        }
643                        tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
644                        if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
645                                tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
646                                WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
647                        }
648                        for (j = 0; j < adev->usec_timeout; j++) {
649                                tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
650                                if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
651                                        break;
652                                udelay(1);
653                        }
654                        tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
655                        tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
656                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
657                        WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
658                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
659                        /* wait for the next frame */
660                        frame_count = amdgpu_display_vblank_get_counter(adev, i);
661                        for (j = 0; j < adev->usec_timeout; j++) {
662                                if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
663                                        break;
664                                udelay(1);
665                        }
666                }
667        }
668
669        WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
670        WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
671
672        /* Unlock vga access */
673        WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
674        mdelay(1);
675        WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
676}
677
678static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
679                                           bool render)
680{
681        u32 tmp;
682
683        /* Lockout access through VGA aperture*/
684        tmp = RREG32(mmVGA_HDP_CONTROL);
685        if (render)
686                tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
687        else
688                tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
689        WREG32(mmVGA_HDP_CONTROL, tmp);
690
691        /* disable VGA render */
692        tmp = RREG32(mmVGA_RENDER_CONTROL);
693        if (render)
694                tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
695        else
696                tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
697        WREG32(mmVGA_RENDER_CONTROL, tmp);
698}
699
700static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
701{
702        struct drm_device *dev = encoder->dev;
703        struct amdgpu_device *adev = dev->dev_private;
704        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
705        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
706        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
707        int bpc = 0;
708        u32 tmp = 0;
709        enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
710
711        if (connector) {
712                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
713                bpc = amdgpu_connector_get_monitor_bpc(connector);
714                dither = amdgpu_connector->dither;
715        }
716
717        /* LVDS/eDP FMT is set up by atom */
718        if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
719                return;
720
721        /* not needed for analog */
722        if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
723            (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
724                return;
725
726        if (bpc == 0)
727                return;
728
729        switch (bpc) {
730        case 6:
731                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
732                        /* XXX sort out optimal dither settings */
733                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
734                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
735                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
736                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
737                } else {
738                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
739                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
740                }
741                break;
742        case 8:
743                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
744                        /* XXX sort out optimal dither settings */
745                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
746                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
747                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
748                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
749                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
750                } else {
751                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
752                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
753                }
754                break;
755        case 10:
756                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
757                        /* XXX sort out optimal dither settings */
758                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
759                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
760                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
761                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
762                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
763                } else {
764                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
765                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
766                }
767                break;
768        default:
769                /* not needed */
770                break;
771        }
772
773        WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
774}
775
776
777/* display watermark setup */
778/**
779 * dce_v11_0_line_buffer_adjust - Set up the line buffer
780 *
781 * @adev: amdgpu_device pointer
782 * @amdgpu_crtc: the selected display controller
783 * @mode: the current display mode on the selected display
784 * controller
785 *
786 * Setup up the line buffer allocation for
787 * the selected display controller (CIK).
788 * Returns the line buffer size in pixels.
789 */
790static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
791                                       struct amdgpu_crtc *amdgpu_crtc,
792                                       struct drm_display_mode *mode)
793{
794        u32 tmp, buffer_alloc, i, mem_cfg;
795        u32 pipe_offset = amdgpu_crtc->crtc_id;
796        /*
797         * Line Buffer Setup
798         * There are 6 line buffers, one for each display controllers.
799         * There are 3 partitions per LB. Select the number of partitions
800         * to enable based on the display width.  For display widths larger
801         * than 4096, you need use to use 2 display controllers and combine
802         * them using the stereo blender.
803         */
804        if (amdgpu_crtc->base.enabled && mode) {
805                if (mode->crtc_hdisplay < 1920) {
806                        mem_cfg = 1;
807                        buffer_alloc = 2;
808                } else if (mode->crtc_hdisplay < 2560) {
809                        mem_cfg = 2;
810                        buffer_alloc = 2;
811                } else if (mode->crtc_hdisplay < 4096) {
812                        mem_cfg = 0;
813                        buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
814                } else {
815                        DRM_DEBUG_KMS("Mode too big for LB!\n");
816                        mem_cfg = 0;
817                        buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
818                }
819        } else {
820                mem_cfg = 1;
821                buffer_alloc = 0;
822        }
823
824        tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
825        tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
826        WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
827
828        tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
829        tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
830        WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
831
832        for (i = 0; i < adev->usec_timeout; i++) {
833                tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
834                if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
835                        break;
836                udelay(1);
837        }
838
839        if (amdgpu_crtc->base.enabled && mode) {
840                switch (mem_cfg) {
841                case 0:
842                default:
843                        return 4096 * 2;
844                case 1:
845                        return 1920 * 2;
846                case 2:
847                        return 2560 * 2;
848                }
849        }
850
851        /* controller not enabled, so no lb used */
852        return 0;
853}
854
855/**
856 * cik_get_number_of_dram_channels - get the number of dram channels
857 *
858 * @adev: amdgpu_device pointer
859 *
860 * Look up the number of video ram channels (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the number of dram channels
863 */
864static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
865{
866        u32 tmp = RREG32(mmMC_SHARED_CHMAP);
867
868        switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
869        case 0:
870        default:
871                return 1;
872        case 1:
873                return 2;
874        case 2:
875                return 4;
876        case 3:
877                return 8;
878        case 4:
879                return 3;
880        case 5:
881                return 6;
882        case 6:
883                return 10;
884        case 7:
885                return 12;
886        case 8:
887                return 16;
888        }
889}
890
891struct dce10_wm_params {
892        u32 dram_channels; /* number of dram channels */
893        u32 yclk;          /* bandwidth per dram data pin in kHz */
894        u32 sclk;          /* engine clock in kHz */
895        u32 disp_clk;      /* display clock in kHz */
896        u32 src_width;     /* viewport width */
897        u32 active_time;   /* active display time in ns */
898        u32 blank_time;    /* blank time in ns */
899        bool interlaced;    /* mode is interlaced */
900        fixed20_12 vsc;    /* vertical scale ratio */
901        u32 num_heads;     /* number of active crtcs */
902        u32 bytes_per_pixel; /* bytes per pixel display + overlay */
903        u32 lb_size;       /* line buffer allocated to pipe */
904        u32 vtaps;         /* vertical scaler taps */
905};
906
907/**
908 * dce_v11_0_dram_bandwidth - get the dram bandwidth
909 *
910 * @wm: watermark calculation data
911 *
912 * Calculate the raw dram bandwidth (CIK).
913 * Used for display watermark bandwidth calculations
914 * Returns the dram bandwidth in MBytes/s
915 */
916static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
917{
918        /* Calculate raw DRAM Bandwidth */
919        fixed20_12 dram_efficiency; /* 0.7 */
920        fixed20_12 yclk, dram_channels, bandwidth;
921        fixed20_12 a;
922
923        a.full = dfixed_const(1000);
924        yclk.full = dfixed_const(wm->yclk);
925        yclk.full = dfixed_div(yclk, a);
926        dram_channels.full = dfixed_const(wm->dram_channels * 4);
927        a.full = dfixed_const(10);
928        dram_efficiency.full = dfixed_const(7);
929        dram_efficiency.full = dfixed_div(dram_efficiency, a);
930        bandwidth.full = dfixed_mul(dram_channels, yclk);
931        bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
932
933        return dfixed_trunc(bandwidth);
934}
935
936/**
937 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
938 *
939 * @wm: watermark calculation data
940 *
941 * Calculate the dram bandwidth used for display (CIK).
942 * Used for display watermark bandwidth calculations
943 * Returns the dram bandwidth for display in MBytes/s
944 */
945static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
946{
947        /* Calculate DRAM Bandwidth and the part allocated to display. */
948        fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
949        fixed20_12 yclk, dram_channels, bandwidth;
950        fixed20_12 a;
951
952        a.full = dfixed_const(1000);
953        yclk.full = dfixed_const(wm->yclk);
954        yclk.full = dfixed_div(yclk, a);
955        dram_channels.full = dfixed_const(wm->dram_channels * 4);
956        a.full = dfixed_const(10);
957        disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
958        disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
959        bandwidth.full = dfixed_mul(dram_channels, yclk);
960        bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
961
962        return dfixed_trunc(bandwidth);
963}
964
965/**
966 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
967 *
968 * @wm: watermark calculation data
969 *
970 * Calculate the data return bandwidth used for display (CIK).
971 * Used for display watermark bandwidth calculations
972 * Returns the data return bandwidth in MBytes/s
973 */
974static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
975{
976        /* Calculate the display Data return Bandwidth */
977        fixed20_12 return_efficiency; /* 0.8 */
978        fixed20_12 sclk, bandwidth;
979        fixed20_12 a;
980
981        a.full = dfixed_const(1000);
982        sclk.full = dfixed_const(wm->sclk);
983        sclk.full = dfixed_div(sclk, a);
984        a.full = dfixed_const(10);
985        return_efficiency.full = dfixed_const(8);
986        return_efficiency.full = dfixed_div(return_efficiency, a);
987        a.full = dfixed_const(32);
988        bandwidth.full = dfixed_mul(a, sclk);
989        bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
990
991        return dfixed_trunc(bandwidth);
992}
993
994/**
995 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
996 *
997 * @wm: watermark calculation data
998 *
999 * Calculate the dmif bandwidth used for display (CIK).
1000 * Used for display watermark bandwidth calculations
1001 * Returns the dmif bandwidth in MBytes/s
1002 */
1003static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1004{
1005        /* Calculate the DMIF Request Bandwidth */
1006        fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1007        fixed20_12 disp_clk, bandwidth;
1008        fixed20_12 a, b;
1009
1010        a.full = dfixed_const(1000);
1011        disp_clk.full = dfixed_const(wm->disp_clk);
1012        disp_clk.full = dfixed_div(disp_clk, a);
1013        a.full = dfixed_const(32);
1014        b.full = dfixed_mul(a, disp_clk);
1015
1016        a.full = dfixed_const(10);
1017        disp_clk_request_efficiency.full = dfixed_const(8);
1018        disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1019
1020        bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1021
1022        return dfixed_trunc(bandwidth);
1023}
1024
1025/**
1026 * dce_v11_0_available_bandwidth - get the min available bandwidth
1027 *
1028 * @wm: watermark calculation data
1029 *
1030 * Calculate the min available bandwidth used for display (CIK).
1031 * Used for display watermark bandwidth calculations
1032 * Returns the min available bandwidth in MBytes/s
1033 */
1034static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1035{
1036        /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1037        u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1038        u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1039        u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1040
1041        return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1042}
1043
1044/**
1045 * dce_v11_0_average_bandwidth - get the average available bandwidth
1046 *
1047 * @wm: watermark calculation data
1048 *
1049 * Calculate the average available bandwidth used for display (CIK).
1050 * Used for display watermark bandwidth calculations
1051 * Returns the average available bandwidth in MBytes/s
1052 */
1053static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1054{
1055        /* Calculate the display mode Average Bandwidth
1056         * DisplayMode should contain the source and destination dimensions,
1057         * timing, etc.
1058         */
1059        fixed20_12 bpp;
1060        fixed20_12 line_time;
1061        fixed20_12 src_width;
1062        fixed20_12 bandwidth;
1063        fixed20_12 a;
1064
1065        a.full = dfixed_const(1000);
1066        line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1067        line_time.full = dfixed_div(line_time, a);
1068        bpp.full = dfixed_const(wm->bytes_per_pixel);
1069        src_width.full = dfixed_const(wm->src_width);
1070        bandwidth.full = dfixed_mul(src_width, bpp);
1071        bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1072        bandwidth.full = dfixed_div(bandwidth, line_time);
1073
1074        return dfixed_trunc(bandwidth);
1075}
1076
1077/**
1078 * dce_v11_0_latency_watermark - get the latency watermark
1079 *
1080 * @wm: watermark calculation data
1081 *
1082 * Calculate the latency watermark (CIK).
1083 * Used for display watermark bandwidth calculations
1084 * Returns the latency watermark in ns
1085 */
1086static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1087{
1088        /* First calculate the latency in ns */
1089        u32 mc_latency = 2000; /* 2000 ns. */
1090        u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1091        u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1092        u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1093        u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1094        u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1095                (wm->num_heads * cursor_line_pair_return_time);
1096        u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1097        u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1098        u32 tmp, dmif_size = 12288;
1099        fixed20_12 a, b, c;
1100
1101        if (wm->num_heads == 0)
1102                return 0;
1103
1104        a.full = dfixed_const(2);
1105        b.full = dfixed_const(1);
1106        if ((wm->vsc.full > a.full) ||
1107            ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1108            (wm->vtaps >= 5) ||
1109            ((wm->vsc.full >= a.full) && wm->interlaced))
1110                max_src_lines_per_dst_line = 4;
1111        else
1112                max_src_lines_per_dst_line = 2;
1113
1114        a.full = dfixed_const(available_bandwidth);
1115        b.full = dfixed_const(wm->num_heads);
1116        a.full = dfixed_div(a, b);
1117
1118        b.full = dfixed_const(mc_latency + 512);
1119        c.full = dfixed_const(wm->disp_clk);
1120        b.full = dfixed_div(b, c);
1121
1122        c.full = dfixed_const(dmif_size);
1123        b.full = dfixed_div(c, b);
1124
1125        tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1126
1127        b.full = dfixed_const(1000);
1128        c.full = dfixed_const(wm->disp_clk);
1129        b.full = dfixed_div(c, b);
1130        c.full = dfixed_const(wm->bytes_per_pixel);
1131        b.full = dfixed_mul(b, c);
1132
1133        lb_fill_bw = min(tmp, dfixed_trunc(b));
1134
1135        a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1136        b.full = dfixed_const(1000);
1137        c.full = dfixed_const(lb_fill_bw);
1138        b.full = dfixed_div(c, b);
1139        a.full = dfixed_div(a, b);
1140        line_fill_time = dfixed_trunc(a);
1141
1142        if (line_fill_time < wm->active_time)
1143                return latency;
1144        else
1145                return latency + (line_fill_time - wm->active_time);
1146
1147}
1148
1149/**
1150 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1151 * average and available dram bandwidth
1152 *
1153 * @wm: watermark calculation data
1154 *
1155 * Check if the display average bandwidth fits in the display
1156 * dram bandwidth (CIK).
1157 * Used for display watermark bandwidth calculations
1158 * Returns true if the display fits, false if not.
1159 */
1160static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1161{
1162        if (dce_v11_0_average_bandwidth(wm) <=
1163            (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1164                return true;
1165        else
1166                return false;
1167}
1168
1169/**
1170 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1171 * average and available bandwidth
1172 *
1173 * @wm: watermark calculation data
1174 *
1175 * Check if the display average bandwidth fits in the display
1176 * available bandwidth (CIK).
1177 * Used for display watermark bandwidth calculations
1178 * Returns true if the display fits, false if not.
1179 */
1180static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1181{
1182        if (dce_v11_0_average_bandwidth(wm) <=
1183            (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1184                return true;
1185        else
1186                return false;
1187}
1188
1189/**
1190 * dce_v11_0_check_latency_hiding - check latency hiding
1191 *
1192 * @wm: watermark calculation data
1193 *
1194 * Check latency hiding (CIK).
1195 * Used for display watermark bandwidth calculations
1196 * Returns true if the display fits, false if not.
1197 */
1198static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1199{
1200        u32 lb_partitions = wm->lb_size / wm->src_width;
1201        u32 line_time = wm->active_time + wm->blank_time;
1202        u32 latency_tolerant_lines;
1203        u32 latency_hiding;
1204        fixed20_12 a;
1205
1206        a.full = dfixed_const(1);
1207        if (wm->vsc.full > a.full)
1208                latency_tolerant_lines = 1;
1209        else {
1210                if (lb_partitions <= (wm->vtaps + 1))
1211                        latency_tolerant_lines = 1;
1212                else
1213                        latency_tolerant_lines = 2;
1214        }
1215
1216        latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1217
1218        if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1219                return true;
1220        else
1221                return false;
1222}
1223
1224/**
1225 * dce_v11_0_program_watermarks - program display watermarks
1226 *
1227 * @adev: amdgpu_device pointer
1228 * @amdgpu_crtc: the selected display controller
1229 * @lb_size: line buffer size
1230 * @num_heads: number of display controllers in use
1231 *
1232 * Calculate and program the display watermarks for the
1233 * selected display controller (CIK).
1234 */
1235static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1236                                        struct amdgpu_crtc *amdgpu_crtc,
1237                                        u32 lb_size, u32 num_heads)
1238{
1239        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1240        struct dce10_wm_params wm_low, wm_high;
1241        u32 pixel_period;
1242        u32 line_time = 0;
1243        u32 latency_watermark_a = 0, latency_watermark_b = 0;
1244        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1245
1246        if (amdgpu_crtc->base.enabled && num_heads && mode) {
1247                pixel_period = 1000000 / (u32)mode->clock;
1248                line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1249
1250                /* watermark for high clocks */
1251                if (adev->pm.dpm_enabled) {
1252                        wm_high.yclk =
1253                                amdgpu_dpm_get_mclk(adev, false) * 10;
1254                        wm_high.sclk =
1255                                amdgpu_dpm_get_sclk(adev, false) * 10;
1256                } else {
1257                        wm_high.yclk = adev->pm.current_mclk * 10;
1258                        wm_high.sclk = adev->pm.current_sclk * 10;
1259                }
1260
1261                wm_high.disp_clk = mode->clock;
1262                wm_high.src_width = mode->crtc_hdisplay;
1263                wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1264                wm_high.blank_time = line_time - wm_high.active_time;
1265                wm_high.interlaced = false;
1266                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1267                        wm_high.interlaced = true;
1268                wm_high.vsc = amdgpu_crtc->vsc;
1269                wm_high.vtaps = 1;
1270                if (amdgpu_crtc->rmx_type != RMX_OFF)
1271                        wm_high.vtaps = 2;
1272                wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1273                wm_high.lb_size = lb_size;
1274                wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1275                wm_high.num_heads = num_heads;
1276
1277                /* set for high clocks */
1278                latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1279
1280                /* possibly force display priority to high */
1281                /* should really do this at mode validation time... */
1282                if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1283                    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1284                    !dce_v11_0_check_latency_hiding(&wm_high) ||
1285                    (adev->mode_info.disp_priority == 2)) {
1286                        DRM_DEBUG_KMS("force priority to high\n");
1287                }
1288
1289                /* watermark for low clocks */
1290                if (adev->pm.dpm_enabled) {
1291                        wm_low.yclk =
1292                                amdgpu_dpm_get_mclk(adev, true) * 10;
1293                        wm_low.sclk =
1294                                amdgpu_dpm_get_sclk(adev, true) * 10;
1295                } else {
1296                        wm_low.yclk = adev->pm.current_mclk * 10;
1297                        wm_low.sclk = adev->pm.current_sclk * 10;
1298                }
1299
1300                wm_low.disp_clk = mode->clock;
1301                wm_low.src_width = mode->crtc_hdisplay;
1302                wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1303                wm_low.blank_time = line_time - wm_low.active_time;
1304                wm_low.interlaced = false;
1305                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1306                        wm_low.interlaced = true;
1307                wm_low.vsc = amdgpu_crtc->vsc;
1308                wm_low.vtaps = 1;
1309                if (amdgpu_crtc->rmx_type != RMX_OFF)
1310                        wm_low.vtaps = 2;
1311                wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1312                wm_low.lb_size = lb_size;
1313                wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1314                wm_low.num_heads = num_heads;
1315
1316                /* set for low clocks */
1317                latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1318
1319                /* possibly force display priority to high */
1320                /* should really do this at mode validation time... */
1321                if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1322                    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1323                    !dce_v11_0_check_latency_hiding(&wm_low) ||
1324                    (adev->mode_info.disp_priority == 2)) {
1325                        DRM_DEBUG_KMS("force priority to high\n");
1326                }
1327                lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1328        }
1329
1330        /* select wm A */
1331        wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1332        tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1333        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1334        tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1335        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1336        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1337        WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1338        /* select wm B */
1339        tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1340        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1341        tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1342        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1343        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1344        WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1345        /* restore original selection */
1346        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1347
1348        /* save values for DPM */
1349        amdgpu_crtc->line_time = line_time;
1350        amdgpu_crtc->wm_high = latency_watermark_a;
1351        amdgpu_crtc->wm_low = latency_watermark_b;
1352        /* Save number of lines the linebuffer leads before the scanout */
1353        amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1354}
1355
1356/**
1357 * dce_v11_0_bandwidth_update - program display watermarks
1358 *
1359 * @adev: amdgpu_device pointer
1360 *
1361 * Calculate and program the display watermarks and line
1362 * buffer allocation (CIK).
1363 */
1364static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1365{
1366        struct drm_display_mode *mode = NULL;
1367        u32 num_heads = 0, lb_size;
1368        int i;
1369
1370        amdgpu_update_display_priority(adev);
1371
1372        for (i = 0; i < adev->mode_info.num_crtc; i++) {
1373                if (adev->mode_info.crtcs[i]->base.enabled)
1374                        num_heads++;
1375        }
1376        for (i = 0; i < adev->mode_info.num_crtc; i++) {
1377                mode = &adev->mode_info.crtcs[i]->base.mode;
1378                lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1379                dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1380                                            lb_size, num_heads);
1381        }
1382}
1383
1384static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1385{
1386        int i;
1387        u32 offset, tmp;
1388
1389        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1390                offset = adev->mode_info.audio.pin[i].offset;
1391                tmp = RREG32_AUDIO_ENDPT(offset,
1392                                         ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1393                if (((tmp &
1394                AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1395                AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1396                        adev->mode_info.audio.pin[i].connected = false;
1397                else
1398                        adev->mode_info.audio.pin[i].connected = true;
1399        }
1400}
1401
1402static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1403{
1404        int i;
1405
1406        dce_v11_0_audio_get_connected_pins(adev);
1407
1408        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1409                if (adev->mode_info.audio.pin[i].connected)
1410                        return &adev->mode_info.audio.pin[i];
1411        }
1412        DRM_ERROR("No connected audio pins found!\n");
1413        return NULL;
1414}
1415
1416static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1417{
1418        struct amdgpu_device *adev = encoder->dev->dev_private;
1419        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1420        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1421        u32 tmp;
1422
1423        if (!dig || !dig->afmt || !dig->afmt->pin)
1424                return;
1425
1426        tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1427        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1428        WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1429}
1430
1431static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1432                                                struct drm_display_mode *mode)
1433{
1434        struct amdgpu_device *adev = encoder->dev->dev_private;
1435        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1436        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1437        struct drm_connector *connector;
1438        struct amdgpu_connector *amdgpu_connector = NULL;
1439        u32 tmp;
1440        int interlace = 0;
1441
1442        if (!dig || !dig->afmt || !dig->afmt->pin)
1443                return;
1444
1445        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1446                if (connector->encoder == encoder) {
1447                        amdgpu_connector = to_amdgpu_connector(connector);
1448                        break;
1449                }
1450        }
1451
1452        if (!amdgpu_connector) {
1453                DRM_ERROR("Couldn't find encoder's connector\n");
1454                return;
1455        }
1456
1457        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1458                interlace = 1;
1459        if (connector->latency_present[interlace]) {
1460                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1461                                    VIDEO_LIPSYNC, connector->video_latency[interlace]);
1462                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1463                                    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1464        } else {
1465                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1466                                    VIDEO_LIPSYNC, 0);
1467                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1468                                    AUDIO_LIPSYNC, 0);
1469        }
1470        WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1471                           ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1472}
1473
1474static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1475{
1476        struct amdgpu_device *adev = encoder->dev->dev_private;
1477        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1478        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1479        struct drm_connector *connector;
1480        struct amdgpu_connector *amdgpu_connector = NULL;
1481        u32 tmp;
1482        u8 *sadb = NULL;
1483        int sad_count;
1484
1485        if (!dig || !dig->afmt || !dig->afmt->pin)
1486                return;
1487
1488        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1489                if (connector->encoder == encoder) {
1490                        amdgpu_connector = to_amdgpu_connector(connector);
1491                        break;
1492                }
1493        }
1494
1495        if (!amdgpu_connector) {
1496                DRM_ERROR("Couldn't find encoder's connector\n");
1497                return;
1498        }
1499
1500        sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1501        if (sad_count < 0) {
1502                DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1503                sad_count = 0;
1504        }
1505
1506        /* program the speaker allocation */
1507        tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1508                                 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1509        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1510                            DP_CONNECTION, 0);
1511        /* set HDMI mode */
1512        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1513                            HDMI_CONNECTION, 1);
1514        if (sad_count)
1515                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1516                                    SPEAKER_ALLOCATION, sadb[0]);
1517        else
1518                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1519                                    SPEAKER_ALLOCATION, 5); /* stereo */
1520        WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1521                           ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1522
1523        kfree(sadb);
1524}
1525
1526static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1527{
1528        struct amdgpu_device *adev = encoder->dev->dev_private;
1529        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1530        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1531        struct drm_connector *connector;
1532        struct amdgpu_connector *amdgpu_connector = NULL;
1533        struct cea_sad *sads;
1534        int i, sad_count;
1535
1536        static const u16 eld_reg_to_type[][2] = {
1537                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1538                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1539                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1540                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1541                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1542                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1543                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1544                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1545                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1546                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1547                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1548                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1549        };
1550
1551        if (!dig || !dig->afmt || !dig->afmt->pin)
1552                return;
1553
1554        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1555                if (connector->encoder == encoder) {
1556                        amdgpu_connector = to_amdgpu_connector(connector);
1557                        break;
1558                }
1559        }
1560
1561        if (!amdgpu_connector) {
1562                DRM_ERROR("Couldn't find encoder's connector\n");
1563                return;
1564        }
1565
1566        sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1567        if (sad_count <= 0) {
1568                DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1569                return;
1570        }
1571        BUG_ON(!sads);
1572
1573        for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1574                u32 tmp = 0;
1575                u8 stereo_freqs = 0;
1576                int max_channels = -1;
1577                int j;
1578
1579                for (j = 0; j < sad_count; j++) {
1580                        struct cea_sad *sad = &sads[j];
1581
1582                        if (sad->format == eld_reg_to_type[i][1]) {
1583                                if (sad->channels > max_channels) {
1584                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1585                                                            MAX_CHANNELS, sad->channels);
1586                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1587                                                            DESCRIPTOR_BYTE_2, sad->byte2);
1588                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1589                                                            SUPPORTED_FREQUENCIES, sad->freq);
1590                                        max_channels = sad->channels;
1591                                }
1592
1593                                if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1594                                        stereo_freqs |= sad->freq;
1595                                else
1596                                        break;
1597                        }
1598                }
1599
1600                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1601                                    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1602                WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1603        }
1604
1605        kfree(sads);
1606}
1607
1608static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1609                                  struct amdgpu_audio_pin *pin,
1610                                  bool enable)
1611{
1612        if (!pin)
1613                return;
1614
1615        WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1616                           enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1617}
1618
1619static const u32 pin_offsets[] =
1620{
1621        AUD0_REGISTER_OFFSET,
1622        AUD1_REGISTER_OFFSET,
1623        AUD2_REGISTER_OFFSET,
1624        AUD3_REGISTER_OFFSET,
1625        AUD4_REGISTER_OFFSET,
1626        AUD5_REGISTER_OFFSET,
1627        AUD6_REGISTER_OFFSET,
1628};
1629
1630static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1631{
1632        int i;
1633
1634        if (!amdgpu_audio)
1635                return 0;
1636
1637        adev->mode_info.audio.enabled = true;
1638
1639        adev->mode_info.audio.num_pins = 7;
1640
1641        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1642                adev->mode_info.audio.pin[i].channels = -1;
1643                adev->mode_info.audio.pin[i].rate = -1;
1644                adev->mode_info.audio.pin[i].bits_per_sample = -1;
1645                adev->mode_info.audio.pin[i].status_bits = 0;
1646                adev->mode_info.audio.pin[i].category_code = 0;
1647                adev->mode_info.audio.pin[i].connected = false;
1648                adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1649                adev->mode_info.audio.pin[i].id = i;
1650                /* disable audio.  it will be set up later */
1651                /* XXX remove once we switch to ip funcs */
1652                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1653        }
1654
1655        return 0;
1656}
1657
1658static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1659{
1660        int i;
1661
1662        if (!adev->mode_info.audio.enabled)
1663                return;
1664
1665        for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1666                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1667
1668        adev->mode_info.audio.enabled = false;
1669}
1670
1671/*
1672 * update the N and CTS parameters for a given pixel clock rate
1673 */
1674static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1675{
1676        struct drm_device *dev = encoder->dev;
1677        struct amdgpu_device *adev = dev->dev_private;
1678        struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1679        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1680        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1681        u32 tmp;
1682
1683        tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1684        tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1685        WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1686        tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1687        tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1688        WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1689
1690        tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1691        tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1692        WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1693        tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1694        tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1695        WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1696
1697        tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1698        tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1699        WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1700        tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1701        tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1702        WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1703
1704}
1705
1706/*
1707 * build a HDMI Video Info Frame
1708 */
1709static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1710                                               void *buffer, size_t size)
1711{
1712        struct drm_device *dev = encoder->dev;
1713        struct amdgpu_device *adev = dev->dev_private;
1714        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1715        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1716        uint8_t *frame = buffer + 3;
1717        uint8_t *header = buffer;
1718
1719        WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1720                frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1721        WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1722                frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1723        WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1724                frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1725        WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1726                frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1727}
1728
1729static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1730{
1731        struct drm_device *dev = encoder->dev;
1732        struct amdgpu_device *adev = dev->dev_private;
1733        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1734        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1735        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1736        u32 dto_phase = 24 * 1000;
1737        u32 dto_modulo = clock;
1738        u32 tmp;
1739
1740        if (!dig || !dig->afmt)
1741                return;
1742
1743        /* XXX two dtos; generally use dto0 for hdmi */
1744        /* Express [24MHz / target pixel clock] as an exact rational
1745         * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1746         * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1747         */
1748        tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1749        tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1750                            amdgpu_crtc->crtc_id);
1751        WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1752        WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1753        WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1754}
1755
1756/*
1757 * update the info frames with the data from the current display mode
1758 */
1759static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1760                                  struct drm_display_mode *mode)
1761{
1762        struct drm_device *dev = encoder->dev;
1763        struct amdgpu_device *adev = dev->dev_private;
1764        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1765        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1766        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1767        u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1768        struct hdmi_avi_infoframe frame;
1769        ssize_t err;
1770        u32 tmp;
1771        int bpc = 8;
1772
1773        if (!dig || !dig->afmt)
1774                return;
1775
1776        /* Silent, r600_hdmi_enable will raise WARN for us */
1777        if (!dig->afmt->enabled)
1778                return;
1779
1780        /* hdmi deep color mode general control packets setup, if bpc > 8 */
1781        if (encoder->crtc) {
1782                struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1783                bpc = amdgpu_crtc->bpc;
1784        }
1785
1786        /* disable audio prior to setting up hw */
1787        dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1788        dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1789
1790        dce_v11_0_audio_set_dto(encoder, mode->clock);
1791
1792        tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1793        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1794        WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1795
1796        WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1797
1798        tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1799        switch (bpc) {
1800        case 0:
1801        case 6:
1802        case 8:
1803        case 16:
1804        default:
1805                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1806                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1807                DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1808                          connector->name, bpc);
1809                break;
1810        case 10:
1811                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1812                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1813                DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1814                          connector->name);
1815                break;
1816        case 12:
1817                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1818                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1819                DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1820                          connector->name);
1821                break;
1822        }
1823        WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1824
1825        tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1826        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1827        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1828        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1829        WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1830
1831        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1832        /* enable audio info frames (frames won't be set until audio is enabled) */
1833        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1834        /* required for audio info values to be updated */
1835        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1836        WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1837
1838        tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1839        /* required for audio info values to be updated */
1840        tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1841        WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1842
1843        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1844        /* anything other than 0 */
1845        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1846        WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1847
1848        WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1849
1850        tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1851        /* set the default audio delay */
1852        tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1853        /* should be suffient for all audio modes and small enough for all hblanks */
1854        tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1855        WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1856
1857        tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1858        /* allow 60958 channel status fields to be updated */
1859        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1860        WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1861
1862        tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1863        if (bpc > 8)
1864                /* clear SW CTS value */
1865                tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1866        else
1867                /* select SW CTS value */
1868                tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1869        /* allow hw to sent ACR packets when required */
1870        tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1871        WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1872
1873        dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1874
1875        tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1876        tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1877        WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1878
1879        tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1880        tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1881        WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1882
1883        tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1884        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1885        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1886        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1887        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1888        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1889        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1890        WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1891
1892        dce_v11_0_audio_write_speaker_allocation(encoder);
1893
1894        WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1895               (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1896
1897        dce_v11_0_afmt_audio_select_pin(encoder);
1898        dce_v11_0_audio_write_sad_regs(encoder);
1899        dce_v11_0_audio_write_latency_fields(encoder, mode);
1900
1901        err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1902        if (err < 0) {
1903                DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1904                return;
1905        }
1906
1907        err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1908        if (err < 0) {
1909                DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1910                return;
1911        }
1912
1913        dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1914
1915        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1916        /* enable AVI info frames */
1917        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1918        /* required for audio info values to be updated */
1919        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1920        WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1921
1922        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1923        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1924        WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1925
1926        tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1927        /* send audio packets */
1928        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1929        WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1930
1931        WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1932        WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1933        WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1934        WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1935
1936        /* enable audio after to setting up hw */
1937        dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1938}
1939
1940static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1941{
1942        struct drm_device *dev = encoder->dev;
1943        struct amdgpu_device *adev = dev->dev_private;
1944        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1945        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1946
1947        if (!dig || !dig->afmt)
1948                return;
1949
1950        /* Silent, r600_hdmi_enable will raise WARN for us */
1951        if (enable && dig->afmt->enabled)
1952                return;
1953        if (!enable && !dig->afmt->enabled)
1954                return;
1955
1956        if (!enable && dig->afmt->pin) {
1957                dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1958                dig->afmt->pin = NULL;
1959        }
1960
1961        dig->afmt->enabled = enable;
1962
1963        DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1964                  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1965}
1966
1967static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1968{
1969        int i;
1970
1971        for (i = 0; i < adev->mode_info.num_dig; i++)
1972                adev->mode_info.afmt[i] = NULL;
1973
1974        /* DCE11 has audio blocks tied to DIG encoders */
1975        for (i = 0; i < adev->mode_info.num_dig; i++) {
1976                adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1977                if (adev->mode_info.afmt[i]) {
1978                        adev->mode_info.afmt[i]->offset = dig_offsets[i];
1979                        adev->mode_info.afmt[i]->id = i;
1980                }
1981        }
1982}
1983
1984static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1985{
1986        int i;
1987
1988        for (i = 0; i < adev->mode_info.num_dig; i++) {
1989                kfree(adev->mode_info.afmt[i]);
1990                adev->mode_info.afmt[i] = NULL;
1991        }
1992}
1993
1994static const u32 vga_control_regs[6] =
1995{
1996        mmD1VGA_CONTROL,
1997        mmD2VGA_CONTROL,
1998        mmD3VGA_CONTROL,
1999        mmD4VGA_CONTROL,
2000        mmD5VGA_CONTROL,
2001        mmD6VGA_CONTROL,
2002};
2003
2004static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2005{
2006        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2007        struct drm_device *dev = crtc->dev;
2008        struct amdgpu_device *adev = dev->dev_private;
2009        u32 vga_control;
2010
2011        vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2012        if (enable)
2013                WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2014        else
2015                WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2016}
2017
2018static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2019{
2020        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2021        struct drm_device *dev = crtc->dev;
2022        struct amdgpu_device *adev = dev->dev_private;
2023
2024        if (enable)
2025                WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2026        else
2027                WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2028}
2029
2030static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2031                                     struct drm_framebuffer *fb,
2032                                     int x, int y, int atomic)
2033{
2034        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2035        struct drm_device *dev = crtc->dev;
2036        struct amdgpu_device *adev = dev->dev_private;
2037        struct amdgpu_framebuffer *amdgpu_fb;
2038        struct drm_framebuffer *target_fb;
2039        struct drm_gem_object *obj;
2040        struct amdgpu_bo *rbo;
2041        uint64_t fb_location, tiling_flags;
2042        uint32_t fb_format, fb_pitch_pixels;
2043        u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2044        u32 pipe_config;
2045        u32 tmp, viewport_w, viewport_h;
2046        int r;
2047        bool bypass_lut = false;
2048
2049        /* no fb bound */
2050        if (!atomic && !crtc->primary->fb) {
2051                DRM_DEBUG_KMS("No FB bound\n");
2052                return 0;
2053        }
2054
2055        if (atomic) {
2056                amdgpu_fb = to_amdgpu_framebuffer(fb);
2057                target_fb = fb;
2058        }
2059        else {
2060                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2061                target_fb = crtc->primary->fb;
2062        }
2063
2064        /* If atomic, assume fb object is pinned & idle & fenced and
2065         * just update base pointers
2066         */
2067        obj = amdgpu_fb->obj;
2068        rbo = gem_to_amdgpu_bo(obj);
2069        r = amdgpu_bo_reserve(rbo, false);
2070        if (unlikely(r != 0))
2071                return r;
2072
2073        if (atomic)
2074                fb_location = amdgpu_bo_gpu_offset(rbo);
2075        else {
2076                r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2077                if (unlikely(r != 0)) {
2078                        amdgpu_bo_unreserve(rbo);
2079                        return -EINVAL;
2080                }
2081        }
2082
2083        amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2084        amdgpu_bo_unreserve(rbo);
2085
2086        pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2087
2088        switch (target_fb->pixel_format) {
2089        case DRM_FORMAT_C8:
2090                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2091                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2092                break;
2093        case DRM_FORMAT_XRGB4444:
2094        case DRM_FORMAT_ARGB4444:
2095                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2096                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2097#ifdef __BIG_ENDIAN
2098                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099                                        ENDIAN_8IN16);
2100#endif
2101                break;
2102        case DRM_FORMAT_XRGB1555:
2103        case DRM_FORMAT_ARGB1555:
2104                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2105                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2106#ifdef __BIG_ENDIAN
2107                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108                                        ENDIAN_8IN16);
2109#endif
2110                break;
2111        case DRM_FORMAT_BGRX5551:
2112        case DRM_FORMAT_BGRA5551:
2113                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2114                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2115#ifdef __BIG_ENDIAN
2116                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117                                        ENDIAN_8IN16);
2118#endif
2119                break;
2120        case DRM_FORMAT_RGB565:
2121                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2122                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2123#ifdef __BIG_ENDIAN
2124                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125                                        ENDIAN_8IN16);
2126#endif
2127                break;
2128        case DRM_FORMAT_XRGB8888:
2129        case DRM_FORMAT_ARGB8888:
2130                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2131                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2132#ifdef __BIG_ENDIAN
2133                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2134                                        ENDIAN_8IN32);
2135#endif
2136                break;
2137        case DRM_FORMAT_XRGB2101010:
2138        case DRM_FORMAT_ARGB2101010:
2139                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2140                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2141#ifdef __BIG_ENDIAN
2142                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143                                        ENDIAN_8IN32);
2144#endif
2145                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2146                bypass_lut = true;
2147                break;
2148        case DRM_FORMAT_BGRX1010102:
2149        case DRM_FORMAT_BGRA1010102:
2150                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2151                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2152#ifdef __BIG_ENDIAN
2153                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2154                                        ENDIAN_8IN32);
2155#endif
2156                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2157                bypass_lut = true;
2158                break;
2159        default:
2160                DRM_ERROR("Unsupported screen format %s\n",
2161                        drm_get_format_name(target_fb->pixel_format));
2162                return -EINVAL;
2163        }
2164
2165        if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2166                unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2167
2168                bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2169                bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2170                mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2171                tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2172                num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2173
2174                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2175                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2176                                          ARRAY_2D_TILED_THIN1);
2177                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2178                                          tile_split);
2179                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2180                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2181                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2182                                          mtaspect);
2183                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2184                                          ADDR_SURF_MICRO_TILING_DISPLAY);
2185        } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2186                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2187                                          ARRAY_1D_TILED_THIN1);
2188        }
2189
2190        fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2191                                  pipe_config);
2192
2193        dce_v11_0_vga_enable(crtc, false);
2194
2195        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2196               upper_32_bits(fb_location));
2197        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2198               upper_32_bits(fb_location));
2199        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2200               (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2201        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2202               (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2203        WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2204        WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2205
2206        /*
2207         * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2208         * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2209         * retain the full precision throughout the pipeline.
2210         */
2211        tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2212        if (bypass_lut)
2213                tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2214        else
2215                tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2216        WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2217
2218        if (bypass_lut)
2219                DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2220
2221        WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2222        WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2223        WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2224        WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2225        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2226        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2227
2228        fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2229        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2230
2231        dce_v11_0_grph_enable(crtc, true);
2232
2233        WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2234               target_fb->height);
2235
2236        x &= ~3;
2237        y &= ~1;
2238        WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2239               (x << 16) | y);
2240        viewport_w = crtc->mode.hdisplay;
2241        viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2242        WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2243               (viewport_w << 16) | viewport_h);
2244
2245        /* pageflip setup */
2246        /* make sure flip is at vb rather than hb */
2247        tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2248        tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2249                            GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2250        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2251
2252        /* set pageflip to happen only at start of vblank interval (front porch) */
2253        WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2254
2255        if (!atomic && fb && fb != crtc->primary->fb) {
2256                amdgpu_fb = to_amdgpu_framebuffer(fb);
2257                rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2258                r = amdgpu_bo_reserve(rbo, false);
2259                if (unlikely(r != 0))
2260                        return r;
2261                amdgpu_bo_unpin(rbo);
2262                amdgpu_bo_unreserve(rbo);
2263        }
2264
2265        /* Bytes per pixel may have changed */
2266        dce_v11_0_bandwidth_update(adev);
2267
2268        return 0;
2269}
2270
2271static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2272                                     struct drm_display_mode *mode)
2273{
2274        struct drm_device *dev = crtc->dev;
2275        struct amdgpu_device *adev = dev->dev_private;
2276        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277        u32 tmp;
2278
2279        tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2280        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2281                tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2282        else
2283                tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2284        WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2285}
2286
2287static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2288{
2289        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2290        struct drm_device *dev = crtc->dev;
2291        struct amdgpu_device *adev = dev->dev_private;
2292        int i;
2293        u32 tmp;
2294
2295        DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2296
2297        tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2298        tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2299        WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2300
2301        tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2302        tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2303        WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2304
2305        tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2306        tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2307        WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308
2309        WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2310
2311        WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2312        WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2313        WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2314
2315        WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2316        WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2317        WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2318
2319        WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2320        WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2321
2322        WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2323        for (i = 0; i < 256; i++) {
2324                WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2325                       (amdgpu_crtc->lut_r[i] << 20) |
2326                       (amdgpu_crtc->lut_g[i] << 10) |
2327                       (amdgpu_crtc->lut_b[i] << 0));
2328        }
2329
2330        tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2331        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2332        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2333        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2334        WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2335
2336        tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2337        tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2338        WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2339
2340        tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2341        tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2342        WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2343
2344        tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2345        tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2346        WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2347
2348        /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2349        WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2350        /* XXX this only needs to be programmed once per crtc at startup,
2351         * not sure where the best place for it is
2352         */
2353        tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2354        tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2355        WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2356}
2357
2358static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2359{
2360        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2361        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2362
2363        switch (amdgpu_encoder->encoder_id) {
2364        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2365                if (dig->linkb)
2366                        return 1;
2367                else
2368                        return 0;
2369                break;
2370        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2371                if (dig->linkb)
2372                        return 3;
2373                else
2374                        return 2;
2375                break;
2376        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2377                if (dig->linkb)
2378                        return 5;
2379                else
2380                        return 4;
2381                break;
2382        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2383                return 6;
2384                break;
2385        default:
2386                DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2387                return 0;
2388        }
2389}
2390
2391/**
2392 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2393 *
2394 * @crtc: drm crtc
2395 *
2396 * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2397 * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2398 * monitors a dedicated PPLL must be used.  If a particular board has
2399 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2400 * as there is no need to program the PLL itself.  If we are not able to
2401 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2402 * avoid messing up an existing monitor.
2403 *
2404 * Asic specific PLL information
2405 *
2406 * DCE 10.x
2407 * Tonga
2408 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2409 * CI
2410 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2411 *
2412 */
2413static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2414{
2415        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2416        struct drm_device *dev = crtc->dev;
2417        struct amdgpu_device *adev = dev->dev_private;
2418        u32 pll_in_use;
2419        int pll;
2420
2421        if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2422                if (adev->clock.dp_extclk)
2423                        /* skip PPLL programming if using ext clock */
2424                        return ATOM_PPLL_INVALID;
2425                else {
2426                        /* use the same PPLL for all DP monitors */
2427                        pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2428                        if (pll != ATOM_PPLL_INVALID)
2429                                return pll;
2430                }
2431        } else {
2432                /* use the same PPLL for all monitors with the same clock */
2433                pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2434                if (pll != ATOM_PPLL_INVALID)
2435                        return pll;
2436        }
2437
2438        /* XXX need to determine what plls are available on each DCE11 part */
2439        pll_in_use = amdgpu_pll_get_use_mask(crtc);
2440        if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2441                if (!(pll_in_use & (1 << ATOM_PPLL1)))
2442                        return ATOM_PPLL1;
2443                if (!(pll_in_use & (1 << ATOM_PPLL0)))
2444                        return ATOM_PPLL0;
2445                DRM_ERROR("unable to allocate a PPLL\n");
2446                return ATOM_PPLL_INVALID;
2447        } else {
2448                if (!(pll_in_use & (1 << ATOM_PPLL2)))
2449                        return ATOM_PPLL2;
2450                if (!(pll_in_use & (1 << ATOM_PPLL1)))
2451                        return ATOM_PPLL1;
2452                if (!(pll_in_use & (1 << ATOM_PPLL0)))
2453                        return ATOM_PPLL0;
2454                DRM_ERROR("unable to allocate a PPLL\n");
2455                return ATOM_PPLL_INVALID;
2456        }
2457        return ATOM_PPLL_INVALID;
2458}
2459
2460static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2461{
2462        struct amdgpu_device *adev = crtc->dev->dev_private;
2463        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464        uint32_t cur_lock;
2465
2466        cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2467        if (lock)
2468                cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2469        else
2470                cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2471        WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2472}
2473
2474static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2475{
2476        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2477        struct amdgpu_device *adev = crtc->dev->dev_private;
2478        u32 tmp;
2479
2480        tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2481        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2482        WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2483}
2484
2485static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2486{
2487        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2488        struct amdgpu_device *adev = crtc->dev->dev_private;
2489        u32 tmp;
2490
2491        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2492               upper_32_bits(amdgpu_crtc->cursor_addr));
2493        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2494               lower_32_bits(amdgpu_crtc->cursor_addr));
2495
2496        tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2497        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2498        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2499        WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2500}
2501
2502static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2503                                        int x, int y)
2504{
2505        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2506        struct amdgpu_device *adev = crtc->dev->dev_private;
2507        int xorigin = 0, yorigin = 0;
2508
2509        /* avivo cursor are offset into the total surface */
2510        x += crtc->x;
2511        y += crtc->y;
2512        DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2513
2514        if (x < 0) {
2515                xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2516                x = 0;
2517        }
2518        if (y < 0) {
2519                yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2520                y = 0;
2521        }
2522
2523        WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2524        WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2525        WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2526               ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2527
2528        amdgpu_crtc->cursor_x = x;
2529        amdgpu_crtc->cursor_y = y;
2530
2531        return 0;
2532}
2533
2534static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2535                                      int x, int y)
2536{
2537        int ret;
2538
2539        dce_v11_0_lock_cursor(crtc, true);
2540        ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2541        dce_v11_0_lock_cursor(crtc, false);
2542
2543        return ret;
2544}
2545
2546static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2547                                      struct drm_file *file_priv,
2548                                      uint32_t handle,
2549                                      uint32_t width,
2550                                      uint32_t height,
2551                                      int32_t hot_x,
2552                                      int32_t hot_y)
2553{
2554        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2555        struct drm_gem_object *obj;
2556        struct amdgpu_bo *aobj;
2557        int ret;
2558
2559        if (!handle) {
2560                /* turn off cursor */
2561                dce_v11_0_hide_cursor(crtc);
2562                obj = NULL;
2563                goto unpin;
2564        }
2565
2566        if ((width > amdgpu_crtc->max_cursor_width) ||
2567            (height > amdgpu_crtc->max_cursor_height)) {
2568                DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2569                return -EINVAL;
2570        }
2571
2572        obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2573        if (!obj) {
2574                DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2575                return -ENOENT;
2576        }
2577
2578        aobj = gem_to_amdgpu_bo(obj);
2579        ret = amdgpu_bo_reserve(aobj, false);
2580        if (ret != 0) {
2581                drm_gem_object_unreference_unlocked(obj);
2582                return ret;
2583        }
2584
2585        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2586        amdgpu_bo_unreserve(aobj);
2587        if (ret) {
2588                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2589                drm_gem_object_unreference_unlocked(obj);
2590                return ret;
2591        }
2592
2593        amdgpu_crtc->cursor_width = width;
2594        amdgpu_crtc->cursor_height = height;
2595
2596        dce_v11_0_lock_cursor(crtc, true);
2597
2598        if (hot_x != amdgpu_crtc->cursor_hot_x ||
2599            hot_y != amdgpu_crtc->cursor_hot_y) {
2600                int x, y;
2601
2602                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2603                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2604
2605                dce_v11_0_cursor_move_locked(crtc, x, y);
2606
2607                amdgpu_crtc->cursor_hot_x = hot_x;
2608                amdgpu_crtc->cursor_hot_y = hot_y;
2609        }
2610
2611        dce_v11_0_show_cursor(crtc);
2612        dce_v11_0_lock_cursor(crtc, false);
2613
2614unpin:
2615        if (amdgpu_crtc->cursor_bo) {
2616                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2617                ret = amdgpu_bo_reserve(aobj, false);
2618                if (likely(ret == 0)) {
2619                        amdgpu_bo_unpin(aobj);
2620                        amdgpu_bo_unreserve(aobj);
2621                }
2622                drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2623        }
2624
2625        amdgpu_crtc->cursor_bo = obj;
2626        return 0;
2627}
2628
2629static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2630{
2631        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2632
2633        if (amdgpu_crtc->cursor_bo) {
2634                dce_v11_0_lock_cursor(crtc, true);
2635
2636                dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2637                                             amdgpu_crtc->cursor_y);
2638
2639                dce_v11_0_show_cursor(crtc);
2640
2641                dce_v11_0_lock_cursor(crtc, false);
2642        }
2643}
2644
2645static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2646                                    u16 *blue, uint32_t start, uint32_t size)
2647{
2648        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2649        int end = (start + size > 256) ? 256 : start + size, i;
2650
2651        /* userspace palettes are always correct as is */
2652        for (i = start; i < end; i++) {
2653                amdgpu_crtc->lut_r[i] = red[i] >> 6;
2654                amdgpu_crtc->lut_g[i] = green[i] >> 6;
2655                amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2656        }
2657        dce_v11_0_crtc_load_lut(crtc);
2658}
2659
2660static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2661{
2662        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663
2664        drm_crtc_cleanup(crtc);
2665        destroy_workqueue(amdgpu_crtc->pflip_queue);
2666        kfree(amdgpu_crtc);
2667}
2668
2669static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2670        .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2671        .cursor_move = dce_v11_0_crtc_cursor_move,
2672        .gamma_set = dce_v11_0_crtc_gamma_set,
2673        .set_config = amdgpu_crtc_set_config,
2674        .destroy = dce_v11_0_crtc_destroy,
2675        .page_flip = amdgpu_crtc_page_flip,
2676};
2677
2678static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2679{
2680        struct drm_device *dev = crtc->dev;
2681        struct amdgpu_device *adev = dev->dev_private;
2682        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2683        unsigned type;
2684
2685        switch (mode) {
2686        case DRM_MODE_DPMS_ON:
2687                amdgpu_crtc->enabled = true;
2688                amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2689                dce_v11_0_vga_enable(crtc, true);
2690                amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2691                dce_v11_0_vga_enable(crtc, false);
2692                /* Make sure VBLANK and PFLIP interrupts are still enabled */
2693                type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2694                amdgpu_irq_update(adev, &adev->crtc_irq, type);
2695                amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2696                drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2697                dce_v11_0_crtc_load_lut(crtc);
2698                break;
2699        case DRM_MODE_DPMS_STANDBY:
2700        case DRM_MODE_DPMS_SUSPEND:
2701        case DRM_MODE_DPMS_OFF:
2702                drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2703                if (amdgpu_crtc->enabled) {
2704                        dce_v11_0_vga_enable(crtc, true);
2705                        amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2706                        dce_v11_0_vga_enable(crtc, false);
2707                }
2708                amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2709                amdgpu_crtc->enabled = false;
2710                break;
2711        }
2712        /* adjust pm to dpms */
2713        amdgpu_pm_compute_clocks(adev);
2714}
2715
2716static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2717{
2718        /* disable crtc pair power gating before programming */
2719        amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2720        amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2721        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2722}
2723
2724static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2725{
2726        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2727        amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2728}
2729
2730static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2731{
2732        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2733        struct drm_device *dev = crtc->dev;
2734        struct amdgpu_device *adev = dev->dev_private;
2735        struct amdgpu_atom_ss ss;
2736        int i;
2737
2738        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2739        if (crtc->primary->fb) {
2740                int r;
2741                struct amdgpu_framebuffer *amdgpu_fb;
2742                struct amdgpu_bo *rbo;
2743
2744                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2745                rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2746                r = amdgpu_bo_reserve(rbo, false);
2747                if (unlikely(r))
2748                        DRM_ERROR("failed to reserve rbo before unpin\n");
2749                else {
2750                        amdgpu_bo_unpin(rbo);
2751                        amdgpu_bo_unreserve(rbo);
2752                }
2753        }
2754        /* disable the GRPH */
2755        dce_v11_0_grph_enable(crtc, false);
2756
2757        amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2758
2759        for (i = 0; i < adev->mode_info.num_crtc; i++) {
2760                if (adev->mode_info.crtcs[i] &&
2761                    adev->mode_info.crtcs[i]->enabled &&
2762                    i != amdgpu_crtc->crtc_id &&
2763                    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2764                        /* one other crtc is using this pll don't turn
2765                         * off the pll
2766                         */
2767                        goto done;
2768                }
2769        }
2770
2771        switch (amdgpu_crtc->pll_id) {
2772        case ATOM_PPLL0:
2773        case ATOM_PPLL1:
2774        case ATOM_PPLL2:
2775                /* disable the ppll */
2776                amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2777                                          0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2778                break;
2779        default:
2780                break;
2781        }
2782done:
2783        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2784        amdgpu_crtc->adjusted_clock = 0;
2785        amdgpu_crtc->encoder = NULL;
2786        amdgpu_crtc->connector = NULL;
2787}
2788
2789static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2790                                  struct drm_display_mode *mode,
2791                                  struct drm_display_mode *adjusted_mode,
2792                                  int x, int y, struct drm_framebuffer *old_fb)
2793{
2794        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2795
2796        if (!amdgpu_crtc->adjusted_clock)
2797                return -EINVAL;
2798
2799        amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2800        amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2801        dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2802        amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2803        amdgpu_atombios_crtc_scaler_setup(crtc);
2804        dce_v11_0_cursor_reset(crtc);
2805        /* update the hw version fpr dpm */
2806        amdgpu_crtc->hw_mode = *adjusted_mode;
2807
2808        return 0;
2809}
2810
2811static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2812                                     const struct drm_display_mode *mode,
2813                                     struct drm_display_mode *adjusted_mode)
2814{
2815        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2816        struct drm_device *dev = crtc->dev;
2817        struct drm_encoder *encoder;
2818
2819        /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2820        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2821                if (encoder->crtc == crtc) {
2822                        amdgpu_crtc->encoder = encoder;
2823                        amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2824                        break;
2825                }
2826        }
2827        if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2828                amdgpu_crtc->encoder = NULL;
2829                amdgpu_crtc->connector = NULL;
2830                return false;
2831        }
2832        if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2833                return false;
2834        if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2835                return false;
2836        /* pick pll */
2837        amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2838        /* if we can't get a PPLL for a non-DP encoder, fail */
2839        if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2840            !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2841                return false;
2842
2843        return true;
2844}
2845
2846static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2847                                  struct drm_framebuffer *old_fb)
2848{
2849        return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2850}
2851
2852static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2853                                         struct drm_framebuffer *fb,
2854                                         int x, int y, enum mode_set_atomic state)
2855{
2856       return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2857}
2858
2859static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2860        .dpms = dce_v11_0_crtc_dpms,
2861        .mode_fixup = dce_v11_0_crtc_mode_fixup,
2862        .mode_set = dce_v11_0_crtc_mode_set,
2863        .mode_set_base = dce_v11_0_crtc_set_base,
2864        .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2865        .prepare = dce_v11_0_crtc_prepare,
2866        .commit = dce_v11_0_crtc_commit,
2867        .load_lut = dce_v11_0_crtc_load_lut,
2868        .disable = dce_v11_0_crtc_disable,
2869};
2870
2871static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2872{
2873        struct amdgpu_crtc *amdgpu_crtc;
2874        int i;
2875
2876        amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2877                              (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2878        if (amdgpu_crtc == NULL)
2879                return -ENOMEM;
2880
2881        drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2882
2883        drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2884        amdgpu_crtc->crtc_id = index;
2885        amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2886        adev->mode_info.crtcs[index] = amdgpu_crtc;
2887
2888        amdgpu_crtc->max_cursor_width = 128;
2889        amdgpu_crtc->max_cursor_height = 128;
2890        adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2891        adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2892
2893        for (i = 0; i < 256; i++) {
2894                amdgpu_crtc->lut_r[i] = i << 2;
2895                amdgpu_crtc->lut_g[i] = i << 2;
2896                amdgpu_crtc->lut_b[i] = i << 2;
2897        }
2898
2899        switch (amdgpu_crtc->crtc_id) {
2900        case 0:
2901        default:
2902                amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2903                break;
2904        case 1:
2905                amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2906                break;
2907        case 2:
2908                amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2909                break;
2910        case 3:
2911                amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2912                break;
2913        case 4:
2914                amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2915                break;
2916        case 5:
2917                amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2918                break;
2919        }
2920
2921        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2922        amdgpu_crtc->adjusted_clock = 0;
2923        amdgpu_crtc->encoder = NULL;
2924        amdgpu_crtc->connector = NULL;
2925        drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2926
2927        return 0;
2928}
2929
2930static int dce_v11_0_early_init(void *handle)
2931{
2932        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2933
2934        adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2935        adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2936
2937        dce_v11_0_set_display_funcs(adev);
2938        dce_v11_0_set_irq_funcs(adev);
2939
2940        switch (adev->asic_type) {
2941        case CHIP_CARRIZO:
2942                adev->mode_info.num_crtc = 3;
2943                adev->mode_info.num_hpd = 6;
2944                adev->mode_info.num_dig = 9;
2945                break;
2946        case CHIP_STONEY:
2947                adev->mode_info.num_crtc = 2;
2948                adev->mode_info.num_hpd = 6;
2949                adev->mode_info.num_dig = 9;
2950                break;
2951        default:
2952                /* FIXME: not supported yet */
2953                return -EINVAL;
2954        }
2955
2956        return 0;
2957}
2958
2959static int dce_v11_0_sw_init(void *handle)
2960{
2961        int r, i;
2962        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2963
2964        for (i = 0; i < adev->mode_info.num_crtc; i++) {
2965                r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2966                if (r)
2967                return r;
2968        }
2969
2970        for (i = 8; i < 20; i += 2) {
2971                r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2972                if (r)
2973                        return r;
2974        }
2975
2976        /* HPD hotplug */
2977        r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2978        if (r)
2979        return r;
2980
2981        adev->mode_info.mode_config_initialized = true;
2982
2983        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2984
2985        adev->ddev->mode_config.max_width = 16384;
2986        adev->ddev->mode_config.max_height = 16384;
2987
2988        adev->ddev->mode_config.preferred_depth = 24;
2989        adev->ddev->mode_config.prefer_shadow = 1;
2990
2991        adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2992
2993        r = amdgpu_modeset_create_props(adev);
2994        if (r)
2995                return r;
2996
2997        adev->ddev->mode_config.max_width = 16384;
2998        adev->ddev->mode_config.max_height = 16384;
2999
3000        /* allocate crtcs */
3001        for (i = 0; i < adev->mode_info.num_crtc; i++) {
3002                r = dce_v11_0_crtc_init(adev, i);
3003                if (r)
3004                        return r;
3005        }
3006
3007        if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3008                amdgpu_print_display_setup(adev->ddev);
3009        else
3010                return -EINVAL;
3011
3012        /* setup afmt */
3013        dce_v11_0_afmt_init(adev);
3014
3015        r = dce_v11_0_audio_init(adev);
3016        if (r)
3017                return r;
3018
3019        drm_kms_helper_poll_init(adev->ddev);
3020
3021        return r;
3022}
3023
3024static int dce_v11_0_sw_fini(void *handle)
3025{
3026        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3027
3028        kfree(adev->mode_info.bios_hardcoded_edid);
3029
3030        drm_kms_helper_poll_fini(adev->ddev);
3031
3032        dce_v11_0_audio_fini(adev);
3033
3034        dce_v11_0_afmt_fini(adev);
3035
3036        drm_mode_config_cleanup(adev->ddev);
3037        adev->mode_info.mode_config_initialized = false;
3038
3039        return 0;
3040}
3041
3042static int dce_v11_0_hw_init(void *handle)
3043{
3044        int i;
3045        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046
3047        dce_v11_0_init_golden_registers(adev);
3048
3049        /* init dig PHYs, disp eng pll */
3050        amdgpu_atombios_crtc_powergate_init(adev);
3051        amdgpu_atombios_encoder_init_dig(adev);
3052        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3053
3054        /* initialize hpd */
3055        dce_v11_0_hpd_init(adev);
3056
3057        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3058                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3059        }
3060
3061        dce_v11_0_pageflip_interrupt_init(adev);
3062
3063        return 0;
3064}
3065
3066static int dce_v11_0_hw_fini(void *handle)
3067{
3068        int i;
3069        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3070
3071        dce_v11_0_hpd_fini(adev);
3072
3073        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3074                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3075        }
3076
3077        dce_v11_0_pageflip_interrupt_fini(adev);
3078
3079        return 0;
3080}
3081
3082static int dce_v11_0_suspend(void *handle)
3083{
3084        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3085
3086        amdgpu_atombios_scratch_regs_save(adev);
3087
3088        return dce_v11_0_hw_fini(handle);
3089}
3090
3091static int dce_v11_0_resume(void *handle)
3092{
3093        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3094        int ret;
3095
3096        ret = dce_v11_0_hw_init(handle);
3097
3098        amdgpu_atombios_scratch_regs_restore(adev);
3099
3100        /* turn on the BL */
3101        if (adev->mode_info.bl_encoder) {
3102                u8 bl_level = amdgpu_display_backlight_get_level(adev,
3103                                                                  adev->mode_info.bl_encoder);
3104                amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3105                                                    bl_level);
3106        }
3107
3108        return ret;
3109}
3110
3111static bool dce_v11_0_is_idle(void *handle)
3112{
3113        return true;
3114}
3115
3116static int dce_v11_0_wait_for_idle(void *handle)
3117{
3118        return 0;
3119}
3120
3121static void dce_v11_0_print_status(void *handle)
3122{
3123        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3124
3125        dev_info(adev->dev, "DCE 10.x registers\n");
3126        /* XXX todo */
3127}
3128
3129static int dce_v11_0_soft_reset(void *handle)
3130{
3131        u32 srbm_soft_reset = 0, tmp;
3132        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3133
3134        if (dce_v11_0_is_display_hung(adev))
3135                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3136
3137        if (srbm_soft_reset) {
3138                dce_v11_0_print_status((void *)adev);
3139
3140                tmp = RREG32(mmSRBM_SOFT_RESET);
3141                tmp |= srbm_soft_reset;
3142                dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3143                WREG32(mmSRBM_SOFT_RESET, tmp);
3144                tmp = RREG32(mmSRBM_SOFT_RESET);
3145
3146                udelay(50);
3147
3148                tmp &= ~srbm_soft_reset;
3149                WREG32(mmSRBM_SOFT_RESET, tmp);
3150                tmp = RREG32(mmSRBM_SOFT_RESET);
3151
3152                /* Wait a little for things to settle down */
3153                udelay(50);
3154                dce_v11_0_print_status((void *)adev);
3155        }
3156        return 0;
3157}
3158
3159static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3160                                                     int crtc,
3161                                                     enum amdgpu_interrupt_state state)
3162{
3163        u32 lb_interrupt_mask;
3164
3165        if (crtc >= adev->mode_info.num_crtc) {
3166                DRM_DEBUG("invalid crtc %d\n", crtc);
3167                return;
3168        }
3169
3170        switch (state) {
3171        case AMDGPU_IRQ_STATE_DISABLE:
3172                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3173                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3174                                                  VBLANK_INTERRUPT_MASK, 0);
3175                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3176                break;
3177        case AMDGPU_IRQ_STATE_ENABLE:
3178                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3179                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3180                                                  VBLANK_INTERRUPT_MASK, 1);
3181                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3182                break;
3183        default:
3184                break;
3185        }
3186}
3187
3188static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3189                                                    int crtc,
3190                                                    enum amdgpu_interrupt_state state)
3191{
3192        u32 lb_interrupt_mask;
3193
3194        if (crtc >= adev->mode_info.num_crtc) {
3195                DRM_DEBUG("invalid crtc %d\n", crtc);
3196                return;
3197        }
3198
3199        switch (state) {
3200        case AMDGPU_IRQ_STATE_DISABLE:
3201                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3202                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3203                                                  VLINE_INTERRUPT_MASK, 0);
3204                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3205                break;
3206        case AMDGPU_IRQ_STATE_ENABLE:
3207                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3208                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3209                                                  VLINE_INTERRUPT_MASK, 1);
3210                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3211                break;
3212        default:
3213                break;
3214        }
3215}
3216
3217static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3218                                        struct amdgpu_irq_src *source,
3219                                        unsigned hpd,
3220                                        enum amdgpu_interrupt_state state)
3221{
3222        u32 tmp;
3223
3224        if (hpd >= adev->mode_info.num_hpd) {
3225                DRM_DEBUG("invalid hdp %d\n", hpd);
3226                return 0;
3227        }
3228
3229        switch (state) {
3230        case AMDGPU_IRQ_STATE_DISABLE:
3231                tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3232                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3233                WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3234                break;
3235        case AMDGPU_IRQ_STATE_ENABLE:
3236                tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3237                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3238                WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3239                break;
3240        default:
3241                break;
3242        }
3243
3244        return 0;
3245}
3246
3247static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3248                                        struct amdgpu_irq_src *source,
3249                                        unsigned type,
3250                                        enum amdgpu_interrupt_state state)
3251{
3252        switch (type) {
3253        case AMDGPU_CRTC_IRQ_VBLANK1:
3254                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3255                break;
3256        case AMDGPU_CRTC_IRQ_VBLANK2:
3257                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3258                break;
3259        case AMDGPU_CRTC_IRQ_VBLANK3:
3260                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3261                break;
3262        case AMDGPU_CRTC_IRQ_VBLANK4:
3263                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3264                break;
3265        case AMDGPU_CRTC_IRQ_VBLANK5:
3266                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3267                break;
3268        case AMDGPU_CRTC_IRQ_VBLANK6:
3269                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3270                break;
3271        case AMDGPU_CRTC_IRQ_VLINE1:
3272                dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3273                break;
3274        case AMDGPU_CRTC_IRQ_VLINE2:
3275                dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3276                break;
3277        case AMDGPU_CRTC_IRQ_VLINE3:
3278                dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3279                break;
3280        case AMDGPU_CRTC_IRQ_VLINE4:
3281                dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3282                break;
3283        case AMDGPU_CRTC_IRQ_VLINE5:
3284                dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3285                break;
3286         case AMDGPU_CRTC_IRQ_VLINE6:
3287                dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3288                break;
3289        default:
3290                break;
3291        }
3292        return 0;
3293}
3294
3295static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3296                                            struct amdgpu_irq_src *src,
3297                                            unsigned type,
3298                                            enum amdgpu_interrupt_state state)
3299{
3300        u32 reg;
3301
3302        if (type >= adev->mode_info.num_crtc) {
3303                DRM_ERROR("invalid pageflip crtc %d\n", type);
3304                return -EINVAL;
3305        }
3306
3307        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3308        if (state == AMDGPU_IRQ_STATE_DISABLE)
3309                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3310                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3311        else
3312                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3313                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3314
3315        return 0;
3316}
3317
3318static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3319                                  struct amdgpu_irq_src *source,
3320                                  struct amdgpu_iv_entry *entry)
3321{
3322        unsigned long flags;
3323        unsigned crtc_id;
3324        struct amdgpu_crtc *amdgpu_crtc;
3325        struct amdgpu_flip_work *works;
3326
3327        crtc_id = (entry->src_id - 8) >> 1;
3328        amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3329
3330        if (crtc_id >= adev->mode_info.num_crtc) {
3331                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3332                return -EINVAL;
3333        }
3334
3335        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3336            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3337                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3338                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3339
3340        /* IRQ could occur when in initial stage */
3341        if(amdgpu_crtc == NULL)
3342                return 0;
3343
3344        spin_lock_irqsave(&adev->ddev->event_lock, flags);
3345        works = amdgpu_crtc->pflip_works;
3346        if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3347                DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3348                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3349                                                 amdgpu_crtc->pflip_status,
3350                                                 AMDGPU_FLIP_SUBMITTED);
3351                spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3352                return 0;
3353        }
3354
3355        /* page flip completed. clean up */
3356        amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3357        amdgpu_crtc->pflip_works = NULL;
3358
3359        /* wakeup usersapce */
3360        if(works->event)
3361                drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3362
3363        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3364
3365        drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3366        queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3367
3368        return 0;
3369}
3370
3371static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3372                                  int hpd)
3373{
3374        u32 tmp;
3375
3376        if (hpd >= adev->mode_info.num_hpd) {
3377                DRM_DEBUG("invalid hdp %d\n", hpd);
3378                return;
3379        }
3380
3381        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3382        tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3383        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3384}
3385
3386static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3387                                          int crtc)
3388{
3389        u32 tmp;
3390
3391        if (crtc >= adev->mode_info.num_crtc) {
3392                DRM_DEBUG("invalid crtc %d\n", crtc);
3393                return;
3394        }
3395
3396        tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3397        tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3398        WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3399}
3400
3401static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3402                                         int crtc)
3403{
3404        u32 tmp;
3405
3406        if (crtc >= adev->mode_info.num_crtc) {
3407                DRM_DEBUG("invalid crtc %d\n", crtc);
3408                return;
3409        }
3410
3411        tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3412        tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3413        WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3414}
3415
3416static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3417                                struct amdgpu_irq_src *source,
3418                                struct amdgpu_iv_entry *entry)
3419{
3420        unsigned crtc = entry->src_id - 1;
3421        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3422        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3423
3424        switch (entry->src_data) {
3425        case 0: /* vblank */
3426                if (disp_int & interrupt_status_offsets[crtc].vblank)
3427                        dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3428                else
3429                        DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3430
3431                if (amdgpu_irq_enabled(adev, source, irq_type)) {
3432                        drm_handle_vblank(adev->ddev, crtc);
3433                }
3434                DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3435
3436                break;
3437        case 1: /* vline */
3438                if (disp_int & interrupt_status_offsets[crtc].vline)
3439                        dce_v11_0_crtc_vline_int_ack(adev, crtc);
3440                else
3441                        DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3442
3443                DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3444
3445                break;
3446        default:
3447                DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3448                break;
3449        }
3450
3451        return 0;
3452}
3453
3454static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3455                             struct amdgpu_irq_src *source,
3456                             struct amdgpu_iv_entry *entry)
3457{
3458        uint32_t disp_int, mask;
3459        unsigned hpd;
3460
3461        if (entry->src_data >= adev->mode_info.num_hpd) {
3462                DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3463                return 0;
3464        }
3465
3466        hpd = entry->src_data;
3467        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3468        mask = interrupt_status_offsets[hpd].hpd;
3469
3470        if (disp_int & mask) {
3471                dce_v11_0_hpd_int_ack(adev, hpd);
3472                schedule_work(&adev->hotplug_work);
3473                DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3474        }
3475
3476        return 0;
3477}
3478
3479static int dce_v11_0_set_clockgating_state(void *handle,
3480                                          enum amd_clockgating_state state)
3481{
3482        return 0;
3483}
3484
3485static int dce_v11_0_set_powergating_state(void *handle,
3486                                          enum amd_powergating_state state)
3487{
3488        return 0;
3489}
3490
3491const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3492        .early_init = dce_v11_0_early_init,
3493        .late_init = NULL,
3494        .sw_init = dce_v11_0_sw_init,
3495        .sw_fini = dce_v11_0_sw_fini,
3496        .hw_init = dce_v11_0_hw_init,
3497        .hw_fini = dce_v11_0_hw_fini,
3498        .suspend = dce_v11_0_suspend,
3499        .resume = dce_v11_0_resume,
3500        .is_idle = dce_v11_0_is_idle,
3501        .wait_for_idle = dce_v11_0_wait_for_idle,
3502        .soft_reset = dce_v11_0_soft_reset,
3503        .print_status = dce_v11_0_print_status,
3504        .set_clockgating_state = dce_v11_0_set_clockgating_state,
3505        .set_powergating_state = dce_v11_0_set_powergating_state,
3506};
3507
3508static void
3509dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3510                          struct drm_display_mode *mode,
3511                          struct drm_display_mode *adjusted_mode)
3512{
3513        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3514
3515        amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3516
3517        /* need to call this here rather than in prepare() since we need some crtc info */
3518        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3519
3520        /* set scaler clears this on some chips */
3521        dce_v11_0_set_interleave(encoder->crtc, mode);
3522
3523        if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3524                dce_v11_0_afmt_enable(encoder, true);
3525                dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3526        }
3527}
3528
3529static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3530{
3531        struct amdgpu_device *adev = encoder->dev->dev_private;
3532        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3533        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3534
3535        if ((amdgpu_encoder->active_device &
3536             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3537            (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3538             ENCODER_OBJECT_ID_NONE)) {
3539                struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3540                if (dig) {
3541                        dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3542                        if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3543                                dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3544                }
3545        }
3546
3547        amdgpu_atombios_scratch_regs_lock(adev, true);
3548
3549        if (connector) {
3550                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3551
3552                /* select the clock/data port if it uses a router */
3553                if (amdgpu_connector->router.cd_valid)
3554                        amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3555
3556                /* turn eDP panel on for mode set */
3557                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3558                        amdgpu_atombios_encoder_set_edp_panel_power(connector,
3559                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
3560        }
3561
3562        /* this is needed for the pll/ss setup to work correctly in some cases */
3563        amdgpu_atombios_encoder_set_crtc_source(encoder);
3564        /* set up the FMT blocks */
3565        dce_v11_0_program_fmt(encoder);
3566}
3567
3568static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3569{
3570        struct drm_device *dev = encoder->dev;
3571        struct amdgpu_device *adev = dev->dev_private;
3572
3573        /* need to call this here as we need the crtc set up */
3574        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3575        amdgpu_atombios_scratch_regs_lock(adev, false);
3576}
3577
3578static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3579{
3580        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3581        struct amdgpu_encoder_atom_dig *dig;
3582
3583        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3584
3585        if (amdgpu_atombios_encoder_is_digital(encoder)) {
3586                if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3587                        dce_v11_0_afmt_enable(encoder, false);
3588                dig = amdgpu_encoder->enc_priv;
3589                dig->dig_encoder = -1;
3590        }
3591        amdgpu_encoder->active_device = 0;
3592}
3593
3594/* these are handled by the primary encoders */
3595static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3596{
3597
3598}
3599
3600static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3601{
3602
3603}
3604
3605static void
3606dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3607                      struct drm_display_mode *mode,
3608                      struct drm_display_mode *adjusted_mode)
3609{
3610
3611}
3612
3613static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3614{
3615
3616}
3617
3618static void
3619dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3620{
3621
3622}
3623
3624static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3625                                    const struct drm_display_mode *mode,
3626                                    struct drm_display_mode *adjusted_mode)
3627{
3628        return true;
3629}
3630
3631static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3632        .dpms = dce_v11_0_ext_dpms,
3633        .mode_fixup = dce_v11_0_ext_mode_fixup,
3634        .prepare = dce_v11_0_ext_prepare,
3635        .mode_set = dce_v11_0_ext_mode_set,
3636        .commit = dce_v11_0_ext_commit,
3637        .disable = dce_v11_0_ext_disable,
3638        /* no detect for TMDS/LVDS yet */
3639};
3640
3641static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3642        .dpms = amdgpu_atombios_encoder_dpms,
3643        .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3644        .prepare = dce_v11_0_encoder_prepare,
3645        .mode_set = dce_v11_0_encoder_mode_set,
3646        .commit = dce_v11_0_encoder_commit,
3647        .disable = dce_v11_0_encoder_disable,
3648        .detect = amdgpu_atombios_encoder_dig_detect,
3649};
3650
3651static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3652        .dpms = amdgpu_atombios_encoder_dpms,
3653        .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3654        .prepare = dce_v11_0_encoder_prepare,
3655        .mode_set = dce_v11_0_encoder_mode_set,
3656        .commit = dce_v11_0_encoder_commit,
3657        .detect = amdgpu_atombios_encoder_dac_detect,
3658};
3659
3660static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3661{
3662        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3663        if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3664                amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3665        kfree(amdgpu_encoder->enc_priv);
3666        drm_encoder_cleanup(encoder);
3667        kfree(amdgpu_encoder);
3668}
3669
3670static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3671        .destroy = dce_v11_0_encoder_destroy,
3672};
3673
3674static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3675                                 uint32_t encoder_enum,
3676                                 uint32_t supported_device,
3677                                 u16 caps)
3678{
3679        struct drm_device *dev = adev->ddev;
3680        struct drm_encoder *encoder;
3681        struct amdgpu_encoder *amdgpu_encoder;
3682
3683        /* see if we already added it */
3684        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3685                amdgpu_encoder = to_amdgpu_encoder(encoder);
3686                if (amdgpu_encoder->encoder_enum == encoder_enum) {
3687                        amdgpu_encoder->devices |= supported_device;
3688                        return;
3689                }
3690
3691        }
3692
3693        /* add a new one */
3694        amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3695        if (!amdgpu_encoder)
3696                return;
3697
3698        encoder = &amdgpu_encoder->base;
3699        switch (adev->mode_info.num_crtc) {
3700        case 1:
3701                encoder->possible_crtcs = 0x1;
3702                break;
3703        case 2:
3704        default:
3705                encoder->possible_crtcs = 0x3;
3706                break;
3707        case 3:
3708                encoder->possible_crtcs = 0x7;
3709                break;
3710        case 4:
3711                encoder->possible_crtcs = 0xf;
3712                break;
3713        case 5:
3714                encoder->possible_crtcs = 0x1f;
3715                break;
3716        case 6:
3717                encoder->possible_crtcs = 0x3f;
3718                break;
3719        }
3720
3721        amdgpu_encoder->enc_priv = NULL;
3722
3723        amdgpu_encoder->encoder_enum = encoder_enum;
3724        amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3725        amdgpu_encoder->devices = supported_device;
3726        amdgpu_encoder->rmx_type = RMX_OFF;
3727        amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3728        amdgpu_encoder->is_ext_encoder = false;
3729        amdgpu_encoder->caps = caps;
3730
3731        switch (amdgpu_encoder->encoder_id) {
3732        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3733        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3734                drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3735                                 DRM_MODE_ENCODER_DAC);
3736                drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3737                break;
3738        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3739        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3740        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3741        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3742        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3743                if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3744                        amdgpu_encoder->rmx_type = RMX_FULL;
3745                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3746                                         DRM_MODE_ENCODER_LVDS);
3747                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3748                } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3749                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3750                                         DRM_MODE_ENCODER_DAC);
3751                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3752                } else {
3753                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3754                                         DRM_MODE_ENCODER_TMDS);
3755                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3756                }
3757                drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3758                break;
3759        case ENCODER_OBJECT_ID_SI170B:
3760        case ENCODER_OBJECT_ID_CH7303:
3761        case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3762        case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3763        case ENCODER_OBJECT_ID_TITFP513:
3764        case ENCODER_OBJECT_ID_VT1623:
3765        case ENCODER_OBJECT_ID_HDMI_SI1930:
3766        case ENCODER_OBJECT_ID_TRAVIS:
3767        case ENCODER_OBJECT_ID_NUTMEG:
3768                /* these are handled by the primary encoders */
3769                amdgpu_encoder->is_ext_encoder = true;
3770                if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3771                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3772                                         DRM_MODE_ENCODER_LVDS);
3773                else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3774                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3775                                         DRM_MODE_ENCODER_DAC);
3776                else
3777                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3778                                         DRM_MODE_ENCODER_TMDS);
3779                drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3780                break;
3781        }
3782}
3783
3784static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3785        .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3786        .bandwidth_update = &dce_v11_0_bandwidth_update,
3787        .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3788        .vblank_wait = &dce_v11_0_vblank_wait,
3789        .is_display_hung = &dce_v11_0_is_display_hung,
3790        .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3791        .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3792        .hpd_sense = &dce_v11_0_hpd_sense,
3793        .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3794        .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3795        .page_flip = &dce_v11_0_page_flip,
3796        .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3797        .add_encoder = &dce_v11_0_encoder_add,
3798        .add_connector = &amdgpu_connector_add,
3799        .stop_mc_access = &dce_v11_0_stop_mc_access,
3800        .resume_mc_access = &dce_v11_0_resume_mc_access,
3801};
3802
3803static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3804{
3805        if (adev->mode_info.funcs == NULL)
3806                adev->mode_info.funcs = &dce_v11_0_display_funcs;
3807}
3808
3809static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3810        .set = dce_v11_0_set_crtc_irq_state,
3811        .process = dce_v11_0_crtc_irq,
3812};
3813
3814static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3815        .set = dce_v11_0_set_pageflip_irq_state,
3816        .process = dce_v11_0_pageflip_irq,
3817};
3818
3819static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3820        .set = dce_v11_0_set_hpd_irq_state,
3821        .process = dce_v11_0_hpd_irq,
3822};
3823
3824static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3825{
3826        adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3827        adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3828
3829        adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3830        adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3831
3832        adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3833        adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3834}
Note: See TracBrowser for help on using the repository browser.