source: src/linux/universal/linux-4.4/drivers/gpu/drm/i915/i915_drv.h @ 30821

Last change on this file since 30821 was 30821, checked in by brainslayer, 6 months ago

update kernel

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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include "i915_reg.h"
37#include "intel_bios.h"
38#include "intel_ringbuffer.h"
39#include "intel_lrc.h"
40#include "i915_gem_gtt.h"
41#include "i915_gem_render_state.h"
42#include <linux/io-mapping.h>
43#include <linux/i2c.h>
44#include <linux/i2c-algo-bit.h>
45#include <drm/intel-gtt.h>
46#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47#include <drm/drm_gem.h>
48#include <linux/backlight.h>
49#include <linux/hashtable.h>
50#include <linux/intel-iommu.h>
51#include <linux/kref.h>
52#include <linux/pm_qos.h>
53#include "intel_guc.h"
54
55/* General customization:
56 */
57
58#define DRIVER_NAME             "i915"
59#define DRIVER_DESC             "Intel Graphics"
60#define DRIVER_DATE             "20151010"
61
62#undef WARN_ON
63/* Many gcc seem to no see through this and fall over :( */
64#if 0
65#define WARN_ON(x) ({ \
66        bool __i915_warn_cond = (x); \
67        if (__builtin_constant_p(__i915_warn_cond)) \
68                BUILD_BUG_ON(__i915_warn_cond); \
69        WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70#else
71#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
72#endif
73
74#undef WARN_ON_ONCE
75#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
76
77#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78                             (long) (x), __func__);
79
80/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem.  This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
85 * spam.
86 */
87#define I915_STATE_WARN(condition, format...) ({                        \
88        int __ret_warn_on = !!(condition);                              \
89        if (unlikely(__ret_warn_on)) {                                  \
90                if (i915.verbose_state_checks)                          \
91                        WARN(1, format);                                \
92                else                                                    \
93                        DRM_ERROR(format);                              \
94        }                                                               \
95        unlikely(__ret_warn_on);                                        \
96})
97
98#define I915_STATE_WARN_ON(condition) ({                                \
99        int __ret_warn_on = !!(condition);                              \
100        if (unlikely(__ret_warn_on)) {                                  \
101                if (i915.verbose_state_checks)                          \
102                        WARN(1, "WARN_ON(" #condition ")\n");           \
103                else                                                    \
104                        DRM_ERROR("WARN_ON(" #condition ")\n");         \
105        }                                                               \
106        unlikely(__ret_warn_on);                                        \
107})
108
109static inline const char *yesno(bool v)
110{
111        return v ? "yes" : "no";
112}
113
114enum pipe {
115        INVALID_PIPE = -1,
116        PIPE_A = 0,
117        PIPE_B,
118        PIPE_C,
119        _PIPE_EDP,
120        I915_MAX_PIPES = _PIPE_EDP
121};
122#define pipe_name(p) ((p) + 'A')
123
124enum transcoder {
125        TRANSCODER_A = 0,
126        TRANSCODER_B,
127        TRANSCODER_C,
128        TRANSCODER_EDP,
129        I915_MAX_TRANSCODERS
130};
131#define transcoder_name(t) ((t) + 'A')
132
133/*
134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
135 * number of planes per CRTC.  Not all platforms really have this many planes,
136 * which means some arrays of size I915_MAX_PLANES may have unused entries
137 * between the topmost sprite plane and the cursor plane.
138 */
139enum plane {
140        PLANE_A = 0,
141        PLANE_B,
142        PLANE_C,
143        PLANE_CURSOR,
144        I915_MAX_PLANES,
145};
146#define plane_name(p) ((p) + 'A')
147
148#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
149
150enum port {
151        PORT_A = 0,
152        PORT_B,
153        PORT_C,
154        PORT_D,
155        PORT_E,
156        I915_MAX_PORTS
157};
158#define port_name(p) ((p) + 'A')
159
160#define I915_NUM_PHYS_VLV 2
161
162enum dpio_channel {
163        DPIO_CH0,
164        DPIO_CH1
165};
166
167enum dpio_phy {
168        DPIO_PHY0,
169        DPIO_PHY1
170};
171
172enum intel_display_power_domain {
173        POWER_DOMAIN_PIPE_A,
174        POWER_DOMAIN_PIPE_B,
175        POWER_DOMAIN_PIPE_C,
176        POWER_DOMAIN_PIPE_A_PANEL_FITTER,
177        POWER_DOMAIN_PIPE_B_PANEL_FITTER,
178        POWER_DOMAIN_PIPE_C_PANEL_FITTER,
179        POWER_DOMAIN_TRANSCODER_A,
180        POWER_DOMAIN_TRANSCODER_B,
181        POWER_DOMAIN_TRANSCODER_C,
182        POWER_DOMAIN_TRANSCODER_EDP,
183        POWER_DOMAIN_PORT_DDI_A_2_LANES,
184        POWER_DOMAIN_PORT_DDI_A_4_LANES,
185        POWER_DOMAIN_PORT_DDI_B_2_LANES,
186        POWER_DOMAIN_PORT_DDI_B_4_LANES,
187        POWER_DOMAIN_PORT_DDI_C_2_LANES,
188        POWER_DOMAIN_PORT_DDI_C_4_LANES,
189        POWER_DOMAIN_PORT_DDI_D_2_LANES,
190        POWER_DOMAIN_PORT_DDI_D_4_LANES,
191        POWER_DOMAIN_PORT_DDI_E_2_LANES,
192        POWER_DOMAIN_PORT_DSI,
193        POWER_DOMAIN_PORT_CRT,
194        POWER_DOMAIN_PORT_OTHER,
195        POWER_DOMAIN_VGA,
196        POWER_DOMAIN_AUDIO,
197        POWER_DOMAIN_PLLS,
198        POWER_DOMAIN_AUX_A,
199        POWER_DOMAIN_AUX_B,
200        POWER_DOMAIN_AUX_C,
201        POWER_DOMAIN_AUX_D,
202        POWER_DOMAIN_GMBUS,
203        POWER_DOMAIN_INIT,
204
205        POWER_DOMAIN_NUM,
206};
207
208#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
209#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
210                ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
211#define POWER_DOMAIN_TRANSCODER(tran) \
212        ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
213         (tran) + POWER_DOMAIN_TRANSCODER_A)
214
215enum hpd_pin {
216        HPD_NONE = 0,
217        HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
218        HPD_CRT,
219        HPD_SDVO_B,
220        HPD_SDVO_C,
221        HPD_PORT_A,
222        HPD_PORT_B,
223        HPD_PORT_C,
224        HPD_PORT_D,
225        HPD_PORT_E,
226        HPD_NUM_PINS
227};
228
229#define for_each_hpd_pin(__pin) \
230        for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
231
232struct i915_hotplug {
233        struct work_struct hotplug_work;
234
235        struct {
236                unsigned long last_jiffies;
237                int count;
238                enum {
239                        HPD_ENABLED = 0,
240                        HPD_DISABLED = 1,
241                        HPD_MARK_DISABLED = 2
242                } state;
243        } stats[HPD_NUM_PINS];
244        u32 event_bits;
245        struct delayed_work reenable_work;
246
247        struct intel_digital_port *irq_port[I915_MAX_PORTS];
248        u32 long_port_mask;
249        u32 short_port_mask;
250        struct work_struct dig_port_work;
251
252        /*
253         * if we get a HPD irq from DP and a HPD irq from non-DP
254         * the non-DP HPD could block the workqueue on a mode config
255         * mutex getting, that userspace may have taken. However
256         * userspace is waiting on the DP workqueue to run which is
257         * blocked behind the non-DP one.
258         */
259        struct workqueue_struct *dp_wq;
260};
261
262#define I915_GEM_GPU_DOMAINS \
263        (I915_GEM_DOMAIN_RENDER | \
264         I915_GEM_DOMAIN_SAMPLER | \
265         I915_GEM_DOMAIN_COMMAND | \
266         I915_GEM_DOMAIN_INSTRUCTION | \
267         I915_GEM_DOMAIN_VERTEX)
268
269#define for_each_pipe(__dev_priv, __p) \
270        for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
271#define for_each_plane(__dev_priv, __pipe, __p)                         \
272        for ((__p) = 0;                                                 \
273             (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
274             (__p)++)
275#define for_each_sprite(__dev_priv, __p, __s)                           \
276        for ((__s) = 0;                                                 \
277             (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
278             (__s)++)
279
280#define for_each_crtc(dev, crtc) \
281        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
282
283#define for_each_intel_plane(dev, intel_plane) \
284        list_for_each_entry(intel_plane,                        \
285                            &dev->mode_config.plane_list,       \
286                            base.head)
287
288#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
289        list_for_each_entry(intel_plane,                                \
290                            &(dev)->mode_config.plane_list,             \
291                            base.head)                                  \
292                if ((intel_plane)->pipe == (intel_crtc)->pipe)
293
294#define for_each_intel_crtc(dev, intel_crtc) \
295        list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
296
297#define for_each_intel_encoder(dev, intel_encoder)              \
298        list_for_each_entry(intel_encoder,                      \
299                            &(dev)->mode_config.encoder_list,   \
300                            base.head)
301
302#define for_each_intel_connector(dev, intel_connector)          \
303        list_for_each_entry(intel_connector,                    \
304                            &dev->mode_config.connector_list,   \
305                            base.head)
306
307#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
308        list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
309                if ((intel_encoder)->base.crtc == (__crtc))
310
311#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
312        list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
313                if ((intel_connector)->base.encoder == (__encoder))
314
315#define for_each_power_domain(domain, mask)                             \
316        for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
317                if ((1 << (domain)) & (mask))
318
319struct drm_i915_private;
320struct i915_mm_struct;
321struct i915_mmu_object;
322
323struct drm_i915_file_private {
324        struct drm_i915_private *dev_priv;
325        struct drm_file *file;
326
327        struct {
328                spinlock_t lock;
329                struct list_head request_list;
330/* 20ms is a fairly arbitrary limit (greater than the average frame time)
331 * chosen to prevent the CPU getting more than a frame ahead of the GPU
332 * (when using lax throttling for the frontbuffer). We also use it to
333 * offer free GPU waitboosts for severely congested workloads.
334 */
335#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
336        } mm;
337        struct idr context_idr;
338
339        struct intel_rps_client {
340                struct list_head link;
341                unsigned boosts;
342        } rps;
343
344        struct intel_engine_cs *bsd_ring;
345};
346
347enum intel_dpll_id {
348        DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
349        /* real shared dpll ids must be >= 0 */
350        DPLL_ID_PCH_PLL_A = 0,
351        DPLL_ID_PCH_PLL_B = 1,
352        /* hsw/bdw */
353        DPLL_ID_WRPLL1 = 0,
354        DPLL_ID_WRPLL2 = 1,
355        DPLL_ID_SPLL = 2,
356
357        /* skl */
358        DPLL_ID_SKL_DPLL1 = 0,
359        DPLL_ID_SKL_DPLL2 = 1,
360        DPLL_ID_SKL_DPLL3 = 2,
361};
362#define I915_NUM_PLLS 3
363
364struct intel_dpll_hw_state {
365        /* i9xx, pch plls */
366        uint32_t dpll;
367        uint32_t dpll_md;
368        uint32_t fp0;
369        uint32_t fp1;
370
371        /* hsw, bdw */
372        uint32_t wrpll;
373        uint32_t spll;
374
375        /* skl */
376        /*
377         * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
378         * lower part of ctrl1 and they get shifted into position when writing
379         * the register.  This allows us to easily compare the state to share
380         * the DPLL.
381         */
382        uint32_t ctrl1;
383        /* HDMI only, 0 when used for DP */
384        uint32_t cfgcr1, cfgcr2;
385
386        /* bxt */
387        uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
388                 pcsdw12;
389};
390
391struct intel_shared_dpll_config {
392        unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
393        struct intel_dpll_hw_state hw_state;
394};
395
396struct intel_shared_dpll {
397        struct intel_shared_dpll_config config;
398
399        int active; /* count of number of active CRTCs (i.e. DPMS on) */
400        bool on; /* is the PLL actually active? Disabled during modeset */
401        const char *name;
402        /* should match the index in the dev_priv->shared_dplls array */
403        enum intel_dpll_id id;
404        /* The mode_set hook is optional and should be used together with the
405         * intel_prepare_shared_dpll function. */
406        void (*mode_set)(struct drm_i915_private *dev_priv,
407                         struct intel_shared_dpll *pll);
408        void (*enable)(struct drm_i915_private *dev_priv,
409                       struct intel_shared_dpll *pll);
410        void (*disable)(struct drm_i915_private *dev_priv,
411                        struct intel_shared_dpll *pll);
412        bool (*get_hw_state)(struct drm_i915_private *dev_priv,
413                             struct intel_shared_dpll *pll,
414                             struct intel_dpll_hw_state *hw_state);
415};
416
417#define SKL_DPLL0 0
418#define SKL_DPLL1 1
419#define SKL_DPLL2 2
420#define SKL_DPLL3 3
421
422/* Used by dp and fdi links */
423struct intel_link_m_n {
424        uint32_t        tu;
425        uint32_t        gmch_m;
426        uint32_t        gmch_n;
427        uint32_t        link_m;
428        uint32_t        link_n;
429};
430
431void intel_link_compute_m_n(int bpp, int nlanes,
432                            int pixel_clock, int link_clock,
433                            struct intel_link_m_n *m_n);
434
435/* Interface history:
436 *
437 * 1.1: Original.
438 * 1.2: Add Power Management
439 * 1.3: Add vblank support
440 * 1.4: Fix cmdbuffer path, add heap destroy
441 * 1.5: Add vblank pipe configuration
442 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
443 *      - Support vertical blank on secondary display pipe
444 */
445#define DRIVER_MAJOR            1
446#define DRIVER_MINOR            6
447#define DRIVER_PATCHLEVEL       0
448
449#define WATCH_LISTS     0
450
451struct opregion_header;
452struct opregion_acpi;
453struct opregion_swsci;
454struct opregion_asle;
455
456struct intel_opregion {
457        struct opregion_header *header;
458        struct opregion_acpi *acpi;
459        struct opregion_swsci *swsci;
460        u32 swsci_gbda_sub_functions;
461        u32 swsci_sbcb_sub_functions;
462        struct opregion_asle *asle;
463        void *vbt;
464        u32 *lid_state;
465        struct work_struct asle_work;
466};
467#define OPREGION_SIZE            (8*1024)
468
469struct intel_overlay;
470struct intel_overlay_error_state;
471
472#define I915_FENCE_REG_NONE -1
473#define I915_MAX_NUM_FENCES 32
474/* 32 fences + sign bit for FENCE_REG_NONE */
475#define I915_MAX_NUM_FENCE_BITS 6
476
477struct drm_i915_fence_reg {
478        struct list_head lru_list;
479        struct drm_i915_gem_object *obj;
480        int pin_count;
481};
482
483struct sdvo_device_mapping {
484        u8 initialized;
485        u8 dvo_port;
486        u8 slave_addr;
487        u8 dvo_wiring;
488        u8 i2c_pin;
489        u8 ddc_pin;
490};
491
492struct intel_display_error_state;
493
494struct drm_i915_error_state {
495        struct kref ref;
496        struct timeval time;
497
498        char error_msg[128];
499        int iommu;
500        u32 reset_count;
501        u32 suspend_count;
502
503        /* Generic register state */
504        u32 eir;
505        u32 pgtbl_er;
506        u32 ier;
507        u32 gtier[4];
508        u32 ccid;
509        u32 derrmr;
510        u32 forcewake;
511        u32 error; /* gen6+ */
512        u32 err_int; /* gen7 */
513        u32 fault_data0; /* gen8, gen9 */
514        u32 fault_data1; /* gen8, gen9 */
515        u32 done_reg;
516        u32 gac_eco;
517        u32 gam_ecochk;
518        u32 gab_ctl;
519        u32 gfx_mode;
520        u32 extra_instdone[I915_NUM_INSTDONE_REG];
521        u64 fence[I915_MAX_NUM_FENCES];
522        struct intel_overlay_error_state *overlay;
523        struct intel_display_error_state *display;
524        struct drm_i915_error_object *semaphore_obj;
525
526        struct drm_i915_error_ring {
527                bool valid;
528                /* Software tracked state */
529                bool waiting;
530                int hangcheck_score;
531                enum intel_ring_hangcheck_action hangcheck_action;
532                int num_requests;
533
534                /* our own tracking of ring head and tail */
535                u32 cpu_ring_head;
536                u32 cpu_ring_tail;
537
538                u32 semaphore_seqno[I915_NUM_RINGS - 1];
539
540                /* Register state */
541                u32 start;
542                u32 tail;
543                u32 head;
544                u32 ctl;
545                u32 hws;
546                u32 ipeir;
547                u32 ipehr;
548                u32 instdone;
549                u32 bbstate;
550                u32 instpm;
551                u32 instps;
552                u32 seqno;
553                u64 bbaddr;
554                u64 acthd;
555                u32 fault_reg;
556                u64 faddr;
557                u32 rc_psmi; /* sleep state */
558                u32 semaphore_mboxes[I915_NUM_RINGS - 1];
559
560                struct drm_i915_error_object {
561                        int page_count;
562                        u64 gtt_offset;
563                        u32 *pages[0];
564                } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
565
566                struct drm_i915_error_request {
567                        long jiffies;
568                        u32 seqno;
569                        u32 tail;
570                } *requests;
571
572                struct {
573                        u32 gfx_mode;
574                        union {
575                                u64 pdp[4];
576                                u32 pp_dir_base;
577                        };
578                } vm_info;
579
580                pid_t pid;
581                char comm[TASK_COMM_LEN];
582        } ring[I915_NUM_RINGS];
583
584        struct drm_i915_error_buffer {
585                u32 size;
586                u32 name;
587                u32 rseqno[I915_NUM_RINGS], wseqno;
588                u64 gtt_offset;
589                u32 read_domains;
590                u32 write_domain;
591                s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
592                s32 pinned:2;
593                u32 tiling:2;
594                u32 dirty:1;
595                u32 purgeable:1;
596                u32 userptr:1;
597                s32 ring:4;
598                u32 cache_level:3;
599        } **active_bo, **pinned_bo;
600
601        u32 *active_bo_count, *pinned_bo_count;
602        u32 vm_count;
603};
604
605struct intel_connector;
606struct intel_encoder;
607struct intel_crtc_state;
608struct intel_initial_plane_config;
609struct intel_crtc;
610struct intel_limit;
611struct dpll;
612
613struct drm_i915_display_funcs {
614        int (*get_display_clock_speed)(struct drm_device *dev);
615        int (*get_fifo_size)(struct drm_device *dev, int plane);
616        /**
617         * find_dpll() - Find the best values for the PLL
618         * @limit: limits for the PLL
619         * @crtc: current CRTC
620         * @target: target frequency in kHz
621         * @refclk: reference clock frequency in kHz
622         * @match_clock: if provided, @best_clock P divider must
623         *               match the P divider from @match_clock
624         *               used for LVDS downclocking
625         * @best_clock: best PLL values found
626         *
627         * Returns true on success, false on failure.
628         */
629        bool (*find_dpll)(const struct intel_limit *limit,
630                          struct intel_crtc_state *crtc_state,
631                          int target, int refclk,
632                          struct dpll *match_clock,
633                          struct dpll *best_clock);
634        void (*update_wm)(struct drm_crtc *crtc);
635        void (*update_sprite_wm)(struct drm_plane *plane,
636                                 struct drm_crtc *crtc,
637                                 uint32_t sprite_width, uint32_t sprite_height,
638                                 int pixel_size, bool enable, bool scaled);
639        int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
640        void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
641        /* Returns the active state of the crtc, and if the crtc is active,
642         * fills out the pipe-config with the hw state. */
643        bool (*get_pipe_config)(struct intel_crtc *,
644                                struct intel_crtc_state *);
645        void (*get_initial_plane_config)(struct intel_crtc *,
646                                         struct intel_initial_plane_config *);
647        int (*crtc_compute_clock)(struct intel_crtc *crtc,
648                                  struct intel_crtc_state *crtc_state);
649        void (*crtc_enable)(struct drm_crtc *crtc);
650        void (*crtc_disable)(struct drm_crtc *crtc);
651        void (*audio_codec_enable)(struct drm_connector *connector,
652                                   struct intel_encoder *encoder,
653                                   const struct drm_display_mode *adjusted_mode);
654        void (*audio_codec_disable)(struct intel_encoder *encoder);
655        void (*fdi_link_train)(struct drm_crtc *crtc);
656        void (*init_clock_gating)(struct drm_device *dev);
657        int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
658                          struct drm_framebuffer *fb,
659                          struct drm_i915_gem_object *obj,
660                          struct drm_i915_gem_request *req,
661                          uint32_t flags);
662        void (*update_primary_plane)(struct drm_crtc *crtc,
663                                     struct drm_framebuffer *fb,
664                                     int x, int y);
665        void (*hpd_irq_setup)(struct drm_device *dev);
666        /* clock updates for mode set */
667        /* cursor updates */
668        /* render clock increase/decrease */
669        /* display clock increase/decrease */
670        /* pll clock increase/decrease */
671};
672
673enum forcewake_domain_id {
674        FW_DOMAIN_ID_RENDER = 0,
675        FW_DOMAIN_ID_BLITTER,
676        FW_DOMAIN_ID_MEDIA,
677
678        FW_DOMAIN_ID_COUNT
679};
680
681enum forcewake_domains {
682        FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
683        FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
684        FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
685        FORCEWAKE_ALL = (FORCEWAKE_RENDER |
686                         FORCEWAKE_BLITTER |
687                         FORCEWAKE_MEDIA)
688};
689
690struct intel_uncore_funcs {
691        void (*force_wake_get)(struct drm_i915_private *dev_priv,
692                                                        enum forcewake_domains domains);
693        void (*force_wake_put)(struct drm_i915_private *dev_priv,
694                                                        enum forcewake_domains domains);
695
696        uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
697        uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
698        uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
699        uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
700
701        void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
702                                uint8_t val, bool trace);
703        void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
704                                uint16_t val, bool trace);
705        void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
706                                uint32_t val, bool trace);
707        void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
708                                uint64_t val, bool trace);
709};
710
711struct intel_uncore {
712        spinlock_t lock; /** lock is also taken in irq contexts. */
713
714        struct intel_uncore_funcs funcs;
715
716        unsigned fifo_count;
717        enum forcewake_domains fw_domains;
718
719        struct intel_uncore_forcewake_domain {
720                struct drm_i915_private *i915;
721                enum forcewake_domain_id id;
722                unsigned wake_count;
723                struct timer_list timer;
724                u32 reg_set;
725                u32 val_set;
726                u32 val_clear;
727                u32 reg_ack;
728                u32 reg_post;
729                u32 val_reset;
730        } fw_domain[FW_DOMAIN_ID_COUNT];
731};
732
733/* Iterate over initialised fw domains */
734#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
735        for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
736             (i__) < FW_DOMAIN_ID_COUNT; \
737             (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
738                if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
739
740#define for_each_fw_domain(domain__, dev_priv__, i__) \
741        for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
742
743enum csr_state {
744        FW_UNINITIALIZED = 0,
745        FW_LOADED,
746        FW_FAILED
747};
748
749struct intel_csr {
750        const char *fw_path;
751        uint32_t *dmc_payload;
752        uint32_t dmc_fw_size;
753        uint32_t mmio_count;
754        uint32_t mmioaddr[8];
755        uint32_t mmiodata[8];
756        enum csr_state state;
757};
758
759#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
760        func(is_mobile) sep \
761        func(is_i85x) sep \
762        func(is_i915g) sep \
763        func(is_i945gm) sep \
764        func(is_g33) sep \
765        func(need_gfx_hws) sep \
766        func(is_g4x) sep \
767        func(is_pineview) sep \
768        func(is_broadwater) sep \
769        func(is_crestline) sep \
770        func(is_ivybridge) sep \
771        func(is_valleyview) sep \
772        func(is_haswell) sep \
773        func(is_skylake) sep \
774        func(is_preliminary) sep \
775        func(has_fbc) sep \
776        func(has_pipe_cxsr) sep \
777        func(has_hotplug) sep \
778        func(cursor_needs_physical) sep \
779        func(has_overlay) sep \
780        func(overlay_needs_physical) sep \
781        func(supports_tv) sep \
782        func(has_llc) sep \
783        func(has_ddi) sep \
784        func(has_fpga_dbg)
785
786#define DEFINE_FLAG(name) u8 name:1
787#define SEP_SEMICOLON ;
788
789struct intel_device_info {
790        u32 display_mmio_offset;
791        u16 device_id;
792        u8 num_pipes:3;
793        u8 num_sprites[I915_MAX_PIPES];
794        u8 gen;
795        u8 ring_mask; /* Rings supported by the HW */
796        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
797        /* Register offsets for the various display pipes and transcoders */
798        int pipe_offsets[I915_MAX_TRANSCODERS];
799        int trans_offsets[I915_MAX_TRANSCODERS];
800        int palette_offsets[I915_MAX_PIPES];
801        int cursor_offsets[I915_MAX_PIPES];
802
803        /* Slice/subslice/EU info */
804        u8 slice_total;
805        u8 subslice_total;
806        u8 subslice_per_slice;
807        u8 eu_total;
808        u8 eu_per_subslice;
809        /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
810        u8 subslice_7eu[3];
811        u8 has_slice_pg:1;
812        u8 has_subslice_pg:1;
813        u8 has_eu_pg:1;
814};
815
816#undef DEFINE_FLAG
817#undef SEP_SEMICOLON
818
819enum i915_cache_level {
820        I915_CACHE_NONE = 0,
821        I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
822        I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
823                              caches, eg sampler/render caches, and the
824                              large Last-Level-Cache. LLC is coherent with
825                              the CPU, but L3 is only visible to the GPU. */
826        I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
827};
828
829struct i915_ctx_hang_stats {
830        /* This context had batch pending when hang was declared */
831        unsigned batch_pending;
832
833        /* This context had batch active when hang was declared */
834        unsigned batch_active;
835
836        /* Time when this context was last blamed for a GPU reset */
837        unsigned long guilty_ts;
838
839        /* If the contexts causes a second GPU hang within this time,
840         * it is permanently banned from submitting any more work.
841         */
842        unsigned long ban_period_seconds;
843
844        /* This context is banned to submit more work */
845        bool banned;
846};
847
848/* This must match up with the value previously used for execbuf2.rsvd1. */
849#define DEFAULT_CONTEXT_HANDLE 0
850
851#define CONTEXT_NO_ZEROMAP (1<<0)
852/**
853 * struct intel_context - as the name implies, represents a context.
854 * @ref: reference count.
855 * @user_handle: userspace tracking identity for this context.
856 * @remap_slice: l3 row remapping information.
857 * @flags: context specific flags:
858 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
859 * @file_priv: filp associated with this context (NULL for global default
860 *             context).
861 * @hang_stats: information about the role of this context in possible GPU
862 *              hangs.
863 * @ppgtt: virtual memory space used by this context.
864 * @legacy_hw_ctx: render context backing object and whether it is correctly
865 *                initialized (legacy ring submission mechanism only).
866 * @link: link in the global list of contexts.
867 *
868 * Contexts are memory images used by the hardware to store copies of their
869 * internal state.
870 */
871struct intel_context {
872        struct kref ref;
873        int user_handle;
874        uint8_t remap_slice;
875        struct drm_i915_private *i915;
876        int flags;
877        struct drm_i915_file_private *file_priv;
878        struct i915_ctx_hang_stats hang_stats;
879        struct i915_hw_ppgtt *ppgtt;
880
881        /* Legacy ring buffer submission */
882        struct {
883                struct drm_i915_gem_object *rcs_state;
884                bool initialized;
885        } legacy_hw_ctx;
886
887        /* Execlists */
888        struct {
889                struct drm_i915_gem_object *state;
890                struct intel_ringbuffer *ringbuf;
891                int pin_count;
892        } engine[I915_NUM_RINGS];
893
894        struct list_head link;
895};
896
897enum fb_op_origin {
898        ORIGIN_GTT,
899        ORIGIN_CPU,
900        ORIGIN_CS,
901        ORIGIN_FLIP,
902        ORIGIN_DIRTYFB,
903};
904
905struct i915_fbc {
906        /* This is always the inner lock when overlapping with struct_mutex and
907         * it's the outer lock when overlapping with stolen_lock. */
908        struct mutex lock;
909        unsigned long uncompressed_size;
910        unsigned threshold;
911        unsigned int fb_id;
912        unsigned int possible_framebuffer_bits;
913        unsigned int busy_bits;
914        struct intel_crtc *crtc;
915        int y;
916
917        struct drm_mm_node compressed_fb;
918        struct drm_mm_node *compressed_llb;
919
920        bool false_color;
921
922        /* Tracks whether the HW is actually enabled, not whether the feature is
923         * possible. */
924        bool enabled;
925
926        struct intel_fbc_work {
927                struct delayed_work work;
928                struct intel_crtc *crtc;
929                struct drm_framebuffer *fb;
930        } *fbc_work;
931
932        enum no_fbc_reason {
933                FBC_OK, /* FBC is enabled */
934                FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
935                FBC_NO_OUTPUT, /* no outputs enabled to compress */
936                FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
937                FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
938                FBC_MODE_TOO_LARGE, /* mode too large for compression */
939                FBC_BAD_PLANE, /* fbc not supported on plane */
940                FBC_NOT_TILED, /* buffer not tiled */
941                FBC_MULTIPLE_PIPES, /* more than one pipe active */
942                FBC_MODULE_PARAM,
943                FBC_CHIP_DEFAULT, /* disabled by default on this chip */
944                FBC_ROTATION, /* rotation is not supported */
945                FBC_IN_DBG_MASTER, /* kernel debugger is active */
946                FBC_BAD_STRIDE, /* stride is not supported */
947                FBC_PIXEL_RATE, /* pixel rate is too big */
948                FBC_PIXEL_FORMAT /* pixel format is invalid */
949        } no_fbc_reason;
950
951        bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
952        void (*enable_fbc)(struct intel_crtc *crtc);
953        void (*disable_fbc)(struct drm_i915_private *dev_priv);
954};
955
956/**
957 * HIGH_RR is the highest eDP panel refresh rate read from EDID
958 * LOW_RR is the lowest eDP panel refresh rate found from EDID
959 * parsing for same resolution.
960 */
961enum drrs_refresh_rate_type {
962        DRRS_HIGH_RR,
963        DRRS_LOW_RR,
964        DRRS_MAX_RR, /* RR count */
965};
966
967enum drrs_support_type {
968        DRRS_NOT_SUPPORTED = 0,
969        STATIC_DRRS_SUPPORT = 1,
970        SEAMLESS_DRRS_SUPPORT = 2
971};
972
973struct intel_dp;
974struct i915_drrs {
975        struct mutex mutex;
976        struct delayed_work work;
977        struct intel_dp *dp;
978        unsigned busy_frontbuffer_bits;
979        enum drrs_refresh_rate_type refresh_rate_type;
980        enum drrs_support_type type;
981};
982
983struct i915_psr {
984        struct mutex lock;
985        bool sink_support;
986        bool source_ok;
987        struct intel_dp *enabled;
988        bool active;
989        struct delayed_work work;
990        unsigned busy_frontbuffer_bits;
991        bool psr2_support;
992        bool aux_frame_sync;
993};
994
995enum intel_pch {
996        PCH_NONE = 0,   /* No PCH present */
997        PCH_IBX,        /* Ibexpeak PCH */
998        PCH_CPT,        /* Cougarpoint PCH */
999        PCH_LPT,        /* Lynxpoint PCH */
1000        PCH_SPT,        /* Sunrisepoint PCH */
1001        PCH_NOP,
1002};
1003
1004enum intel_sbi_destination {
1005        SBI_ICLK,
1006        SBI_MPHY,
1007};
1008
1009#define QUIRK_PIPEA_FORCE (1<<0)
1010#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1011#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1012#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1013#define QUIRK_PIPEB_FORCE (1<<4)
1014#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1015
1016struct intel_fbdev;
1017struct intel_fbc_work;
1018
1019struct intel_gmbus {
1020        struct i2c_adapter adapter;
1021        u32 force_bit;
1022        u32 reg0;
1023        u32 gpio_reg;
1024        struct i2c_algo_bit_data bit_algo;
1025        struct drm_i915_private *dev_priv;
1026};
1027
1028struct i915_suspend_saved_registers {
1029        u32 saveDSPARB;
1030        u32 saveLVDS;
1031        u32 savePP_ON_DELAYS;
1032        u32 savePP_OFF_DELAYS;
1033        u32 savePP_ON;
1034        u32 savePP_OFF;
1035        u32 savePP_CONTROL;
1036        u32 savePP_DIVISOR;
1037        u32 saveFBC_CONTROL;
1038        u32 saveCACHE_MODE_0;
1039        u32 saveMI_ARB_STATE;
1040        u32 saveSWF0[16];
1041        u32 saveSWF1[16];
1042        u32 saveSWF3[3];
1043        uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1044        u32 savePCH_PORT_HOTPLUG;
1045        u16 saveGCDGMBUS;
1046};
1047
1048struct vlv_s0ix_state {
1049        /* GAM */
1050        u32 wr_watermark;
1051        u32 gfx_prio_ctrl;
1052        u32 arb_mode;
1053        u32 gfx_pend_tlb0;
1054        u32 gfx_pend_tlb1;
1055        u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1056        u32 media_max_req_count;
1057        u32 gfx_max_req_count;
1058        u32 render_hwsp;
1059        u32 ecochk;
1060        u32 bsd_hwsp;
1061        u32 blt_hwsp;
1062        u32 tlb_rd_addr;
1063
1064        /* MBC */
1065        u32 g3dctl;
1066        u32 gsckgctl;
1067        u32 mbctl;
1068
1069        /* GCP */
1070        u32 ucgctl1;
1071        u32 ucgctl3;
1072        u32 rcgctl1;
1073        u32 rcgctl2;
1074        u32 rstctl;
1075        u32 misccpctl;
1076
1077        /* GPM */
1078        u32 gfxpause;
1079        u32 rpdeuhwtc;
1080        u32 rpdeuc;
1081        u32 ecobus;
1082        u32 pwrdwnupctl;
1083        u32 rp_down_timeout;
1084        u32 rp_deucsw;
1085        u32 rcubmabdtmr;
1086        u32 rcedata;
1087        u32 spare2gh;
1088
1089        /* Display 1 CZ domain */
1090        u32 gt_imr;
1091        u32 gt_ier;
1092        u32 pm_imr;
1093        u32 pm_ier;
1094        u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1095
1096        /* GT SA CZ domain */
1097        u32 tilectl;
1098        u32 gt_fifoctl;
1099        u32 gtlc_wake_ctrl;
1100        u32 gtlc_survive;
1101        u32 pmwgicz;
1102
1103        /* Display 2 CZ domain */
1104        u32 gu_ctl0;
1105        u32 gu_ctl1;
1106        u32 pcbr;
1107        u32 clock_gate_dis2;
1108};
1109
1110struct intel_rps_ei {
1111        u32 cz_clock;
1112        u32 render_c0;
1113        u32 media_c0;
1114};
1115
1116struct intel_gen6_power_mgmt {
1117        /*
1118         * work, interrupts_enabled and pm_iir are protected by
1119         * dev_priv->irq_lock
1120         */
1121        struct work_struct work;
1122        bool interrupts_enabled;
1123        u32 pm_iir;
1124
1125        /* Frequencies are stored in potentially platform dependent multiples.
1126         * In other words, *_freq needs to be multiplied by X to be interesting.
1127         * Soft limits are those which are used for the dynamic reclocking done
1128         * by the driver (raise frequencies under heavy loads, and lower for
1129         * lighter loads). Hard limits are those imposed by the hardware.
1130         *
1131         * A distinction is made for overclocking, which is never enabled by
1132         * default, and is considered to be above the hard limit if it's
1133         * possible at all.
1134         */
1135        u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1136        u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1137        u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1138        u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1139        u8 min_freq;            /* AKA RPn. Minimum frequency */
1140        u8 idle_freq;           /* Frequency to request when we are idle */
1141        u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1142        u8 rp1_freq;            /* "less than" RP0 power/freqency */
1143        u8 rp0_freq;            /* Non-overclocked max frequency. */
1144
1145        u8 up_threshold; /* Current %busy required to uplock */
1146        u8 down_threshold; /* Current %busy required to downclock */
1147
1148        int last_adj;
1149        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1150
1151        spinlock_t client_lock;
1152        struct list_head clients;
1153        bool client_boost;
1154
1155        bool enabled;
1156        struct delayed_work delayed_resume_work;
1157        unsigned boosts;
1158
1159        struct intel_rps_client semaphores, mmioflips;
1160
1161        /* manual wa residency calculations */
1162        struct intel_rps_ei up_ei, down_ei;
1163
1164        /*
1165         * Protects RPS/RC6 register access and PCU communication.
1166         * Must be taken after struct_mutex if nested. Note that
1167         * this lock may be held for long periods of time when
1168         * talking to hw - so only take it when talking to hw!
1169         */
1170        struct mutex hw_lock;
1171};
1172
1173/* defined intel_pm.c */
1174extern spinlock_t mchdev_lock;
1175
1176struct intel_ilk_power_mgmt {
1177        u8 cur_delay;
1178        u8 min_delay;
1179        u8 max_delay;
1180        u8 fmax;
1181        u8 fstart;
1182
1183        u64 last_count1;
1184        unsigned long last_time1;
1185        unsigned long chipset_power;
1186        u64 last_count2;
1187        u64 last_time2;
1188        unsigned long gfx_power;
1189        u8 corr;
1190
1191        int c_m;
1192        int r_t;
1193};
1194
1195struct drm_i915_private;
1196struct i915_power_well;
1197
1198struct i915_power_well_ops {
1199        /*
1200         * Synchronize the well's hw state to match the current sw state, for
1201         * example enable/disable it based on the current refcount. Called
1202         * during driver init and resume time, possibly after first calling
1203         * the enable/disable handlers.
1204         */
1205        void (*sync_hw)(struct drm_i915_private *dev_priv,
1206                        struct i915_power_well *power_well);
1207        /*
1208         * Enable the well and resources that depend on it (for example
1209         * interrupts located on the well). Called after the 0->1 refcount
1210         * transition.
1211         */
1212        void (*enable)(struct drm_i915_private *dev_priv,
1213                       struct i915_power_well *power_well);
1214        /*
1215         * Disable the well and resources that depend on it. Called after
1216         * the 1->0 refcount transition.
1217         */
1218        void (*disable)(struct drm_i915_private *dev_priv,
1219                        struct i915_power_well *power_well);
1220        /* Returns the hw enabled state. */
1221        bool (*is_enabled)(struct drm_i915_private *dev_priv,
1222                           struct i915_power_well *power_well);
1223};
1224
1225/* Power well structure for haswell */
1226struct i915_power_well {
1227        const char *name;
1228        bool always_on;
1229        /* power well enable/disable usage count */
1230        int count;
1231        /* cached hw enabled state */
1232        bool hw_enabled;
1233        unsigned long domains;
1234        unsigned long data;
1235        const struct i915_power_well_ops *ops;
1236};
1237
1238struct i915_power_domains {
1239        /*
1240         * Power wells needed for initialization at driver init and suspend
1241         * time are on. They are kept on until after the first modeset.
1242         */
1243        bool init_power_on;
1244        bool initializing;
1245        int power_well_count;
1246
1247        struct mutex lock;
1248        int domain_use_count[POWER_DOMAIN_NUM];
1249        struct i915_power_well *power_wells;
1250};
1251
1252#define MAX_L3_SLICES 2
1253struct intel_l3_parity {
1254        u32 *remap_info[MAX_L3_SLICES];
1255        struct work_struct error_work;
1256        int which_slice;
1257};
1258
1259struct i915_gem_mm {
1260        /** Memory allocator for GTT stolen memory */
1261        struct drm_mm stolen;
1262        /** Protects the usage of the GTT stolen memory allocator. This is
1263         * always the inner lock when overlapping with struct_mutex. */
1264        struct mutex stolen_lock;
1265
1266        /** List of all objects in gtt_space. Used to restore gtt
1267         * mappings on resume */
1268        struct list_head bound_list;
1269        /**
1270         * List of objects which are not bound to the GTT (thus
1271         * are idle and not used by the GPU) but still have
1272         * (presumably uncached) pages still attached.
1273         */
1274        struct list_head unbound_list;
1275
1276        /** Usable portion of the GTT for GEM */
1277        unsigned long stolen_base; /* limited to low memory (32-bit) */
1278
1279        /** PPGTT used for aliasing the PPGTT with the GTT */
1280        struct i915_hw_ppgtt *aliasing_ppgtt;
1281
1282        struct notifier_block oom_notifier;
1283        struct shrinker shrinker;
1284        bool shrinker_no_lock_stealing;
1285
1286        /** LRU list of objects with fence regs on them. */
1287        struct list_head fence_list;
1288
1289        /**
1290         * We leave the user IRQ off as much as possible,
1291         * but this means that requests will finish and never
1292         * be retired once the system goes idle. Set a timer to
1293         * fire periodically while the ring is running. When it
1294         * fires, go retire requests.
1295         */
1296        struct delayed_work retire_work;
1297
1298        /**
1299         * When we detect an idle GPU, we want to turn on
1300         * powersaving features. So once we see that there
1301         * are no more requests outstanding and no more
1302         * arrive within a small period of time, we fire
1303         * off the idle_work.
1304         */
1305        struct delayed_work idle_work;
1306
1307        /**
1308         * Are we in a non-interruptible section of code like
1309         * modesetting?
1310         */
1311        bool interruptible;
1312
1313        /**
1314         * Is the GPU currently considered idle, or busy executing userspace
1315         * requests?  Whilst idle, we attempt to power down the hardware and
1316         * display clocks. In order to reduce the effect on performance, there
1317         * is a slight delay before we do so.
1318         */
1319        bool busy;
1320
1321        /* the indicator for dispatch video commands on two BSD rings */
1322        int bsd_ring_dispatch_index;
1323
1324        /** Bit 6 swizzling required for X tiling */
1325        uint32_t bit_6_swizzle_x;
1326        /** Bit 6 swizzling required for Y tiling */
1327        uint32_t bit_6_swizzle_y;
1328
1329        /* accounting, useful for userland debugging */
1330        spinlock_t object_stat_lock;
1331        size_t object_memory;
1332        u32 object_count;
1333};
1334
1335struct drm_i915_error_state_buf {
1336        struct drm_i915_private *i915;
1337        unsigned bytes;
1338        unsigned size;
1339        int err;
1340        u8 *buf;
1341        loff_t start;
1342        loff_t pos;
1343};
1344
1345struct i915_error_state_file_priv {
1346        struct drm_device *dev;
1347        struct drm_i915_error_state *error;
1348};
1349
1350struct i915_gpu_error {
1351        /* For hangcheck timer */
1352#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1353#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1354        /* Hang gpu twice in this window and your context gets banned */
1355#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1356
1357        struct workqueue_struct *hangcheck_wq;
1358        struct delayed_work hangcheck_work;
1359
1360        /* For reset and error_state handling. */
1361        spinlock_t lock;
1362        /* Protected by the above dev->gpu_error.lock. */
1363        struct drm_i915_error_state *first_error;
1364
1365        unsigned long missed_irq_rings;
1366
1367        /**
1368         * State variable controlling the reset flow and count
1369         *
1370         * This is a counter which gets incremented when reset is triggered,
1371         * and again when reset has been handled. So odd values (lowest bit set)
1372         * means that reset is in progress and even values that
1373         * (reset_counter >> 1):th reset was successfully completed.
1374         *
1375         * If reset is not completed succesfully, the I915_WEDGE bit is
1376         * set meaning that hardware is terminally sour and there is no
1377         * recovery. All waiters on the reset_queue will be woken when
1378         * that happens.
1379         *
1380         * This counter is used by the wait_seqno code to notice that reset
1381         * event happened and it needs to restart the entire ioctl (since most
1382         * likely the seqno it waited for won't ever signal anytime soon).
1383         *
1384         * This is important for lock-free wait paths, where no contended lock
1385         * naturally enforces the correct ordering between the bail-out of the
1386         * waiter and the gpu reset work code.
1387         */
1388        atomic_t reset_counter;
1389
1390#define I915_RESET_IN_PROGRESS_FLAG     1
1391#define I915_WEDGED                     (1 << 31)
1392
1393        /**
1394         * Waitqueue to signal when the reset has completed. Used by clients
1395         * that wait for dev_priv->mm.wedged to settle.
1396         */
1397        wait_queue_head_t reset_queue;
1398
1399        /* Userspace knobs for gpu hang simulation;
1400         * combines both a ring mask, and extra flags
1401         */
1402        u32 stop_rings;
1403#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1404#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1405
1406        /* For missed irq/seqno simulation. */
1407        unsigned int test_irq_rings;
1408
1409        /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
1410        bool reload_in_reset;
1411};
1412
1413enum modeset_restore {
1414        MODESET_ON_LID_OPEN,
1415        MODESET_DONE,
1416        MODESET_SUSPENDED,
1417};
1418
1419#define DP_AUX_A 0x40
1420#define DP_AUX_B 0x10
1421#define DP_AUX_C 0x20
1422#define DP_AUX_D 0x30
1423
1424#define DDC_PIN_B  0x05
1425#define DDC_PIN_C  0x04
1426#define DDC_PIN_D  0x06
1427
1428struct ddi_vbt_port_info {
1429        /*
1430         * This is an index in the HDMI/DVI DDI buffer translation table.
1431         * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1432         * populate this field.
1433         */
1434#define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1435        uint8_t hdmi_level_shift;
1436
1437        uint8_t supports_dvi:1;
1438        uint8_t supports_hdmi:1;
1439        uint8_t supports_dp:1;
1440
1441        uint8_t alternate_aux_channel;
1442        uint8_t alternate_ddc_pin;
1443
1444        uint8_t dp_boost_level;
1445        uint8_t hdmi_boost_level;
1446};
1447
1448enum psr_lines_to_wait {
1449        PSR_0_LINES_TO_WAIT = 0,
1450        PSR_1_LINE_TO_WAIT,
1451        PSR_4_LINES_TO_WAIT,
1452        PSR_8_LINES_TO_WAIT
1453};
1454
1455struct intel_vbt_data {
1456        struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1457        struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1458
1459        /* Feature bits */
1460        unsigned int int_tv_support:1;
1461        unsigned int lvds_dither:1;
1462        unsigned int lvds_vbt:1;
1463        unsigned int int_crt_support:1;
1464        unsigned int lvds_use_ssc:1;
1465        unsigned int display_clock_mode:1;
1466        unsigned int fdi_rx_polarity_inverted:1;
1467        unsigned int has_mipi:1;
1468        int lvds_ssc_freq;
1469        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1470
1471        enum drrs_support_type drrs_type;
1472
1473        /* eDP */
1474        int edp_rate;
1475        int edp_lanes;
1476        int edp_preemphasis;
1477        int edp_vswing;
1478        bool edp_initialized;
1479        bool edp_support;
1480        int edp_bpp;
1481        struct edp_power_seq edp_pps;
1482
1483        struct {
1484                bool full_link;
1485                bool require_aux_wakeup;
1486                int idle_frames;
1487                enum psr_lines_to_wait lines_to_wait;
1488                int tp1_wakeup_time;
1489                int tp2_tp3_wakeup_time;
1490        } psr;
1491
1492        struct {
1493                u16 pwm_freq_hz;
1494                bool present;
1495                bool active_low_pwm;
1496                u8 min_brightness;      /* min_brightness/255 of max */
1497        } backlight;
1498
1499        /* MIPI DSI */
1500        struct {
1501                u16 port;
1502                u16 panel_id;
1503                struct mipi_config *config;
1504                struct mipi_pps_data *pps;
1505                u8 seq_version;
1506                u32 size;
1507                u8 *data;
1508                u8 *sequence[MIPI_SEQ_MAX];
1509        } dsi;
1510
1511        int crt_ddc_pin;
1512
1513        int child_dev_num;
1514        union child_device_config *child_dev;
1515
1516        struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1517};
1518
1519enum intel_ddb_partitioning {
1520        INTEL_DDB_PART_1_2,
1521        INTEL_DDB_PART_5_6, /* IVB+ */
1522};
1523
1524struct intel_wm_level {
1525        bool enable;
1526        uint32_t pri_val;
1527        uint32_t spr_val;
1528        uint32_t cur_val;
1529        uint32_t fbc_val;
1530};
1531
1532struct ilk_wm_values {
1533        uint32_t wm_pipe[3];
1534        uint32_t wm_lp[3];
1535        uint32_t wm_lp_spr[3];
1536        uint32_t wm_linetime[3];
1537        bool enable_fbc_wm;
1538        enum intel_ddb_partitioning partitioning;
1539};
1540
1541struct vlv_pipe_wm {
1542        uint16_t primary;
1543        uint16_t sprite[2];
1544        uint8_t cursor;
1545};
1546
1547struct vlv_sr_wm {
1548        uint16_t plane;
1549        uint8_t cursor;
1550};
1551
1552struct vlv_wm_values {
1553        struct vlv_pipe_wm pipe[3];
1554        struct vlv_sr_wm sr;
1555        struct {
1556                uint8_t cursor;
1557                uint8_t sprite[2];
1558                uint8_t primary;
1559        } ddl[3];
1560        uint8_t level;
1561        bool cxsr;
1562};
1563
1564struct skl_ddb_entry {
1565        uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1566};
1567
1568static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1569{
1570        return entry->end - entry->start;
1571}
1572
1573static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1574                                       const struct skl_ddb_entry *e2)
1575{
1576        if (e1->start == e2->start && e1->end == e2->end)
1577                return true;
1578
1579        return false;
1580}
1581
1582struct skl_ddb_allocation {
1583        struct skl_ddb_entry pipe[I915_MAX_PIPES];
1584        struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1585        struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1586};
1587
1588struct skl_wm_values {
1589        bool dirty[I915_MAX_PIPES];
1590        struct skl_ddb_allocation ddb;
1591        uint32_t wm_linetime[I915_MAX_PIPES];
1592        uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1593        uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1594};
1595
1596struct skl_wm_level {
1597        bool plane_en[I915_MAX_PLANES];
1598        uint16_t plane_res_b[I915_MAX_PLANES];
1599        uint8_t plane_res_l[I915_MAX_PLANES];
1600};
1601
1602/*
1603 * This struct helps tracking the state needed for runtime PM, which puts the
1604 * device in PCI D3 state. Notice that when this happens, nothing on the
1605 * graphics device works, even register access, so we don't get interrupts nor
1606 * anything else.
1607 *
1608 * Every piece of our code that needs to actually touch the hardware needs to
1609 * either call intel_runtime_pm_get or call intel_display_power_get with the
1610 * appropriate power domain.
1611 *
1612 * Our driver uses the autosuspend delay feature, which means we'll only really
1613 * suspend if we stay with zero refcount for a certain amount of time. The
1614 * default value is currently very conservative (see intel_runtime_pm_enable), but
1615 * it can be changed with the standard runtime PM files from sysfs.
1616 *
1617 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1618 * goes back to false exactly before we reenable the IRQs. We use this variable
1619 * to check if someone is trying to enable/disable IRQs while they're supposed
1620 * to be disabled. This shouldn't happen and we'll print some error messages in
1621 * case it happens.
1622 *
1623 * For more, read the Documentation/power/runtime_pm.txt.
1624 */
1625struct i915_runtime_pm {
1626        bool suspended;
1627        bool irqs_enabled;
1628};
1629
1630enum intel_pipe_crc_source {
1631        INTEL_PIPE_CRC_SOURCE_NONE,
1632        INTEL_PIPE_CRC_SOURCE_PLANE1,
1633        INTEL_PIPE_CRC_SOURCE_PLANE2,
1634        INTEL_PIPE_CRC_SOURCE_PF,
1635        INTEL_PIPE_CRC_SOURCE_PIPE,
1636        /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1637        INTEL_PIPE_CRC_SOURCE_TV,
1638        INTEL_PIPE_CRC_SOURCE_DP_B,
1639        INTEL_PIPE_CRC_SOURCE_DP_C,
1640        INTEL_PIPE_CRC_SOURCE_DP_D,
1641        INTEL_PIPE_CRC_SOURCE_AUTO,
1642        INTEL_PIPE_CRC_SOURCE_MAX,
1643};
1644
1645struct intel_pipe_crc_entry {
1646        uint32_t frame;
1647        uint32_t crc[5];
1648};
1649
1650#define INTEL_PIPE_CRC_ENTRIES_NR       128
1651struct intel_pipe_crc {
1652        spinlock_t lock;
1653        bool opened;            /* exclusive access to the result file */
1654        struct intel_pipe_crc_entry *entries;
1655        enum intel_pipe_crc_source source;
1656        int head, tail;
1657        wait_queue_head_t wq;
1658};
1659
1660struct i915_frontbuffer_tracking {
1661        struct mutex lock;
1662
1663        /*
1664         * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1665         * scheduled flips.
1666         */
1667        unsigned busy_bits;
1668        unsigned flip_bits;
1669};
1670
1671struct i915_wa_reg {
1672        u32 addr;
1673        u32 value;
1674        /* bitmask representing WA bits */
1675        u32 mask;
1676};
1677
1678#define I915_MAX_WA_REGS 16
1679
1680struct i915_workarounds {
1681        struct i915_wa_reg reg[I915_MAX_WA_REGS];
1682        u32 count;
1683};
1684
1685struct i915_virtual_gpu {
1686        bool active;
1687};
1688
1689struct i915_execbuffer_params {
1690        struct drm_device               *dev;
1691        struct drm_file                 *file;
1692        uint32_t                        dispatch_flags;
1693        uint32_t                        args_batch_start_offset;
1694        uint64_t                        batch_obj_vm_offset;
1695        struct intel_engine_cs          *ring;
1696        struct drm_i915_gem_object      *batch_obj;
1697        struct intel_context            *ctx;
1698        struct drm_i915_gem_request     *request;
1699};
1700
1701struct drm_i915_private {
1702        struct drm_device *dev;
1703        struct kmem_cache *objects;
1704        struct kmem_cache *vmas;
1705        struct kmem_cache *requests;
1706
1707        const struct intel_device_info info;
1708
1709        int relative_constants_mode;
1710
1711        void __iomem *regs;
1712
1713        struct intel_uncore uncore;
1714
1715        struct i915_virtual_gpu vgpu;
1716
1717        struct intel_guc guc;
1718
1719        struct intel_csr csr;
1720
1721        /* Display CSR-related protection */
1722        struct mutex csr_lock;
1723
1724        struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1725
1726        /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1727         * controller on different i2c buses. */
1728        struct mutex gmbus_mutex;
1729
1730        /**
1731         * Base address of the gmbus and gpio block.
1732         */
1733        uint32_t gpio_mmio_base;
1734
1735        /* MMIO base address for MIPI regs */
1736        uint32_t mipi_mmio_base;
1737
1738        wait_queue_head_t gmbus_wait_queue;
1739
1740        struct pci_dev *bridge_dev;
1741        struct intel_engine_cs ring[I915_NUM_RINGS];
1742        struct drm_i915_gem_object *semaphore_obj;
1743        uint32_t last_seqno, next_seqno;
1744
1745        struct drm_dma_handle *status_page_dmah;
1746        struct resource mch_res;
1747
1748        /* protects the irq masks */
1749        spinlock_t irq_lock;
1750
1751        /* protects the mmio flip data */
1752        spinlock_t mmio_flip_lock;
1753
1754        bool display_irqs_enabled;
1755
1756        /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1757        struct pm_qos_request pm_qos;
1758
1759        /* Sideband mailbox protection */
1760        struct mutex sb_lock;
1761
1762        /** Cached value of IMR to avoid reads in updating the bitfield */
1763        union {
1764                u32 irq_mask;
1765                u32 de_irq_mask[I915_MAX_PIPES];
1766        };
1767        u32 gt_irq_mask;
1768        u32 pm_irq_mask;
1769        u32 pm_rps_events;
1770        u32 pipestat_irq_mask[I915_MAX_PIPES];
1771
1772        struct i915_hotplug hotplug;
1773        struct i915_fbc fbc;
1774        struct i915_drrs drrs;
1775        struct intel_opregion opregion;
1776        struct intel_vbt_data vbt;
1777
1778        bool preserve_bios_swizzle;
1779
1780        /* overlay */
1781        struct intel_overlay *overlay;
1782
1783        /* backlight registers and fields in struct intel_panel */
1784        struct mutex backlight_lock;
1785
1786        /* LVDS info */
1787        bool no_aux_handshake;
1788
1789        /* protects panel power sequencer state */
1790        struct mutex pps_mutex;
1791
1792        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1793        int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1794
1795        unsigned int fsb_freq, mem_freq, is_ddr3;
1796        unsigned int skl_boot_cdclk;
1797        unsigned int cdclk_freq, max_cdclk_freq;
1798        unsigned int max_dotclk_freq;
1799        unsigned int hpll_freq;
1800        unsigned int czclk_freq;
1801
1802        /**
1803         * wq - Driver workqueue for GEM.
1804         *
1805         * NOTE: Work items scheduled here are not allowed to grab any modeset
1806         * locks, for otherwise the flushing done in the pageflip code will
1807         * result in deadlocks.
1808         */
1809        struct workqueue_struct *wq;
1810
1811        /* Display functions */
1812        struct drm_i915_display_funcs display;
1813
1814        /* PCH chipset type */
1815        enum intel_pch pch_type;
1816        unsigned short pch_id;
1817
1818        unsigned long quirks;
1819
1820        enum modeset_restore modeset_restore;
1821        struct mutex modeset_restore_lock;
1822
1823        struct list_head vm_list; /* Global list of all address spaces */
1824        struct i915_gtt gtt; /* VM representing the global address space */
1825
1826        struct i915_gem_mm mm;
1827        DECLARE_HASHTABLE(mm_structs, 7);
1828        struct mutex mm_lock;
1829
1830        /* Kernel Modesetting */
1831
1832        struct sdvo_device_mapping sdvo_mappings[2];
1833
1834        struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1835        struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1836        wait_queue_head_t pending_flip_queue;
1837
1838#ifdef CONFIG_DEBUG_FS
1839        struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1840#endif
1841
1842        int num_shared_dpll;
1843        struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1844        int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1845
1846        struct i915_workarounds workarounds;
1847
1848        /* Reclocking support */
1849        bool render_reclock_avail;
1850
1851        struct i915_frontbuffer_tracking fb_tracking;
1852
1853        u16 orig_clock;
1854
1855        bool mchbar_need_disable;
1856
1857        struct intel_l3_parity l3_parity;
1858
1859        /* Cannot be determined by PCIID. You must always read a register. */
1860        size_t ellc_size;
1861
1862        /* gen6+ rps state */
1863        struct intel_gen6_power_mgmt rps;
1864
1865        /* ilk-only ips/rps state. Everything in here is protected by the global
1866         * mchdev_lock in intel_pm.c */
1867        struct intel_ilk_power_mgmt ips;
1868
1869        struct i915_power_domains power_domains;
1870
1871        struct i915_psr psr;
1872
1873        struct i915_gpu_error gpu_error;
1874
1875        struct drm_i915_gem_object *vlv_pctx;
1876
1877#ifdef CONFIG_DRM_FBDEV_EMULATION
1878        /* list of fbdev register on this device */
1879        struct intel_fbdev *fbdev;
1880        struct work_struct fbdev_suspend_work;
1881#endif
1882
1883        struct drm_property *broadcast_rgb_property;
1884        struct drm_property *force_audio_property;
1885
1886        /* hda/i915 audio component */
1887        struct i915_audio_component *audio_component;
1888        bool audio_component_registered;
1889        /**
1890         * av_mutex - mutex for audio/video sync
1891         *
1892         */
1893        struct mutex av_mutex;
1894
1895        uint32_t hw_context_size;
1896        struct list_head context_list;
1897
1898        u32 fdi_rx_config;
1899
1900        u32 chv_phy_control;
1901
1902        u32 suspend_count;
1903        struct i915_suspend_saved_registers regfile;
1904        struct vlv_s0ix_state vlv_s0ix_state;
1905
1906        struct {
1907                /*
1908                 * Raw watermark latency values:
1909                 * in 0.1us units for WM0,
1910                 * in 0.5us units for WM1+.
1911                 */
1912                /* primary */
1913                uint16_t pri_latency[5];
1914                /* sprite */
1915                uint16_t spr_latency[5];
1916                /* cursor */
1917                uint16_t cur_latency[5];
1918                /*
1919                 * Raw watermark memory latency values
1920                 * for SKL for all 8 levels
1921                 * in 1us units.
1922                 */
1923                uint16_t skl_latency[8];
1924
1925                /*
1926                 * The skl_wm_values structure is a bit too big for stack
1927                 * allocation, so we keep the staging struct where we store
1928                 * intermediate results here instead.
1929                 */
1930                struct skl_wm_values skl_results;
1931
1932                /* current hardware state */
1933                union {
1934                        struct ilk_wm_values hw;
1935                        struct skl_wm_values skl_hw;
1936                        struct vlv_wm_values vlv;
1937                };
1938
1939                uint8_t max_level;
1940        } wm;
1941
1942        struct i915_runtime_pm pm;
1943
1944        /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1945        struct {
1946                int (*execbuf_submit)(struct i915_execbuffer_params *params,
1947                                      struct drm_i915_gem_execbuffer2 *args,
1948                                      struct list_head *vmas);
1949                int (*init_rings)(struct drm_device *dev);
1950                void (*cleanup_ring)(struct intel_engine_cs *ring);
1951                void (*stop_ring)(struct intel_engine_cs *ring);
1952        } gt;
1953
1954        bool edp_low_vswing;
1955
1956        /* perform PHY state sanity checks? */
1957        bool chv_phy_assert[2];
1958
1959        /*
1960         * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1961         * will be rejected. Instead look for a better place.
1962         */
1963};
1964
1965static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1966{
1967        return dev->dev_private;
1968}
1969
1970static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1971{
1972        return to_i915(dev_get_drvdata(dev));
1973}
1974
1975static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1976{
1977        return container_of(guc, struct drm_i915_private, guc);
1978}
1979
1980/* Iterate over initialised rings */
1981#define for_each_ring(ring__, dev_priv__, i__) \
1982        for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1983                if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1984
1985enum hdmi_force_audio {
1986        HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1987        HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1988        HDMI_AUDIO_AUTO,                /* trust EDID */
1989        HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1990};
1991
1992#define I915_GTT_OFFSET_NONE ((u32)-1)
1993
1994struct drm_i915_gem_object_ops {
1995        /* Interface between the GEM object and its backing storage.
1996         * get_pages() is called once prior to the use of the associated set
1997         * of pages before to binding them into the GTT, and put_pages() is
1998         * called after we no longer need them. As we expect there to be
1999         * associated cost with migrating pages between the backing storage
2000         * and making them available for the GPU (e.g. clflush), we may hold
2001         * onto the pages after they are no longer referenced by the GPU
2002         * in case they may be used again shortly (for example migrating the
2003         * pages to a different memory domain within the GTT). put_pages()
2004         * will therefore most likely be called when the object itself is
2005         * being released or under memory pressure (where we attempt to
2006         * reap pages for the shrinker).
2007         */
2008        int (*get_pages)(struct drm_i915_gem_object *);
2009        void (*put_pages)(struct drm_i915_gem_object *);
2010        int (*dmabuf_export)(struct drm_i915_gem_object *);
2011        void (*release)(struct drm_i915_gem_object *);
2012};
2013
2014/*
2015 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2016 * considered to be the frontbuffer for the given plane interface-wise. This
2017 * doesn't mean that the hw necessarily already scans it out, but that any
2018 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2019 *
2020 * We have one bit per pipe and per scanout plane type.
2021 */
2022#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2023#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2024#define INTEL_FRONTBUFFER_BITS \
2025        (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2026#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2027        (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2028#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2029        (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2030#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2031        (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2032#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2033        (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2034#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2035        (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2036
2037struct drm_i915_gem_object {
2038        struct drm_gem_object base;
2039
2040        const struct drm_i915_gem_object_ops *ops;
2041
2042        /** List of VMAs backed by this object */
2043        struct list_head vma_list;
2044
2045        /** Stolen memory for this object, instead of being backed by shmem. */
2046        struct drm_mm_node *stolen;
2047        struct list_head global_list;
2048
2049        struct list_head ring_list[I915_NUM_RINGS];
2050        /** Used in execbuf to temporarily hold a ref */
2051        struct list_head obj_exec_link;
2052
2053        struct list_head batch_pool_link;
2054
2055        /**
2056         * This is set if the object is on the active lists (has pending
2057         * rendering and so a non-zero seqno), and is not set if it i s on
2058         * inactive (ready to be unbound) list.
2059         */
2060        unsigned int active:I915_NUM_RINGS;
2061
2062        /**
2063         * This is set if the object has been written to since last bound
2064         * to the GTT
2065         */
2066        unsigned int dirty:1;
2067
2068        /**
2069         * Fence register bits (if any) for this object.  Will be set
2070         * as needed when mapped into the GTT.
2071         * Protected by dev->struct_mutex.
2072         */
2073        signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2074
2075        /**
2076         * Advice: are the backing pages purgeable?
2077         */
2078        unsigned int madv:2;
2079
2080        /**
2081         * Current tiling mode for the object.
2082         */
2083        unsigned int tiling_mode:2;
2084        /**
2085         * Whether the tiling parameters for the currently associated fence
2086         * register have changed. Note that for the purposes of tracking
2087         * tiling changes we also treat the unfenced register, the register
2088         * slot that the object occupies whilst it executes a fenced
2089         * command (such as BLT on gen2/3), as a "fence".
2090         */
2091        unsigned int fence_dirty:1;
2092
2093        /**
2094         * Is the object at the current location in the gtt mappable and
2095         * fenceable? Used to avoid costly recalculations.
2096         */
2097        unsigned int map_and_fenceable:1;
2098
2099        /**
2100         * Whether the current gtt mapping needs to be mappable (and isn't just
2101         * mappable by accident). Track pin and fault separate for a more
2102         * accurate mappable working set.
2103         */
2104        unsigned int fault_mappable:1;
2105
2106        /*
2107         * Is the object to be mapped as read-only to the GPU
2108         * Only honoured if hardware has relevant pte bit
2109         */
2110        unsigned long gt_ro:1;
2111        unsigned int cache_level:3;
2112        unsigned int cache_dirty:1;
2113
2114        unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2115
2116        unsigned int pin_display;
2117
2118        struct sg_table *pages;
2119        int pages_pin_count;
2120        struct get_page {
2121                struct scatterlist *sg;
2122                int last;
2123        } get_page;
2124
2125        /* prime dma-buf support */
2126        void *dma_buf_vmapping;
2127        int vmapping_count;
2128
2129        /** Breadcrumb of last rendering to the buffer.
2130         * There can only be one writer, but we allow for multiple readers.
2131         * If there is a writer that necessarily implies that all other
2132         * read requests are complete - but we may only be lazily clearing
2133         * the read requests. A read request is naturally the most recent
2134         * request on a ring, so we may have two different write and read
2135         * requests on one ring where the write request is older than the
2136         * read request. This allows for the CPU to read from an active
2137         * buffer by only waiting for the write to complete.
2138         * */
2139        struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2140        struct drm_i915_gem_request *last_write_req;
2141        /** Breadcrumb of last fenced GPU access to the buffer. */
2142        struct drm_i915_gem_request *last_fenced_req;
2143
2144        /** Current tiling stride for the object, if it's tiled. */
2145        uint32_t stride;
2146
2147        /** References from framebuffers, locks out tiling changes. */
2148        unsigned long framebuffer_references;
2149
2150        /** Record of address bit 17 of each page at last unbind. */
2151        unsigned long *bit_17;
2152
2153        struct i915_gem_userptr {
2154                uintptr_t ptr;
2155                unsigned read_only :1;
2156                unsigned workers :4;
2157#define I915_GEM_USERPTR_MAX_WORKERS 15
2158
2159                struct i915_mm_struct *mm;
2160                struct i915_mmu_object *mmu_object;
2161                struct work_struct *work;
2162        } userptr;
2163
2164        /** for phys allocated objects */
2165        struct drm_dma_handle *phys_handle;
2166};
2167#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2168
2169void i915_gem_track_fb(struct drm_i915_gem_object *old,
2170                       struct drm_i915_gem_object *new,
2171                       unsigned frontbuffer_bits);
2172
2173/**
2174 * Request queue structure.
2175 *
2176 * The request queue allows us to note sequence numbers that have been emitted
2177 * and may be associated with active buffers to be retired.
2178 *
2179 * By keeping this list, we can avoid having to do questionable sequence
2180 * number comparisons on buffer last_read|write_seqno. It also allows an
2181 * emission time to be associated with the request for tracking how far ahead
2182 * of the GPU the submission is.
2183 *
2184 * The requests are reference counted, so upon creation they should have an
2185 * initial reference taken using kref_init
2186 */
2187struct drm_i915_gem_request {
2188        struct kref ref;
2189
2190        /** On Which ring this request was generated */
2191        struct drm_i915_private *i915;
2192        struct intel_engine_cs *ring;
2193
2194         /** GEM sequence number associated with the previous request,
2195          * when the HWS breadcrumb is equal to this the GPU is processing
2196          * this request.
2197          */
2198        u32 previous_seqno;
2199
2200         /** GEM sequence number associated with this request,
2201          * when the HWS breadcrumb is equal or greater than this the GPU
2202          * has finished processing this request.
2203          */
2204        u32 seqno;
2205
2206        /** Position in the ringbuffer of the start of the request */
2207        u32 head;
2208
2209        /**
2210         * Position in the ringbuffer of the start of the postfix.
2211         * This is required to calculate the maximum available ringbuffer
2212         * space without overwriting the postfix.
2213         */
2214         u32 postfix;
2215
2216        /** Position in the ringbuffer of the end of the whole request */
2217        u32 tail;
2218
2219        /**
2220         * Context and ring buffer related to this request
2221         * Contexts are refcounted, so when this request is associated with a
2222         * context, we must increment the context's refcount, to guarantee that
2223         * it persists while any request is linked to it. Requests themselves
2224         * are also refcounted, so the request will only be freed when the last
2225         * reference to it is dismissed, and the code in
2226         * i915_gem_request_free() will then decrement the refcount on the
2227         * context.
2228         */
2229        struct intel_context *ctx;
2230        struct intel_ringbuffer *ringbuf;
2231
2232        /** Batch buffer related to this request if any (used for
2233            error state dump only) */
2234        struct drm_i915_gem_object *batch_obj;
2235
2236        /** Time at which this request was emitted, in jiffies. */
2237        unsigned long emitted_jiffies;
2238
2239        /** global list entry for this request */
2240        struct list_head list;
2241
2242        struct drm_i915_file_private *file_priv;
2243        /** file_priv list entry for this request */
2244        struct list_head client_list;
2245
2246        /** process identifier submitting this request */
2247        struct pid *pid;
2248
2249        /**
2250         * The ELSP only accepts two elements at a time, so we queue
2251         * context/tail pairs on a given queue (ring->execlist_queue) until the
2252         * hardware is available. The queue serves a double purpose: we also use
2253         * it to keep track of the up to 2 contexts currently in the hardware
2254         * (usually one in execution and the other queued up by the GPU): We
2255         * only remove elements from the head of the queue when the hardware
2256         * informs us that an element has been completed.
2257         *
2258         * All accesses to the queue are mediated by a spinlock
2259         * (ring->execlist_lock).
2260         */
2261
2262        /** Execlist link in the submission queue.*/
2263        struct list_head execlist_link;
2264
2265        /** Execlists no. of times this request has been sent to the ELSP */
2266        int elsp_submitted;
2267
2268};
2269
2270int i915_gem_request_alloc(struct intel_engine_cs *ring,
2271                           struct intel_context *ctx,
2272                           struct drm_i915_gem_request **req_out);
2273void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2274void i915_gem_request_free(struct kref *req_ref);
2275int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2276                                   struct drm_file *file);
2277
2278static inline uint32_t
2279i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2280{
2281        return req ? req->seqno : 0;
2282}
2283
2284static inline struct intel_engine_cs *
2285i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2286{
2287        return req ? req->ring : NULL;
2288}
2289
2290static inline struct drm_i915_gem_request *
2291i915_gem_request_reference(struct drm_i915_gem_request *req)
2292{
2293        if (req)
2294                kref_get(&req->ref);
2295        return req;
2296}
2297
2298static inline void
2299i915_gem_request_unreference(struct drm_i915_gem_request *req)
2300{
2301        WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2302        kref_put(&req->ref, i915_gem_request_free);
2303}
2304
2305static inline void
2306i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2307{
2308        struct drm_device *dev;
2309
2310        if (!req)
2311                return;
2312
2313        dev = req->ring->dev;
2314        if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2315                mutex_unlock(&dev->struct_mutex);
2316}
2317
2318static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2319                                           struct drm_i915_gem_request *src)
2320{
2321        if (src)
2322                i915_gem_request_reference(src);
2323
2324        if (*pdst)
2325                i915_gem_request_unreference(*pdst);
2326
2327        *pdst = src;
2328}
2329
2330/*
2331 * XXX: i915_gem_request_completed should be here but currently needs the
2332 * definition of i915_seqno_passed() which is below. It will be moved in
2333 * a later patch when the call to i915_seqno_passed() is obsoleted...
2334 */
2335
2336/*
2337 * A command that requires special handling by the command parser.
2338 */
2339struct drm_i915_cmd_descriptor {
2340        /*
2341         * Flags describing how the command parser processes the command.
2342         *
2343         * CMD_DESC_FIXED: The command has a fixed length if this is set,
2344         *                 a length mask if not set
2345         * CMD_DESC_SKIP: The command is allowed but does not follow the
2346         *                standard length encoding for the opcode range in
2347         *                which it falls
2348         * CMD_DESC_REJECT: The command is never allowed
2349         * CMD_DESC_REGISTER: The command should be checked against the
2350         *                    register whitelist for the appropriate ring
2351         * CMD_DESC_MASTER: The command is allowed if the submitting process
2352         *                  is the DRM master
2353         */
2354        u32 flags;
2355#define CMD_DESC_FIXED    (1<<0)
2356#define CMD_DESC_SKIP     (1<<1)
2357#define CMD_DESC_REJECT   (1<<2)
2358#define CMD_DESC_REGISTER (1<<3)
2359#define CMD_DESC_BITMASK  (1<<4)
2360#define CMD_DESC_MASTER   (1<<5)
2361
2362        /*
2363         * The command's unique identification bits and the bitmask to get them.
2364         * This isn't strictly the opcode field as defined in the spec and may
2365         * also include type, subtype, and/or subop fields.
2366         */
2367        struct {
2368                u32 value;
2369                u32 mask;
2370        } cmd;
2371
2372        /*
2373         * The command's length. The command is either fixed length (i.e. does
2374         * not include a length field) or has a length field mask. The flag
2375         * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2376         * a length mask. All command entries in a command table must include
2377         * length information.
2378         */
2379        union {
2380                u32 fixed;
2381                u32 mask;
2382        } length;
2383
2384        /*
2385         * Describes where to find a register address in the command to check
2386         * against the ring's register whitelist. Only valid if flags has the
2387         * CMD_DESC_REGISTER bit set.
2388         *
2389         * A non-zero step value implies that the command may access multiple
2390         * registers in sequence (e.g. LRI), in that case step gives the
2391         * distance in dwords between individual offset fields.
2392         */
2393        struct {
2394                u32 offset;
2395                u32 mask;
2396                u32 step;
2397        } reg;
2398
2399#define MAX_CMD_DESC_BITMASKS 3
2400        /*
2401         * Describes command checks where a particular dword is masked and
2402         * compared against an expected value. If the command does not match
2403         * the expected value, the parser rejects it. Only valid if flags has
2404         * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2405         * are valid.
2406         *
2407         * If the check specifies a non-zero condition_mask then the parser
2408         * only performs the check when the bits specified by condition_mask
2409         * are non-zero.
2410         */
2411        struct {
2412                u32 offset;
2413                u32 mask;
2414                u32 expected;
2415                u32 condition_offset;
2416                u32 condition_mask;
2417        } bits[MAX_CMD_DESC_BITMASKS];
2418};
2419
2420/*
2421 * A table of commands requiring special handling by the command parser.
2422 *
2423 * Each ring has an array of tables. Each table consists of an array of command
2424 * descriptors, which must be sorted with command opcodes in ascending order.
2425 */
2426struct drm_i915_cmd_table {
2427        const struct drm_i915_cmd_descriptor *table;
2428        int count;
2429};
2430
2431/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2432#define __I915__(p) ({ \
2433        struct drm_i915_private *__p; \
2434        if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2435                __p = (struct drm_i915_private *)p; \
2436        else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2437                __p = to_i915((struct drm_device *)p); \
2438        else \
2439                BUILD_BUG(); \
2440        __p; \
2441})
2442#define INTEL_INFO(p)   (&__I915__(p)->info)
2443#define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
2444#define INTEL_REVID(p)  (__I915__(p)->dev->pdev->revision)
2445
2446#define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
2447#define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
2448#define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
2449#define IS_I865G(dev)           (INTEL_DEVID(dev) == 0x2572)
2450#define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
2451#define IS_I915GM(dev)          (INTEL_DEVID(dev) == 0x2592)
2452#define IS_I945G(dev)           (INTEL_DEVID(dev) == 0x2772)
2453#define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
2454#define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
2455#define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
2456#define IS_GM45(dev)            (INTEL_DEVID(dev) == 0x2A42)
2457#define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
2458#define IS_PINEVIEW_G(dev)      (INTEL_DEVID(dev) == 0xa001)
2459#define IS_PINEVIEW_M(dev)      (INTEL_DEVID(dev) == 0xa011)
2460#define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
2461#define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
2462#define IS_IRONLAKE_M(dev)      (INTEL_DEVID(dev) == 0x0046)
2463#define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
2464#define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
2465                                 INTEL_DEVID(dev) == 0x0152 || \
2466                                 INTEL_DEVID(dev) == 0x015a)
2467#define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
2468#define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2469#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2470#define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2471#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2472#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2473#define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
2474#define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
2475                                 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2476#define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
2477                                 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||    \
2478                                 (INTEL_DEVID(dev) & 0xf) == 0xb ||     \
2479                                 (INTEL_DEVID(dev) & 0xf) == 0xe))
2480/* ULX machines are also considered ULT. */
2481#define IS_BDW_ULX(dev)         (IS_BROADWELL(dev) && \
2482                                 (INTEL_DEVID(dev) & 0xf) == 0xe)
2483#define IS_BDW_GT3(dev)         (IS_BROADWELL(dev) && \
2484                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2485#define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
2486                                 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2487#define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
2488                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2489/* ULX machines are also considered ULT. */
2490#define IS_HSW_ULX(dev)         (INTEL_DEVID(dev) == 0x0A0E || \
2491                                 INTEL_DEVID(dev) == 0x0A1E)
2492#define IS_SKL_ULT(dev)         (INTEL_DEVID(dev) == 0x1906 || \
2493                                 INTEL_DEVID(dev) == 0x1913 || \
2494                                 INTEL_DEVID(dev) == 0x1916 || \
2495                                 INTEL_DEVID(dev) == 0x1921 || \
2496                                 INTEL_DEVID(dev) == 0x1926)
2497#define IS_SKL_ULX(dev)         (INTEL_DEVID(dev) == 0x190E || \
2498                                 INTEL_DEVID(dev) == 0x1915 || \
2499                                 INTEL_DEVID(dev) == 0x191E)
2500#define IS_SKL_GT3(dev)         (IS_SKYLAKE(dev) && \
2501                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2502#define IS_SKL_GT4(dev)         (IS_SKYLAKE(dev) && \
2503                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2504
2505#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2506
2507#define SKL_REVID_A0            (0x0)
2508#define SKL_REVID_B0            (0x1)
2509#define SKL_REVID_C0            (0x2)
2510#define SKL_REVID_D0            (0x3)
2511#define SKL_REVID_E0            (0x4)
2512#define SKL_REVID_F0            (0x5)
2513
2514#define BXT_REVID_A0            (0x0)
2515#define BXT_REVID_B0            (0x3)
2516#define BXT_REVID_C0            (0x9)
2517
2518/*
2519 * The genX designation typically refers to the render engine, so render
2520 * capability related checks should use IS_GEN, while display and other checks
2521 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2522 * chips, etc.).
2523 */
2524#define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
2525#define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
2526#define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
2527#define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
2528#define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
2529#define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
2530#define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
2531#define IS_GEN9(dev)    (INTEL_INFO(dev)->gen == 9)
2532
2533#define RENDER_RING             (1<<RCS)
2534#define BSD_RING                (1<<VCS)
2535#define BLT_RING                (1<<BCS)
2536#define VEBOX_RING              (1<<VECS)
2537#define BSD2_RING               (1<<VCS2)
2538#define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
2539#define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2540#define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
2541#define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2542#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
2543#define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2544                                 __I915__(dev)->ellc_size)
2545#define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
2546
2547#define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
2548#define HAS_LOGICAL_RING_CONTEXTS(dev)  (INTEL_INFO(dev)->gen >= 8)
2549#define USES_PPGTT(dev)         (i915.enable_ppgtt)
2550#define USES_FULL_PPGTT(dev)    (i915.enable_ppgtt >= 2)
2551#define USES_FULL_48BIT_PPGTT(dev)      (i915.enable_ppgtt == 3)
2552
2553#define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
2554#define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
2555
2556/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2557#define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
2558/*
2559 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2560 * even when in MSI mode. This results in spurious interrupt warnings if the
2561 * legacy irq no. is shared with another device. The kernel then disables that
2562 * interrupt source and so prevents the other device from working properly.
2563 */
2564#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2565#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2566
2567/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2568 * rows, which changed the alignment requirements and fence programming.
2569 */
2570#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2571                                                      IS_I915GM(dev)))
2572#define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
2573#define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
2574
2575#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2576#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2577#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2578
2579#define HAS_IPS(dev)            (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2580
2581#define HAS_DP_MST(dev)         (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2582                                 INTEL_INFO(dev)->gen >= 9)
2583
2584#define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
2585#define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
2586#define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2587                                 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2588                                 IS_SKYLAKE(dev))
2589#define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
2590                                 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2591                                 IS_SKYLAKE(dev))
2592#define HAS_RC6(dev)            (INTEL_INFO(dev)->gen >= 6)
2593#define HAS_RC6p(dev)           (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2594
2595#define HAS_CSR(dev)    (IS_GEN9(dev))
2596
2597#define HAS_GUC_UCODE(dev)      (IS_GEN9(dev))
2598#define HAS_GUC_SCHED(dev)      (IS_GEN9(dev))
2599
2600#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2601                                    INTEL_INFO(dev)->gen >= 8)
2602
2603#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2604                                 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2605
2606#define INTEL_PCH_DEVICE_ID_MASK                0xff00
2607#define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2608#define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2609#define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2610#define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2611#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2612#define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2613#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2614#define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2615#define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2616
2617#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2618#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2619#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2620#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2621#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2622#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2623#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2624#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2625
2626#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2627
2628/* DPF == dynamic parity feature */
2629#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2630#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2631
2632#define GT_FREQUENCY_MULTIPLIER 50
2633#define GEN9_FREQ_SCALER 3
2634
2635#include "i915_trace.h"
2636
2637extern const struct drm_ioctl_desc i915_ioctls[];
2638extern int i915_max_ioctl;
2639
2640extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2641extern int i915_resume_switcheroo(struct drm_device *dev);
2642
2643/* i915_params.c */
2644struct i915_params {
2645        int modeset;
2646        int panel_ignore_lid;
2647        int semaphores;
2648        int lvds_channel_mode;
2649        int panel_use_ssc;
2650        int vbt_sdvo_panel_type;
2651        int enable_rc6;
2652        int enable_fbc;
2653        int enable_ppgtt;
2654        int enable_execlists;
2655        int enable_psr;
2656        unsigned int preliminary_hw_support;
2657        int disable_power_well;
2658        int enable_ips;
2659        int invert_brightness;
2660        int enable_cmd_parser;
2661        /* leave bools at the end to not create holes */
2662        bool enable_hangcheck;
2663        bool fastboot;
2664        bool prefault_disable;
2665        bool load_detect_test;
2666        bool reset;
2667        bool disable_display;
2668        bool disable_vtd_wa;
2669        bool enable_guc_submission;
2670        int guc_log_level;
2671        int use_mmio_flip;
2672        int mmio_debug;
2673        bool verbose_state_checks;
2674        bool nuclear_pageflip;
2675        int edp_vswing;
2676};
2677extern struct i915_params i915 __read_mostly;
2678
2679                                /* i915_dma.c */
2680extern int i915_driver_load(struct drm_device *, unsigned long flags);
2681extern int i915_driver_unload(struct drm_device *);
2682extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2683extern void i915_driver_lastclose(struct drm_device * dev);
2684extern void i915_driver_preclose(struct drm_device *dev,
2685                                 struct drm_file *file);
2686extern void i915_driver_postclose(struct drm_device *dev,
2687                                  struct drm_file *file);
2688#ifdef CONFIG_COMPAT
2689extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2690                              unsigned long arg);
2691#endif
2692extern int intel_gpu_reset(struct drm_device *dev);
2693extern bool intel_has_gpu_reset(struct drm_device *dev);
2694extern int i915_reset(struct drm_device *dev);
2695extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2696extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2697extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2698extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2699int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2700void i915_firmware_load_error_print(const char *fw_path, int err);
2701
2702/* intel_hotplug.c */
2703void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2704void intel_hpd_init(struct drm_i915_private *dev_priv);
2705void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2706void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2707bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2708
2709/* i915_irq.c */
2710void i915_queue_hangcheck(struct drm_device *dev);
2711__printf(3, 4)
2712void i915_handle_error(struct drm_device *dev, bool wedged,
2713                       const char *fmt, ...);
2714
2715extern void intel_irq_init(struct drm_i915_private *dev_priv);
2716int intel_irq_install(struct drm_i915_private *dev_priv);
2717void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2718
2719extern void intel_uncore_sanitize(struct drm_device *dev);
2720extern void intel_uncore_early_sanitize(struct drm_device *dev,
2721                                        bool restore_forcewake);
2722extern void intel_uncore_init(struct drm_device *dev);
2723extern void intel_uncore_check_errors(struct drm_device *dev);
2724extern void intel_uncore_fini(struct drm_device *dev);
2725extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2726const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2727void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2728                                enum forcewake_domains domains);
2729void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2730                                enum forcewake_domains domains);
2731/* Like above but the caller must manage the uncore.lock itself.
2732 * Must be used with I915_READ_FW and friends.
2733 */
2734void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2735                                        enum forcewake_domains domains);
2736void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2737                                        enum forcewake_domains domains);
2738void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2739static inline bool intel_vgpu_active(struct drm_device *dev)
2740{
2741        return to_i915(dev)->vgpu.active;
2742}
2743
2744void
2745i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2746                     u32 status_mask);
2747
2748void
2749i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2750                      u32 status_mask);
2751
2752void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2753void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2754void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2755                                   uint32_t mask,
2756                                   uint32_t bits);
2757void
2758ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2759void
2760ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2761void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2762                                  uint32_t interrupt_mask,
2763                                  uint32_t enabled_irq_mask);
2764#define ibx_enable_display_interrupt(dev_priv, bits) \
2765        ibx_display_interrupt_update((dev_priv), (bits), (bits))
2766#define ibx_disable_display_interrupt(dev_priv, bits) \
2767        ibx_display_interrupt_update((dev_priv), (bits), 0)
2768
2769/* i915_gem.c */
2770int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2771                          struct drm_file *file_priv);
2772int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2773                         struct drm_file *file_priv);
2774int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2775                          struct drm_file *file_priv);
2776int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2777                        struct drm_file *file_priv);
2778int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2779                        struct drm_file *file_priv);
2780int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2781                              struct drm_file *file_priv);
2782int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2783                             struct drm_file *file_priv);
2784void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2785                                        struct drm_i915_gem_request *req);
2786void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2787int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2788                                   struct drm_i915_gem_execbuffer2 *args,
2789                                   struct list_head *vmas);
2790int i915_gem_execbuffer(struct drm_device *dev, void *data,
2791                        struct drm_file *file_priv);
2792int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2793                         struct drm_file *file_priv);
2794int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2795                        struct drm_file *file_priv);
2796int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2797                               struct drm_file *file);
2798int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2799                               struct drm_file *file);
2800int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2801                            struct drm_file *file_priv);
2802int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2803                           struct drm_file *file_priv);
2804int i915_gem_set_tiling(struct drm_device *dev, void *data,
2805                        struct drm_file *file_priv);
2806int i915_gem_get_tiling(struct drm_device *dev, void *data,
2807                        struct drm_file *file_priv);
2808int i915_gem_init_userptr(struct drm_device *dev);
2809int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2810                           struct drm_file *file);
2811int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2812                                struct drm_file *file_priv);
2813int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2814                        struct drm_file *file_priv);
2815void i915_gem_load(struct drm_device *dev);
2816void *i915_gem_object_alloc(struct drm_device *dev);
2817void i915_gem_object_free(struct drm_i915_gem_object *obj);
2818void i915_gem_object_init(struct drm_i915_gem_object *obj,
2819                         const struct drm_i915_gem_object_ops *ops);
2820struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2821                                                  size_t size);
2822struct drm_i915_gem_object *i915_gem_object_create_from_data(
2823                struct drm_device *dev, const void *data, size_t size);
2824void i915_gem_free_object(struct drm_gem_object *obj);
2825void i915_gem_vma_destroy(struct i915_vma *vma);
2826
2827/* Flags used by pin/bind&friends. */
2828#define PIN_MAPPABLE    (1<<0)
2829#define PIN_NONBLOCK    (1<<1)
2830#define PIN_GLOBAL      (1<<2)
2831#define PIN_OFFSET_BIAS (1<<3)
2832#define PIN_USER        (1<<4)
2833#define PIN_UPDATE      (1<<5)
2834#define PIN_ZONE_4G     (1<<6)
2835#define PIN_HIGH        (1<<7)
2836#define PIN_OFFSET_MASK (~4095)
2837int __must_check
2838i915_gem_object_pin(struct drm_i915_gem_object *obj,
2839                    struct i915_address_space *vm,
2840                    uint32_t alignment,
2841                    uint64_t flags);
2842int __must_check
2843i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2844                         const struct i915_ggtt_view *view,
2845                         uint32_t alignment,
2846                         uint64_t flags);
2847
2848int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2849                  u32 flags);
2850void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2851int __must_check i915_vma_unbind(struct i915_vma *vma);
2852/*
2853 * BEWARE: Do not use the function below unless you can _absolutely_
2854 * _guarantee_ VMA in question is _not in use_ anywhere.
2855 */
2856int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2857int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2858void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2859void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2860
2861int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2862                                    int *needs_clflush);
2863
2864int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2865
2866static inline int __sg_page_count(struct scatterlist *sg)
2867{
2868        return sg->length >> PAGE_SHIFT;
2869}
2870
2871static inline struct page *
2872i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2873{
2874        if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2875                return NULL;
2876
2877        if (n < obj->get_page.last) {
2878                obj->get_page.sg = obj->pages->sgl;
2879                obj->get_page.last = 0;
2880        }
2881
2882        while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2883                obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2884                if (unlikely(sg_is_chain(obj->get_page.sg)))
2885                        obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2886        }
2887
2888        return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2889}
2890
2891static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2892{
2893        BUG_ON(obj->pages == NULL);
2894        obj->pages_pin_count++;
2895}
2896static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2897{
2898        BUG_ON(obj->pages_pin_count == 0);
2899        obj->pages_pin_count--;
2900}
2901
2902int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2903int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2904                         struct intel_engine_cs *to,
2905                         struct drm_i915_gem_request **to_req);
2906void i915_vma_move_to_active(struct i915_vma *vma,
2907                             struct drm_i915_gem_request *req);
2908int i915_gem_dumb_create(struct drm_file *file_priv,
2909                         struct drm_device *dev,
2910                         struct drm_mode_create_dumb *args);
2911int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2912                      uint32_t handle, uint64_t *offset);
2913/**
2914 * Returns true if seq1 is later than seq2.
2915 */
2916static inline bool
2917i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2918{
2919        return (int32_t)(seq1 - seq2) >= 0;
2920}
2921
2922static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2923                                           bool lazy_coherency)
2924{
2925        u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2926        return i915_seqno_passed(seqno, req->previous_seqno);
2927}
2928
2929static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2930                                              bool lazy_coherency)
2931{
2932        u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2933        return i915_seqno_passed(seqno, req->seqno);
2934}
2935
2936int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2937int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2938
2939struct drm_i915_gem_request *
2940i915_gem_find_active_request(struct intel_engine_cs *ring);
2941
2942bool i915_gem_retire_requests(struct drm_device *dev);
2943void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2944int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2945                                      bool interruptible);
2946
2947static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2948{
2949        return unlikely(atomic_read(&error->reset_counter)
2950                        & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2951}
2952
2953static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2954{
2955        return atomic_read(&error->reset_counter) & I915_WEDGED;
2956}
2957
2958static inline u32 i915_reset_count(struct i915_gpu_error *error)
2959{
2960        return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2961}
2962
2963static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2964{
2965        return dev_priv->gpu_error.stop_rings == 0 ||
2966                dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2967}
2968
2969static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2970{
2971        return dev_priv->gpu_error.stop_rings == 0 ||
2972                dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2973}
2974
2975void i915_gem_reset(struct drm_device *dev);
2976bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2977int __must_check i915_gem_init(struct drm_device *dev);
2978int i915_gem_init_rings(struct drm_device *dev);
2979int __must_check i915_gem_init_hw(struct drm_device *dev);
2980int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2981void i915_gem_init_swizzling(struct drm_device *dev);
2982void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2983int __must_check i915_gpu_idle(struct drm_device *dev);
2984int __must_check i915_gem_suspend(struct drm_device *dev);
2985void __i915_add_request(struct drm_i915_gem_request *req,
2986                        struct drm_i915_gem_object *batch_obj,
2987                        bool flush_caches);
2988#define i915_add_request(req) \
2989        __i915_add_request(req, NULL, true)
2990#define i915_add_request_no_flush(req) \
2991        __i915_add_request(req, NULL, false)
2992int __i915_wait_request(struct drm_i915_gem_request *req,
2993                        unsigned reset_counter,
2994                        bool interruptible,
2995                        s64 *timeout,
2996                        struct intel_rps_client *rps);
2997int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2998int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2999int __must_check
3000i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3001                               bool readonly);
3002int __must_check
3003i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3004                                  bool write);
3005int __must_check
3006i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3007int __must_check
3008i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3009                                     u32 alignment,
3010                                     struct intel_engine_cs *pipelined,
3011                                     struct drm_i915_gem_request **pipelined_request,
3012                                     const struct i915_ggtt_view *view);
3013void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3014                                              const struct i915_ggtt_view *view);
3015int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3016                                int align);
3017int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3018void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3019
3020uint32_t
3021i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3022uint32_t
3023i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3024                            int tiling_mode, bool fenced);
3025
3026int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3027                                    enum i915_cache_level cache_level);
3028
3029struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3030                                struct dma_buf *dma_buf);
3031
3032struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3033                                struct drm_gem_object *gem_obj, int flags);
3034
3035u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3036                                  const struct i915_ggtt_view *view);
3037u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3038                        struct i915_address_space *vm);
3039static inline u64
3040i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3041{
3042        return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3043}
3044
3045bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3046bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3047                                  const struct i915_ggtt_view *view);
3048bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3049                        struct i915_address_space *vm);
3050
3051unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3052                                struct i915_address_space *vm);
3053struct i915_vma *
3054i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3055                    struct i915_address_space *vm);
3056struct i915_vma *
3057i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3058                          const struct i915_ggtt_view *view);
3059
3060struct i915_vma *
3061i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3062                                  struct i915_address_space *vm);
3063struct i915_vma *
3064i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3065                                       const struct i915_ggtt_view *view);
3066
3067static inline struct i915_vma *
3068i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3069{
3070        return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3071}
3072bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3073
3074/* Some GGTT VM helpers */
3075#define i915_obj_to_ggtt(obj) \
3076        (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3077static inline bool i915_is_ggtt(struct i915_address_space *vm)
3078{
3079        struct i915_address_space *ggtt =
3080                &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3081        return vm == ggtt;
3082}
3083
3084static inline struct i915_hw_ppgtt *
3085i915_vm_to_ppgtt(struct i915_address_space *vm)
3086{
3087        WARN_ON(i915_is_ggtt(vm));
3088
3089        return container_of(vm, struct i915_hw_ppgtt, base);
3090}
3091
3092
3093static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3094{
3095        return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3096}
3097
3098static inline unsigned long
3099i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3100{
3101        return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3102}
3103
3104static inline int __must_check
3105i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3106                      uint32_t alignment,
3107                      unsigned flags)
3108{
3109        return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3110                                   alignment, flags | PIN_GLOBAL);
3111}
3112
3113static inline int
3114i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3115{
3116        return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3117}
3118
3119void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3120                                     const struct i915_ggtt_view *view);
3121static inline void
3122i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3123{
3124        i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3125}
3126
3127/* i915_gem_fence.c */
3128int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3129int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3130
3131bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3132void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3133
3134void i915_gem_restore_fences(struct drm_device *dev);
3135
3136void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3137void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3138void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3139
3140/* i915_gem_context.c */
3141int __must_check i915_gem_context_init(struct drm_device *dev);
3142void i915_gem_context_fini(struct drm_device *dev);
3143void i915_gem_context_reset(struct drm_device *dev);
3144int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3145int i915_gem_context_enable(struct drm_i915_gem_request *req);
3146void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3147int i915_switch_context(struct drm_i915_gem_request *req);
3148struct intel_context *
3149i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3150void i915_gem_context_free(struct kref *ctx_ref);
3151struct drm_i915_gem_object *
3152i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3153static inline void i915_gem_context_reference(struct intel_context *ctx)
3154{
3155        kref_get(&ctx->ref);
3156}
3157
3158static inline void i915_gem_context_unreference(struct intel_context *ctx)
3159{
3160        kref_put(&ctx->ref, i915_gem_context_free);
3161}
3162
3163static inline bool i915_gem_context_is_default(const struct intel_context *c)
3164{
3165        return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3166}
3167
3168int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3169                                  struct drm_file *file);
3170int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3171                                   struct drm_file *file);
3172int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3173                                    struct drm_file *file_priv);
3174int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3175                                    struct drm_file *file_priv);
3176
3177/* i915_gem_evict.c */
3178int __must_check i915_gem_evict_something(struct drm_device *dev,
3179                                          struct i915_address_space *vm,
3180                                          int min_size,
3181                                          unsigned alignment,
3182                                          unsigned cache_level,
3183                                          unsigned long start,
3184                                          unsigned long end,
3185                                          unsigned flags);
3186int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3187
3188/* belongs in i915_gem_gtt.h */
3189static inline void i915_gem_chipset_flush(struct drm_device *dev)
3190{
3191        if (INTEL_INFO(dev)->gen < 6)
3192                intel_gtt_chipset_flush();
3193}
3194
3195/* i915_gem_stolen.c */
3196int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3197                                struct drm_mm_node *node, u64 size,
3198                                unsigned alignment);
3199int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3200                                         struct drm_mm_node *node, u64 size,
3201                                         unsigned alignment, u64 start,
3202                                         u64 end);
3203void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3204                                 struct drm_mm_node *node);
3205int i915_gem_init_stolen(struct drm_device *dev);
3206void i915_gem_cleanup_stolen(struct drm_device *dev);
3207struct drm_i915_gem_object *
3208i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3209struct drm_i915_gem_object *
3210i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3211                                               u32 stolen_offset,
3212                                               u32 gtt_offset,
3213                                               u32 size);
3214
3215/* i915_gem_shrinker.c */
3216unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3217                              unsigned long target,
3218                              unsigned flags);
3219#define I915_SHRINK_PURGEABLE 0x1
3220#define I915_SHRINK_UNBOUND 0x2
3221#define I915_SHRINK_BOUND 0x4
3222#define I915_SHRINK_ACTIVE 0x8
3223unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3224void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3225
3226
3227/* i915_gem_tiling.c */
3228static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3229{
3230        struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3231
3232        return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3233                obj->tiling_mode != I915_TILING_NONE;
3234}
3235
3236/* i915_gem_debug.c */
3237#if WATCH_LISTS
3238int i915_verify_lists(struct drm_device *dev);
3239#else
3240#define i915_verify_lists(dev) 0
3241#endif
3242
3243/* i915_debugfs.c */
3244int i915_debugfs_init(struct drm_minor *minor);
3245void i915_debugfs_cleanup(struct drm_minor *minor);
3246#ifdef CONFIG_DEBUG_FS
3247int i915_debugfs_connector_add(struct drm_connector *connector);
3248void intel_display_crc_init(struct drm_device *dev);
3249#else
3250static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3251{ return 0; }
3252static inline void intel_display_crc_init(struct drm_device *dev) {}
3253#endif
3254
3255/* i915_gpu_error.c */
3256__printf(2, 3)
3257void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3258int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3259                            const struct i915_error_state_file_priv *error);
3260int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3261                              struct drm_i915_private *i915,
3262                              size_t count, loff_t pos);
3263static inline void i915_error_state_buf_release(
3264        struct drm_i915_error_state_buf *eb)
3265{
3266        kfree(eb->buf);
3267}
3268void i915_capture_error_state(struct drm_device *dev, bool wedge,
3269                              const char *error_msg);
3270void i915_error_state_get(struct drm_device *dev,
3271                          struct i915_error_state_file_priv *error_priv);
3272void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3273void i915_destroy_error_state(struct drm_device *dev);
3274
3275void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3276const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3277
3278/* i915_cmd_parser.c */
3279int i915_cmd_parser_get_version(void);
3280int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3281void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3282bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3283int i915_parse_cmds(struct intel_engine_cs *ring,
3284                    struct drm_i915_gem_object *batch_obj,
3285                    struct drm_i915_gem_object *shadow_batch_obj,
3286                    u32 batch_start_offset,
3287                    u32 batch_len,
3288                    bool is_master);
3289
3290/* i915_suspend.c */
3291extern int i915_save_state(struct drm_device *dev);
3292extern int i915_restore_state(struct drm_device *dev);
3293
3294/* i915_sysfs.c */
3295void i915_setup_sysfs(struct drm_device *dev_priv);
3296void i915_teardown_sysfs(struct drm_device *dev_priv);
3297
3298/* intel_i2c.c */
3299extern int intel_setup_gmbus(struct drm_device *dev);
3300extern void intel_teardown_gmbus(struct drm_device *dev);
3301extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3302                                     unsigned int pin);
3303
3304extern struct i2c_adapter *
3305intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3306extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3307extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3308static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3309{
3310        return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3311}
3312extern void intel_i2c_reset(struct drm_device *dev);
3313
3314/* intel_bios.c */
3315bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3316
3317/* intel_opregion.c */
3318#ifdef CONFIG_ACPI
3319extern int intel_opregion_setup(struct drm_device *dev);
3320extern void intel_opregion_init(struct drm_device *dev);
3321extern void intel_opregion_fini(struct drm_device *dev);
3322extern void intel_opregion_asle_intr(struct drm_device *dev);
3323extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3324                                         bool enable);
3325extern int intel_opregion_notify_adapter(struct drm_device *dev,
3326                                         pci_power_t state);
3327#else
3328static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3329static inline void intel_opregion_init(struct drm_device *dev) { return; }
3330static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3331static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3332static inline int
3333intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3334{
3335        return 0;
3336}
3337static inline int
3338intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3339{
3340        return 0;
3341}
3342#endif
3343
3344/* intel_acpi.c */
3345#ifdef CONFIG_ACPI
3346extern void intel_register_dsm_handler(void);
3347extern void intel_unregister_dsm_handler(void);
3348#else
3349static inline void intel_register_dsm_handler(void) { return; }
3350static inline void intel_unregister_dsm_handler(void) { return; }
3351#endif /* CONFIG_ACPI */
3352
3353/* modesetting */
3354extern void intel_modeset_init_hw(struct drm_device *dev);
3355extern void intel_modeset_init(struct drm_device *dev);
3356extern void intel_modeset_gem_init(struct drm_device *dev);
3357extern void intel_modeset_cleanup(struct drm_device *dev);
3358extern void intel_connector_unregister(struct intel_connector *);
3359extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3360extern void intel_display_resume(struct drm_device *dev);
3361extern void i915_redisable_vga(struct drm_device *dev);
3362extern void i915_redisable_vga_power_on(struct drm_device *dev);
3363extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3364extern void intel_init_pch_refclk(struct drm_device *dev);
3365extern void intel_set_rps(struct drm_device *dev, u8 val);
3366extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3367                                  bool enable);
3368extern void intel_detect_pch(struct drm_device *dev);
3369extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3370extern int intel_enable_rc6(const struct drm_device *dev);
3371
3372extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3373int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3374                        struct drm_file *file);
3375int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3376                               struct drm_file *file);
3377
3378/* overlay */
3379extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3380extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3381                                            struct intel_overlay_error_state *error);
3382
3383extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3384extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3385                                            struct drm_device *dev,
3386                                            struct intel_display_error_state *error);
3387
3388int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3389int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3390
3391/* intel_sideband.c */
3392u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3393void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3394u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3395u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3396void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3397u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3398void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3399u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3400void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3401u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3402void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3403u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3404void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3405u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3406void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3407u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3408                   enum intel_sbi_destination destination);
3409void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3410                     enum intel_sbi_destination destination);
3411u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3412void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3413
3414int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3415int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3416
3417#define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3418#define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3419
3420#define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3421#define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3422#define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3423#define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3424
3425#define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3426#define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3427#define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3428#define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3429
3430/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3431 * will be implemented using 2 32-bit writes in an arbitrary order with
3432 * an arbitrary delay between them. This can cause the hardware to
3433 * act upon the intermediate value, possibly leading to corruption and
3434 * machine death. You have been warned.
3435 */
3436#define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3437#define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3438
3439#define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3440        u32 upper, lower, old_upper, loop = 0;                          \
3441        upper = I915_READ(upper_reg);                                   \
3442        do {                                                            \
3443                old_upper = upper;                                      \
3444                lower = I915_READ(lower_reg);                           \
3445                upper = I915_READ(upper_reg);                           \
3446        } while (upper != old_upper && loop++ < 2);                     \
3447        (u64)upper << 32 | lower; })
3448
3449#define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3450#define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3451
3452/* These are untraced mmio-accessors that are only valid to be used inside
3453 * criticial sections inside IRQ handlers where forcewake is explicitly
3454 * controlled.
3455 * Think twice, and think again, before using these.
3456 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3457 * intel_uncore_forcewake_irqunlock().
3458 */
3459#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3460#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3461#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3462
3463/* "Broadcast RGB" property */
3464#define INTEL_BROADCAST_RGB_AUTO 0
3465#define INTEL_BROADCAST_RGB_FULL 1
3466#define INTEL_BROADCAST_RGB_LIMITED 2
3467
3468static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3469{
3470        if (IS_VALLEYVIEW(dev))
3471                return VLV_VGACNTRL;
3472        else if (INTEL_INFO(dev)->gen >= 5)
3473                return CPU_VGACNTRL;
3474        else
3475                return VGACNTRL;
3476}
3477
3478static inline void __user *to_user_ptr(u64 address)
3479{
3480        return (void __user *)(uintptr_t)address;
3481}
3482
3483static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3484{
3485        unsigned long j = msecs_to_jiffies(m);
3486
3487        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3488}
3489
3490static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3491{
3492        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3493}
3494
3495static inline unsigned long
3496timespec_to_jiffies_timeout(const struct timespec *value)
3497{
3498        unsigned long j = timespec_to_jiffies(value);
3499
3500        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3501}
3502
3503/*
3504 * If you need to wait X milliseconds between events A and B, but event B
3505 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3506 * when event A happened, then just before event B you call this function and
3507 * pass the timestamp as the first argument, and X as the second argument.
3508 */
3509static inline void
3510wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3511{
3512        unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3513
3514        /*
3515         * Don't re-read the value of "jiffies" every time since it may change
3516         * behind our back and break the math.
3517         */
3518        tmp_jiffies = jiffies;
3519        target_jiffies = timestamp_jiffies +
3520                         msecs_to_jiffies_timeout(to_wait_ms);
3521
3522        if (time_after(target_jiffies, tmp_jiffies)) {
3523                remaining_jiffies = target_jiffies - tmp_jiffies;
3524                while (remaining_jiffies)
3525                        remaining_jiffies =
3526                            schedule_timeout_uninterruptible(remaining_jiffies);
3527        }
3528}
3529
3530static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3531                                      struct drm_i915_gem_request *req)
3532{
3533        if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3534                i915_gem_request_assign(&ring->trace_irq_req, req);
3535}
3536
3537#endif
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