source: src/linux/universal/linux-4.4/drivers/gpu/drm/i915/intel_pm.c @ 31884

Last change on this file since 31884 was 31884, checked in by brainslayer, 4 months ago

update kernels

File size: 207.1 KB
Line 
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include "i915_drv.h"
30#include "intel_drv.h"
31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
33
34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage.  This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE                        (1<<0)
52#define INTEL_RC6p_ENABLE                       (1<<1)
53#define INTEL_RC6pp_ENABLE                      (1<<2)
54
55static void bxt_init_clock_gating(struct drm_device *dev)
56{
57        struct drm_i915_private *dev_priv = dev->dev_private;
58
59        /* WaDisableSDEUnitClockGating:bxt */
60        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
63        /*
64         * FIXME:
65         * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
66         */
67        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
68                   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
69}
70
71static void i915_pineview_get_mem_freq(struct drm_device *dev)
72{
73        struct drm_i915_private *dev_priv = dev->dev_private;
74        u32 tmp;
75
76        tmp = I915_READ(CLKCFG);
77
78        switch (tmp & CLKCFG_FSB_MASK) {
79        case CLKCFG_FSB_533:
80                dev_priv->fsb_freq = 533; /* 133*4 */
81                break;
82        case CLKCFG_FSB_800:
83                dev_priv->fsb_freq = 800; /* 200*4 */
84                break;
85        case CLKCFG_FSB_667:
86                dev_priv->fsb_freq =  667; /* 167*4 */
87                break;
88        case CLKCFG_FSB_400:
89                dev_priv->fsb_freq = 400; /* 100*4 */
90                break;
91        }
92
93        switch (tmp & CLKCFG_MEM_MASK) {
94        case CLKCFG_MEM_533:
95                dev_priv->mem_freq = 533;
96                break;
97        case CLKCFG_MEM_667:
98                dev_priv->mem_freq = 667;
99                break;
100        case CLKCFG_MEM_800:
101                dev_priv->mem_freq = 800;
102                break;
103        }
104
105        /* detect pineview DDR3 setting */
106        tmp = I915_READ(CSHRDDR3CTL);
107        dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
108}
109
110static void i915_ironlake_get_mem_freq(struct drm_device *dev)
111{
112        struct drm_i915_private *dev_priv = dev->dev_private;
113        u16 ddrpll, csipll;
114
115        ddrpll = I915_READ16(DDRMPLL1);
116        csipll = I915_READ16(CSIPLL0);
117
118        switch (ddrpll & 0xff) {
119        case 0xc:
120                dev_priv->mem_freq = 800;
121                break;
122        case 0x10:
123                dev_priv->mem_freq = 1066;
124                break;
125        case 0x14:
126                dev_priv->mem_freq = 1333;
127                break;
128        case 0x18:
129                dev_priv->mem_freq = 1600;
130                break;
131        default:
132                DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
133                                 ddrpll & 0xff);
134                dev_priv->mem_freq = 0;
135                break;
136        }
137
138        dev_priv->ips.r_t = dev_priv->mem_freq;
139
140        switch (csipll & 0x3ff) {
141        case 0x00c:
142                dev_priv->fsb_freq = 3200;
143                break;
144        case 0x00e:
145                dev_priv->fsb_freq = 3733;
146                break;
147        case 0x010:
148                dev_priv->fsb_freq = 4266;
149                break;
150        case 0x012:
151                dev_priv->fsb_freq = 4800;
152                break;
153        case 0x014:
154                dev_priv->fsb_freq = 5333;
155                break;
156        case 0x016:
157                dev_priv->fsb_freq = 5866;
158                break;
159        case 0x018:
160                dev_priv->fsb_freq = 6400;
161                break;
162        default:
163                DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
164                                 csipll & 0x3ff);
165                dev_priv->fsb_freq = 0;
166                break;
167        }
168
169        if (dev_priv->fsb_freq == 3200) {
170                dev_priv->ips.c_m = 0;
171        } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
172                dev_priv->ips.c_m = 1;
173        } else {
174                dev_priv->ips.c_m = 2;
175        }
176}
177
178static const struct cxsr_latency cxsr_latency_table[] = {
179        {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
180        {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
181        {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
182        {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
183        {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
184
185        {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
186        {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
187        {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
188        {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
189        {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
190
191        {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
192        {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
193        {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
194        {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
195        {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
196
197        {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
198        {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
199        {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
200        {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
201        {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
202
203        {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
204        {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
205        {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
206        {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
207        {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
208
209        {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
210        {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
211        {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
212        {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
213        {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
214};
215
216static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
217                                                         int is_ddr3,
218                                                         int fsb,
219                                                         int mem)
220{
221        const struct cxsr_latency *latency;
222        int i;
223
224        if (fsb == 0 || mem == 0)
225                return NULL;
226
227        for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
228                latency = &cxsr_latency_table[i];
229                if (is_desktop == latency->is_desktop &&
230                    is_ddr3 == latency->is_ddr3 &&
231                    fsb == latency->fsb_freq && mem == latency->mem_freq)
232                        return latency;
233        }
234
235        DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
236
237        return NULL;
238}
239
240static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
241{
242        u32 val;
243
244        mutex_lock(&dev_priv->rps.hw_lock);
245
246        val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
247        if (enable)
248                val &= ~FORCE_DDR_HIGH_FREQ;
249        else
250                val |= FORCE_DDR_HIGH_FREQ;
251        val &= ~FORCE_DDR_LOW_FREQ;
252        val |= FORCE_DDR_FREQ_REQ_ACK;
253        vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
254
255        if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
256                      FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
257                DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
258
259        mutex_unlock(&dev_priv->rps.hw_lock);
260}
261
262static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
263{
264        u32 val;
265
266        mutex_lock(&dev_priv->rps.hw_lock);
267
268        val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
269        if (enable)
270                val |= DSP_MAXFIFO_PM5_ENABLE;
271        else
272                val &= ~DSP_MAXFIFO_PM5_ENABLE;
273        vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
274
275        mutex_unlock(&dev_priv->rps.hw_lock);
276}
277
278#define FW_WM(value, plane) \
279        (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
280
281void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
282{
283        struct drm_device *dev = dev_priv->dev;
284        u32 val;
285
286        if (IS_VALLEYVIEW(dev)) {
287                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
288                POSTING_READ(FW_BLC_SELF_VLV);
289                dev_priv->wm.vlv.cxsr = enable;
290        } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
291                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
292                POSTING_READ(FW_BLC_SELF);
293        } else if (IS_PINEVIEW(dev)) {
294                val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
295                val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
296                I915_WRITE(DSPFW3, val);
297                POSTING_READ(DSPFW3);
298        } else if (IS_I945G(dev) || IS_I945GM(dev)) {
299                val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
300                               _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
301                I915_WRITE(FW_BLC_SELF, val);
302                POSTING_READ(FW_BLC_SELF);
303        } else if (IS_I915GM(dev)) {
304                val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
305                               _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
306                I915_WRITE(INSTPM, val);
307                POSTING_READ(INSTPM);
308        } else {
309                return;
310        }
311
312        DRM_DEBUG_KMS("memory self-refresh is %s\n",
313                      enable ? "enabled" : "disabled");
314}
315
316
317/*
318 * Latency for FIFO fetches is dependent on several factors:
319 *   - memory configuration (speed, channels)
320 *   - chipset
321 *   - current MCH state
322 * It can be fairly high in some situations, so here we assume a fairly
323 * pessimal value.  It's a tradeoff between extra memory fetches (if we
324 * set this value too high, the FIFO will fetch frequently to stay full)
325 * and power consumption (set it too low to save power and we might see
326 * FIFO underruns and display "flicker").
327 *
328 * A value of 5us seems to be a good balance; safe for very low end
329 * platforms but not overly aggressive on lower latency configs.
330 */
331static const int pessimal_latency_ns = 5000;
332
333#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
334        ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
335
336static int vlv_get_fifo_size(struct drm_device *dev,
337                              enum pipe pipe, int plane)
338{
339        struct drm_i915_private *dev_priv = dev->dev_private;
340        int sprite0_start, sprite1_start, size;
341
342        switch (pipe) {
343                uint32_t dsparb, dsparb2, dsparb3;
344        case PIPE_A:
345                dsparb = I915_READ(DSPARB);
346                dsparb2 = I915_READ(DSPARB2);
347                sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
348                sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
349                break;
350        case PIPE_B:
351                dsparb = I915_READ(DSPARB);
352                dsparb2 = I915_READ(DSPARB2);
353                sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
354                sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
355                break;
356        case PIPE_C:
357                dsparb2 = I915_READ(DSPARB2);
358                dsparb3 = I915_READ(DSPARB3);
359                sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
360                sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
361                break;
362        default:
363                return 0;
364        }
365
366        switch (plane) {
367        case 0:
368                size = sprite0_start;
369                break;
370        case 1:
371                size = sprite1_start - sprite0_start;
372                break;
373        case 2:
374                size = 512 - 1 - sprite1_start;
375                break;
376        default:
377                return 0;
378        }
379
380        DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
381                      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
382                      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
383                      size);
384
385        return size;
386}
387
388static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
389{
390        struct drm_i915_private *dev_priv = dev->dev_private;
391        uint32_t dsparb = I915_READ(DSPARB);
392        int size;
393
394        size = dsparb & 0x7f;
395        if (plane)
396                size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
397
398        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
399                      plane ? "B" : "A", size);
400
401        return size;
402}
403
404static int i830_get_fifo_size(struct drm_device *dev, int plane)
405{
406        struct drm_i915_private *dev_priv = dev->dev_private;
407        uint32_t dsparb = I915_READ(DSPARB);
408        int size;
409
410        size = dsparb & 0x1ff;
411        if (plane)
412                size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
413        size >>= 1; /* Convert to cachelines */
414
415        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
416                      plane ? "B" : "A", size);
417
418        return size;
419}
420
421static int i845_get_fifo_size(struct drm_device *dev, int plane)
422{
423        struct drm_i915_private *dev_priv = dev->dev_private;
424        uint32_t dsparb = I915_READ(DSPARB);
425        int size;
426
427        size = dsparb & 0x7f;
428        size >>= 2; /* Convert to cachelines */
429
430        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
431                      plane ? "B" : "A",
432                      size);
433
434        return size;
435}
436
437/* Pineview has different values for various configs */
438static const struct intel_watermark_params pineview_display_wm = {
439        .fifo_size = PINEVIEW_DISPLAY_FIFO,
440        .max_wm = PINEVIEW_MAX_WM,
441        .default_wm = PINEVIEW_DFT_WM,
442        .guard_size = PINEVIEW_GUARD_WM,
443        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
444};
445static const struct intel_watermark_params pineview_display_hplloff_wm = {
446        .fifo_size = PINEVIEW_DISPLAY_FIFO,
447        .max_wm = PINEVIEW_MAX_WM,
448        .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
449        .guard_size = PINEVIEW_GUARD_WM,
450        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
451};
452static const struct intel_watermark_params pineview_cursor_wm = {
453        .fifo_size = PINEVIEW_CURSOR_FIFO,
454        .max_wm = PINEVIEW_CURSOR_MAX_WM,
455        .default_wm = PINEVIEW_CURSOR_DFT_WM,
456        .guard_size = PINEVIEW_CURSOR_GUARD_WM,
457        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
458};
459static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
460        .fifo_size = PINEVIEW_CURSOR_FIFO,
461        .max_wm = PINEVIEW_CURSOR_MAX_WM,
462        .default_wm = PINEVIEW_CURSOR_DFT_WM,
463        .guard_size = PINEVIEW_CURSOR_GUARD_WM,
464        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
465};
466static const struct intel_watermark_params g4x_wm_info = {
467        .fifo_size = G4X_FIFO_SIZE,
468        .max_wm = G4X_MAX_WM,
469        .default_wm = G4X_MAX_WM,
470        .guard_size = 2,
471        .cacheline_size = G4X_FIFO_LINE_SIZE,
472};
473static const struct intel_watermark_params g4x_cursor_wm_info = {
474        .fifo_size = I965_CURSOR_FIFO,
475        .max_wm = I965_CURSOR_MAX_WM,
476        .default_wm = I965_CURSOR_DFT_WM,
477        .guard_size = 2,
478        .cacheline_size = G4X_FIFO_LINE_SIZE,
479};
480static const struct intel_watermark_params valleyview_wm_info = {
481        .fifo_size = VALLEYVIEW_FIFO_SIZE,
482        .max_wm = VALLEYVIEW_MAX_WM,
483        .default_wm = VALLEYVIEW_MAX_WM,
484        .guard_size = 2,
485        .cacheline_size = G4X_FIFO_LINE_SIZE,
486};
487static const struct intel_watermark_params valleyview_cursor_wm_info = {
488        .fifo_size = I965_CURSOR_FIFO,
489        .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
490        .default_wm = I965_CURSOR_DFT_WM,
491        .guard_size = 2,
492        .cacheline_size = G4X_FIFO_LINE_SIZE,
493};
494static const struct intel_watermark_params i965_cursor_wm_info = {
495        .fifo_size = I965_CURSOR_FIFO,
496        .max_wm = I965_CURSOR_MAX_WM,
497        .default_wm = I965_CURSOR_DFT_WM,
498        .guard_size = 2,
499        .cacheline_size = I915_FIFO_LINE_SIZE,
500};
501static const struct intel_watermark_params i945_wm_info = {
502        .fifo_size = I945_FIFO_SIZE,
503        .max_wm = I915_MAX_WM,
504        .default_wm = 1,
505        .guard_size = 2,
506        .cacheline_size = I915_FIFO_LINE_SIZE,
507};
508static const struct intel_watermark_params i915_wm_info = {
509        .fifo_size = I915_FIFO_SIZE,
510        .max_wm = I915_MAX_WM,
511        .default_wm = 1,
512        .guard_size = 2,
513        .cacheline_size = I915_FIFO_LINE_SIZE,
514};
515static const struct intel_watermark_params i830_a_wm_info = {
516        .fifo_size = I855GM_FIFO_SIZE,
517        .max_wm = I915_MAX_WM,
518        .default_wm = 1,
519        .guard_size = 2,
520        .cacheline_size = I830_FIFO_LINE_SIZE,
521};
522static const struct intel_watermark_params i830_bc_wm_info = {
523        .fifo_size = I855GM_FIFO_SIZE,
524        .max_wm = I915_MAX_WM/2,
525        .default_wm = 1,
526        .guard_size = 2,
527        .cacheline_size = I830_FIFO_LINE_SIZE,
528};
529static const struct intel_watermark_params i845_wm_info = {
530        .fifo_size = I830_FIFO_SIZE,
531        .max_wm = I915_MAX_WM,
532        .default_wm = 1,
533        .guard_size = 2,
534        .cacheline_size = I830_FIFO_LINE_SIZE,
535};
536
537/**
538 * intel_calculate_wm - calculate watermark level
539 * @clock_in_khz: pixel clock
540 * @wm: chip FIFO params
541 * @pixel_size: display pixel size
542 * @latency_ns: memory latency for the platform
543 *
544 * Calculate the watermark level (the level at which the display plane will
545 * start fetching from memory again).  Each chip has a different display
546 * FIFO size and allocation, so the caller needs to figure that out and pass
547 * in the correct intel_watermark_params structure.
548 *
549 * As the pixel clock runs, the FIFO will be drained at a rate that depends
550 * on the pixel size.  When it reaches the watermark level, it'll start
551 * fetching FIFO line sized based chunks from memory until the FIFO fills
552 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
553 * will occur, and a display engine hang could result.
554 */
555static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
556                                        const struct intel_watermark_params *wm,
557                                        int fifo_size,
558                                        int pixel_size,
559                                        unsigned long latency_ns)
560{
561        long entries_required, wm_size;
562
563        /*
564         * Note: we need to make sure we don't overflow for various clock &
565         * latency values.
566         * clocks go from a few thousand to several hundred thousand.
567         * latency is usually a few thousand
568         */
569        entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
570                1000;
571        entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
572
573        DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
574
575        wm_size = fifo_size - (entries_required + wm->guard_size);
576
577        DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
578
579        /* Don't promote wm_size to unsigned... */
580        if (wm_size > (long)wm->max_wm)
581                wm_size = wm->max_wm;
582        if (wm_size <= 0)
583                wm_size = wm->default_wm;
584
585        /*
586         * Bspec seems to indicate that the value shouldn't be lower than
587         * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588         * Lets go for 8 which is the burst size since certain platforms
589         * already use a hardcoded 8 (which is what the spec says should be
590         * done).
591         */
592        if (wm_size <= 8)
593                wm_size = 8;
594
595        return wm_size;
596}
597
598static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
599{
600        struct drm_crtc *crtc, *enabled = NULL;
601
602        for_each_crtc(dev, crtc) {
603                if (intel_crtc_active(crtc)) {
604                        if (enabled)
605                                return NULL;
606                        enabled = crtc;
607                }
608        }
609
610        return enabled;
611}
612
613static void pineview_update_wm(struct drm_crtc *unused_crtc)
614{
615        struct drm_device *dev = unused_crtc->dev;
616        struct drm_i915_private *dev_priv = dev->dev_private;
617        struct drm_crtc *crtc;
618        const struct cxsr_latency *latency;
619        u32 reg;
620        unsigned long wm;
621
622        latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623                                         dev_priv->fsb_freq, dev_priv->mem_freq);
624        if (!latency) {
625                DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
626                intel_set_memory_cxsr(dev_priv, false);
627                return;
628        }
629
630        crtc = single_enabled_crtc(dev);
631        if (crtc) {
632                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
633                int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
634                int clock = adjusted_mode->crtc_clock;
635
636                /* Display SR */
637                wm = intel_calculate_wm(clock, &pineview_display_wm,
638                                        pineview_display_wm.fifo_size,
639                                        pixel_size, latency->display_sr);
640                reg = I915_READ(DSPFW1);
641                reg &= ~DSPFW_SR_MASK;
642                reg |= FW_WM(wm, SR);
643                I915_WRITE(DSPFW1, reg);
644                DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
645
646                /* cursor SR */
647                wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648                                        pineview_display_wm.fifo_size,
649                                        pixel_size, latency->cursor_sr);
650                reg = I915_READ(DSPFW3);
651                reg &= ~DSPFW_CURSOR_SR_MASK;
652                reg |= FW_WM(wm, CURSOR_SR);
653                I915_WRITE(DSPFW3, reg);
654
655                /* Display HPLL off SR */
656                wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657                                        pineview_display_hplloff_wm.fifo_size,
658                                        pixel_size, latency->display_hpll_disable);
659                reg = I915_READ(DSPFW3);
660                reg &= ~DSPFW_HPLL_SR_MASK;
661                reg |= FW_WM(wm, HPLL_SR);
662                I915_WRITE(DSPFW3, reg);
663
664                /* cursor HPLL off SR */
665                wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666                                        pineview_display_hplloff_wm.fifo_size,
667                                        pixel_size, latency->cursor_hpll_disable);
668                reg = I915_READ(DSPFW3);
669                reg &= ~DSPFW_HPLL_CURSOR_MASK;
670                reg |= FW_WM(wm, HPLL_CURSOR);
671                I915_WRITE(DSPFW3, reg);
672                DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
673
674                intel_set_memory_cxsr(dev_priv, true);
675        } else {
676                intel_set_memory_cxsr(dev_priv, false);
677        }
678}
679
680static bool g4x_compute_wm0(struct drm_device *dev,
681                            int plane,
682                            const struct intel_watermark_params *display,
683                            int display_latency_ns,
684                            const struct intel_watermark_params *cursor,
685                            int cursor_latency_ns,
686                            int *plane_wm,
687                            int *cursor_wm)
688{
689        struct drm_crtc *crtc;
690        const struct drm_display_mode *adjusted_mode;
691        int htotal, hdisplay, clock, pixel_size;
692        int line_time_us, line_count;
693        int entries, tlb_miss;
694
695        crtc = intel_get_crtc_for_plane(dev, plane);
696        if (!intel_crtc_active(crtc)) {
697                *cursor_wm = cursor->guard_size;
698                *plane_wm = display->guard_size;
699                return false;
700        }
701
702        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
703        clock = adjusted_mode->crtc_clock;
704        htotal = adjusted_mode->crtc_htotal;
705        hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
706        pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
707
708        /* Use the small buffer method to calculate plane watermark */
709        entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
710        tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
711        if (tlb_miss > 0)
712                entries += tlb_miss;
713        entries = DIV_ROUND_UP(entries, display->cacheline_size);
714        *plane_wm = entries + display->guard_size;
715        if (*plane_wm > (int)display->max_wm)
716                *plane_wm = display->max_wm;
717
718        /* Use the large buffer method to calculate cursor watermark */
719        line_time_us = max(htotal * 1000 / clock, 1);
720        line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
721        entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
722        tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
723        if (tlb_miss > 0)
724                entries += tlb_miss;
725        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726        *cursor_wm = entries + cursor->guard_size;
727        if (*cursor_wm > (int)cursor->max_wm)
728                *cursor_wm = (int)cursor->max_wm;
729
730        return true;
731}
732
733/*
734 * Check the wm result.
735 *
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
738 * must be disabled.
739 */
740static bool g4x_check_srwm(struct drm_device *dev,
741                           int display_wm, int cursor_wm,
742                           const struct intel_watermark_params *display,
743                           const struct intel_watermark_params *cursor)
744{
745        DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746                      display_wm, cursor_wm);
747
748        if (display_wm > display->max_wm) {
749                DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750                              display_wm, display->max_wm);
751                return false;
752        }
753
754        if (cursor_wm > cursor->max_wm) {
755                DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756                              cursor_wm, cursor->max_wm);
757                return false;
758        }
759
760        if (!(display_wm || cursor_wm)) {
761                DRM_DEBUG_KMS("SR latency is 0, disabling\n");
762                return false;
763        }
764
765        return true;
766}
767
768static bool g4x_compute_srwm(struct drm_device *dev,
769                             int plane,
770                             int latency_ns,
771                             const struct intel_watermark_params *display,
772                             const struct intel_watermark_params *cursor,
773                             int *display_wm, int *cursor_wm)
774{
775        struct drm_crtc *crtc;
776        const struct drm_display_mode *adjusted_mode;
777        int hdisplay, htotal, pixel_size, clock;
778        unsigned long line_time_us;
779        int line_count, line_size;
780        int small, large;
781        int entries;
782
783        if (!latency_ns) {
784                *display_wm = *cursor_wm = 0;
785                return false;
786        }
787
788        crtc = intel_get_crtc_for_plane(dev, plane);
789        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
790        clock = adjusted_mode->crtc_clock;
791        htotal = adjusted_mode->crtc_htotal;
792        hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
793        pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
794
795        line_time_us = max(htotal * 1000 / clock, 1);
796        line_count = (latency_ns / line_time_us + 1000) / 1000;
797        line_size = hdisplay * pixel_size;
798
799        /* Use the minimum of the small and large buffer method for primary */
800        small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
801        large = line_count * line_size;
802
803        entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804        *display_wm = entries + display->guard_size;
805
806        /* calculate the self-refresh watermark for display cursor */
807        entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
808        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809        *cursor_wm = entries + cursor->guard_size;
810
811        return g4x_check_srwm(dev,
812                              *display_wm, *cursor_wm,
813                              display, cursor);
814}
815
816#define FW_WM_VLV(value, plane) \
817        (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
818
819static void vlv_write_wm_values(struct intel_crtc *crtc,
820                                const struct vlv_wm_values *wm)
821{
822        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823        enum pipe pipe = crtc->pipe;
824
825        I915_WRITE(VLV_DDL(pipe),
826                   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827                   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828                   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829                   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
830
831        I915_WRITE(DSPFW1,
832                   FW_WM(wm->sr.plane, SR) |
833                   FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834                   FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835                   FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
836        I915_WRITE(DSPFW2,
837                   FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838                   FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839                   FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
840        I915_WRITE(DSPFW3,
841                   FW_WM(wm->sr.cursor, CURSOR_SR));
842
843        if (IS_CHERRYVIEW(dev_priv)) {
844                I915_WRITE(DSPFW7_CHV,
845                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
847                I915_WRITE(DSPFW8_CHV,
848                           FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849                           FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
850                I915_WRITE(DSPFW9_CHV,
851                           FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852                           FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
853                I915_WRITE(DSPHOWM,
854                           FW_WM(wm->sr.plane >> 9, SR_HI) |
855                           FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856                           FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857                           FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858                           FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859                           FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860                           FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861                           FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862                           FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863                           FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
864        } else {
865                I915_WRITE(DSPFW7,
866                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
868                I915_WRITE(DSPHOWM,
869                           FW_WM(wm->sr.plane >> 9, SR_HI) |
870                           FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871                           FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872                           FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873                           FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874                           FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875                           FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
876        }
877
878        /* zero (unused) WM1 watermarks */
879        I915_WRITE(DSPFW4, 0);
880        I915_WRITE(DSPFW5, 0);
881        I915_WRITE(DSPFW6, 0);
882        I915_WRITE(DSPHOWM1, 0);
883
884        POSTING_READ(DSPFW1);
885}
886
887#undef FW_WM_VLV
888
889enum vlv_wm_level {
890        VLV_WM_LEVEL_PM2,
891        VLV_WM_LEVEL_PM5,
892        VLV_WM_LEVEL_DDR_DVFS,
893};
894
895/* latency must be in 0.1us units. */
896static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897                                   unsigned int pipe_htotal,
898                                   unsigned int horiz_pixels,
899                                   unsigned int bytes_per_pixel,
900                                   unsigned int latency)
901{
902        unsigned int ret;
903
904        ret = (latency * pixel_rate) / (pipe_htotal * 10000);
905        ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
906        ret = DIV_ROUND_UP(ret, 64);
907
908        return ret;
909}
910
911static void vlv_setup_wm_latency(struct drm_device *dev)
912{
913        struct drm_i915_private *dev_priv = dev->dev_private;
914
915        /* all latencies in usec */
916        dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
917
918        dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
919
920        if (IS_CHERRYVIEW(dev_priv)) {
921                dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922                dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
923
924                dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
925        }
926}
927
928static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929                                     struct intel_crtc *crtc,
930                                     const struct intel_plane_state *state,
931                                     int level)
932{
933        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
934        int clock, htotal, pixel_size, width, wm;
935
936        if (dev_priv->wm.pri_latency[level] == 0)
937                return USHRT_MAX;
938
939        if (!state->visible)
940                return 0;
941
942        pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
943        clock = crtc->config->base.adjusted_mode.crtc_clock;
944        htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945        width = crtc->config->pipe_src_w;
946        if (WARN_ON(htotal == 0))
947                htotal = 1;
948
949        if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
950                /*
951                 * FIXME the formula gives values that are
952                 * too big for the cursor FIFO, and hence we
953                 * would never be able to use cursors. For
954                 * now just hardcode the watermark.
955                 */
956                wm = 63;
957        } else {
958                wm = vlv_wm_method2(clock, htotal, width, pixel_size,
959                                    dev_priv->wm.pri_latency[level] * 10);
960        }
961
962        return min_t(int, wm, USHRT_MAX);
963}
964
965static void vlv_compute_fifo(struct intel_crtc *crtc)
966{
967        struct drm_device *dev = crtc->base.dev;
968        struct vlv_wm_state *wm_state = &crtc->wm_state;
969        struct intel_plane *plane;
970        unsigned int total_rate = 0;
971        const int fifo_size = 512 - 1;
972        int fifo_extra, fifo_left = fifo_size;
973
974        for_each_intel_plane_on_crtc(dev, crtc, plane) {
975                struct intel_plane_state *state =
976                        to_intel_plane_state(plane->base.state);
977
978                if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
979                        continue;
980
981                if (state->visible) {
982                        wm_state->num_active_planes++;
983                        total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
984                }
985        }
986
987        for_each_intel_plane_on_crtc(dev, crtc, plane) {
988                struct intel_plane_state *state =
989                        to_intel_plane_state(plane->base.state);
990                unsigned int rate;
991
992                if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993                        plane->wm.fifo_size = 63;
994                        continue;
995                }
996
997                if (!state->visible) {
998                        plane->wm.fifo_size = 0;
999                        continue;
1000                }
1001
1002                rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003                plane->wm.fifo_size = fifo_size * rate / total_rate;
1004                fifo_left -= plane->wm.fifo_size;
1005        }
1006
1007        fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009        /* spread the remainder evenly */
1010        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011                int plane_extra;
1012
1013                if (fifo_left == 0)
1014                        break;
1015
1016                if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017                        continue;
1018
1019                /* give it all to the first plane if none are active */
1020                if (plane->wm.fifo_size == 0 &&
1021                    wm_state->num_active_planes)
1022                        continue;
1023
1024                plane_extra = min(fifo_extra, fifo_left);
1025                plane->wm.fifo_size += plane_extra;
1026                fifo_left -= plane_extra;
1027        }
1028
1029        WARN_ON(fifo_left != 0);
1030}
1031
1032static void vlv_invert_wms(struct intel_crtc *crtc)
1033{
1034        struct vlv_wm_state *wm_state = &crtc->wm_state;
1035        int level;
1036
1037        for (level = 0; level < wm_state->num_levels; level++) {
1038                struct drm_device *dev = crtc->base.dev;
1039                const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040                struct intel_plane *plane;
1041
1042                wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043                wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045                for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046                        switch (plane->base.type) {
1047                                int sprite;
1048                        case DRM_PLANE_TYPE_CURSOR:
1049                                wm_state->wm[level].cursor = plane->wm.fifo_size -
1050                                        wm_state->wm[level].cursor;
1051                                break;
1052                        case DRM_PLANE_TYPE_PRIMARY:
1053                                wm_state->wm[level].primary = plane->wm.fifo_size -
1054                                        wm_state->wm[level].primary;
1055                                break;
1056                        case DRM_PLANE_TYPE_OVERLAY:
1057                                sprite = plane->plane;
1058                                wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059                                        wm_state->wm[level].sprite[sprite];
1060                                break;
1061                        }
1062                }
1063        }
1064}
1065
1066static void vlv_compute_wm(struct intel_crtc *crtc)
1067{
1068        struct drm_device *dev = crtc->base.dev;
1069        struct vlv_wm_state *wm_state = &crtc->wm_state;
1070        struct intel_plane *plane;
1071        int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072        int level;
1073
1074        memset(wm_state, 0, sizeof(*wm_state));
1075
1076        wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077        wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1078
1079        wm_state->num_active_planes = 0;
1080
1081        vlv_compute_fifo(crtc);
1082
1083        if (wm_state->num_active_planes != 1)
1084                wm_state->cxsr = false;
1085
1086        if (wm_state->cxsr) {
1087                for (level = 0; level < wm_state->num_levels; level++) {
1088                        wm_state->sr[level].plane = sr_fifo_size;
1089                        wm_state->sr[level].cursor = 63;
1090                }
1091        }
1092
1093        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094                struct intel_plane_state *state =
1095                        to_intel_plane_state(plane->base.state);
1096
1097                if (!state->visible)
1098                        continue;
1099
1100                /* normal watermarks */
1101                for (level = 0; level < wm_state->num_levels; level++) {
1102                        int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103                        int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105                        /* hack */
1106                        if (WARN_ON(level == 0 && wm > max_wm))
1107                                wm = max_wm;
1108
1109                        if (wm > plane->wm.fifo_size)
1110                                break;
1111
1112                        switch (plane->base.type) {
1113                                int sprite;
1114                        case DRM_PLANE_TYPE_CURSOR:
1115                                wm_state->wm[level].cursor = wm;
1116                                break;
1117                        case DRM_PLANE_TYPE_PRIMARY:
1118                                wm_state->wm[level].primary = wm;
1119                                break;
1120                        case DRM_PLANE_TYPE_OVERLAY:
1121                                sprite = plane->plane;
1122                                wm_state->wm[level].sprite[sprite] = wm;
1123                                break;
1124                        }
1125                }
1126
1127                wm_state->num_levels = level;
1128
1129                if (!wm_state->cxsr)
1130                        continue;
1131
1132                /* maxfifo watermarks */
1133                switch (plane->base.type) {
1134                        int sprite, level;
1135                case DRM_PLANE_TYPE_CURSOR:
1136                        for (level = 0; level < wm_state->num_levels; level++)
1137                                wm_state->sr[level].cursor =
1138                                        wm_state->wm[level].cursor;
1139                        break;
1140                case DRM_PLANE_TYPE_PRIMARY:
1141                        for (level = 0; level < wm_state->num_levels; level++)
1142                                wm_state->sr[level].plane =
1143                                        min(wm_state->sr[level].plane,
1144                                            wm_state->wm[level].primary);
1145                        break;
1146                case DRM_PLANE_TYPE_OVERLAY:
1147                        sprite = plane->plane;
1148                        for (level = 0; level < wm_state->num_levels; level++)
1149                                wm_state->sr[level].plane =
1150                                        min(wm_state->sr[level].plane,
1151                                            wm_state->wm[level].sprite[sprite]);
1152                        break;
1153                }
1154        }
1155
1156        /* clear any (partially) filled invalid levels */
1157        for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158                memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159                memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160        }
1161
1162        vlv_invert_wms(crtc);
1163}
1164
1165#define VLV_FIFO(plane, value) \
1166        (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169{
1170        struct drm_device *dev = crtc->base.dev;
1171        struct drm_i915_private *dev_priv = to_i915(dev);
1172        struct intel_plane *plane;
1173        int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176                if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177                        WARN_ON(plane->wm.fifo_size != 63);
1178                        continue;
1179                }
1180
1181                if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182                        sprite0_start = plane->wm.fifo_size;
1183                else if (plane->plane == 0)
1184                        sprite1_start = sprite0_start + plane->wm.fifo_size;
1185                else
1186                        fifo_size = sprite1_start + plane->wm.fifo_size;
1187        }
1188
1189        WARN_ON(fifo_size != 512 - 1);
1190
1191        DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192                      pipe_name(crtc->pipe), sprite0_start,
1193                      sprite1_start, fifo_size);
1194
1195        switch (crtc->pipe) {
1196                uint32_t dsparb, dsparb2, dsparb3;
1197        case PIPE_A:
1198                dsparb = I915_READ(DSPARB);
1199                dsparb2 = I915_READ(DSPARB2);
1200
1201                dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202                            VLV_FIFO(SPRITEB, 0xff));
1203                dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204                           VLV_FIFO(SPRITEB, sprite1_start));
1205
1206                dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207                             VLV_FIFO(SPRITEB_HI, 0x1));
1208                dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209                           VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211                I915_WRITE(DSPARB, dsparb);
1212                I915_WRITE(DSPARB2, dsparb2);
1213                break;
1214        case PIPE_B:
1215                dsparb = I915_READ(DSPARB);
1216                dsparb2 = I915_READ(DSPARB2);
1217
1218                dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219                            VLV_FIFO(SPRITED, 0xff));
1220                dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221                           VLV_FIFO(SPRITED, sprite1_start));
1222
1223                dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224                             VLV_FIFO(SPRITED_HI, 0xff));
1225                dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226                           VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228                I915_WRITE(DSPARB, dsparb);
1229                I915_WRITE(DSPARB2, dsparb2);
1230                break;
1231        case PIPE_C:
1232                dsparb3 = I915_READ(DSPARB3);
1233                dsparb2 = I915_READ(DSPARB2);
1234
1235                dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236                             VLV_FIFO(SPRITEF, 0xff));
1237                dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238                            VLV_FIFO(SPRITEF, sprite1_start));
1239
1240                dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241                             VLV_FIFO(SPRITEF_HI, 0xff));
1242                dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243                           VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245                I915_WRITE(DSPARB3, dsparb3);
1246                I915_WRITE(DSPARB2, dsparb2);
1247                break;
1248        default:
1249                break;
1250        }
1251}
1252
1253#undef VLV_FIFO
1254
1255static void vlv_merge_wm(struct drm_device *dev,
1256                         struct vlv_wm_values *wm)
1257{
1258        struct intel_crtc *crtc;
1259        int num_active_crtcs = 0;
1260
1261        wm->level = to_i915(dev)->wm.max_level;
1262        wm->cxsr = true;
1263
1264        for_each_intel_crtc(dev, crtc) {
1265                const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267                if (!crtc->active)
1268                        continue;
1269
1270                if (!wm_state->cxsr)
1271                        wm->cxsr = false;
1272
1273                num_active_crtcs++;
1274                wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275        }
1276
1277        if (num_active_crtcs != 1)
1278                wm->cxsr = false;
1279
1280        if (num_active_crtcs > 1)
1281                wm->level = VLV_WM_LEVEL_PM2;
1282
1283        for_each_intel_crtc(dev, crtc) {
1284                struct vlv_wm_state *wm_state = &crtc->wm_state;
1285                enum pipe pipe = crtc->pipe;
1286
1287                if (!crtc->active)
1288                        continue;
1289
1290                wm->pipe[pipe] = wm_state->wm[wm->level];
1291                if (wm->cxsr)
1292                        wm->sr = wm_state->sr[wm->level];
1293
1294                wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295                wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296                wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297                wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298        }
1299}
1300
1301static void vlv_update_wm(struct drm_crtc *crtc)
1302{
1303        struct drm_device *dev = crtc->dev;
1304        struct drm_i915_private *dev_priv = dev->dev_private;
1305        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306        enum pipe pipe = intel_crtc->pipe;
1307        struct vlv_wm_values wm = {};
1308
1309        vlv_compute_wm(intel_crtc);
1310        vlv_merge_wm(dev, &wm);
1311
1312        if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313                /* FIXME should be part of crtc atomic commit */
1314                vlv_pipe_set_fifo_size(intel_crtc);
1315                return;
1316        }
1317
1318        if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319            dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320                chv_set_memory_dvfs(dev_priv, false);
1321
1322        if (wm.level < VLV_WM_LEVEL_PM5 &&
1323            dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324                chv_set_memory_pm5(dev_priv, false);
1325
1326        if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327                intel_set_memory_cxsr(dev_priv, false);
1328
1329        /* FIXME should be part of crtc atomic commit */
1330        vlv_pipe_set_fifo_size(intel_crtc);
1331
1332        vlv_write_wm_values(intel_crtc, &wm);
1333
1334        DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335                      "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336                      pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337                      wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338                      wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
1340        if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341                intel_set_memory_cxsr(dev_priv, true);
1342
1343        if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344            dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345                chv_set_memory_pm5(dev_priv, true);
1346
1347        if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348            dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349                chv_set_memory_dvfs(dev_priv, true);
1350
1351        dev_priv->wm.vlv = wm;
1352}
1353
1354#define single_plane_enabled(mask) is_power_of_2(mask)
1355
1356static void g4x_update_wm(struct drm_crtc *crtc)
1357{
1358        struct drm_device *dev = crtc->dev;
1359        static const int sr_latency_ns = 12000;
1360        struct drm_i915_private *dev_priv = dev->dev_private;
1361        int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362        int plane_sr, cursor_sr;
1363        unsigned int enabled = 0;
1364        bool cxsr_enabled;
1365
1366        if (g4x_compute_wm0(dev, PIPE_A,
1367                            &g4x_wm_info, pessimal_latency_ns,
1368                            &g4x_cursor_wm_info, pessimal_latency_ns,
1369                            &planea_wm, &cursora_wm))
1370                enabled |= 1 << PIPE_A;
1371
1372        if (g4x_compute_wm0(dev, PIPE_B,
1373                            &g4x_wm_info, pessimal_latency_ns,
1374                            &g4x_cursor_wm_info, pessimal_latency_ns,
1375                            &planeb_wm, &cursorb_wm))
1376                enabled |= 1 << PIPE_B;
1377
1378        if (single_plane_enabled(enabled) &&
1379            g4x_compute_srwm(dev, ffs(enabled) - 1,
1380                             sr_latency_ns,
1381                             &g4x_wm_info,
1382                             &g4x_cursor_wm_info,
1383                             &plane_sr, &cursor_sr)) {
1384                cxsr_enabled = true;
1385        } else {
1386                cxsr_enabled = false;
1387                intel_set_memory_cxsr(dev_priv, false);
1388                plane_sr = cursor_sr = 0;
1389        }
1390
1391        DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392                      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393                      planea_wm, cursora_wm,
1394                      planeb_wm, cursorb_wm,
1395                      plane_sr, cursor_sr);
1396
1397        I915_WRITE(DSPFW1,
1398                   FW_WM(plane_sr, SR) |
1399                   FW_WM(cursorb_wm, CURSORB) |
1400                   FW_WM(planeb_wm, PLANEB) |
1401                   FW_WM(planea_wm, PLANEA));
1402        I915_WRITE(DSPFW2,
1403                   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404                   FW_WM(cursora_wm, CURSORA));
1405        /* HPLL off in SR has some issues on G4x... disable it */
1406        I915_WRITE(DSPFW3,
1407                   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408                   FW_WM(cursor_sr, CURSOR_SR));
1409
1410        if (cxsr_enabled)
1411                intel_set_memory_cxsr(dev_priv, true);
1412}
1413
1414static void i965_update_wm(struct drm_crtc *unused_crtc)
1415{
1416        struct drm_device *dev = unused_crtc->dev;
1417        struct drm_i915_private *dev_priv = dev->dev_private;
1418        struct drm_crtc *crtc;
1419        int srwm = 1;
1420        int cursor_sr = 16;
1421        bool cxsr_enabled;
1422
1423        /* Calc sr entries for one plane configs */
1424        crtc = single_enabled_crtc(dev);
1425        if (crtc) {
1426                /* self-refresh has much higher latency */
1427                static const int sr_latency_ns = 12000;
1428                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429                int clock = adjusted_mode->crtc_clock;
1430                int htotal = adjusted_mode->crtc_htotal;
1431                int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432                int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1433                unsigned long line_time_us;
1434                int entries;
1435
1436                line_time_us = max(htotal * 1000 / clock, 1);
1437
1438                /* Use ns/us then divide to preserve precision */
1439                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440                        pixel_size * hdisplay;
1441                entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442                srwm = I965_FIFO_SIZE - entries;
1443                if (srwm < 0)
1444                        srwm = 1;
1445                srwm &= 0x1ff;
1446                DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447                              entries, srwm);
1448
1449                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                        pixel_size * crtc->cursor->state->crtc_w;
1451                entries = DIV_ROUND_UP(entries,
1452                                          i965_cursor_wm_info.cacheline_size);
1453                cursor_sr = i965_cursor_wm_info.fifo_size -
1454                        (entries + i965_cursor_wm_info.guard_size);
1455
1456                if (cursor_sr > i965_cursor_wm_info.max_wm)
1457                        cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459                DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460                              "cursor %d\n", srwm, cursor_sr);
1461
1462                cxsr_enabled = true;
1463        } else {
1464                cxsr_enabled = false;
1465                /* Turn off self refresh if both pipes are enabled */
1466                intel_set_memory_cxsr(dev_priv, false);
1467        }
1468
1469        DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470                      srwm);
1471
1472        /* 965 has limitations... */
1473        I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474                   FW_WM(8, CURSORB) |
1475                   FW_WM(8, PLANEB) |
1476                   FW_WM(8, PLANEA));
1477        I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478                   FW_WM(8, PLANEC_OLD));
1479        /* update cursor SR watermark */
1480        I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1481
1482        if (cxsr_enabled)
1483                intel_set_memory_cxsr(dev_priv, true);
1484}
1485
1486#undef FW_WM
1487
1488static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1489{
1490        struct drm_device *dev = unused_crtc->dev;
1491        struct drm_i915_private *dev_priv = dev->dev_private;
1492        const struct intel_watermark_params *wm_info;
1493        uint32_t fwater_lo;
1494        uint32_t fwater_hi;
1495        int cwm, srwm = 1;
1496        int fifo_size;
1497        int planea_wm, planeb_wm;
1498        struct drm_crtc *crtc, *enabled = NULL;
1499
1500        if (IS_I945GM(dev))
1501                wm_info = &i945_wm_info;
1502        else if (!IS_GEN2(dev))
1503                wm_info = &i915_wm_info;
1504        else
1505                wm_info = &i830_a_wm_info;
1506
1507        fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508        crtc = intel_get_crtc_for_plane(dev, 0);
1509        if (intel_crtc_active(crtc)) {
1510                const struct drm_display_mode *adjusted_mode;
1511                int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1512                if (IS_GEN2(dev))
1513                        cpp = 4;
1514
1515                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516                planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517                                               wm_info, fifo_size, cpp,
1518                                               pessimal_latency_ns);
1519                enabled = crtc;
1520        } else {
1521                planea_wm = fifo_size - wm_info->guard_size;
1522                if (planea_wm > (long)wm_info->max_wm)
1523                        planea_wm = wm_info->max_wm;
1524        }
1525
1526        if (IS_GEN2(dev))
1527                wm_info = &i830_bc_wm_info;
1528
1529        fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530        crtc = intel_get_crtc_for_plane(dev, 1);
1531        if (intel_crtc_active(crtc)) {
1532                const struct drm_display_mode *adjusted_mode;
1533                int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1534                if (IS_GEN2(dev))
1535                        cpp = 4;
1536
1537                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538                planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539                                               wm_info, fifo_size, cpp,
1540                                               pessimal_latency_ns);
1541                if (enabled == NULL)
1542                        enabled = crtc;
1543                else
1544                        enabled = NULL;
1545        } else {
1546                planeb_wm = fifo_size - wm_info->guard_size;
1547                if (planeb_wm > (long)wm_info->max_wm)
1548                        planeb_wm = wm_info->max_wm;
1549        }
1550
1551        DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
1553        if (IS_I915GM(dev) && enabled) {
1554                struct drm_i915_gem_object *obj;
1555
1556                obj = intel_fb_obj(enabled->primary->state->fb);
1557
1558                /* self-refresh seems busted with untiled */
1559                if (obj->tiling_mode == I915_TILING_NONE)
1560                        enabled = NULL;
1561        }
1562
1563        /*
1564         * Overlay gets an aggressive default since video jitter is bad.
1565         */
1566        cwm = 2;
1567
1568        /* Play safe and disable self-refresh before adjusting watermarks. */
1569        intel_set_memory_cxsr(dev_priv, false);
1570
1571        /* Calc sr entries for one plane configs */
1572        if (HAS_FW_BLC(dev) && enabled) {
1573                /* self-refresh has much higher latency */
1574                static const int sr_latency_ns = 6000;
1575                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576                int clock = adjusted_mode->crtc_clock;
1577                int htotal = adjusted_mode->crtc_htotal;
1578                int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579                int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1580                unsigned long line_time_us;
1581                int entries;
1582
1583                line_time_us = max(htotal * 1000 / clock, 1);
1584
1585                /* Use ns/us then divide to preserve precision */
1586                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587                        pixel_size * hdisplay;
1588                entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589                DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590                srwm = wm_info->fifo_size - entries;
1591                if (srwm < 0)
1592                        srwm = 1;
1593
1594                if (IS_I945G(dev) || IS_I945GM(dev))
1595                        I915_WRITE(FW_BLC_SELF,
1596                                   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597                else if (IS_I915GM(dev))
1598                        I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599        }
1600
1601        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602                      planea_wm, planeb_wm, cwm, srwm);
1603
1604        fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605        fwater_hi = (cwm & 0x1f);
1606
1607        /* Set request length to 8 cachelines per fetch */
1608        fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609        fwater_hi = fwater_hi | (1 << 8);
1610
1611        I915_WRITE(FW_BLC, fwater_lo);
1612        I915_WRITE(FW_BLC2, fwater_hi);
1613
1614        if (enabled)
1615                intel_set_memory_cxsr(dev_priv, true);
1616}
1617
1618static void i845_update_wm(struct drm_crtc *unused_crtc)
1619{
1620        struct drm_device *dev = unused_crtc->dev;
1621        struct drm_i915_private *dev_priv = dev->dev_private;
1622        struct drm_crtc *crtc;
1623        const struct drm_display_mode *adjusted_mode;
1624        uint32_t fwater_lo;
1625        int planea_wm;
1626
1627        crtc = single_enabled_crtc(dev);
1628        if (crtc == NULL)
1629                return;
1630
1631        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632        planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1633                                       &i845_wm_info,
1634                                       dev_priv->display.get_fifo_size(dev, 0),
1635                                       4, pessimal_latency_ns);
1636        fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637        fwater_lo |= (3<<8) | planea_wm;
1638
1639        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641        I915_WRITE(FW_BLC, fwater_lo);
1642}
1643
1644uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1645{
1646        uint32_t pixel_rate;
1647
1648        pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1649
1650        /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651         * adjust the pixel_rate here. */
1652
1653        if (pipe_config->pch_pfit.enabled) {
1654                uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655                uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657                pipe_w = pipe_config->pipe_src_w;
1658                pipe_h = pipe_config->pipe_src_h;
1659
1660                pfit_w = (pfit_size >> 16) & 0xFFFF;
1661                pfit_h = pfit_size & 0xFFFF;
1662                if (pipe_w < pfit_w)
1663                        pipe_w = pfit_w;
1664                if (pipe_h < pfit_h)
1665                        pipe_h = pfit_h;
1666
1667                pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668                                     pfit_w * pfit_h);
1669        }
1670
1671        return pixel_rate;
1672}
1673
1674/* latency must be in 0.1us units. */
1675static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1676                               uint32_t latency)
1677{
1678        uint64_t ret;
1679
1680        if (WARN(latency == 0, "Latency value missing\n"))
1681                return UINT_MAX;
1682
1683        ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684        ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686        return ret;
1687}
1688
1689/* latency must be in 0.1us units. */
1690static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1691                               uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692                               uint32_t latency)
1693{
1694        uint32_t ret;
1695
1696        if (WARN(latency == 0, "Latency value missing\n"))
1697                return UINT_MAX;
1698
1699        ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700        ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701        ret = DIV_ROUND_UP(ret, 64) + 2;
1702        return ret;
1703}
1704
1705static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1706                           uint8_t bytes_per_pixel)
1707{
1708        return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709}
1710
1711struct skl_pipe_wm_parameters {
1712        bool active;
1713        uint32_t pipe_htotal;
1714        uint32_t pixel_rate; /* in KHz */
1715        struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1716};
1717
1718struct ilk_wm_maximums {
1719        uint16_t pri;
1720        uint16_t spr;
1721        uint16_t cur;
1722        uint16_t fbc;
1723};
1724
1725/* used in computing the new watermarks state */
1726struct intel_wm_config {
1727        unsigned int num_pipes_active;
1728        bool sprites_enabled;
1729        bool sprites_scaled;
1730};
1731
1732/*
1733 * For both WM_PIPE and WM_LP.
1734 * mem_value must be in 0.1us units.
1735 */
1736static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1737                                   const struct intel_plane_state *pstate,
1738                                   uint32_t mem_value,
1739                                   bool is_lp)
1740{
1741        int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1742        uint32_t method1, method2;
1743
1744        if (!cstate->base.active || !pstate->visible)
1745                return 0;
1746
1747        method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1748
1749        if (!is_lp)
1750                return method1;
1751
1752        method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1753                                 cstate->base.adjusted_mode.crtc_htotal,
1754                                 drm_rect_width(&pstate->dst),
1755                                 bpp,
1756                                 mem_value);
1757
1758        return min(method1, method2);
1759}
1760
1761/*
1762 * For both WM_PIPE and WM_LP.
1763 * mem_value must be in 0.1us units.
1764 */
1765static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1766                                   const struct intel_plane_state *pstate,
1767                                   uint32_t mem_value)
1768{
1769        int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1770        uint32_t method1, method2;
1771
1772        if (!cstate->base.active || !pstate->visible)
1773                return 0;
1774
1775        method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1776        method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1777                                 cstate->base.adjusted_mode.crtc_htotal,
1778                                 drm_rect_width(&pstate->dst),
1779                                 bpp,
1780                                 mem_value);
1781        return min(method1, method2);
1782}
1783
1784/*
1785 * For both WM_PIPE and WM_LP.
1786 * mem_value must be in 0.1us units.
1787 */
1788static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1789                                   const struct intel_plane_state *pstate,
1790                                   uint32_t mem_value)
1791{
1792        /*
1793         * We treat the cursor plane as always-on for the purposes of watermark
1794         * calculation.  Until we have two-stage watermark programming merged,
1795         * this is necessary to avoid flickering.
1796         */
1797        int cpp = 4;
1798        int width = pstate->visible ? pstate->base.crtc_w : 64;
1799
1800        if (!cstate->base.active)
1801                return 0;
1802
1803        return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1804                              cstate->base.adjusted_mode.crtc_htotal,
1805                              width, cpp, mem_value);
1806}
1807
1808/* Only for WM_LP. */
1809static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1810                                   const struct intel_plane_state *pstate,
1811                                   uint32_t pri_val)
1812{
1813        int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1814
1815        if (!cstate->base.active || !pstate->visible)
1816                return 0;
1817
1818        return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1819}
1820
1821static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1822{
1823        if (INTEL_INFO(dev)->gen >= 8)
1824                return 3072;
1825        else if (INTEL_INFO(dev)->gen >= 7)
1826                return 768;
1827        else
1828                return 512;
1829}
1830
1831static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1832                                         int level, bool is_sprite)
1833{
1834        if (INTEL_INFO(dev)->gen >= 8)
1835                /* BDW primary/sprite plane watermarks */
1836                return level == 0 ? 255 : 2047;
1837        else if (INTEL_INFO(dev)->gen >= 7)
1838                /* IVB/HSW primary/sprite plane watermarks */
1839                return level == 0 ? 127 : 1023;
1840        else if (!is_sprite)
1841                /* ILK/SNB primary plane watermarks */
1842                return level == 0 ? 127 : 511;
1843        else
1844                /* ILK/SNB sprite plane watermarks */
1845                return level == 0 ? 63 : 255;
1846}
1847
1848static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1849                                          int level)
1850{
1851        if (INTEL_INFO(dev)->gen >= 7)
1852                return level == 0 ? 63 : 255;
1853        else
1854                return level == 0 ? 31 : 63;
1855}
1856
1857static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1858{
1859        if (INTEL_INFO(dev)->gen >= 8)
1860                return 31;
1861        else
1862                return 15;
1863}
1864
1865/* Calculate the maximum primary/sprite plane watermark */
1866static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1867                                     int level,
1868                                     const struct intel_wm_config *config,
1869                                     enum intel_ddb_partitioning ddb_partitioning,
1870                                     bool is_sprite)
1871{
1872        unsigned int fifo_size = ilk_display_fifo_size(dev);
1873
1874        /* if sprites aren't enabled, sprites get nothing */
1875        if (is_sprite && !config->sprites_enabled)
1876                return 0;
1877
1878        /* HSW allows LP1+ watermarks even with multiple pipes */
1879        if (level == 0 || config->num_pipes_active > 1) {
1880                fifo_size /= INTEL_INFO(dev)->num_pipes;
1881
1882                /*
1883                 * For some reason the non self refresh
1884                 * FIFO size is only half of the self
1885                 * refresh FIFO size on ILK/SNB.
1886                 */
1887                if (INTEL_INFO(dev)->gen <= 6)
1888                        fifo_size /= 2;
1889        }
1890
1891        if (config->sprites_enabled) {
1892                /* level 0 is always calculated with 1:1 split */
1893                if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1894                        if (is_sprite)
1895                                fifo_size *= 5;
1896                        fifo_size /= 6;
1897                } else {
1898                        fifo_size /= 2;
1899                }
1900        }
1901
1902        /* clamp to max that the registers can hold */
1903        return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1904}
1905
1906/* Calculate the maximum cursor plane watermark */
1907static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1908                                      int level,
1909                                      const struct intel_wm_config *config)
1910{
1911        /* HSW LP1+ watermarks w/ multiple pipes */
1912        if (level > 0 && config->num_pipes_active > 1)
1913                return 64;
1914
1915        /* otherwise just report max that registers can hold */
1916        return ilk_cursor_wm_reg_max(dev, level);
1917}
1918
1919static void ilk_compute_wm_maximums(const struct drm_device *dev,
1920                                    int level,
1921                                    const struct intel_wm_config *config,
1922                                    enum intel_ddb_partitioning ddb_partitioning,
1923                                    struct ilk_wm_maximums *max)
1924{
1925        max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1926        max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1927        max->cur = ilk_cursor_wm_max(dev, level, config);
1928        max->fbc = ilk_fbc_wm_reg_max(dev);
1929}
1930
1931static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1932                                        int level,
1933                                        struct ilk_wm_maximums *max)
1934{
1935        max->pri = ilk_plane_wm_reg_max(dev, level, false);
1936        max->spr = ilk_plane_wm_reg_max(dev, level, true);
1937        max->cur = ilk_cursor_wm_reg_max(dev, level);
1938        max->fbc = ilk_fbc_wm_reg_max(dev);
1939}
1940
1941static bool ilk_validate_wm_level(int level,
1942                                  const struct ilk_wm_maximums *max,
1943                                  struct intel_wm_level *result)
1944{
1945        bool ret;
1946
1947        /* already determined to be invalid? */
1948        if (!result->enable)
1949                return false;
1950
1951        result->enable = result->pri_val <= max->pri &&
1952                         result->spr_val <= max->spr &&
1953                         result->cur_val <= max->cur;
1954
1955        ret = result->enable;
1956
1957        /*
1958         * HACK until we can pre-compute everything,
1959         * and thus fail gracefully if LP0 watermarks
1960         * are exceeded...
1961         */
1962        if (level == 0 && !result->enable) {
1963                if (result->pri_val > max->pri)
1964                        DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1965                                      level, result->pri_val, max->pri);
1966                if (result->spr_val > max->spr)
1967                        DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1968                                      level, result->spr_val, max->spr);
1969                if (result->cur_val > max->cur)
1970                        DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1971                                      level, result->cur_val, max->cur);
1972
1973                result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1974                result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1975                result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1976                result->enable = true;
1977        }
1978
1979        return ret;
1980}
1981
1982static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1983                                 const struct intel_crtc *intel_crtc,
1984                                 int level,
1985                                 struct intel_crtc_state *cstate,
1986                                 struct intel_wm_level *result)
1987{
1988        struct intel_plane *intel_plane;
1989        uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1990        uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1991        uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1992
1993        /* WM1+ latency values stored in 0.5us units */
1994        if (level > 0) {
1995                pri_latency *= 5;
1996                spr_latency *= 5;
1997                cur_latency *= 5;
1998        }
1999
2000        for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
2001                struct intel_plane_state *pstate =
2002                        to_intel_plane_state(intel_plane->base.state);
2003
2004                switch (intel_plane->base.type) {
2005                case DRM_PLANE_TYPE_PRIMARY:
2006                        result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2007                                                             pri_latency,
2008                                                             level);
2009                        result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2010                                                             result->pri_val);
2011                        break;
2012                case DRM_PLANE_TYPE_OVERLAY:
2013                        result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2014                                                             spr_latency);
2015                        break;
2016                case DRM_PLANE_TYPE_CURSOR:
2017                        result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2018                                                             cur_latency);
2019                        break;
2020                }
2021        }
2022
2023        result->enable = true;
2024}
2025
2026static uint32_t
2027hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2028{
2029        struct drm_i915_private *dev_priv = dev->dev_private;
2030        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031        const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2032        u32 linetime, ips_linetime;
2033
2034        if (!intel_crtc->active)
2035                return 0;
2036
2037        /* The WM are computed with base on how long it takes to fill a single
2038         * row at the given clock rate, multiplied by 8.
2039         * */
2040        linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041                                     adjusted_mode->crtc_clock);
2042        ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2043                                         dev_priv->cdclk_freq);
2044
2045        return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046               PIPE_WM_LINETIME_TIME(linetime);
2047}
2048
2049static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2050{
2051        struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053        if (IS_GEN9(dev)) {
2054                uint32_t val;
2055                int ret, i;
2056                int level, max_level = ilk_wm_max_level(dev);
2057
2058                /* read the first set of memory latencies[0:3] */
2059                val = 0; /* data0 to be programmed to 0 for first set */
2060                mutex_lock(&dev_priv->rps.hw_lock);
2061                ret = sandybridge_pcode_read(dev_priv,
2062                                             GEN9_PCODE_READ_MEM_LATENCY,
2063                                             &val);
2064                mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066                if (ret) {
2067                        DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068                        return;
2069                }
2070
2071                wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072                wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073                                GEN9_MEM_LATENCY_LEVEL_MASK;
2074                wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075                                GEN9_MEM_LATENCY_LEVEL_MASK;
2076                wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077                                GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079                /* read the second set of memory latencies[4:7] */
2080                val = 1; /* data0 to be programmed to 1 for second set */
2081                mutex_lock(&dev_priv->rps.hw_lock);
2082                ret = sandybridge_pcode_read(dev_priv,
2083                                             GEN9_PCODE_READ_MEM_LATENCY,
2084                                             &val);
2085                mutex_unlock(&dev_priv->rps.hw_lock);
2086                if (ret) {
2087                        DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088                        return;
2089                }
2090
2091                wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092                wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093                                GEN9_MEM_LATENCY_LEVEL_MASK;
2094                wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095                                GEN9_MEM_LATENCY_LEVEL_MASK;
2096                wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097                                GEN9_MEM_LATENCY_LEVEL_MASK;
2098
2099                /*
2100                 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2101                 * need to be disabled. We make sure to sanitize the values out
2102                 * of the punit to satisfy this requirement.
2103                 */
2104                for (level = 1; level <= max_level; level++) {
2105                        if (wm[level] == 0) {
2106                                for (i = level + 1; i <= max_level; i++)
2107                                        wm[i] = 0;
2108                                break;
2109                        }
2110                }
2111
2112                /*
2113                 * WaWmMemoryReadLatency:skl
2114                 *
2115                 * punit doesn't take into account the read latency so we need
2116                 * to add 2us to the various latency levels we retrieve from the
2117                 * punit when level 0 response data us 0us.
2118                 */
2119                if (wm[0] == 0) {
2120                        wm[0] += 2;
2121                        for (level = 1; level <= max_level; level++) {
2122                                if (wm[level] == 0)
2123                                        break;
2124                                wm[level] += 2;
2125                        }
2126                }
2127
2128        } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2129                uint64_t sskpd = I915_READ64(MCH_SSKPD);
2130
2131                wm[0] = (sskpd >> 56) & 0xFF;
2132                if (wm[0] == 0)
2133                        wm[0] = sskpd & 0xF;
2134                wm[1] = (sskpd >> 4) & 0xFF;
2135                wm[2] = (sskpd >> 12) & 0xFF;
2136                wm[3] = (sskpd >> 20) & 0x1FF;
2137                wm[4] = (sskpd >> 32) & 0x1FF;
2138        } else if (INTEL_INFO(dev)->gen >= 6) {
2139                uint32_t sskpd = I915_READ(MCH_SSKPD);
2140
2141                wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2142                wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2143                wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2144                wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2145        } else if (INTEL_INFO(dev)->gen >= 5) {
2146                uint32_t mltr = I915_READ(MLTR_ILK);
2147
2148                /* ILK primary LP0 latency is 700 ns */
2149                wm[0] = 7;
2150                wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2151                wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2152        }
2153}
2154
2155static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2156{
2157        /* ILK sprite LP0 latency is 1300 ns */
2158        if (INTEL_INFO(dev)->gen == 5)
2159                wm[0] = 13;
2160}
2161
2162static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2163{
2164        /* ILK cursor LP0 latency is 1300 ns */
2165        if (INTEL_INFO(dev)->gen == 5)
2166                wm[0] = 13;
2167
2168        /* WaDoubleCursorLP3Latency:ivb */
2169        if (IS_IVYBRIDGE(dev))
2170                wm[3] *= 2;
2171}
2172
2173int ilk_wm_max_level(const struct drm_device *dev)
2174{
2175        /* how many WM levels are we expecting */
2176        if (INTEL_INFO(dev)->gen >= 9)
2177                return 7;
2178        else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2179                return 4;
2180        else if (INTEL_INFO(dev)->gen >= 6)
2181                return 3;
2182        else
2183                return 2;
2184}
2185
2186static void intel_print_wm_latency(struct drm_device *dev,
2187                                   const char *name,
2188                                   const uint16_t wm[8])
2189{
2190        int level, max_level = ilk_wm_max_level(dev);
2191
2192        for (level = 0; level <= max_level; level++) {
2193                unsigned int latency = wm[level];
2194
2195                if (latency == 0) {
2196                        DRM_ERROR("%s WM%d latency not provided\n",
2197                                  name, level);
2198                        continue;
2199                }
2200
2201                /*
2202                 * - latencies are in us on gen9.
2203                 * - before then, WM1+ latency values are in 0.5us units
2204                 */
2205                if (IS_GEN9(dev))
2206                        latency *= 10;
2207                else if (level > 0)
2208                        latency *= 5;
2209
2210                DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2211                              name, level, wm[level],
2212                              latency / 10, latency % 10);
2213        }
2214}
2215
2216static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2217                                    uint16_t wm[5], uint16_t min)
2218{
2219        int level, max_level = ilk_wm_max_level(dev_priv->dev);
2220
2221        if (wm[0] >= min)
2222                return false;
2223
2224        wm[0] = max(wm[0], min);
2225        for (level = 1; level <= max_level; level++)
2226                wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2227
2228        return true;
2229}
2230
2231static void snb_wm_latency_quirk(struct drm_device *dev)
2232{
2233        struct drm_i915_private *dev_priv = dev->dev_private;
2234        bool changed;
2235
2236        /*
2237         * The BIOS provided WM memory latency values are often
2238         * inadequate for high resolution displays. Adjust them.
2239         */
2240        changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2241                ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2242                ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2243
2244        if (!changed)
2245                return;
2246
2247        DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2248        intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2249        intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2250        intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2251}
2252
2253static void ilk_setup_wm_latency(struct drm_device *dev)
2254{
2255        struct drm_i915_private *dev_priv = dev->dev_private;
2256
2257        intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2258
2259        memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2260               sizeof(dev_priv->wm.pri_latency));
2261        memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2262               sizeof(dev_priv->wm.pri_latency));
2263
2264        intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2265        intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2266
2267        intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2268        intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2269        intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2270
2271        if (IS_GEN6(dev))
2272                snb_wm_latency_quirk(dev);
2273}
2274
2275static void skl_setup_wm_latency(struct drm_device *dev)
2276{
2277        struct drm_i915_private *dev_priv = dev->dev_private;
2278
2279        intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2280        intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2281}
2282
2283static void ilk_compute_wm_config(struct drm_device *dev,
2284                                  struct intel_wm_config *config)
2285{
2286        struct intel_crtc *intel_crtc;
2287
2288        /* Compute the currently _active_ config */
2289        for_each_intel_crtc(dev, intel_crtc) {
2290                const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2291
2292                if (!wm->pipe_enabled)
2293                        continue;
2294
2295                config->sprites_enabled |= wm->sprites_enabled;
2296                config->sprites_scaled |= wm->sprites_scaled;
2297                config->num_pipes_active++;
2298        }
2299}
2300
2301/* Compute new watermarks for the pipe */
2302static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2303                                  struct intel_pipe_wm *pipe_wm)
2304{
2305        struct drm_crtc *crtc = cstate->base.crtc;
2306        struct drm_device *dev = crtc->dev;
2307        const struct drm_i915_private *dev_priv = dev->dev_private;
2308        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309        struct intel_plane *intel_plane;
2310        struct intel_plane_state *sprstate = NULL;
2311        int level, max_level = ilk_wm_max_level(dev);
2312        /* LP0 watermark maximums depend on this pipe alone */
2313        struct intel_wm_config config = {
2314                .num_pipes_active = 1,
2315        };
2316        struct ilk_wm_maximums max;
2317
2318        for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2319                if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2320                        sprstate = to_intel_plane_state(intel_plane->base.state);
2321                        break;
2322                }
2323        }
2324
2325        config.sprites_enabled = sprstate->visible;
2326        config.sprites_scaled = sprstate->visible &&
2327                (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2328                drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2329
2330        pipe_wm->pipe_enabled = cstate->base.active;
2331        pipe_wm->sprites_enabled = sprstate->visible;
2332        pipe_wm->sprites_scaled = config.sprites_scaled;
2333
2334        /* ILK/SNB: LP2+ watermarks only w/o sprites */
2335        if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2336                max_level = 1;
2337
2338        /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2339        if (config.sprites_scaled)
2340                max_level = 0;
2341
2342        ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2343
2344        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2345                pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2346
2347        /* LP0 watermarks always use 1/2 DDB partitioning */
2348        ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2349
2350        /* At least LP0 must be valid */
2351        if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2352                return false;
2353
2354        ilk_compute_wm_reg_maximums(dev, 1, &max);
2355
2356        for (level = 1; level <= max_level; level++) {
2357                struct intel_wm_level wm = {};
2358
2359                ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2360
2361                /*
2362                 * Disable any watermark level that exceeds the
2363                 * register maximums since such watermarks are
2364                 * always invalid.
2365                 */
2366                if (!ilk_validate_wm_level(level, &max, &wm))
2367                        break;
2368
2369                pipe_wm->wm[level] = wm;
2370        }
2371
2372        return true;
2373}
2374
2375/*
2376 * Merge the watermarks from all active pipes for a specific level.
2377 */
2378static void ilk_merge_wm_level(struct drm_device *dev,
2379                               int level,
2380                               struct intel_wm_level *ret_wm)
2381{
2382        const struct intel_crtc *intel_crtc;
2383
2384        ret_wm->enable = true;
2385
2386        for_each_intel_crtc(dev, intel_crtc) {
2387                const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2388                const struct intel_wm_level *wm = &active->wm[level];
2389
2390                if (!active->pipe_enabled)
2391                        continue;
2392
2393                /*
2394                 * The watermark values may have been used in the past,
2395                 * so we must maintain them in the registers for some
2396                 * time even if the level is now disabled.
2397                 */
2398                if (!wm->enable)
2399                        ret_wm->enable = false;
2400
2401                ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2402                ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2403                ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2404                ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2405        }
2406}
2407
2408/*
2409 * Merge all low power watermarks for all active pipes.
2410 */
2411static void ilk_wm_merge(struct drm_device *dev,
2412                         const struct intel_wm_config *config,
2413                         const struct ilk_wm_maximums *max,
2414                         struct intel_pipe_wm *merged)
2415{
2416        struct drm_i915_private *dev_priv = dev->dev_private;
2417        int level, max_level = ilk_wm_max_level(dev);
2418        int last_enabled_level = max_level;
2419
2420        /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2421        if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2422            config->num_pipes_active > 1)
2423                return;
2424
2425        /* ILK: FBC WM must be disabled always */
2426        merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2427
2428        /* merge each WM1+ level */
2429        for (level = 1; level <= max_level; level++) {
2430                struct intel_wm_level *wm = &merged->wm[level];
2431
2432                ilk_merge_wm_level(dev, level, wm);
2433
2434                if (level > last_enabled_level)
2435                        wm->enable = false;
2436                else if (!ilk_validate_wm_level(level, max, wm))
2437                        /* make sure all following levels get disabled */
2438                        last_enabled_level = level - 1;
2439
2440                /*
2441                 * The spec says it is preferred to disable
2442                 * FBC WMs instead of disabling a WM level.
2443                 */
2444                if (wm->fbc_val > max->fbc) {
2445                        if (wm->enable)
2446                                merged->fbc_wm_enabled = false;
2447                        wm->fbc_val = 0;
2448                }
2449        }
2450
2451        /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2452        /*
2453         * FIXME this is racy. FBC might get enabled later.
2454         * What we should check here is whether FBC can be
2455         * enabled sometime later.
2456         */
2457        if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2458            intel_fbc_enabled(dev_priv)) {
2459                for (level = 2; level <= max_level; level++) {
2460                        struct intel_wm_level *wm = &merged->wm[level];
2461
2462                        wm->enable = false;
2463                }
2464        }
2465}
2466
2467static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2468{
2469        /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2470        return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2471}
2472
2473/* The value we need to program into the WM_LPx latency field */
2474static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2475{
2476        struct drm_i915_private *dev_priv = dev->dev_private;
2477
2478        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479                return 2 * level;
2480        else
2481                return dev_priv->wm.pri_latency[level];
2482}
2483
2484static void ilk_compute_wm_results(struct drm_device *dev,
2485                                   const struct intel_pipe_wm *merged,
2486                                   enum intel_ddb_partitioning partitioning,
2487                                   struct ilk_wm_values *results)
2488{
2489        struct intel_crtc *intel_crtc;
2490        int level, wm_lp;
2491
2492        results->enable_fbc_wm = merged->fbc_wm_enabled;
2493        results->partitioning = partitioning;
2494
2495        /* LP1+ register values */
2496        for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2497                const struct intel_wm_level *r;
2498
2499                level = ilk_wm_lp_to_level(wm_lp, merged);
2500
2501                r = &merged->wm[level];
2502
2503                /*
2504                 * Maintain the watermark values even if the level is
2505                 * disabled. Doing otherwise could cause underruns.
2506                 */
2507                results->wm_lp[wm_lp - 1] =
2508                        (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2509                        (r->pri_val << WM1_LP_SR_SHIFT) |
2510                        r->cur_val;
2511
2512                if (r->enable)
2513                        results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2514
2515                if (INTEL_INFO(dev)->gen >= 8)
2516                        results->wm_lp[wm_lp - 1] |=
2517                                r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2518                else
2519                        results->wm_lp[wm_lp - 1] |=
2520                                r->fbc_val << WM1_LP_FBC_SHIFT;
2521
2522                /*
2523                 * Always set WM1S_LP_EN when spr_val != 0, even if the
2524                 * level is disabled. Doing otherwise could cause underruns.
2525                 */
2526                if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2527                        WARN_ON(wm_lp != 1);
2528                        results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2529                } else
2530                        results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2531        }
2532
2533        /* LP0 register values */
2534        for_each_intel_crtc(dev, intel_crtc) {
2535                enum pipe pipe = intel_crtc->pipe;
2536                const struct intel_wm_level *r =
2537                        &intel_crtc->wm.active.wm[0];
2538
2539                if (WARN_ON(!r->enable))
2540                        continue;
2541
2542                results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2543
2544                results->wm_pipe[pipe] =
2545                        (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2546                        (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2547                        r->cur_val;
2548        }
2549}
2550
2551/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2552 * case both are at the same level. Prefer r1 in case they're the same. */
2553static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2554                                                  struct intel_pipe_wm *r1,
2555                                                  struct intel_pipe_wm *r2)
2556{
2557        int level, max_level = ilk_wm_max_level(dev);
2558        int level1 = 0, level2 = 0;
2559
2560        for (level = 1; level <= max_level; level++) {
2561                if (r1->wm[level].enable)
2562                        level1 = level;
2563                if (r2->wm[level].enable)
2564                        level2 = level;
2565        }
2566
2567        if (level1 == level2) {
2568                if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2569                        return r2;
2570                else
2571                        return r1;
2572        } else if (level1 > level2) {
2573                return r1;
2574        } else {
2575                return r2;
2576        }
2577}
2578
2579/* dirty bits used to track which watermarks need changes */
2580#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2581#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2582#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2583#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2584#define WM_DIRTY_FBC (1 << 24)
2585#define WM_DIRTY_DDB (1 << 25)
2586
2587static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2588                                         const struct ilk_wm_values *old,
2589                                         const struct ilk_wm_values *new)
2590{
2591        unsigned int dirty = 0;
2592        enum pipe pipe;
2593        int wm_lp;
2594
2595        for_each_pipe(dev_priv, pipe) {
2596                if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2597                        dirty |= WM_DIRTY_LINETIME(pipe);
2598                        /* Must disable LP1+ watermarks too */
2599                        dirty |= WM_DIRTY_LP_ALL;
2600                }
2601
2602                if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2603                        dirty |= WM_DIRTY_PIPE(pipe);
2604                        /* Must disable LP1+ watermarks too */
2605                        dirty |= WM_DIRTY_LP_ALL;
2606                }
2607        }
2608
2609        if (old->enable_fbc_wm != new->enable_fbc_wm) {
2610                dirty |= WM_DIRTY_FBC;
2611                /* Must disable LP1+ watermarks too */
2612                dirty |= WM_DIRTY_LP_ALL;
2613        }
2614
2615        if (old->partitioning != new->partitioning) {
2616                dirty |= WM_DIRTY_DDB;
2617                /* Must disable LP1+ watermarks too */
2618                dirty |= WM_DIRTY_LP_ALL;
2619        }
2620
2621        /* LP1+ watermarks already deemed dirty, no need to continue */
2622        if (dirty & WM_DIRTY_LP_ALL)
2623                return dirty;
2624
2625        /* Find the lowest numbered LP1+ watermark in need of an update... */
2626        for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2627                if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2628                    old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2629                        break;
2630        }
2631
2632        /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2633        for (; wm_lp <= 3; wm_lp++)
2634                dirty |= WM_DIRTY_LP(wm_lp);
2635
2636        return dirty;
2637}
2638
2639static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2640                               unsigned int dirty)
2641{
2642        struct ilk_wm_values *previous = &dev_priv->wm.hw;
2643        bool changed = false;
2644
2645        if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2646                previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2647                I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2648                changed = true;
2649        }
2650        if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2651                previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2652                I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2653                changed = true;
2654        }
2655        if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2656                previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2657                I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2658                changed = true;
2659        }
2660
2661        /*
2662         * Don't touch WM1S_LP_EN here.
2663         * Doing so could cause underruns.
2664         */
2665
2666        return changed;
2667}
2668
2669/*
2670 * The spec says we shouldn't write when we don't need, because every write
2671 * causes WMs to be re-evaluated, expending some power.
2672 */
2673static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2674                                struct ilk_wm_values *results)
2675{
2676        struct drm_device *dev = dev_priv->dev;
2677        struct ilk_wm_values *previous = &dev_priv->wm.hw;
2678        unsigned int dirty;
2679        uint32_t val;
2680
2681        dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2682        if (!dirty)
2683                return;
2684
2685        _ilk_disable_lp_wm(dev_priv, dirty);
2686
2687        if (dirty & WM_DIRTY_PIPE(PIPE_A))
2688                I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2689        if (dirty & WM_DIRTY_PIPE(PIPE_B))
2690                I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2691        if (dirty & WM_DIRTY_PIPE(PIPE_C))
2692                I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2693
2694        if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2695                I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2696        if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2697                I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2698        if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2699                I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2700
2701        if (dirty & WM_DIRTY_DDB) {
2702                if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2703                        val = I915_READ(WM_MISC);
2704                        if (results->partitioning == INTEL_DDB_PART_1_2)
2705                                val &= ~WM_MISC_DATA_PARTITION_5_6;
2706                        else
2707                                val |= WM_MISC_DATA_PARTITION_5_6;
2708                        I915_WRITE(WM_MISC, val);
2709                } else {
2710                        val = I915_READ(DISP_ARB_CTL2);
2711                        if (results->partitioning == INTEL_DDB_PART_1_2)
2712                                val &= ~DISP_DATA_PARTITION_5_6;
2713                        else
2714                                val |= DISP_DATA_PARTITION_5_6;
2715                        I915_WRITE(DISP_ARB_CTL2, val);
2716                }
2717        }
2718
2719        if (dirty & WM_DIRTY_FBC) {
2720                val = I915_READ(DISP_ARB_CTL);
2721                if (results->enable_fbc_wm)
2722                        val &= ~DISP_FBC_WM_DIS;
2723                else
2724                        val |= DISP_FBC_WM_DIS;
2725                I915_WRITE(DISP_ARB_CTL, val);
2726        }
2727
2728        if (dirty & WM_DIRTY_LP(1) &&
2729            previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2730                I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2731
2732        if (INTEL_INFO(dev)->gen >= 7) {
2733                if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2734                        I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2735                if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2736                        I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2737        }
2738
2739        if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2740                I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2741        if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2742                I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2743        if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2744                I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2745
2746        dev_priv->wm.hw = *results;
2747}
2748
2749static bool ilk_disable_lp_wm(struct drm_device *dev)
2750{
2751        struct drm_i915_private *dev_priv = dev->dev_private;
2752
2753        return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2754}
2755
2756/*
2757 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2758 * different active planes.
2759 */
2760
2761#define SKL_DDB_SIZE            896     /* in blocks */
2762#define BXT_DDB_SIZE            512
2763
2764static void
2765skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2766                                   struct drm_crtc *for_crtc,
2767                                   const struct intel_wm_config *config,
2768                                   const struct skl_pipe_wm_parameters *params,
2769                                   struct skl_ddb_entry *alloc /* out */)
2770{
2771        struct drm_crtc *crtc;
2772        unsigned int pipe_size, ddb_size;
2773        int nth_active_pipe;
2774
2775        if (!params->active) {
2776                alloc->start = 0;
2777                alloc->end = 0;
2778                return;
2779        }
2780
2781        if (IS_BROXTON(dev))
2782                ddb_size = BXT_DDB_SIZE;
2783        else
2784                ddb_size = SKL_DDB_SIZE;
2785
2786        ddb_size -= 4; /* 4 blocks for bypass path allocation */
2787
2788        nth_active_pipe = 0;
2789        for_each_crtc(dev, crtc) {
2790                if (!to_intel_crtc(crtc)->active)
2791                        continue;
2792
2793                if (crtc == for_crtc)
2794                        break;
2795
2796                nth_active_pipe++;
2797        }
2798
2799        pipe_size = ddb_size / config->num_pipes_active;
2800        alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2801        alloc->end = alloc->start + pipe_size;
2802}
2803
2804static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2805{
2806        if (config->num_pipes_active == 1)
2807                return 32;
2808
2809        return 8;
2810}
2811
2812static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2813{
2814        entry->start = reg & 0x3ff;
2815        entry->end = (reg >> 16) & 0x3ff;
2816        if (entry->end)
2817                entry->end += 1;
2818}
2819
2820void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2821                          struct skl_ddb_allocation *ddb /* out */)
2822{
2823        enum pipe pipe;
2824        int plane;
2825        u32 val;
2826
2827        memset(ddb, 0, sizeof(*ddb));
2828
2829        for_each_pipe(dev_priv, pipe) {
2830                if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2831                        continue;
2832
2833                for_each_plane(dev_priv, pipe, plane) {
2834                        val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2835                        skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2836                                                   val);
2837                }
2838
2839                val = I915_READ(CUR_BUF_CFG(pipe));
2840                skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2841                                           val);
2842        }
2843}
2844
2845static unsigned int
2846skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2847{
2848
2849        /* for planar format */
2850        if (p->y_bytes_per_pixel) {
2851                if (y)  /* y-plane data rate */
2852                        return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2853                else    /* uv-plane data rate */
2854                        return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2855        }
2856
2857        /* for packed formats */
2858        return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2859}
2860
2861/*
2862 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2863 * a 8192x4096@32bpp framebuffer:
2864 *   3 * 4096 * 8192  * 4 < 2^32
2865 */
2866static unsigned int
2867skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2868                                 const struct skl_pipe_wm_parameters *params)
2869{
2870        unsigned int total_data_rate = 0;
2871        int plane;
2872
2873        for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2874                const struct intel_plane_wm_parameters *p;
2875
2876                p = &params->plane[plane];
2877                if (!p->enabled)
2878                        continue;
2879
2880                total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2881                if (p->y_bytes_per_pixel) {
2882                        total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2883                }
2884        }
2885
2886        return total_data_rate;
2887}
2888
2889static void
2890skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2891                      const struct intel_wm_config *config,
2892                      const struct skl_pipe_wm_parameters *params,
2893                      struct skl_ddb_allocation *ddb /* out */)
2894{
2895        struct drm_device *dev = crtc->dev;
2896        struct drm_i915_private *dev_priv = dev->dev_private;
2897        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898        enum pipe pipe = intel_crtc->pipe;
2899        struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2900        uint16_t alloc_size, start, cursor_blocks;
2901        uint16_t minimum[I915_MAX_PLANES];
2902        uint16_t y_minimum[I915_MAX_PLANES];
2903        unsigned int total_data_rate;
2904        int plane;
2905
2906        skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2907        alloc_size = skl_ddb_entry_size(alloc);
2908        if (alloc_size == 0) {
2909                memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2910                memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2911                       sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2912                return;
2913        }
2914
2915        cursor_blocks = skl_cursor_allocation(config);
2916        ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2917        ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2918
2919        alloc_size -= cursor_blocks;
2920        alloc->end -= cursor_blocks;
2921
2922        /* 1. Allocate the mininum required blocks for each active plane */
2923        for_each_plane(dev_priv, pipe, plane) {
2924                const struct intel_plane_wm_parameters *p;
2925
2926                p = &params->plane[plane];
2927                if (!p->enabled)
2928                        continue;
2929
2930                minimum[plane] = 8;
2931                alloc_size -= minimum[plane];
2932                y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2933                alloc_size -= y_minimum[plane];
2934        }
2935
2936        /*
2937         * 2. Distribute the remaining space in proportion to the amount of
2938         * data each plane needs to fetch from memory.
2939         *
2940         * FIXME: we may not allocate every single block here.
2941         */
2942        total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2943
2944        start = alloc->start;
2945        for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2946                const struct intel_plane_wm_parameters *p;
2947                unsigned int data_rate, y_data_rate;
2948                uint16_t plane_blocks, y_plane_blocks = 0;
2949
2950                p = &params->plane[plane];
2951                if (!p->enabled)
2952                        continue;
2953
2954                data_rate = skl_plane_relative_data_rate(p, 0);
2955
2956                /*
2957                 * allocation for (packed formats) or (uv-plane part of planar format):
2958                 * promote the expression to 64 bits to avoid overflowing, the
2959                 * result is < available as data_rate / total_data_rate < 1
2960                 */
2961                plane_blocks = minimum[plane];
2962                plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2963                                        total_data_rate);
2964
2965                ddb->plane[pipe][plane].start = start;
2966                ddb->plane[pipe][plane].end = start + plane_blocks;
2967
2968                start += plane_blocks;
2969
2970                /*
2971                 * allocation for y_plane part of planar format:
2972                 */
2973                if (p->y_bytes_per_pixel) {
2974                        y_data_rate = skl_plane_relative_data_rate(p, 1);
2975                        y_plane_blocks = y_minimum[plane];
2976                        y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2977                                                total_data_rate);
2978
2979                        ddb->y_plane[pipe][plane].start = start;
2980                        ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2981
2982                        start += y_plane_blocks;
2983                }
2984
2985        }
2986
2987}
2988
2989static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2990{
2991        /* TODO: Take into account the scalers once we support them */
2992        return config->base.adjusted_mode.crtc_clock;
2993}
2994
2995/*
2996 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2997 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2998 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2999 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3000*/
3001static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3002                               uint32_t latency)
3003{
3004        uint32_t wm_intermediate_val, ret;
3005
3006        if (latency == 0)
3007                return UINT_MAX;
3008
3009        wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3010        ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3011
3012        return ret;
3013}
3014
3015static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3016                               uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3017                               uint64_t tiling, uint32_t latency)
3018{
3019        uint32_t ret;
3020        uint32_t plane_bytes_per_line, plane_blocks_per_line;
3021        uint32_t wm_intermediate_val;
3022
3023        if (latency == 0)
3024                return UINT_MAX;
3025
3026        plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3027
3028        if (tiling == I915_FORMAT_MOD_Y_TILED ||
3029            tiling == I915_FORMAT_MOD_Yf_TILED) {
3030                plane_bytes_per_line *= 4;
3031                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3032                plane_blocks_per_line /= 4;
3033        } else {
3034                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3035        }
3036
3037        wm_intermediate_val = latency * pixel_rate;
3038        ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3039                                plane_blocks_per_line;
3040
3041        return ret;
3042}
3043
3044static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3045                                       const struct intel_crtc *intel_crtc)
3046{
3047        struct drm_device *dev = intel_crtc->base.dev;
3048        struct drm_i915_private *dev_priv = dev->dev_private;
3049        const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3050        enum pipe pipe = intel_crtc->pipe;
3051
3052        if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3053                   sizeof(new_ddb->plane[pipe])))
3054                return true;
3055
3056        if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3057                    sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3058                return true;
3059
3060        return false;
3061}
3062
3063static void skl_compute_wm_global_parameters(struct drm_device *dev,
3064                                             struct intel_wm_config *config)
3065{
3066        struct drm_crtc *crtc;
3067        struct drm_plane *plane;
3068
3069        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3070                config->num_pipes_active += to_intel_crtc(crtc)->active;
3071
3072        /* FIXME: I don't think we need those two global parameters on SKL */
3073        list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3074                struct intel_plane *intel_plane = to_intel_plane(plane);
3075
3076                config->sprites_enabled |= intel_plane->wm.enabled;
3077                config->sprites_scaled |= intel_plane->wm.scaled;
3078        }
3079}
3080
3081static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3082                                           struct skl_pipe_wm_parameters *p)
3083{
3084        struct drm_device *dev = crtc->dev;
3085        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3086        enum pipe pipe = intel_crtc->pipe;
3087        struct drm_plane *plane;
3088        struct drm_framebuffer *fb;
3089        int i = 1; /* Index for sprite planes start */
3090
3091        p->active = intel_crtc->active;
3092        if (p->active) {
3093                p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3094                p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3095
3096                fb = crtc->primary->state->fb;
3097                /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3098                if (fb) {
3099                        p->plane[0].enabled = true;
3100                        p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3101                                drm_format_plane_cpp(fb->pixel_format, 1) :
3102                                drm_format_plane_cpp(fb->pixel_format, 0);
3103                        p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3104                                drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3105                        p->plane[0].tiling = fb->modifier[0];
3106                } else {
3107                        p->plane[0].enabled = false;
3108                        p->plane[0].bytes_per_pixel = 0;
3109                        p->plane[0].y_bytes_per_pixel = 0;
3110                        p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3111                }
3112                p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3113                p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3114                p->plane[0].rotation = crtc->primary->state->rotation;
3115
3116                fb = crtc->cursor->state->fb;
3117                p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3118                if (fb) {
3119                        p->plane[PLANE_CURSOR].enabled = true;
3120                        p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3121                        p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3122                        p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3123                } else {
3124                        p->plane[PLANE_CURSOR].enabled = false;
3125                        p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3126                        p->plane[PLANE_CURSOR].horiz_pixels = 64;
3127                        p->plane[PLANE_CURSOR].vert_pixels = 64;
3128                }
3129        }
3130
3131        list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3132                struct intel_plane *intel_plane = to_intel_plane(plane);
3133
3134                if (intel_plane->pipe == pipe &&
3135                        plane->type == DRM_PLANE_TYPE_OVERLAY)
3136                        p->plane[i++] = intel_plane->wm;
3137        }
3138}
3139
3140static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3141                                 struct skl_pipe_wm_parameters *p,
3142                                 struct intel_plane_wm_parameters *p_params,
3143                                 uint16_t ddb_allocation,
3144                                 int level,
3145                                 uint16_t *out_blocks, /* out */
3146                                 uint8_t *out_lines /* out */)
3147{
3148        uint32_t latency = dev_priv->wm.skl_latency[level];
3149        uint32_t method1, method2;
3150        uint32_t plane_bytes_per_line, plane_blocks_per_line;
3151        uint32_t res_blocks, res_lines;
3152        uint32_t selected_result;
3153        uint8_t bytes_per_pixel;
3154
3155        if (latency == 0 || !p->active || !p_params->enabled)
3156                return false;
3157
3158        bytes_per_pixel = p_params->y_bytes_per_pixel ?
3159                p_params->y_bytes_per_pixel :
3160                p_params->bytes_per_pixel;
3161        method1 = skl_wm_method1(p->pixel_rate,
3162                                 bytes_per_pixel,
3163                                 latency);
3164        method2 = skl_wm_method2(p->pixel_rate,
3165                                 p->pipe_htotal,
3166                                 p_params->horiz_pixels,
3167                                 bytes_per_pixel,
3168                                 p_params->tiling,
3169                                 latency);
3170
3171        plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3172        plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3173
3174        if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3175            p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3176                uint32_t min_scanlines = 4;
3177                uint32_t y_tile_minimum;
3178                if (intel_rotation_90_or_270(p_params->rotation)) {
3179                        switch (p_params->bytes_per_pixel) {
3180                        case 1:
3181                                min_scanlines = 16;
3182                                break;
3183                        case 2:
3184                                min_scanlines = 8;
3185                                break;
3186                        case 8:
3187                                WARN(1, "Unsupported pixel depth for rotation");
3188                        }
3189                }
3190                y_tile_minimum = plane_blocks_per_line * min_scanlines;
3191                selected_result = max(method2, y_tile_minimum);
3192        } else {
3193                if ((ddb_allocation / plane_blocks_per_line) >= 1)
3194                        selected_result = min(method1, method2);
3195                else
3196                        selected_result = method1;
3197        }
3198
3199        res_blocks = selected_result + 1;
3200        res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3201
3202        if (level >= 1 && level <= 7) {
3203                if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3204                    p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3205                        res_lines += 4;
3206                else
3207                        res_blocks++;
3208        }
3209
3210        if (res_blocks >= ddb_allocation || res_lines > 31)
3211                return false;
3212
3213        *out_blocks = res_blocks;
3214        *out_lines = res_lines;
3215
3216        return true;
3217}
3218
3219static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3220                                 struct skl_ddb_allocation *ddb,
3221                                 struct skl_pipe_wm_parameters *p,
3222                                 enum pipe pipe,
3223                                 int level,
3224                                 int num_planes,
3225                                 struct skl_wm_level *result)
3226{
3227        uint16_t ddb_blocks;
3228        int i;
3229
3230        for (i = 0; i < num_planes; i++) {
3231                ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3232
3233                result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3234                                                p, &p->plane[i],
3235                                                ddb_blocks,
3236                                                level,
3237                                                &result->plane_res_b[i],
3238                                                &result->plane_res_l[i]);
3239        }
3240
3241        ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3242        result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3243                                                 &p->plane[PLANE_CURSOR],
3244                                                 ddb_blocks, level,
3245                                                 &result->plane_res_b[PLANE_CURSOR],
3246                                                 &result->plane_res_l[PLANE_CURSOR]);
3247}
3248
3249static uint32_t
3250skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3251{
3252        if (!to_intel_crtc(crtc)->active)
3253                return 0;
3254
3255        if (WARN_ON(p->pixel_rate == 0))
3256                return 0;
3257
3258        return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3259}
3260
3261static void skl_compute_transition_wm(struct drm_crtc *crtc,
3262                                      struct skl_pipe_wm_parameters *params,
3263                                      struct skl_wm_level *trans_wm /* out */)
3264{
3265        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266        int i;
3267
3268        if (!params->active)
3269                return;
3270
3271        /* Until we know more, just disable transition WMs */
3272        for (i = 0; i < intel_num_planes(intel_crtc); i++)
3273                trans_wm->plane_en[i] = false;
3274        trans_wm->plane_en[PLANE_CURSOR] = false;
3275}
3276
3277static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3278                                struct skl_ddb_allocation *ddb,
3279                                struct skl_pipe_wm_parameters *params,
3280                                struct skl_pipe_wm *pipe_wm)
3281{
3282        struct drm_device *dev = crtc->dev;
3283        const struct drm_i915_private *dev_priv = dev->dev_private;
3284        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285        int level, max_level = ilk_wm_max_level(dev);
3286
3287        for (level = 0; level <= max_level; level++) {
3288                skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3289                                     level, intel_num_planes(intel_crtc),
3290                                     &pipe_wm->wm[level]);
3291        }
3292        pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3293
3294        skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3295}
3296
3297static void skl_compute_wm_results(struct drm_device *dev,
3298                                   struct skl_pipe_wm_parameters *p,
3299                                   struct skl_pipe_wm *p_wm,
3300                                   struct skl_wm_values *r,
3301                                   struct intel_crtc *intel_crtc)
3302{
3303        int level, max_level = ilk_wm_max_level(dev);
3304        enum pipe pipe = intel_crtc->pipe;
3305        uint32_t temp;
3306        int i;
3307
3308        for (level = 0; level <= max_level; level++) {
3309                for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3310                        temp = 0;
3311
3312                        temp |= p_wm->wm[level].plane_res_l[i] <<
3313                                        PLANE_WM_LINES_SHIFT;
3314                        temp |= p_wm->wm[level].plane_res_b[i];
3315                        if (p_wm->wm[level].plane_en[i])
3316                                temp |= PLANE_WM_EN;
3317
3318                        r->plane[pipe][i][level] = temp;
3319                }
3320
3321                temp = 0;
3322
3323                temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3324                temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3325
3326                if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3327                        temp |= PLANE_WM_EN;
3328
3329                r->plane[pipe][PLANE_CURSOR][level] = temp;
3330
3331        }
3332
3333        /* transition WMs */
3334        for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3335                temp = 0;
3336                temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3337                temp |= p_wm->trans_wm.plane_res_b[i];
3338                if (p_wm->trans_wm.plane_en[i])
3339                        temp |= PLANE_WM_EN;
3340
3341                r->plane_trans[pipe][i] = temp;
3342        }
3343
3344        temp = 0;
3345        temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3346        temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3347        if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3348                temp |= PLANE_WM_EN;
3349
3350        r->plane_trans[pipe][PLANE_CURSOR] = temp;
3351
3352        r->wm_linetime[pipe] = p_wm->linetime;
3353}
3354
3355static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3356                                const struct skl_ddb_entry *entry)
3357{
3358        if (entry->end)
3359                I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3360        else
3361                I915_WRITE(reg, 0);
3362}
3363
3364static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3365                                const struct skl_wm_values *new)
3366{
3367        struct drm_device *dev = dev_priv->dev;
3368        struct intel_crtc *crtc;
3369
3370        list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3371                int i, level, max_level = ilk_wm_max_level(dev);
3372                enum pipe pipe = crtc->pipe;
3373
3374                if (!new->dirty[pipe])
3375                        continue;
3376
3377                I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3378
3379                for (level = 0; level <= max_level; level++) {
3380                        for (i = 0; i < intel_num_planes(crtc); i++)
3381                                I915_WRITE(PLANE_WM(pipe, i, level),
3382                                           new->plane[pipe][i][level]);
3383                        I915_WRITE(CUR_WM(pipe, level),
3384                                   new->plane[pipe][PLANE_CURSOR][level]);
3385                }
3386                for (i = 0; i < intel_num_planes(crtc); i++)
3387                        I915_WRITE(PLANE_WM_TRANS(pipe, i),
3388                                   new->plane_trans[pipe][i]);
3389                I915_WRITE(CUR_WM_TRANS(pipe),
3390                           new->plane_trans[pipe][PLANE_CURSOR]);
3391
3392                for (i = 0; i < intel_num_planes(crtc); i++) {
3393                        skl_ddb_entry_write(dev_priv,
3394                                            PLANE_BUF_CFG(pipe, i),
3395                                            &new->ddb.plane[pipe][i]);
3396                        skl_ddb_entry_write(dev_priv,
3397                                            PLANE_NV12_BUF_CFG(pipe, i),
3398                                            &new->ddb.y_plane[pipe][i]);
3399                }
3400
3401                skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3402                                    &new->ddb.plane[pipe][PLANE_CURSOR]);
3403        }
3404}
3405
3406/*
3407 * When setting up a new DDB allocation arrangement, we need to correctly
3408 * sequence the times at which the new allocations for the pipes are taken into
3409 * account or we'll have pipes fetching from space previously allocated to
3410 * another pipe.
3411 *
3412 * Roughly the sequence looks like:
3413 *  1. re-allocate the pipe(s) with the allocation being reduced and not
3414 *     overlapping with a previous light-up pipe (another way to put it is:
3415 *     pipes with their new allocation strickly included into their old ones).
3416 *  2. re-allocate the other pipes that get their allocation reduced
3417 *  3. allocate the pipes having their allocation increased
3418 *
3419 * Steps 1. and 2. are here to take care of the following case:
3420 * - Initially DDB looks like this:
3421 *     |   B    |   C    |
3422 * - enable pipe A.
3423 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3424 *   allocation
3425 *     |  A  |  B  |  C  |
3426 *
3427 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3428 */
3429
3430static void
3431skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3432{
3433        int plane;
3434
3435        DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3436
3437        for_each_plane(dev_priv, pipe, plane) {
3438                I915_WRITE(PLANE_SURF(pipe, plane),
3439                           I915_READ(PLANE_SURF(pipe, plane)));
3440        }
3441        I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3442}
3443
3444static bool
3445skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3446                            const struct skl_ddb_allocation *new,
3447                            enum pipe pipe)
3448{
3449        uint16_t old_size, new_size;
3450
3451        old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3452        new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3453
3454        return old_size != new_size &&
3455               new->pipe[pipe].start >= old->pipe[pipe].start &&
3456               new->pipe[pipe].end <= old->pipe[pipe].end;
3457}
3458
3459static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3460                                struct skl_wm_values *new_values)
3461{
3462        struct drm_device *dev = dev_priv->dev;
3463        struct skl_ddb_allocation *cur_ddb, *new_ddb;
3464        bool reallocated[I915_MAX_PIPES] = {};
3465        struct intel_crtc *crtc;
3466        enum pipe pipe;
3467
3468        new_ddb = &new_values->ddb;
3469        cur_ddb = &dev_priv->wm.skl_hw.ddb;
3470
3471        /*
3472         * First pass: flush the pipes with the new allocation contained into
3473         * the old space.
3474         *
3475         * We'll wait for the vblank on those pipes to ensure we can safely
3476         * re-allocate the freed space without this pipe fetching from it.
3477         */
3478        for_each_intel_crtc(dev, crtc) {
3479                if (!crtc->active)
3480                        continue;
3481
3482                pipe = crtc->pipe;
3483
3484                if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3485                        continue;
3486
3487                skl_wm_flush_pipe(dev_priv, pipe, 1);
3488                intel_wait_for_vblank(dev, pipe);
3489
3490                reallocated[pipe] = true;
3491        }
3492
3493
3494        /*
3495         * Second pass: flush the pipes that are having their allocation
3496         * reduced, but overlapping with a previous allocation.
3497         *
3498         * Here as well we need to wait for the vblank to make sure the freed
3499         * space is not used anymore.
3500         */
3501        for_each_intel_crtc(dev, crtc) {
3502                if (!crtc->active)
3503                        continue;
3504
3505                pipe = crtc->pipe;
3506
3507                if (reallocated[pipe])
3508                        continue;
3509
3510                if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3511                    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3512                        skl_wm_flush_pipe(dev_priv, pipe, 2);
3513                        intel_wait_for_vblank(dev, pipe);
3514                        reallocated[pipe] = true;
3515                }
3516        }
3517
3518        /*
3519         * Third pass: flush the pipes that got more space allocated.
3520         *
3521         * We don't need to actively wait for the update here, next vblank
3522         * will just get more DDB space with the correct WM values.
3523         */
3524        for_each_intel_crtc(dev, crtc) {
3525                if (!crtc->active)
3526                        continue;
3527
3528                pipe = crtc->pipe;
3529
3530                /*
3531                 * At this point, only the pipes more space than before are
3532                 * left to re-allocate.
3533                 */
3534                if (reallocated[pipe])
3535                        continue;
3536
3537                skl_wm_flush_pipe(dev_priv, pipe, 3);
3538        }
3539}
3540
3541static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3542                               struct skl_pipe_wm_parameters *params,
3543                               struct intel_wm_config *config,
3544                               struct skl_ddb_allocation *ddb, /* out */
3545                               struct skl_pipe_wm *pipe_wm /* out */)
3546{
3547        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548
3549        skl_compute_wm_pipe_parameters(crtc, params);
3550        skl_allocate_pipe_ddb(crtc, config, params, ddb);
3551        skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3552
3553        if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3554                return false;
3555
3556        intel_crtc->wm.skl_active = *pipe_wm;
3557
3558        return true;
3559}
3560
3561static void skl_update_other_pipe_wm(struct drm_device *dev,
3562                                     struct drm_crtc *crtc,
3563                                     struct intel_wm_config *config,
3564                                     struct skl_wm_values *r)
3565{
3566        struct intel_crtc *intel_crtc;
3567        struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3568
3569        /*
3570         * If the WM update hasn't changed the allocation for this_crtc (the
3571         * crtc we are currently computing the new WM values for), other
3572         * enabled crtcs will keep the same allocation and we don't need to
3573         * recompute anything for them.
3574         */
3575        if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3576                return;
3577
3578        /*
3579         * Otherwise, because of this_crtc being freshly enabled/disabled, the
3580         * other active pipes need new DDB allocation and WM values.
3581         */
3582        list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3583                                base.head) {
3584                struct skl_pipe_wm_parameters params = {};
3585                struct skl_pipe_wm pipe_wm = {};
3586                bool wm_changed;
3587
3588                if (this_crtc->pipe == intel_crtc->pipe)
3589                        continue;
3590
3591                if (!intel_crtc->active)
3592                        continue;
3593
3594                wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3595                                                &params, config,
3596                                                &r->ddb, &pipe_wm);
3597
3598                /*
3599                 * If we end up re-computing the other pipe WM values, it's
3600                 * because it was really needed, so we expect the WM values to
3601                 * be different.
3602                 */
3603                WARN_ON(!wm_changed);
3604
3605                skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3606                r->dirty[intel_crtc->pipe] = true;
3607        }
3608}
3609
3610static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3611{
3612        watermarks->wm_linetime[pipe] = 0;
3613        memset(watermarks->plane[pipe], 0,
3614               sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3615        memset(watermarks->plane_trans[pipe],
3616               0, sizeof(uint32_t) * I915_MAX_PLANES);
3617        watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3618
3619        /* Clear ddb entries for pipe */
3620        memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3621        memset(&watermarks->ddb.plane[pipe], 0,
3622               sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3623        memset(&watermarks->ddb.y_plane[pipe], 0,
3624               sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3625        memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3626               sizeof(struct skl_ddb_entry));
3627
3628}
3629
3630static void skl_update_wm(struct drm_crtc *crtc)
3631{
3632        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633        struct drm_device *dev = crtc->dev;
3634        struct drm_i915_private *dev_priv = dev->dev_private;
3635        struct skl_pipe_wm_parameters params = {};
3636        struct skl_wm_values *results = &dev_priv->wm.skl_results;
3637        struct skl_pipe_wm pipe_wm = {};
3638        struct intel_wm_config config = {};
3639
3640
3641        /* Clear all dirty flags */
3642        memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3643
3644        skl_clear_wm(results, intel_crtc->pipe);
3645
3646        skl_compute_wm_global_parameters(dev, &config);
3647
3648        if (!skl_update_pipe_wm(crtc, &params, &config,
3649                                &results->ddb, &pipe_wm))
3650                return;
3651
3652        skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3653        results->dirty[intel_crtc->pipe] = true;
3654
3655        skl_update_other_pipe_wm(dev, crtc, &config, results);
3656        skl_write_wm_values(dev_priv, results);
3657        skl_flush_wm_values(dev_priv, results);
3658
3659        /* store the new configuration */
3660        dev_priv->wm.skl_hw = *results;
3661}
3662
3663static void
3664skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3665                     uint32_t sprite_width, uint32_t sprite_height,
3666                     int pixel_size, bool enabled, bool scaled)
3667{
3668        struct intel_plane *intel_plane = to_intel_plane(plane);
3669        struct drm_framebuffer *fb = plane->state->fb;
3670
3671        intel_plane->wm.enabled = enabled;
3672        intel_plane->wm.scaled = scaled;
3673        intel_plane->wm.horiz_pixels = sprite_width;
3674        intel_plane->wm.vert_pixels = sprite_height;
3675        intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3676
3677        /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3678        intel_plane->wm.bytes_per_pixel =
3679                (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3680                drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3681        intel_plane->wm.y_bytes_per_pixel =
3682                (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3683                drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3684
3685        /*
3686         * Framebuffer can be NULL on plane disable, but it does not
3687         * matter for watermarks if we assume no tiling in that case.
3688         */
3689        if (fb)
3690                intel_plane->wm.tiling = fb->modifier[0];
3691        intel_plane->wm.rotation = plane->state->rotation;
3692
3693        skl_update_wm(crtc);
3694}
3695
3696static void ilk_update_wm(struct drm_crtc *crtc)
3697{
3698        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3699        struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3700        struct drm_device *dev = crtc->dev;
3701        struct drm_i915_private *dev_priv = dev->dev_private;
3702        struct ilk_wm_maximums max;
3703        struct ilk_wm_values results = {};
3704        enum intel_ddb_partitioning partitioning;
3705        struct intel_pipe_wm pipe_wm = {};
3706        struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3707        struct intel_wm_config config = {};
3708
3709        WARN_ON(cstate->base.active != intel_crtc->active);
3710
3711        intel_compute_pipe_wm(cstate, &pipe_wm);
3712
3713        if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3714                return;
3715
3716        intel_crtc->wm.active = pipe_wm;
3717
3718        ilk_compute_wm_config(dev, &config);
3719
3720        ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3721        ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3722
3723        /* 5/6 split only in single pipe config on IVB+ */
3724        if (INTEL_INFO(dev)->gen >= 7 &&
3725            config.num_pipes_active == 1 && config.sprites_enabled) {
3726                ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3727                ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3728
3729                best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3730        } else {
3731                best_lp_wm = &lp_wm_1_2;
3732        }
3733
3734        partitioning = (best_lp_wm == &lp_wm_1_2) ?
3735                       INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3736
3737        ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3738
3739        ilk_write_wm_values(dev_priv, &results);
3740}
3741
3742static void
3743ilk_update_sprite_wm(struct drm_plane *plane,
3744                     struct drm_crtc *crtc,
3745                     uint32_t sprite_width, uint32_t sprite_height,
3746                     int pixel_size, bool enabled, bool scaled)
3747{
3748        struct drm_device *dev = plane->dev;
3749        struct intel_plane *intel_plane = to_intel_plane(plane);
3750
3751        /*
3752         * IVB workaround: must disable low power watermarks for at least
3753         * one frame before enabling scaling.  LP watermarks can be re-enabled
3754         * when scaling is disabled.
3755         *
3756         * WaCxSRDisabledForSpriteScaling:ivb
3757         */
3758        if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3759                intel_wait_for_vblank(dev, intel_plane->pipe);
3760
3761        ilk_update_wm(crtc);
3762}
3763
3764static void skl_pipe_wm_active_state(uint32_t val,
3765                                     struct skl_pipe_wm *active,
3766                                     bool is_transwm,
3767                                     bool is_cursor,
3768                                     int i,
3769                                     int level)
3770{
3771        bool is_enabled = (val & PLANE_WM_EN) != 0;
3772
3773        if (!is_transwm) {
3774                if (!is_cursor) {
3775                        active->wm[level].plane_en[i] = is_enabled;
3776                        active->wm[level].plane_res_b[i] =
3777                                        val & PLANE_WM_BLOCKS_MASK;
3778                        active->wm[level].plane_res_l[i] =
3779                                        (val >> PLANE_WM_LINES_SHIFT) &
3780                                                PLANE_WM_LINES_MASK;
3781                } else {
3782                        active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3783                        active->wm[level].plane_res_b[PLANE_CURSOR] =
3784                                        val & PLANE_WM_BLOCKS_MASK;
3785                        active->wm[level].plane_res_l[PLANE_CURSOR] =
3786                                        (val >> PLANE_WM_LINES_SHIFT) &
3787                                                PLANE_WM_LINES_MASK;
3788                }
3789        } else {
3790                if (!is_cursor) {
3791                        active->trans_wm.plane_en[i] = is_enabled;
3792                        active->trans_wm.plane_res_b[i] =
3793                                        val & PLANE_WM_BLOCKS_MASK;
3794                        active->trans_wm.plane_res_l[i] =
3795                                        (val >> PLANE_WM_LINES_SHIFT) &
3796                                                PLANE_WM_LINES_MASK;
3797                } else {
3798                        active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3799                        active->trans_wm.plane_res_b[PLANE_CURSOR] =
3800                                        val & PLANE_WM_BLOCKS_MASK;
3801                        active->trans_wm.plane_res_l[PLANE_CURSOR] =
3802                                        (val >> PLANE_WM_LINES_SHIFT) &
3803                                                PLANE_WM_LINES_MASK;
3804                }
3805        }
3806}
3807
3808static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3809{
3810        struct drm_device *dev = crtc->dev;
3811        struct drm_i915_private *dev_priv = dev->dev_private;
3812        struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3813        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814        struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3815        enum pipe pipe = intel_crtc->pipe;
3816        int level, i, max_level;
3817        uint32_t temp;
3818
3819        max_level = ilk_wm_max_level(dev);
3820
3821        hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3822
3823        for (level = 0; level <= max_level; level++) {
3824                for (i = 0; i < intel_num_planes(intel_crtc); i++)
3825                        hw->plane[pipe][i][level] =
3826                                        I915_READ(PLANE_WM(pipe, i, level));
3827                hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3828        }
3829
3830        for (i = 0; i < intel_num_planes(intel_crtc); i++)
3831                hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3832        hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3833
3834        if (!intel_crtc->active)
3835                return;
3836
3837        hw->dirty[pipe] = true;
3838
3839        active->linetime = hw->wm_linetime[pipe];
3840
3841        for (level = 0; level <= max_level; level++) {
3842                for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3843                        temp = hw->plane[pipe][i][level];
3844                        skl_pipe_wm_active_state(temp, active, false,
3845                                                false, i, level);
3846                }
3847                temp = hw->plane[pipe][PLANE_CURSOR][level];
3848                skl_pipe_wm_active_state(temp, active, false, true, i, level);
3849        }
3850
3851        for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3852                temp = hw->plane_trans[pipe][i];
3853                skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3854        }
3855
3856        temp = hw->plane_trans[pipe][PLANE_CURSOR];
3857        skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3858}
3859
3860void skl_wm_get_hw_state(struct drm_device *dev)
3861{
3862        struct drm_i915_private *dev_priv = dev->dev_private;
3863        struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3864        struct drm_crtc *crtc;
3865
3866        skl_ddb_get_hw_state(dev_priv, ddb);
3867        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3868                skl_pipe_wm_get_hw_state(crtc);
3869}
3870
3871static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3872{
3873        struct drm_device *dev = crtc->dev;
3874        struct drm_i915_private *dev_priv = dev->dev_private;
3875        struct ilk_wm_values *hw = &dev_priv->wm.hw;
3876        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3877        struct intel_pipe_wm *active = &intel_crtc->wm.active;
3878        enum pipe pipe = intel_crtc->pipe;
3879        static const unsigned int wm0_pipe_reg[] = {
3880                [PIPE_A] = WM0_PIPEA_ILK,
3881                [PIPE_B] = WM0_PIPEB_ILK,
3882                [PIPE_C] = WM0_PIPEC_IVB,
3883        };
3884
3885        hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3886        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3887                hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3888
3889        memset(active, 0, sizeof(*active));
3890
3891        active->pipe_enabled = intel_crtc->active;
3892
3893        if (active->pipe_enabled) {
3894                u32 tmp = hw->wm_pipe[pipe];
3895
3896                /*
3897                 * For active pipes LP0 watermark is marked as
3898                 * enabled, and LP1+ watermaks as disabled since
3899                 * we can't really reverse compute them in case
3900                 * multiple pipes are active.
3901                 */
3902                active->wm[0].enable = true;
3903                active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3904                active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3905                active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3906                active->linetime = hw->wm_linetime[pipe];
3907        } else {
3908                int level, max_level = ilk_wm_max_level(dev);
3909
3910                /*
3911                 * For inactive pipes, all watermark levels
3912                 * should be marked as enabled but zeroed,
3913                 * which is what we'd compute them to.
3914                 */
3915                for (level = 0; level <= max_level; level++)
3916                        active->wm[level].enable = true;
3917        }
3918}
3919
3920#define _FW_WM(value, plane) \
3921        (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3922#define _FW_WM_VLV(value, plane) \
3923        (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3924
3925static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3926                               struct vlv_wm_values *wm)
3927{
3928        enum pipe pipe;
3929        uint32_t tmp;
3930
3931        for_each_pipe(dev_priv, pipe) {
3932                tmp = I915_READ(VLV_DDL(pipe));
3933
3934                wm->ddl[pipe].primary =
3935                        (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3936                wm->ddl[pipe].cursor =
3937                        (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3938                wm->ddl[pipe].sprite[0] =
3939                        (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3940                wm->ddl[pipe].sprite[1] =
3941                        (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3942        }
3943
3944        tmp = I915_READ(DSPFW1);
3945        wm->sr.plane = _FW_WM(tmp, SR);
3946        wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3947        wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3948        wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3949
3950        tmp = I915_READ(DSPFW2);
3951        wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3952        wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3953        wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3954
3955        tmp = I915_READ(DSPFW3);
3956        wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3957
3958        if (IS_CHERRYVIEW(dev_priv)) {
3959                tmp = I915_READ(DSPFW7_CHV);
3960                wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3961                wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3962
3963                tmp = I915_READ(DSPFW8_CHV);
3964                wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3965                wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3966
3967                tmp = I915_READ(DSPFW9_CHV);
3968                wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3969                wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3970
3971                tmp = I915_READ(DSPHOWM);
3972                wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3973                wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3974                wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3975                wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3976                wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3977                wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3978                wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3979                wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3980                wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3981                wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3982        } else {
3983                tmp = I915_READ(DSPFW7);
3984                wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3985                wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3986
3987                tmp = I915_READ(DSPHOWM);
3988                wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3989                wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3990                wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3991                wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3992                wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3993                wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3994                wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3995        }
3996}
3997
3998#undef _FW_WM
3999#undef _FW_WM_VLV
4000
4001void vlv_wm_get_hw_state(struct drm_device *dev)
4002{
4003        struct drm_i915_private *dev_priv = to_i915(dev);
4004        struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4005        struct intel_plane *plane;
4006        enum pipe pipe;
4007        u32 val;
4008
4009        vlv_read_wm_values(dev_priv, wm);
4010
4011        for_each_intel_plane(dev, plane) {
4012                switch (plane->base.type) {
4013                        int sprite;
4014                case DRM_PLANE_TYPE_CURSOR:
4015                        plane->wm.fifo_size = 63;
4016                        break;
4017                case DRM_PLANE_TYPE_PRIMARY:
4018                        plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4019                        break;
4020                case DRM_PLANE_TYPE_OVERLAY:
4021                        sprite = plane->plane;
4022                        plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4023                        break;
4024                }
4025        }
4026
4027        wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4028        wm->level = VLV_WM_LEVEL_PM2;
4029
4030        if (IS_CHERRYVIEW(dev_priv)) {
4031                mutex_lock(&dev_priv->rps.hw_lock);
4032
4033                val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4034                if (val & DSP_MAXFIFO_PM5_ENABLE)
4035                        wm->level = VLV_WM_LEVEL_PM5;
4036
4037                /*
4038                 * If DDR DVFS is disabled in the BIOS, Punit
4039                 * will never ack the request. So if that happens
4040                 * assume we don't have to enable/disable DDR DVFS
4041                 * dynamically. To test that just set the REQ_ACK
4042                 * bit to poke the Punit, but don't change the
4043                 * HIGH/LOW bits so that we don't actually change
4044                 * the current state.
4045                 */
4046                val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4047                val |= FORCE_DDR_FREQ_REQ_ACK;
4048                vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4049
4050                if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4051                              FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4052                        DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4053                                      "assuming DDR DVFS is disabled\n");
4054                        dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4055                } else {
4056                        val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4057                        if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4058                                wm->level = VLV_WM_LEVEL_DDR_DVFS;
4059                }
4060
4061                mutex_unlock(&dev_priv->rps.hw_lock);
4062        }
4063
4064        for_each_pipe(dev_priv, pipe)
4065                DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4066                              pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4067                              wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4068
4069        DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4070                      wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4071}
4072
4073void ilk_wm_get_hw_state(struct drm_device *dev)
4074{
4075        struct drm_i915_private *dev_priv = dev->dev_private;
4076        struct ilk_wm_values *hw = &dev_priv->wm.hw;
4077        struct drm_crtc *crtc;
4078
4079        for_each_crtc(dev, crtc)
4080                ilk_pipe_wm_get_hw_state(crtc);
4081
4082        hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4083        hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4084        hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4085
4086        hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4087        if (INTEL_INFO(dev)->gen >= 7) {
4088                hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4089                hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4090        }
4091
4092        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4093                hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4094                        INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4095        else if (IS_IVYBRIDGE(dev))
4096                hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4097                        INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4098
4099        hw->enable_fbc_wm =
4100                !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4101}
4102
4103/**
4104 * intel_update_watermarks - update FIFO watermark values based on current modes
4105 *
4106 * Calculate watermark values for the various WM regs based on current mode
4107 * and plane configuration.
4108 *
4109 * There are several cases to deal with here:
4110 *   - normal (i.e. non-self-refresh)
4111 *   - self-refresh (SR) mode
4112 *   - lines are large relative to FIFO size (buffer can hold up to 2)
4113 *   - lines are small relative to FIFO size (buffer can hold more than 2
4114 *     lines), so need to account for TLB latency
4115 *
4116 *   The normal calculation is:
4117 *     watermark = dotclock * bytes per pixel * latency
4118 *   where latency is platform & configuration dependent (we assume pessimal
4119 *   values here).
4120 *
4121 *   The SR calculation is:
4122 *     watermark = (trunc(latency/line time)+1) * surface width *
4123 *       bytes per pixel
4124 *   where
4125 *     line time = htotal / dotclock
4126 *     surface width = hdisplay for normal plane and 64 for cursor
4127 *   and latency is assumed to be high, as above.
4128 *
4129 * The final value programmed to the register should always be rounded up,
4130 * and include an extra 2 entries to account for clock crossings.
4131 *
4132 * We don't use the sprite, so we can ignore that.  And on Crestline we have
4133 * to set the non-SR watermarks to 8.
4134 */
4135void intel_update_watermarks(struct drm_crtc *crtc)
4136{
4137        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4138
4139        if (dev_priv->display.update_wm)
4140                dev_priv->display.update_wm(crtc);
4141}
4142
4143void intel_update_sprite_watermarks(struct drm_plane *plane,
4144                                    struct drm_crtc *crtc,
4145                                    uint32_t sprite_width,
4146                                    uint32_t sprite_height,
4147                                    int pixel_size,
4148                                    bool enabled, bool scaled)
4149{
4150        struct drm_i915_private *dev_priv = plane->dev->dev_private;
4151
4152        if (dev_priv->display.update_sprite_wm)
4153                dev_priv->display.update_sprite_wm(plane, crtc,
4154                                                   sprite_width, sprite_height,
4155                                                   pixel_size, enabled, scaled);
4156}
4157
4158/**
4159 * Lock protecting IPS related data structures
4160 */
4161DEFINE_SPINLOCK(mchdev_lock);
4162
4163/* Global for IPS driver to get at the current i915 device. Protected by
4164 * mchdev_lock. */
4165static struct drm_i915_private *i915_mch_dev;
4166
4167bool ironlake_set_drps(struct drm_device *dev, u8 val)
4168{
4169        struct drm_i915_private *dev_priv = dev->dev_private;
4170        u16 rgvswctl;
4171
4172        assert_spin_locked(&mchdev_lock);
4173
4174        rgvswctl = I915_READ16(MEMSWCTL);
4175        if (rgvswctl & MEMCTL_CMD_STS) {
4176                DRM_DEBUG("gpu busy, RCS change rejected\n");
4177                return false; /* still busy with another command */
4178        }
4179
4180        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4181                (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4182        I915_WRITE16(MEMSWCTL, rgvswctl);
4183        POSTING_READ16(MEMSWCTL);
4184
4185        rgvswctl |= MEMCTL_CMD_STS;
4186        I915_WRITE16(MEMSWCTL, rgvswctl);
4187
4188        return true;
4189}
4190
4191static void ironlake_enable_drps(struct drm_device *dev)
4192{
4193        struct drm_i915_private *dev_priv = dev->dev_private;
4194        u32 rgvmodectl = I915_READ(MEMMODECTL);
4195        u8 fmax, fmin, fstart, vstart;
4196
4197        spin_lock_irq(&mchdev_lock);
4198
4199        /* Enable temp reporting */
4200        I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4201        I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4202
4203        /* 100ms RC evaluation intervals */
4204        I915_WRITE(RCUPEI, 100000);
4205        I915_WRITE(RCDNEI, 100000);
4206
4207        /* Set max/min thresholds to 90ms and 80ms respectively */
4208        I915_WRITE(RCBMAXAVG, 90000);
4209        I915_WRITE(RCBMINAVG, 80000);
4210
4211        I915_WRITE(MEMIHYST, 1);
4212
4213        /* Set up min, max, and cur for interrupt handling */
4214        fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4215        fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4216        fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4217                MEMMODE_FSTART_SHIFT;
4218
4219        vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4220                PXVFREQ_PX_SHIFT;
4221
4222        dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4223        dev_priv->ips.fstart = fstart;
4224
4225        dev_priv->ips.max_delay = fstart;
4226        dev_priv->ips.min_delay = fmin;
4227        dev_priv->ips.cur_delay = fstart;
4228
4229        DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4230                         fmax, fmin, fstart);
4231
4232        I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4233
4234        /*
4235         * Interrupts will be enabled in ironlake_irq_postinstall
4236         */
4237
4238        I915_WRITE(VIDSTART, vstart);
4239        POSTING_READ(VIDSTART);
4240
4241        rgvmodectl |= MEMMODE_SWMODE_EN;
4242        I915_WRITE(MEMMODECTL, rgvmodectl);
4243
4244        if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4245                DRM_ERROR("stuck trying to change perf mode\n");
4246        mdelay(1);
4247
4248        ironlake_set_drps(dev, fstart);
4249
4250        dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4251                I915_READ(DDREC) + I915_READ(CSIEC);
4252        dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4253        dev_priv->ips.last_count2 = I915_READ(GFXEC);
4254        dev_priv->ips.last_time2 = ktime_get_raw_ns();
4255
4256        spin_unlock_irq(&mchdev_lock);
4257}
4258
4259static void ironlake_disable_drps(struct drm_device *dev)
4260{
4261        struct drm_i915_private *dev_priv = dev->dev_private;
4262        u16 rgvswctl;
4263
4264        spin_lock_irq(&mchdev_lock);
4265
4266        rgvswctl = I915_READ16(MEMSWCTL);
4267
4268        /* Ack interrupts, disable EFC interrupt */
4269        I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4270        I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4271        I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4272        I915_WRITE(DEIIR, DE_PCU_EVENT);
4273        I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4274
4275        /* Go back to the starting frequency */
4276        ironlake_set_drps(dev, dev_priv->ips.fstart);
4277        mdelay(1);
4278        rgvswctl |= MEMCTL_CMD_STS;
4279        I915_WRITE(MEMSWCTL, rgvswctl);
4280        mdelay(1);
4281
4282        spin_unlock_irq(&mchdev_lock);
4283}
4284
4285/* There's a funny hw issue where the hw returns all 0 when reading from
4286 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4287 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4288 * all limits and the gpu stuck at whatever frequency it is at atm).
4289 */
4290static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4291{
4292        u32 limits;
4293
4294        /* Only set the down limit when we've reached the lowest level to avoid
4295         * getting more interrupts, otherwise leave this clear. This prevents a
4296         * race in the hw when coming out of rc6: There's a tiny window where
4297         * the hw runs at the minimal clock before selecting the desired
4298         * frequency, if the down threshold expires in that window we will not
4299         * receive a down interrupt. */
4300        if (IS_GEN9(dev_priv->dev)) {
4301                limits = (dev_priv->rps.max_freq_softlimit) << 23;
4302                if (val <= dev_priv->rps.min_freq_softlimit)
4303                        limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4304        } else {
4305                limits = dev_priv->rps.max_freq_softlimit << 24;
4306                if (val <= dev_priv->rps.min_freq_softlimit)
4307                        limits |= dev_priv->rps.min_freq_softlimit << 16;
4308        }
4309
4310        return limits;
4311}
4312
4313static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4314{
4315        int new_power;
4316        u32 threshold_up = 0, threshold_down = 0; /* in % */
4317        u32 ei_up = 0, ei_down = 0;
4318
4319        new_power = dev_priv->rps.power;
4320        switch (dev_priv->rps.power) {
4321        case LOW_POWER:
4322                if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4323                        new_power = BETWEEN;
4324                break;
4325
4326        case BETWEEN:
4327                if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4328                        new_power = LOW_POWER;
4329                else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4330                        new_power = HIGH_POWER;
4331                break;
4332
4333        case HIGH_POWER:
4334                if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4335                        new_power = BETWEEN;
4336                break;
4337        }
4338        /* Max/min bins are special */
4339        if (val <= dev_priv->rps.min_freq_softlimit)
4340                new_power = LOW_POWER;
4341        if (val >= dev_priv->rps.max_freq_softlimit)
4342                new_power = HIGH_POWER;
4343        if (new_power == dev_priv->rps.power)
4344                return;
4345
4346        /* Note the units here are not exactly 1us, but 1280ns. */
4347        switch (new_power) {
4348        case LOW_POWER:
4349                /* Upclock if more than 95% busy over 16ms */
4350                ei_up = 16000;
4351                threshold_up = 95;
4352
4353                /* Downclock if less than 85% busy over 32ms */
4354                ei_down = 32000;
4355                threshold_down = 85;
4356                break;
4357
4358        case BETWEEN:
4359                /* Upclock if more than 90% busy over 13ms */
4360                ei_up = 13000;
4361                threshold_up = 90;
4362
4363                /* Downclock if less than 75% busy over 32ms */
4364                ei_down = 32000;
4365                threshold_down = 75;
4366                break;
4367
4368        case HIGH_POWER:
4369                /* Upclock if more than 85% busy over 10ms */
4370                ei_up = 10000;
4371                threshold_up = 85;
4372
4373                /* Downclock if less than 60% busy over 32ms */
4374                ei_down = 32000;
4375                threshold_down = 60;
4376                break;
4377        }
4378
4379        /* When byt can survive without system hang with dynamic
4380         * sw freq adjustments, this restriction can be lifted.
4381         */
4382        if (IS_VALLEYVIEW(dev_priv))
4383                goto skip_hw_write;
4384
4385        I915_WRITE(GEN6_RP_UP_EI,
4386                GT_INTERVAL_FROM_US(dev_priv, ei_up));
4387        I915_WRITE(GEN6_RP_UP_THRESHOLD,
4388                GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4389
4390        I915_WRITE(GEN6_RP_DOWN_EI,
4391                GT_INTERVAL_FROM_US(dev_priv, ei_down));
4392        I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4393                GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4394
4395         I915_WRITE(GEN6_RP_CONTROL,
4396                    GEN6_RP_MEDIA_TURBO |
4397                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4398                    GEN6_RP_MEDIA_IS_GFX |
4399                    GEN6_RP_ENABLE |
4400                    GEN6_RP_UP_BUSY_AVG |
4401                    GEN6_RP_DOWN_IDLE_AVG);
4402
4403skip_hw_write:
4404        dev_priv->rps.power = new_power;
4405        dev_priv->rps.up_threshold = threshold_up;
4406        dev_priv->rps.down_threshold = threshold_down;
4407        dev_priv->rps.last_adj = 0;
4408}
4409
4410static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4411{
4412        u32 mask = 0;
4413
4414        /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
4415        if (val > dev_priv->rps.min_freq_softlimit)
4416                mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4417        if (val < dev_priv->rps.max_freq_softlimit)
4418                mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4419
4420        mask &= dev_priv->pm_rps_events;
4421
4422        return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4423}
4424
4425/* gen6_set_rps is called to update the frequency request, but should also be
4426 * called when the range (min_delay and max_delay) is modified so that we can
4427 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4428static void gen6_set_rps(struct drm_device *dev, u8 val)
4429{
4430        struct drm_i915_private *dev_priv = dev->dev_private;
4431
4432        /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4433        if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4434                return;
4435
4436        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4437        WARN_ON(val > dev_priv->rps.max_freq);
4438        WARN_ON(val < dev_priv->rps.min_freq);
4439
4440        /* min/max delay may still have been modified so be sure to
4441         * write the limits value.
4442         */
4443        if (val != dev_priv->rps.cur_freq) {
4444                gen6_set_rps_thresholds(dev_priv, val);
4445
4446                if (IS_GEN9(dev))
4447                        I915_WRITE(GEN6_RPNSWREQ,
4448                                   GEN9_FREQUENCY(val));
4449                else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4450                        I915_WRITE(GEN6_RPNSWREQ,
4451                                   HSW_FREQUENCY(val));
4452                else
4453                        I915_WRITE(GEN6_RPNSWREQ,
4454                                   GEN6_FREQUENCY(val) |
4455                                   GEN6_OFFSET(0) |
4456                                   GEN6_AGGRESSIVE_TURBO);
4457        }
4458
4459        /* Make sure we continue to get interrupts
4460         * until we hit the minimum or maximum frequencies.
4461         */
4462        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4463        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4464
4465        POSTING_READ(GEN6_RPNSWREQ);
4466
4467        dev_priv->rps.cur_freq = val;
4468        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4469}
4470
4471static void valleyview_set_rps(struct drm_device *dev, u8 val)
4472{
4473        struct drm_i915_private *dev_priv = dev->dev_private;
4474
4475        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4476        WARN_ON(val > dev_priv->rps.max_freq);
4477        WARN_ON(val < dev_priv->rps.min_freq);
4478
4479        if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4480                      "Odd GPU freq value\n"))
4481                val &= ~1;
4482
4483        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4484
4485        if (val != dev_priv->rps.cur_freq) {
4486                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4487                if (!IS_CHERRYVIEW(dev_priv))
4488                        gen6_set_rps_thresholds(dev_priv, val);
4489        }
4490
4491        dev_priv->rps.cur_freq = val;
4492        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4493}
4494
4495/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4496 *
4497 * * If Gfx is Idle, then
4498 * 1. Forcewake Media well.
4499 * 2. Request idle freq.
4500 * 3. Release Forcewake of Media well.
4501*/
4502static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4503{
4504        u32 val = dev_priv->rps.idle_freq;
4505
4506        if (dev_priv->rps.cur_freq <= val)
4507                return;
4508
4509        /* Wake up the media well, as that takes a lot less
4510         * power than the Render well. */
4511        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4512        valleyview_set_rps(dev_priv->dev, val);
4513        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4514}
4515
4516void gen6_rps_busy(struct drm_i915_private *dev_priv)
4517{
4518        mutex_lock(&dev_priv->rps.hw_lock);
4519        if (dev_priv->rps.enabled) {
4520                if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
4521                        gen6_rps_reset_ei(dev_priv);
4522                I915_WRITE(GEN6_PMINTRMSK,
4523                           gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4524        }
4525        mutex_unlock(&dev_priv->rps.hw_lock);
4526}
4527
4528void gen6_rps_idle(struct drm_i915_private *dev_priv)
4529{
4530        struct drm_device *dev = dev_priv->dev;
4531
4532        mutex_lock(&dev_priv->rps.hw_lock);
4533        if (dev_priv->rps.enabled) {
4534                if (IS_VALLEYVIEW(dev))
4535                        vlv_set_rps_idle(dev_priv);
4536                else
4537                        gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4538                dev_priv->rps.last_adj = 0;
4539                I915_WRITE(GEN6_PMINTRMSK,
4540                           gen6_sanitize_rps_pm_mask(dev_priv, ~0));
4541        }
4542        mutex_unlock(&dev_priv->rps.hw_lock);
4543
4544        spin_lock(&dev_priv->rps.client_lock);
4545        while (!list_empty(&dev_priv->rps.clients))
4546                list_del_init(dev_priv->rps.clients.next);
4547        spin_unlock(&dev_priv->rps.client_lock);
4548}
4549
4550void gen6_rps_boost(struct drm_i915_private *dev_priv,
4551                    struct intel_rps_client *rps,
4552                    unsigned long submitted)
4553{
4554        /* This is intentionally racy! We peek at the state here, then
4555         * validate inside the RPS worker.
4556         */
4557        if (!(dev_priv->mm.busy &&
4558              dev_priv->rps.enabled &&
4559              dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4560                return;
4561
4562        /* Force a RPS boost (and don't count it against the client) if
4563         * the GPU is severely congested.
4564         */
4565        if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4566                rps = NULL;
4567
4568        spin_lock(&dev_priv->rps.client_lock);
4569        if (rps == NULL || list_empty(&rps->link)) {
4570                spin_lock_irq(&dev_priv->irq_lock);
4571                if (dev_priv->rps.interrupts_enabled) {
4572                        dev_priv->rps.client_boost = true;
4573                        queue_work(dev_priv->wq, &dev_priv->rps.work);
4574                }
4575                spin_unlock_irq(&dev_priv->irq_lock);
4576
4577                if (rps != NULL) {
4578                        list_add(&rps->link, &dev_priv->rps.clients);
4579                        rps->boosts++;
4580                } else
4581                        dev_priv->rps.boosts++;
4582        }
4583        spin_unlock(&dev_priv->rps.client_lock);
4584}
4585
4586void intel_set_rps(struct drm_device *dev, u8 val)
4587{
4588        if (IS_VALLEYVIEW(dev))
4589                valleyview_set_rps(dev, val);
4590        else
4591                gen6_set_rps(dev, val);
4592}
4593
4594static void gen9_disable_rps(struct drm_device *dev)
4595{
4596        struct drm_i915_private *dev_priv = dev->dev_private;
4597
4598        I915_WRITE(GEN6_RC_CONTROL, 0);
4599        I915_WRITE(GEN9_PG_ENABLE, 0);
4600}
4601
4602static void gen6_disable_rps(struct drm_device *dev)
4603{
4604        struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606        I915_WRITE(GEN6_RC_CONTROL, 0);
4607        I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4608}
4609
4610static void cherryview_disable_rps(struct drm_device *dev)
4611{
4612        struct drm_i915_private *dev_priv = dev->dev_private;
4613
4614        I915_WRITE(GEN6_RC_CONTROL, 0);
4615}
4616
4617static void valleyview_disable_rps(struct drm_device *dev)
4618{
4619        struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621        /* we're doing forcewake before Disabling RC6,
4622         * This what the BIOS expects when going into suspend */
4623        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4624
4625        I915_WRITE(GEN6_RC_CONTROL, 0);
4626
4627        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4628}
4629
4630static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4631{
4632        if (IS_VALLEYVIEW(dev)) {
4633                if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4634                        mode = GEN6_RC_CTL_RC6_ENABLE;
4635                else
4636                        mode = 0;
4637        }
4638        if (HAS_RC6p(dev))
4639                DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4640                              (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4641                              (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4642                              (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4643
4644        else
4645                DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4646                              (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4647}
4648
4649static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4650{
4651        /* No RC6 before Ironlake and code is gone for ilk. */
4652        if (INTEL_INFO(dev)->gen < 6)
4653                return 0;
4654
4655        /* Respect the kernel parameter if it is set */
4656        if (enable_rc6 >= 0) {
4657                int mask;
4658
4659                if (HAS_RC6p(dev))
4660                        mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4661                               INTEL_RC6pp_ENABLE;
4662                else
4663                        mask = INTEL_RC6_ENABLE;
4664
4665                if ((enable_rc6 & mask) != enable_rc6)
4666                        DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4667                                      enable_rc6 & mask, enable_rc6, mask);
4668
4669                return enable_rc6 & mask;
4670        }
4671
4672        if (IS_IVYBRIDGE(dev))
4673                return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4674
4675        return INTEL_RC6_ENABLE;
4676}
4677
4678int intel_enable_rc6(const struct drm_device *dev)
4679{
4680        return i915.enable_rc6;
4681}
4682
4683static void gen6_init_rps_frequencies(struct drm_device *dev)
4684{
4685        struct drm_i915_private *dev_priv = dev->dev_private;
4686        uint32_t rp_state_cap;
4687        u32 ddcc_status = 0;
4688        int ret;
4689
4690        /* All of these values are in units of 50MHz */
4691        dev_priv->rps.cur_freq          = 0;
4692        /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4693        if (IS_BROXTON(dev)) {
4694                rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4695                dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4696                dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4697                dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4698        } else {
4699                rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4700                dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4701                dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4702                dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4703        }
4704
4705        /* hw_max = RP0 until we check for overclocking */
4706        dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4707
4708        dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4709        if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4710                ret = sandybridge_pcode_read(dev_priv,
4711                                        HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4712                                        &ddcc_status);
4713                if (0 == ret)
4714                        dev_priv->rps.efficient_freq =
4715                                clamp_t(u8,
4716                                        ((ddcc_status >> 8) & 0xff),
4717                                        dev_priv->rps.min_freq,
4718                                        dev_priv->rps.max_freq);
4719        }
4720
4721        if (IS_SKYLAKE(dev)) {
4722                /* Store the frequency values in 16.66 MHZ units, which is
4723                   the natural hardware unit for SKL */
4724                dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4725                dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4726                dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4727                dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4728                dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4729        }
4730
4731        dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4732
4733        /* Preserve min/max settings in case of re-init */
4734        if (dev_priv->rps.max_freq_softlimit == 0)
4735                dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4736
4737        if (dev_priv->rps.min_freq_softlimit == 0) {
4738                if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4739                        dev_priv->rps.min_freq_softlimit =
4740                                max_t(int, dev_priv->rps.efficient_freq,
4741                                      intel_freq_opcode(dev_priv, 450));
4742                else
4743                        dev_priv->rps.min_freq_softlimit =
4744                                dev_priv->rps.min_freq;
4745        }
4746}
4747
4748/* See the Gen9_GT_PM_Programming_Guide doc for the below */
4749static void gen9_enable_rps(struct drm_device *dev)
4750{
4751        struct drm_i915_private *dev_priv = dev->dev_private;
4752
4753        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4754
4755        gen6_init_rps_frequencies(dev);
4756
4757        /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4758        if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4759                intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4760                return;
4761        }
4762
4763        /* Program defaults and thresholds for RPS*/
4764        I915_WRITE(GEN6_RC_VIDEO_FREQ,
4765                GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4766
4767        /* 1 second timeout*/
4768        I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4769                GT_INTERVAL_FROM_US(dev_priv, 1000000));
4770
4771        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4772
4773        /* Leaning on the below call to gen6_set_rps to program/setup the
4774         * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4775         * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4776        dev_priv->rps.power = HIGH_POWER; /* force a reset */
4777        gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4778
4779        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4780}
4781
4782static void gen9_enable_rc6(struct drm_device *dev)
4783{
4784        struct drm_i915_private *dev_priv = dev->dev_private;
4785        struct intel_engine_cs *ring;
4786        uint32_t rc6_mask = 0;
4787        int unused;
4788
4789        /* 1a: Software RC state - RC0 */
4790        I915_WRITE(GEN6_RC_STATE, 0);
4791
4792        /* 1b: Get forcewake during program sequence. Although the driver
4793         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4794        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4795
4796        /* 2a: Disable RC states. */
4797        I915_WRITE(GEN6_RC_CONTROL, 0);
4798
4799        /* 2b: Program RC6 thresholds.*/
4800
4801        /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4802        if (IS_SKYLAKE(dev))
4803                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4804        else
4805                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4806        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4807        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4808        for_each_ring(ring, dev_priv, unused)
4809                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4810
4811        if (HAS_GUC_UCODE(dev))
4812                I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4813
4814        I915_WRITE(GEN6_RC_SLEEP, 0);
4815
4816        /* 2c: Program Coarse Power Gating Policies. */
4817        I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4818        I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4819
4820        /* 3a: Enable RC6 */
4821        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4822                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4823        DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4824                        "on" : "off");
4825        /* WaRsUseTimeoutMode */
4826        if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4827            (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4828                I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4829                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4830                           GEN7_RC_CTL_TO_MODE |
4831                           rc6_mask);
4832        } else {
4833                I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4834                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4835                           GEN6_RC_CTL_EI_MODE(1) |
4836                           rc6_mask);
4837        }
4838
4839        /*
4840         * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4841         * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4842         */
4843        if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4844            ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4845                I915_WRITE(GEN9_PG_ENABLE, 0);
4846        else
4847                I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4848                                (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4849
4850        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4851
4852}
4853
4854static void gen8_enable_rps(struct drm_device *dev)
4855{
4856        struct drm_i915_private *dev_priv = dev->dev_private;
4857        struct intel_engine_cs *ring;
4858        uint32_t rc6_mask = 0;
4859        int unused;
4860
4861        /* 1a: Software RC state - RC0 */
4862        I915_WRITE(GEN6_RC_STATE, 0);
4863
4864        /* 1c & 1d: Get forcewake during program sequence. Although the driver
4865         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4866        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4867
4868        /* 2a: Disable RC states. */
4869        I915_WRITE(GEN6_RC_CONTROL, 0);
4870
4871        /* Initialize rps frequencies */
4872        gen6_init_rps_frequencies(dev);
4873
4874        /* 2b: Program RC6 thresholds.*/
4875        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4876        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4877        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4878        for_each_ring(ring, dev_priv, unused)
4879                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4880        I915_WRITE(GEN6_RC_SLEEP, 0);
4881        if (IS_BROADWELL(dev))
4882                I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4883        else
4884                I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4885
4886        /* 3: Enable RC6 */
4887        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4888                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4889        intel_print_rc6_info(dev, rc6_mask);
4890        if (IS_BROADWELL(dev))
4891                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4892                                GEN7_RC_CTL_TO_MODE |
4893                                rc6_mask);
4894        else
4895                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4896                                GEN6_RC_CTL_EI_MODE(1) |
4897                                rc6_mask);
4898
4899        /* 4 Program defaults and thresholds for RPS*/
4900        I915_WRITE(GEN6_RPNSWREQ,
4901                   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4902        I915_WRITE(GEN6_RC_VIDEO_FREQ,
4903                   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4904        /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4905        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4906
4907        /* Docs recommend 900MHz, and 300 MHz respectively */
4908        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4909                   dev_priv->rps.max_freq_softlimit << 24 |
4910                   dev_priv->rps.min_freq_softlimit << 16);
4911
4912        I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4913        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4914        I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4915        I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4916
4917        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4918
4919        /* 5: Enable RPS */
4920        I915_WRITE(GEN6_RP_CONTROL,
4921                   GEN6_RP_MEDIA_TURBO |
4922                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
4923                   GEN6_RP_MEDIA_IS_GFX |
4924                   GEN6_RP_ENABLE |
4925                   GEN6_RP_UP_BUSY_AVG |
4926                   GEN6_RP_DOWN_IDLE_AVG);
4927
4928        /* 6: Ring frequency + overclocking (our driver does this later */
4929
4930        dev_priv->rps.power = HIGH_POWER; /* force a reset */
4931        gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4932
4933        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4934}
4935
4936static void gen6_enable_rps(struct drm_device *dev)
4937{
4938        struct drm_i915_private *dev_priv = dev->dev_private;
4939        struct intel_engine_cs *ring;
4940        u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4941        u32 gtfifodbg;
4942        int rc6_mode;
4943        int i, ret;
4944
4945        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4946
4947        /* Here begins a magic sequence of register writes to enable
4948         * auto-downclocking.
4949         *
4950         * Perhaps there might be some value in exposing these to
4951         * userspace...
4952         */
4953        I915_WRITE(GEN6_RC_STATE, 0);
4954
4955        /* Clear the DBG now so we don't confuse earlier errors */
4956        if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4957                DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4958                I915_WRITE(GTFIFODBG, gtfifodbg);
4959        }
4960
4961        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4962
4963        /* Initialize rps frequencies */
4964        gen6_init_rps_frequencies(dev);
4965
4966        /* disable the counters and set deterministic thresholds */
4967        I915_WRITE(GEN6_RC_CONTROL, 0);
4968
4969        I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4970        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4971        I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4972        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4973        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4974
4975        for_each_ring(ring, dev_priv, i)
4976                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4977
4978        I915_WRITE(GEN6_RC_SLEEP, 0);
4979        I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4980        if (IS_IVYBRIDGE(dev))
4981                I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4982        else
4983                I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4984        I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4985        I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4986
4987        /* Check if we are enabling RC6 */
4988        rc6_mode = intel_enable_rc6(dev_priv->dev);
4989        if (rc6_mode & INTEL_RC6_ENABLE)
4990                rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4991
4992        /* We don't use those on Haswell */
4993        if (!IS_HASWELL(dev)) {
4994                if (rc6_mode & INTEL_RC6p_ENABLE)
4995                        rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4996
4997                if (rc6_mode & INTEL_RC6pp_ENABLE)
4998                        rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4999        }
5000
5001        intel_print_rc6_info(dev, rc6_mask);
5002
5003        I915_WRITE(GEN6_RC_CONTROL,
5004                   rc6_mask |
5005                   GEN6_RC_CTL_EI_MODE(1) |
5006                   GEN6_RC_CTL_HW_ENABLE);
5007
5008        /* Power down if completely idle for over 50ms */
5009        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5010        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5011
5012        ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5013        if (ret)
5014                DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5015
5016        ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5017        if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5018                DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5019                                 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5020                                 (pcu_mbox & 0xff) * 50);
5021                dev_priv->rps.max_freq = pcu_mbox & 0xff;
5022        }
5023
5024        dev_priv->rps.power = HIGH_POWER; /* force a reset */
5025        gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5026
5027        rc6vids = 0;
5028        ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5029        if (IS_GEN6(dev) && ret) {
5030                DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5031        } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5032                DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5033                          GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5034                rc6vids &= 0xffff00;
5035                rc6vids |= GEN6_ENCODE_RC6_VID(450);
5036                ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5037                if (ret)
5038                        DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5039        }
5040
5041        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5042}
5043
5044static void __gen6_update_ring_freq(struct drm_device *dev)
5045{
5046        struct drm_i915_private *dev_priv = dev->dev_private;
5047        int min_freq = 15;
5048        unsigned int gpu_freq;
5049        unsigned int max_ia_freq, min_ring_freq;
5050        unsigned int max_gpu_freq, min_gpu_freq;
5051        int scaling_factor = 180;
5052        struct cpufreq_policy *policy;
5053
5054        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5055
5056        policy = cpufreq_cpu_get(0);
5057        if (policy) {
5058                max_ia_freq = policy->cpuinfo.max_freq;
5059                cpufreq_cpu_put(policy);
5060        } else {
5061                /*
5062                 * Default to measured freq if none found, PCU will ensure we
5063                 * don't go over
5064                 */
5065                max_ia_freq = tsc_khz;
5066        }
5067
5068        /* Convert from kHz to MHz */
5069        max_ia_freq /= 1000;
5070
5071        min_ring_freq = I915_READ(DCLK) & 0xf;
5072        /* convert DDR frequency from units of 266.6MHz to bandwidth */
5073        min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5074
5075        if (IS_SKYLAKE(dev)) {
5076                /* Convert GT frequency to 50 HZ units */
5077                min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5078                max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5079        } else {
5080                min_gpu_freq = dev_priv->rps.min_freq;
5081                max_gpu_freq = dev_priv->rps.max_freq;
5082        }
5083
5084        /*
5085         * For each potential GPU frequency, load a ring frequency we'd like
5086         * to use for memory access.  We do this by specifying the IA frequency
5087         * the PCU should use as a reference to determine the ring frequency.
5088         */
5089        for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5090                int diff = max_gpu_freq - gpu_freq;
5091                unsigned int ia_freq = 0, ring_freq = 0;
5092
5093                if (IS_SKYLAKE(dev)) {
5094                        /*
5095                         * ring_freq = 2 * GT. ring_freq is in 100MHz units
5096                         * No floor required for ring frequency on SKL.
5097                         */
5098                        ring_freq = gpu_freq;
5099                } else if (INTEL_INFO(dev)->gen >= 8) {
5100                        /* max(2 * GT, DDR). NB: GT is 50MHz units */
5101                        ring_freq = max(min_ring_freq, gpu_freq);
5102                } else if (IS_HASWELL(dev)) {
5103                        ring_freq = mult_frac(gpu_freq, 5, 4);
5104                        ring_freq = max(min_ring_freq, ring_freq);
5105                        /* leave ia_freq as the default, chosen by cpufreq */
5106                } else {
5107                        /* On older processors, there is no separate ring
5108                         * clock domain, so in order to boost the bandwidth
5109                         * of the ring, we need to upclock the CPU (ia_freq).
5110                         *
5111                         * For GPU frequencies less than 750MHz,
5112                         * just use the lowest ring freq.
5113                         */
5114                        if (gpu_freq < min_freq)
5115                                ia_freq = 800;
5116                        else
5117                                ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5118                        ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5119                }
5120
5121                sandybridge_pcode_write(dev_priv,
5122                                        GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5123                                        ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5124                                        ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5125                                        gpu_freq);
5126        }
5127}
5128
5129void gen6_update_ring_freq(struct drm_device *dev)
5130{
5131        struct drm_i915_private *dev_priv = dev->dev_private;
5132
5133        if (!HAS_CORE_RING_FREQ(dev))
5134                return;
5135
5136        mutex_lock(&dev_priv->rps.hw_lock);
5137        __gen6_update_ring_freq(dev);
5138        mutex_unlock(&dev_priv->rps.hw_lock);
5139}
5140
5141static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5142{
5143        struct drm_device *dev = dev_priv->dev;
5144        u32 val, rp0;
5145
5146        val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5147
5148        switch (INTEL_INFO(dev)->eu_total) {
5149        case 8:
5150                /* (2 * 4) config */
5151                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5152                break;
5153        case 12:
5154                /* (2 * 6) config */
5155                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5156                break;
5157        case 16:
5158                /* (2 * 8) config */
5159        default:
5160                /* Setting (2 * 8) Min RP0 for any other combination */
5161                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5162                break;
5163        }
5164
5165        rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5166
5167        return rp0;
5168}
5169
5170static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5171{
5172        u32 val, rpe;
5173
5174        val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5175        rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5176
5177        return rpe;
5178}
5179
5180static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5181{
5182        u32 val, rp1;
5183
5184        val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5185        rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5186
5187        return rp1;
5188}
5189
5190static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5191{
5192        u32 val, rp1;
5193
5194        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5195
5196        rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5197
5198        return rp1;
5199}
5200
5201static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5202{
5203        u32 val, rp0;
5204
5205        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5206
5207        rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5208        /* Clamp to max */
5209        rp0 = min_t(u32, rp0, 0xea);
5210
5211        return rp0;
5212}
5213
5214static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5215{
5216        u32 val, rpe;
5217
5218        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5219        rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5220        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5221        rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5222
5223        return rpe;
5224}
5225
5226static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5227{
5228        return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5229}
5230
5231/* Check that the pctx buffer wasn't move under us. */
5232static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5233{
5234        unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5235
5236        WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5237                             dev_priv->vlv_pctx->stolen->start);
5238}
5239
5240
5241/* Check that the pcbr address is not empty. */
5242static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5243{
5244        unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5245
5246        WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5247}
5248
5249static void cherryview_setup_pctx(struct drm_device *dev)
5250{
5251        struct drm_i915_private *dev_priv = dev->dev_private;
5252        unsigned long pctx_paddr, paddr;
5253        struct i915_gtt *gtt = &dev_priv->gtt;
5254        u32 pcbr;
5255        int pctx_size = 32*1024;
5256
5257        WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5258
5259        pcbr = I915_READ(VLV_PCBR);
5260        if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5261                DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5262                paddr = (dev_priv->mm.stolen_base +
5263                         (gtt->stolen_size - pctx_size));
5264
5265                pctx_paddr = (paddr & (~4095));
5266                I915_WRITE(VLV_PCBR, pctx_paddr);
5267        }
5268
5269        DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5270}
5271
5272static void valleyview_setup_pctx(struct drm_device *dev)
5273{
5274        struct drm_i915_private *dev_priv = dev->dev_private;
5275        struct drm_i915_gem_object *pctx;
5276        unsigned long pctx_paddr;
5277        u32 pcbr;
5278        int pctx_size = 24*1024;
5279
5280        WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5281
5282        pcbr = I915_READ(VLV_PCBR);
5283        if (pcbr) {
5284                /* BIOS set it up already, grab the pre-alloc'd space */
5285                int pcbr_offset;
5286
5287                pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5288                pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5289                                                                      pcbr_offset,
5290                                                                      I915_GTT_OFFSET_NONE,
5291                                                                      pctx_size);
5292                goto out;
5293        }
5294
5295        DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5296
5297        /*
5298         * From the Gunit register HAS:
5299         * The Gfx driver is expected to program this register and ensure
5300         * proper allocation within Gfx stolen memory.  For example, this
5301         * register should be programmed such than the PCBR range does not
5302         * overlap with other ranges, such as the frame buffer, protected
5303         * memory, or any other relevant ranges.
5304         */
5305        pctx = i915_gem_object_create_stolen(dev, pctx_size);
5306        if (!pctx) {
5307                DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5308                return;
5309        }
5310
5311        pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5312        I915_WRITE(VLV_PCBR, pctx_paddr);
5313
5314out:
5315        DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5316        dev_priv->vlv_pctx = pctx;
5317}
5318
5319static void valleyview_cleanup_pctx(struct drm_device *dev)
5320{
5321        struct drm_i915_private *dev_priv = dev->dev_private;
5322
5323        if (WARN_ON(!dev_priv->vlv_pctx))
5324                return;
5325
5326        drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5327        dev_priv->vlv_pctx = NULL;
5328}
5329
5330static void valleyview_init_gt_powersave(struct drm_device *dev)
5331{
5332        struct drm_i915_private *dev_priv = dev->dev_private;
5333        u32 val;
5334
5335        valleyview_setup_pctx(dev);
5336
5337        mutex_lock(&dev_priv->rps.hw_lock);
5338
5339        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5340        switch ((val >> 6) & 3) {
5341        case 0:
5342        case 1:
5343                dev_priv->mem_freq = 800;
5344                break;
5345        case 2:
5346                dev_priv->mem_freq = 1066;
5347                break;
5348        case 3:
5349                dev_priv->mem_freq = 1333;
5350                break;
5351        }
5352        DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5353
5354        dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5355        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5356        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5357                         intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5358                         dev_priv->rps.max_freq);
5359
5360        dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5361        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5362                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5363                         dev_priv->rps.efficient_freq);
5364
5365        dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5366        DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5367                         intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5368                         dev_priv->rps.rp1_freq);
5369
5370        dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5371        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5372                         intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5373                         dev_priv->rps.min_freq);
5374
5375        dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5376
5377        /* Preserve min/max settings in case of re-init */
5378        if (dev_priv->rps.max_freq_softlimit == 0)
5379                dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5380
5381        if (dev_priv->rps.min_freq_softlimit == 0)
5382                dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5383
5384        mutex_unlock(&dev_priv->rps.hw_lock);
5385}
5386
5387static void cherryview_init_gt_powersave(struct drm_device *dev)
5388{
5389        struct drm_i915_private *dev_priv = dev->dev_private;
5390        u32 val;
5391
5392        cherryview_setup_pctx(dev);
5393
5394        mutex_lock(&dev_priv->rps.hw_lock);
5395
5396        mutex_lock(&dev_priv->sb_lock);
5397        val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5398        mutex_unlock(&dev_priv->sb_lock);
5399
5400        switch ((val >> 2) & 0x7) {
5401        case 3:
5402                dev_priv->mem_freq = 2000;
5403                break;
5404        default:
5405                dev_priv->mem_freq = 1600;
5406                break;
5407        }
5408        DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5409
5410        dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5411        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5412        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5413                         intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5414                         dev_priv->rps.max_freq);
5415
5416        dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5417        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5418                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5419                         dev_priv->rps.efficient_freq);
5420
5421        dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5422        DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5423                         intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5424                         dev_priv->rps.rp1_freq);
5425
5426        /* PUnit validated range is only [RPe, RP0] */
5427        dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5428        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5429                         intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5430                         dev_priv->rps.min_freq);
5431
5432        WARN_ONCE((dev_priv->rps.max_freq |
5433                   dev_priv->rps.efficient_freq |
5434                   dev_priv->rps.rp1_freq |
5435                   dev_priv->rps.min_freq) & 1,
5436                  "Odd GPU freq values\n");
5437
5438        dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5439
5440        /* Preserve min/max settings in case of re-init */
5441        if (dev_priv->rps.max_freq_softlimit == 0)
5442                dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5443
5444        if (dev_priv->rps.min_freq_softlimit == 0)
5445                dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5446
5447        mutex_unlock(&dev_priv->rps.hw_lock);
5448}
5449
5450static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5451{
5452        valleyview_cleanup_pctx(dev);
5453}
5454
5455static void cherryview_enable_rps(struct drm_device *dev)
5456{
5457        struct drm_i915_private *dev_priv = dev->dev_private;
5458        struct intel_engine_cs *ring;
5459        u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5460        int i;
5461
5462        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5463
5464        gtfifodbg = I915_READ(GTFIFODBG);
5465        if (gtfifodbg) {
5466                DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5467                                 gtfifodbg);
5468                I915_WRITE(GTFIFODBG, gtfifodbg);
5469        }
5470
5471        cherryview_check_pctx(dev_priv);
5472
5473        /* 1a & 1b: Get forcewake during program sequence. Although the driver
5474         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5475        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5476
5477        /*  Disable RC states. */
5478        I915_WRITE(GEN6_RC_CONTROL, 0);
5479
5480        /* 2a: Program RC6 thresholds.*/
5481        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5482        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5483        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5484
5485        for_each_ring(ring, dev_priv, i)
5486                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5487        I915_WRITE(GEN6_RC_SLEEP, 0);
5488
5489        /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5490        I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5491
5492        /* allows RC6 residency counter to work */
5493        I915_WRITE(VLV_COUNTER_CONTROL,
5494                   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5495                                      VLV_MEDIA_RC6_COUNT_EN |
5496                                      VLV_RENDER_RC6_COUNT_EN));
5497
5498        /* For now we assume BIOS is allocating and populating the PCBR  */
5499        pcbr = I915_READ(VLV_PCBR);
5500
5501        /* 3: Enable RC6 */
5502        if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5503                                                (pcbr >> VLV_PCBR_ADDR_SHIFT))
5504                rc6_mode = GEN7_RC_CTL_TO_MODE;
5505
5506        I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5507
5508        /* 4 Program defaults and thresholds for RPS*/
5509        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5510        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5511        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5512        I915_WRITE(GEN6_RP_UP_EI, 66000);
5513        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5514
5515        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5516
5517        /* 5: Enable RPS */
5518        I915_WRITE(GEN6_RP_CONTROL,
5519                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
5520                   GEN6_RP_MEDIA_IS_GFX |
5521                   GEN6_RP_ENABLE |
5522                   GEN6_RP_UP_BUSY_AVG |
5523                   GEN6_RP_DOWN_IDLE_AVG);
5524
5525        /* Setting Fixed Bias */
5526        val = VLV_OVERRIDE_EN |
5527                  VLV_SOC_TDP_EN |
5528                  CHV_BIAS_CPU_50_SOC_50;
5529        vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5530
5531        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5532
5533        /* RPS code assumes GPLL is used */
5534        WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5535
5536        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5537        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5538
5539        dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5540        DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5541                         intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5542                         dev_priv->rps.cur_freq);
5543
5544        DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5545                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5546                         dev_priv->rps.efficient_freq);
5547
5548        valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5549
5550        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5551}
5552
5553static void valleyview_enable_rps(struct drm_device *dev)
5554{
5555        struct drm_i915_private *dev_priv = dev->dev_private;
5556        struct intel_engine_cs *ring;
5557        u32 gtfifodbg, val, rc6_mode = 0;
5558        int i;
5559
5560        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5561
5562        valleyview_check_pctx(dev_priv);
5563
5564        if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5565                DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5566                                 gtfifodbg);
5567                I915_WRITE(GTFIFODBG, gtfifodbg);
5568        }
5569
5570        /* If VLV, Forcewake all wells, else re-direct to regular path */
5571        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5572
5573        /*  Disable RC states. */
5574        I915_WRITE(GEN6_RC_CONTROL, 0);
5575
5576        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5577        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5578        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5579        I915_WRITE(GEN6_RP_UP_EI, 66000);
5580        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5581
5582        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5583
5584        I915_WRITE(GEN6_RP_CONTROL,
5585                   GEN6_RP_MEDIA_TURBO |
5586                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
5587                   GEN6_RP_MEDIA_IS_GFX |
5588                   GEN6_RP_ENABLE |
5589                   GEN6_RP_UP_BUSY_AVG |
5590                   GEN6_RP_DOWN_IDLE_CONT);
5591
5592        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5593        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5594        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5595
5596        for_each_ring(ring, dev_priv, i)
5597                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5598
5599        I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5600
5601        /* allows RC6 residency counter to work */
5602        I915_WRITE(VLV_COUNTER_CONTROL,
5603                   _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5604                                      VLV_RENDER_RC0_COUNT_EN |
5605                                      VLV_MEDIA_RC6_COUNT_EN |
5606                                      VLV_RENDER_RC6_COUNT_EN));
5607
5608        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5609                rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5610
5611        intel_print_rc6_info(dev, rc6_mode);
5612
5613        I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5614
5615        /* Setting Fixed Bias */
5616        val = VLV_OVERRIDE_EN |
5617                  VLV_SOC_TDP_EN |
5618                  VLV_BIAS_CPU_125_SOC_875;
5619        vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5620
5621        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5622
5623        /* RPS code assumes GPLL is used */
5624        WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5625
5626        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5627        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5628
5629        dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5630        DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5631                         intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5632                         dev_priv->rps.cur_freq);
5633
5634        DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5635                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5636                         dev_priv->rps.efficient_freq);
5637
5638        valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5639
5640        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5641}
5642
5643static unsigned long intel_pxfreq(u32 vidfreq)
5644{
5645        unsigned long freq;
5646        int div = (vidfreq & 0x3f0000) >> 16;
5647        int post = (vidfreq & 0x3000) >> 12;
5648        int pre = (vidfreq & 0x7);
5649
5650        if (!pre)
5651                return 0;
5652
5653        freq = ((div * 133333) / ((1<<post) * pre));
5654
5655        return freq;
5656}
5657
5658static const struct cparams {
5659        u16 i;
5660        u16 t;
5661        u16 m;
5662        u16 c;
5663} cparams[] = {
5664        { 1, 1333, 301, 28664 },
5665        { 1, 1066, 294, 24460 },
5666        { 1, 800, 294, 25192 },
5667        { 0, 1333, 276, 27605 },
5668        { 0, 1066, 276, 27605 },
5669        { 0, 800, 231, 23784 },
5670};
5671
5672static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5673{
5674        u64 total_count, diff, ret;
5675        u32 count1, count2, count3, m = 0, c = 0;
5676        unsigned long now = jiffies_to_msecs(jiffies), diff1;
5677        int i;
5678
5679        assert_spin_locked(&mchdev_lock);
5680
5681        diff1 = now - dev_priv->ips.last_time1;
5682
5683        /* Prevent division-by-zero if we are asking too fast.
5684         * Also, we don't get interesting results if we are polling
5685         * faster than once in 10ms, so just return the saved value
5686         * in such cases.
5687         */
5688        if (diff1 <= 10)
5689                return dev_priv->ips.chipset_power;
5690
5691        count1 = I915_READ(DMIEC);
5692        count2 = I915_READ(DDREC);
5693        count3 = I915_READ(CSIEC);
5694
5695        total_count = count1 + count2 + count3;
5696
5697        /* FIXME: handle per-counter overflow */
5698        if (total_count < dev_priv->ips.last_count1) {
5699                diff = ~0UL - dev_priv->ips.last_count1;
5700                diff += total_count;
5701        } else {
5702                diff = total_count - dev_priv->ips.last_count1;
5703        }
5704
5705        for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5706                if (cparams[i].i == dev_priv->ips.c_m &&
5707                    cparams[i].t == dev_priv->ips.r_t) {
5708                        m = cparams[i].m;
5709                        c = cparams[i].c;
5710                        break;
5711                }
5712        }
5713
5714        diff = div_u64(diff, diff1);
5715        ret = ((m * diff) + c);
5716        ret = div_u64(ret, 10);
5717
5718        dev_priv->ips.last_count1 = total_count;
5719        dev_priv->ips.last_time1 = now;
5720
5721        dev_priv->ips.chipset_power = ret;
5722
5723        return ret;
5724}
5725
5726unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5727{
5728        struct drm_device *dev = dev_priv->dev;
5729        unsigned long val;
5730
5731        if (INTEL_INFO(dev)->gen != 5)
5732                return 0;
5733
5734        spin_lock_irq(&mchdev_lock);
5735
5736        val = __i915_chipset_val(dev_priv);
5737
5738        spin_unlock_irq(&mchdev_lock);
5739
5740        return val;
5741}
5742
5743unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5744{
5745        unsigned long m, x, b;
5746        u32 tsfs;
5747
5748        tsfs = I915_READ(TSFS);
5749
5750        m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5751        x = I915_READ8(TR1);
5752
5753        b = tsfs & TSFS_INTR_MASK;
5754
5755        return ((m * x) / 127) - b;
5756}
5757
5758static int _pxvid_to_vd(u8 pxvid)
5759{
5760        if (pxvid == 0)
5761                return 0;
5762
5763        if (pxvid >= 8 && pxvid < 31)
5764                pxvid = 31;
5765
5766        return (pxvid + 2) * 125;
5767}
5768
5769static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5770{
5771        struct drm_device *dev = dev_priv->dev;
5772        const int vd = _pxvid_to_vd(pxvid);
5773        const int vm = vd - 1125;
5774
5775        if (INTEL_INFO(dev)->is_mobile)
5776                return vm > 0 ? vm : 0;
5777
5778        return vd;
5779}
5780
5781static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5782{
5783        u64 now, diff, diffms;
5784        u32 count;
5785
5786        assert_spin_locked(&mchdev_lock);
5787
5788        now = ktime_get_raw_ns();
5789        diffms = now - dev_priv->ips.last_time2;
5790        do_div(diffms, NSEC_PER_MSEC);
5791
5792        /* Don't divide by 0 */
5793        if (!diffms)
5794                return;
5795
5796        count = I915_READ(GFXEC);
5797
5798        if (count < dev_priv->ips.last_count2) {
5799                diff = ~0UL - dev_priv->ips.last_count2;
5800                diff += count;
5801        } else {
5802                diff = count - dev_priv->ips.last_count2;
5803        }
5804
5805        dev_priv->ips.last_count2 = count;
5806        dev_priv->ips.last_time2 = now;
5807
5808        /* More magic constants... */
5809        diff = diff * 1181;
5810        diff = div_u64(diff, diffms * 10);
5811        dev_priv->ips.gfx_power = diff;
5812}
5813
5814void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5815{
5816        struct drm_device *dev = dev_priv->dev;
5817
5818        if (INTEL_INFO(dev)->gen != 5)
5819                return;
5820
5821        spin_lock_irq(&mchdev_lock);
5822
5823        __i915_update_gfx_val(dev_priv);
5824
5825        spin_unlock_irq(&mchdev_lock);
5826}
5827
5828static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5829{
5830        unsigned long t, corr, state1, corr2, state2;
5831        u32 pxvid, ext_v;
5832
5833        assert_spin_locked(&mchdev_lock);
5834
5835        pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5836        pxvid = (pxvid >> 24) & 0x7f;
5837        ext_v = pvid_to_extvid(dev_priv, pxvid);
5838
5839        state1 = ext_v;
5840
5841        t = i915_mch_val(dev_priv);
5842
5843        /* Revel in the empirically derived constants */
5844
5845        /* Correction factor in 1/100000 units */
5846        if (t > 80)
5847                corr = ((t * 2349) + 135940);
5848        else if (t >= 50)
5849                corr = ((t * 964) + 29317);
5850        else /* < 50 */
5851                corr = ((t * 301) + 1004);
5852
5853        corr = corr * ((150142 * state1) / 10000 - 78642);
5854        corr /= 100000;
5855        corr2 = (corr * dev_priv->ips.corr);
5856
5857        state2 = (corr2 * state1) / 10000;
5858        state2 /= 100; /* convert to mW */
5859
5860        __i915_update_gfx_val(dev_priv);
5861
5862        return dev_priv->ips.gfx_power + state2;
5863}
5864
5865unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5866{
5867        struct drm_device *dev = dev_priv->dev;
5868        unsigned long val;
5869
5870        if (INTEL_INFO(dev)->gen != 5)
5871                return 0;
5872
5873        spin_lock_irq(&mchdev_lock);
5874
5875        val = __i915_gfx_val(dev_priv);
5876
5877        spin_unlock_irq(&mchdev_lock);
5878
5879        return val;
5880}
5881
5882/**
5883 * i915_read_mch_val - return value for IPS use
5884 *
5885 * Calculate and return a value for the IPS driver to use when deciding whether
5886 * we have thermal and power headroom to increase CPU or GPU power budget.
5887 */
5888unsigned long i915_read_mch_val(void)
5889{
5890        struct drm_i915_private *dev_priv;
5891        unsigned long chipset_val, graphics_val, ret = 0;
5892
5893        spin_lock_irq(&mchdev_lock);
5894        if (!i915_mch_dev)
5895                goto out_unlock;
5896        dev_priv = i915_mch_dev;
5897
5898        chipset_val = __i915_chipset_val(dev_priv);
5899        graphics_val = __i915_gfx_val(dev_priv);
5900
5901        ret = chipset_val + graphics_val;
5902
5903out_unlock:
5904        spin_unlock_irq(&mchdev_lock);
5905
5906        return ret;
5907}
5908EXPORT_SYMBOL_GPL(i915_read_mch_val);
5909
5910/**
5911 * i915_gpu_raise - raise GPU frequency limit
5912 *
5913 * Raise the limit; IPS indicates we have thermal headroom.
5914 */
5915bool i915_gpu_raise(void)
5916{
5917        struct drm_i915_private *dev_priv;
5918        bool ret = true;
5919
5920        spin_lock_irq(&mchdev_lock);
5921        if (!i915_mch_dev) {
5922                ret = false;
5923                goto out_unlock;
5924        }
5925        dev_priv = i915_mch_dev;
5926
5927        if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5928                dev_priv->ips.max_delay--;
5929
5930out_unlock:
5931        spin_unlock_irq(&mchdev_lock);
5932
5933        return ret;
5934}
5935EXPORT_SYMBOL_GPL(i915_gpu_raise);
5936
5937/**
5938 * i915_gpu_lower - lower GPU frequency limit
5939 *
5940 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5941 * frequency maximum.
5942 */
5943bool i915_gpu_lower(void)
5944{
5945        struct drm_i915_private *dev_priv;
5946        bool ret = true;
5947
5948        spin_lock_irq(&mchdev_lock);
5949        if (!i915_mch_dev) {
5950                ret = false;
5951                goto out_unlock;
5952        }
5953        dev_priv = i915_mch_dev;
5954
5955        if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5956                dev_priv->ips.max_delay++;
5957
5958out_unlock:
5959        spin_unlock_irq(&mchdev_lock);
5960
5961        return ret;
5962}
5963EXPORT_SYMBOL_GPL(i915_gpu_lower);
5964
5965/**
5966 * i915_gpu_busy - indicate GPU business to IPS
5967 *
5968 * Tell the IPS driver whether or not the GPU is busy.
5969 */
5970bool i915_gpu_busy(void)
5971{
5972        struct drm_i915_private *dev_priv;
5973        struct intel_engine_cs *ring;
5974        bool ret = false;
5975        int i;
5976
5977        spin_lock_irq(&mchdev_lock);
5978        if (!i915_mch_dev)
5979                goto out_unlock;
5980        dev_priv = i915_mch_dev;
5981
5982        for_each_ring(ring, dev_priv, i)
5983                ret |= !list_empty(&ring->request_list);
5984
5985out_unlock:
5986        spin_unlock_irq(&mchdev_lock);
5987
5988        return ret;
5989}
5990EXPORT_SYMBOL_GPL(i915_gpu_busy);
5991
5992/**
5993 * i915_gpu_turbo_disable - disable graphics turbo
5994 *
5995 * Disable graphics turbo by resetting the max frequency and setting the
5996 * current frequency to the default.
5997 */
5998bool i915_gpu_turbo_disable(void)
5999{
6000        struct drm_i915_private *dev_priv;
6001        bool ret = true;
6002
6003        spin_lock_irq(&mchdev_lock);
6004        if (!i915_mch_dev) {
6005                ret = false;
6006                goto out_unlock;
6007        }
6008        dev_priv = i915_mch_dev;
6009
6010        dev_priv->ips.max_delay = dev_priv->ips.fstart;
6011
6012        if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6013                ret = false;
6014
6015out_unlock:
6016        spin_unlock_irq(&mchdev_lock);
6017
6018        return ret;
6019}
6020EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6021
6022/**
6023 * Tells the intel_ips driver that the i915 driver is now loaded, if
6024 * IPS got loaded first.
6025 *
6026 * This awkward dance is so that neither module has to depend on the
6027 * other in order for IPS to do the appropriate communication of
6028 * GPU turbo limits to i915.
6029 */
6030static void
6031ips_ping_for_i915_load(void)
6032{
6033        void (*link)(void);
6034
6035        link = symbol_get(ips_link_to_i915_driver);
6036        if (link) {
6037                link();
6038                symbol_put(ips_link_to_i915_driver);
6039        }
6040}
6041
6042void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6043{
6044        /* We only register the i915 ips part with intel-ips once everything is
6045         * set up, to avoid intel-ips sneaking in and reading bogus values. */
6046        spin_lock_irq(&mchdev_lock);
6047        i915_mch_dev = dev_priv;
6048        spin_unlock_irq(&mchdev_lock);
6049
6050        ips_ping_for_i915_load();
6051}
6052
6053void intel_gpu_ips_teardown(void)
6054{
6055        spin_lock_irq(&mchdev_lock);
6056        i915_mch_dev = NULL;
6057        spin_unlock_irq(&mchdev_lock);
6058}
6059
6060static void intel_init_emon(struct drm_device *dev)
6061{
6062        struct drm_i915_private *dev_priv = dev->dev_private;
6063        u32 lcfuse;
6064        u8 pxw[16];
6065        int i;
6066
6067        /* Disable to program */
6068        I915_WRITE(ECR, 0);
6069        POSTING_READ(ECR);
6070
6071        /* Program energy weights for various events */
6072        I915_WRITE(SDEW, 0x15040d00);
6073        I915_WRITE(CSIEW0, 0x007f0000);
6074        I915_WRITE(CSIEW1, 0x1e220004);
6075        I915_WRITE(CSIEW2, 0x04000004);
6076
6077        for (i = 0; i < 5; i++)
6078                I915_WRITE(PEW(i), 0);
6079        for (i = 0; i < 3; i++)
6080                I915_WRITE(DEW(i), 0);
6081
6082        /* Program P-state weights to account for frequency power adjustment */
6083        for (i = 0; i < 16; i++) {
6084                u32 pxvidfreq = I915_READ(PXVFREQ(i));
6085                unsigned long freq = intel_pxfreq(pxvidfreq);
6086                unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6087                        PXVFREQ_PX_SHIFT;
6088                unsigned long val;
6089
6090                val = vid * vid;
6091                val *= (freq / 1000);
6092                val *= 255;
6093                val /= (127*127*900);
6094                if (val > 0xff)
6095                        DRM_ERROR("bad pxval: %ld\n", val);
6096                pxw[i] = val;
6097        }
6098        /* Render standby states get 0 weight */
6099        pxw[14] = 0;
6100        pxw[15] = 0;
6101
6102        for (i = 0; i < 4; i++) {
6103                u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6104                        (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6105                I915_WRITE(PXW(i), val);
6106        }
6107
6108        /* Adjust magic regs to magic values (more experimental results) */
6109        I915_WRITE(OGW0, 0);
6110        I915_WRITE(OGW1, 0);
6111        I915_WRITE(EG0, 0x00007f00);
6112        I915_WRITE(EG1, 0x0000000e);
6113        I915_WRITE(EG2, 0x000e0000);
6114        I915_WRITE(EG3, 0x68000300);
6115        I915_WRITE(EG4, 0x42000000);
6116        I915_WRITE(EG5, 0x00140031);
6117        I915_WRITE(EG6, 0);
6118        I915_WRITE(EG7, 0);
6119
6120        for (i = 0; i < 8; i++)
6121                I915_WRITE(PXWL(i), 0);
6122
6123        /* Enable PMON + select events */
6124        I915_WRITE(ECR, 0x80000019);
6125
6126        lcfuse = I915_READ(LCFUSE02);
6127
6128        dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6129}
6130
6131void intel_init_gt_powersave(struct drm_device *dev)
6132{
6133        i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6134
6135        if (IS_CHERRYVIEW(dev))
6136                cherryview_init_gt_powersave(dev);
6137        else if (IS_VALLEYVIEW(dev))
6138                valleyview_init_gt_powersave(dev);
6139}
6140
6141void intel_cleanup_gt_powersave(struct drm_device *dev)
6142{
6143        if (IS_CHERRYVIEW(dev))
6144                return;
6145        else if (IS_VALLEYVIEW(dev))
6146                valleyview_cleanup_gt_powersave(dev);
6147}
6148
6149static void gen6_suspend_rps(struct drm_device *dev)
6150{
6151        struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6154
6155        gen6_disable_rps_interrupts(dev);
6156}
6157
6158/**
6159 * intel_suspend_gt_powersave - suspend PM work and helper threads
6160 * @dev: drm device
6161 *
6162 * We don't want to disable RC6 or other features here, we just want
6163 * to make sure any work we've queued has finished and won't bother
6164 * us while we're suspended.
6165 */
6166void intel_suspend_gt_powersave(struct drm_device *dev)
6167{
6168        struct drm_i915_private *dev_priv = dev->dev_private;
6169
6170        if (INTEL_INFO(dev)->gen < 6)
6171                return;
6172
6173        gen6_suspend_rps(dev);
6174
6175        /* Force GPU to min freq during suspend */
6176        gen6_rps_idle(dev_priv);
6177}
6178
6179void intel_disable_gt_powersave(struct drm_device *dev)
6180{
6181        struct drm_i915_private *dev_priv = dev->dev_private;
6182
6183        if (IS_IRONLAKE_M(dev)) {
6184                ironlake_disable_drps(dev);
6185        } else if (INTEL_INFO(dev)->gen >= 6) {
6186                intel_suspend_gt_powersave(dev);
6187
6188                mutex_lock(&dev_priv->rps.hw_lock);
6189                if (INTEL_INFO(dev)->gen >= 9)
6190                        gen9_disable_rps(dev);
6191                else if (IS_CHERRYVIEW(dev))
6192                        cherryview_disable_rps(dev);
6193                else if (IS_VALLEYVIEW(dev))
6194                        valleyview_disable_rps(dev);
6195                else
6196                        gen6_disable_rps(dev);
6197
6198                dev_priv->rps.enabled = false;
6199                mutex_unlock(&dev_priv->rps.hw_lock);
6200        }
6201}
6202
6203static void intel_gen6_powersave_work(struct work_struct *work)
6204{
6205        struct drm_i915_private *dev_priv =
6206                container_of(work, struct drm_i915_private,
6207                             rps.delayed_resume_work.work);
6208        struct drm_device *dev = dev_priv->dev;
6209
6210        mutex_lock(&dev_priv->rps.hw_lock);
6211
6212        gen6_reset_rps_interrupts(dev);
6213
6214        if (IS_CHERRYVIEW(dev)) {
6215                cherryview_enable_rps(dev);
6216        } else if (IS_VALLEYVIEW(dev)) {
6217                valleyview_enable_rps(dev);
6218        } else if (INTEL_INFO(dev)->gen >= 9) {
6219                gen9_enable_rc6(dev);
6220                gen9_enable_rps(dev);
6221                if (IS_SKYLAKE(dev))
6222                        __gen6_update_ring_freq(dev);
6223        } else if (IS_BROADWELL(dev)) {
6224                gen8_enable_rps(dev);
6225                __gen6_update_ring_freq(dev);
6226        } else {
6227                gen6_enable_rps(dev);
6228                __gen6_update_ring_freq(dev);
6229        }
6230
6231        WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6232        WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6233
6234        WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6235        WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6236
6237        dev_priv->rps.enabled = true;
6238
6239        gen6_enable_rps_interrupts(dev);
6240
6241        mutex_unlock(&dev_priv->rps.hw_lock);
6242
6243        intel_runtime_pm_put(dev_priv);
6244}
6245
6246void intel_enable_gt_powersave(struct drm_device *dev)
6247{
6248        struct drm_i915_private *dev_priv = dev->dev_private;
6249
6250        /* Powersaving is controlled by the host when inside a VM */
6251        if (intel_vgpu_active(dev))
6252                return;
6253
6254        if (IS_IRONLAKE_M(dev)) {
6255                mutex_lock(&dev->struct_mutex);
6256                ironlake_enable_drps(dev);
6257                intel_init_emon(dev);
6258                mutex_unlock(&dev->struct_mutex);
6259        } else if (INTEL_INFO(dev)->gen >= 6) {
6260                /*
6261                 * PCU communication is slow and this doesn't need to be
6262                 * done at any specific time, so do this out of our fast path
6263                 * to make resume and init faster.
6264                 *
6265                 * We depend on the HW RC6 power context save/restore
6266                 * mechanism when entering D3 through runtime PM suspend. So
6267                 * disable RPM until RPS/RC6 is properly setup. We can only
6268                 * get here via the driver load/system resume/runtime resume
6269                 * paths, so the _noresume version is enough (and in case of
6270                 * runtime resume it's necessary).
6271                 */
6272                if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6273                                           round_jiffies_up_relative(HZ)))
6274                        intel_runtime_pm_get_noresume(dev_priv);
6275        }
6276}
6277
6278void intel_reset_gt_powersave(struct drm_device *dev)
6279{
6280        struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282        if (INTEL_INFO(dev)->gen < 6)
6283                return;
6284
6285        gen6_suspend_rps(dev);
6286        dev_priv->rps.enabled = false;
6287}
6288
6289static void ibx_init_clock_gating(struct drm_device *dev)
6290{
6291        struct drm_i915_private *dev_priv = dev->dev_private;
6292
6293        /*
6294         * On Ibex Peak and Cougar Point, we need to disable clock
6295         * gating for the panel power sequencer or it will fail to
6296         * start up when no ports are active.
6297         */
6298        I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6299}
6300
6301static void g4x_disable_trickle_feed(struct drm_device *dev)
6302{
6303        struct drm_i915_private *dev_priv = dev->dev_private;
6304        enum pipe pipe;
6305
6306        for_each_pipe(dev_priv, pipe) {
6307                I915_WRITE(DSPCNTR(pipe),
6308                           I915_READ(DSPCNTR(pipe)) |
6309                           DISPPLANE_TRICKLE_FEED_DISABLE);
6310
6311                I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6312                POSTING_READ(DSPSURF(pipe));
6313        }
6314}
6315
6316static void ilk_init_lp_watermarks(struct drm_device *dev)
6317{
6318        struct drm_i915_private *dev_priv = dev->dev_private;
6319
6320        I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6321        I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6322        I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6323
6324        /*
6325         * Don't touch WM1S_LP_EN here.
6326         * Doing so could cause underruns.
6327         */
6328}
6329
6330static void ironlake_init_clock_gating(struct drm_device *dev)
6331{
6332        struct drm_i915_private *dev_priv = dev->dev_private;
6333        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6334
6335        /*
6336         * Required for FBC
6337         * WaFbcDisableDpfcClockGating:ilk
6338         */
6339        dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6340                   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6341                   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6342
6343        I915_WRITE(PCH_3DCGDIS0,
6344                   MARIUNIT_CLOCK_GATE_DISABLE |
6345                   SVSMUNIT_CLOCK_GATE_DISABLE);
6346        I915_WRITE(PCH_3DCGDIS1,
6347                   VFMUNIT_CLOCK_GATE_DISABLE);
6348
6349        /*
6350         * According to the spec the following bits should be set in
6351         * order to enable memory self-refresh
6352         * The bit 22/21 of 0x42004
6353         * The bit 5 of 0x42020
6354         * The bit 15 of 0x45000
6355         */
6356        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6357                   (I915_READ(ILK_DISPLAY_CHICKEN2) |
6358                    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6359        dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6360        I915_WRITE(DISP_ARB_CTL,
6361                   (I915_READ(DISP_ARB_CTL) |
6362                    DISP_FBC_WM_DIS));
6363
6364        ilk_init_lp_watermarks(dev);
6365
6366        /*
6367         * Based on the document from hardware guys the following bits
6368         * should be set unconditionally in order to enable FBC.
6369         * The bit 22 of 0x42000
6370         * The bit 22 of 0x42004
6371         * The bit 7,8,9 of 0x42020.
6372         */
6373        if (IS_IRONLAKE_M(dev)) {
6374                /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6375                I915_WRITE(ILK_DISPLAY_CHICKEN1,
6376                           I915_READ(ILK_DISPLAY_CHICKEN1) |
6377                           ILK_FBCQ_DIS);
6378                I915_WRITE(ILK_DISPLAY_CHICKEN2,
6379                           I915_READ(ILK_DISPLAY_CHICKEN2) |
6380                           ILK_DPARB_GATE);
6381        }
6382
6383        I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6384
6385        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6386                   I915_READ(ILK_DISPLAY_CHICKEN2) |
6387                   ILK_ELPIN_409_SELECT);
6388        I915_WRITE(_3D_CHICKEN2,
6389                   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6390                   _3D_CHICKEN2_WM_READ_PIPELINED);
6391
6392        /* WaDisableRenderCachePipelinedFlush:ilk */
6393        I915_WRITE(CACHE_MODE_0,
6394                   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6395
6396        /* WaDisable_RenderCache_OperationalFlush:ilk */
6397        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6398
6399        g4x_disable_trickle_feed(dev);
6400
6401        ibx_init_clock_gating(dev);
6402}
6403
6404static void cpt_init_clock_gating(struct drm_device *dev)
6405{
6406        struct drm_i915_private *dev_priv = dev->dev_private;
6407        int pipe;
6408        uint32_t val;
6409
6410        /*
6411         * On Ibex Peak and Cougar Point, we need to disable clock
6412         * gating for the panel power sequencer or it will fail to
6413         * start up when no ports are active.
6414         */
6415        I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6416                   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6417                   PCH_CPUNIT_CLOCK_GATE_DISABLE);
6418        I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6419                   DPLS_EDP_PPS_FIX_DIS);
6420        /* The below fixes the weird display corruption, a few pixels shifted
6421         * downward, on (only) LVDS of some HP laptops with IVY.
6422         */
6423        for_each_pipe(dev_priv, pipe) {
6424                val = I915_READ(TRANS_CHICKEN2(pipe));
6425                val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6426                val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6427                if (dev_priv->vbt.fdi_rx_polarity_inverted)
6428                        val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6429                val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6430                val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6431                val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6432                I915_WRITE(TRANS_CHICKEN2(pipe), val);
6433        }
6434        /* WADP0ClockGatingDisable */
6435        for_each_pipe(dev_priv, pipe) {
6436                I915_WRITE(TRANS_CHICKEN1(pipe),
6437                           TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6438        }
6439}
6440
6441static void gen6_check_mch_setup(struct drm_device *dev)
6442{
6443        struct drm_i915_private *dev_priv = dev->dev_private;
6444        uint32_t tmp;
6445
6446        tmp = I915_READ(MCH_SSKPD);
6447        if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6448                DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6449                              tmp);
6450}
6451
6452static void gen6_init_clock_gating(struct drm_device *dev)
6453{
6454        struct drm_i915_private *dev_priv = dev->dev_private;
6455        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6456
6457        I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6458
6459        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6460                   I915_READ(ILK_DISPLAY_CHICKEN2) |
6461                   ILK_ELPIN_409_SELECT);
6462
6463        /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6464        I915_WRITE(_3D_CHICKEN,
6465                   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6466
6467        /* WaDisable_RenderCache_OperationalFlush:snb */
6468        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6469
6470        /*
6471         * BSpec recoomends 8x4 when MSAA is used,
6472         * however in practice 16x4 seems fastest.
6473         *
6474         * Note that PS/WM thread counts depend on the WIZ hashing
6475         * disable bit, which we don't touch here, but it's good
6476         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6477         */
6478        I915_WRITE(GEN6_GT_MODE,
6479                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6480
6481        ilk_init_lp_watermarks(dev);
6482
6483        I915_WRITE(CACHE_MODE_0,
6484                   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6485
6486        I915_WRITE(GEN6_UCGCTL1,
6487                   I915_READ(GEN6_UCGCTL1) |
6488                   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6489                   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6490
6491        /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6492         * gating disable must be set.  Failure to set it results in
6493         * flickering pixels due to Z write ordering failures after
6494         * some amount of runtime in the Mesa "fire" demo, and Unigine
6495         * Sanctuary and Tropics, and apparently anything else with
6496         * alpha test or pixel discard.
6497         *
6498         * According to the spec, bit 11 (RCCUNIT) must also be set,
6499         * but we didn't debug actual testcases to find it out.
6500         *
6501         * WaDisableRCCUnitClockGating:snb
6502         * WaDisableRCPBUnitClockGating:snb
6503         */
6504        I915_WRITE(GEN6_UCGCTL2,
6505                   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6506                   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6507
6508        /* WaStripsFansDisableFastClipPerformanceFix:snb */
6509        I915_WRITE(_3D_CHICKEN3,
6510                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6511
6512        /*
6513         * Bspec says:
6514         * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6515         * 3DSTATE_SF number of SF output attributes is more than 16."
6516         */
6517        I915_WRITE(_3D_CHICKEN3,
6518                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6519
6520        /*
6521         * According to the spec the following bits should be
6522         * set in order to enable memory self-refresh and fbc:
6523         * The bit21 and bit22 of 0x42000
6524         * The bit21 and bit22 of 0x42004
6525         * The bit5 and bit7 of 0x42020
6526         * The bit14 of 0x70180
6527         * The bit14 of 0x71180
6528         *
6529         * WaFbcAsynchFlipDisableFbcQueue:snb
6530         */
6531        I915_WRITE(ILK_DISPLAY_CHICKEN1,
6532                   I915_READ(ILK_DISPLAY_CHICKEN1) |
6533                   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6534        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6535                   I915_READ(ILK_DISPLAY_CHICKEN2) |
6536                   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6537        I915_WRITE(ILK_DSPCLK_GATE_D,
6538                   I915_READ(ILK_DSPCLK_GATE_D) |
6539                   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6540                   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6541
6542        g4x_disable_trickle_feed(dev);
6543
6544        cpt_init_clock_gating(dev);
6545
6546        gen6_check_mch_setup(dev);
6547}
6548
6549static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6550{
6551        uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6552
6553        /*
6554         * WaVSThreadDispatchOverride:ivb,vlv
6555         *
6556         * This actually overrides the dispatch
6557         * mode for all thread types.
6558         */
6559        reg &= ~GEN7_FF_SCHED_MASK;
6560        reg |= GEN7_FF_TS_SCHED_HW;
6561        reg |= GEN7_FF_VS_SCHED_HW;
6562        reg |= GEN7_FF_DS_SCHED_HW;
6563
6564        I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6565}
6566
6567static void lpt_init_clock_gating(struct drm_device *dev)
6568{
6569        struct drm_i915_private *dev_priv = dev->dev_private;
6570
6571        /*
6572         * TODO: this bit should only be enabled when really needed, then
6573         * disabled when not needed anymore in order to save power.
6574         */
6575        if (HAS_PCH_LPT_LP(dev))
6576                I915_WRITE(SOUTH_DSPCLK_GATE_D,
6577                           I915_READ(SOUTH_DSPCLK_GATE_D) |
6578                           PCH_LP_PARTITION_LEVEL_DISABLE);
6579
6580        /* WADPOClockGatingDisable:hsw */
6581        I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6582                   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6583                   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6584}
6585
6586static void lpt_suspend_hw(struct drm_device *dev)
6587{
6588        struct drm_i915_private *dev_priv = dev->dev_private;
6589
6590        if (HAS_PCH_LPT_LP(dev)) {
6591                uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6592
6593                val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6594                I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6595        }
6596}
6597
6598static void broadwell_init_clock_gating(struct drm_device *dev)
6599{
6600        struct drm_i915_private *dev_priv = dev->dev_private;
6601        enum pipe pipe;
6602        uint32_t misccpctl;
6603
6604        ilk_init_lp_watermarks(dev);
6605
6606        /* WaSwitchSolVfFArbitrationPriority:bdw */
6607        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6608
6609        /* WaPsrDPAMaskVBlankInSRD:bdw */
6610        I915_WRITE(CHICKEN_PAR1_1,
6611                   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6612
6613        /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6614        for_each_pipe(dev_priv, pipe) {
6615                I915_WRITE(CHICKEN_PIPESL_1(pipe),
6616                           I915_READ(CHICKEN_PIPESL_1(pipe)) |
6617                           BDW_DPRS_MASK_VBLANK_SRD);
6618        }
6619
6620        /* WaVSRefCountFullforceMissDisable:bdw */
6621        /* WaDSRefCountFullforceMissDisable:bdw */
6622        I915_WRITE(GEN7_FF_THREAD_MODE,
6623                   I915_READ(GEN7_FF_THREAD_MODE) &
6624                   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6625
6626        I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6627                   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6628
6629        /* WaDisableSDEUnitClockGating:bdw */
6630        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6631                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6632
6633        /*
6634         * WaProgramL3SqcReg1Default:bdw
6635         * WaTempDisableDOPClkGating:bdw
6636         */
6637        misccpctl = I915_READ(GEN7_MISCCPCTL);
6638        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6639        I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6640        /*
6641         * Wait at least 100 clocks before re-enabling clock gating. See
6642         * the definition of L3SQCREG1 in BSpec.
6643         */
6644        POSTING_READ(GEN8_L3SQCREG1);
6645        udelay(1);
6646        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6647
6648        /*
6649         * WaGttCachingOffByDefault:bdw
6650         * GTT cache may not work with big pages, so if those
6651         * are ever enabled GTT cache may need to be disabled.
6652         */
6653        I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6654
6655        lpt_init_clock_gating(dev);
6656}
6657
6658static void haswell_init_clock_gating(struct drm_device *dev)
6659{
6660        struct drm_i915_private *dev_priv = dev->dev_private;
6661
6662        ilk_init_lp_watermarks(dev);
6663
6664        /* L3 caching of data atomics doesn't work -- disable it. */
6665        I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6666        I915_WRITE(HSW_ROW_CHICKEN3,
6667                   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6668
6669        /* This is required by WaCatErrorRejectionIssue:hsw */
6670        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6671                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6672                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6673
6674        /* WaVSRefCountFullforceMissDisable:hsw */
6675        I915_WRITE(GEN7_FF_THREAD_MODE,
6676                   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6677
6678        /* WaDisable_RenderCache_OperationalFlush:hsw */
6679        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6680
6681        /* enable HiZ Raw Stall Optimization */
6682        I915_WRITE(CACHE_MODE_0_GEN7,
6683                   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6684
6685        /* WaDisable4x2SubspanOptimization:hsw */
6686        I915_WRITE(CACHE_MODE_1,
6687                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6688
6689        /*
6690         * BSpec recommends 8x4 when MSAA is used,
6691         * however in practice 16x4 seems fastest.
6692         *
6693         * Note that PS/WM thread counts depend on the WIZ hashing
6694         * disable bit, which we don't touch here, but it's good
6695         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6696         */
6697        I915_WRITE(GEN7_GT_MODE,
6698                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6699
6700        /* WaSampleCChickenBitEnable:hsw */
6701        I915_WRITE(HALF_SLICE_CHICKEN3,
6702                   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6703
6704        /* WaSwitchSolVfFArbitrationPriority:hsw */
6705        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6706
6707        /* WaRsPkgCStateDisplayPMReq:hsw */
6708        I915_WRITE(CHICKEN_PAR1_1,
6709                   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6710
6711        lpt_init_clock_gating(dev);
6712}
6713
6714static void ivybridge_init_clock_gating(struct drm_device *dev)
6715{
6716        struct drm_i915_private *dev_priv = dev->dev_private;
6717        uint32_t snpcr;
6718
6719        ilk_init_lp_watermarks(dev);
6720
6721        I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6722
6723        /* WaDisableEarlyCull:ivb */
6724        I915_WRITE(_3D_CHICKEN3,
6725                   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6726
6727        /* WaDisableBackToBackFlipFix:ivb */
6728        I915_WRITE(IVB_CHICKEN3,
6729                   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6730                   CHICKEN3_DGMG_DONE_FIX_DISABLE);
6731
6732        /* WaDisablePSDDualDispatchEnable:ivb */
6733        if (IS_IVB_GT1(dev))
6734                I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6735                           _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6736
6737        /* WaDisable_RenderCache_OperationalFlush:ivb */
6738        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6739
6740        /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6741        I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6742                   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6743
6744        /* WaApplyL3ControlAndL3ChickenMode:ivb */
6745        I915_WRITE(GEN7_L3CNTLREG1,
6746                        GEN7_WA_FOR_GEN7_L3_CONTROL);
6747        I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6748                   GEN7_WA_L3_CHICKEN_MODE);
6749        if (IS_IVB_GT1(dev))
6750                I915_WRITE(GEN7_ROW_CHICKEN2,
6751                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6752        else {
6753                /* must write both registers */
6754                I915_WRITE(GEN7_ROW_CHICKEN2,
6755                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6756                I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6757                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6758        }
6759
6760        /* WaForceL3Serialization:ivb */
6761        I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6762                   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6763
6764        /*
6765         * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6766         * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6767         */
6768        I915_WRITE(GEN6_UCGCTL2,
6769                   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6770
6771        /* This is required by WaCatErrorRejectionIssue:ivb */
6772        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6773                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6774                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6775
6776        g4x_disable_trickle_feed(dev);
6777
6778        gen7_setup_fixed_func_scheduler(dev_priv);
6779
6780        if (0) { /* causes HiZ corruption on ivb:gt1 */
6781                /* enable HiZ Raw Stall Optimization */
6782                I915_WRITE(CACHE_MODE_0_GEN7,
6783                           _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6784        }
6785
6786        /* WaDisable4x2SubspanOptimization:ivb */
6787        I915_WRITE(CACHE_MODE_1,
6788                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6789
6790        /*
6791         * BSpec recommends 8x4 when MSAA is used,
6792         * however in practice 16x4 seems fastest.
6793         *
6794         * Note that PS/WM thread counts depend on the WIZ hashing
6795         * disable bit, which we don't touch here, but it's good
6796         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6797         */
6798        I915_WRITE(GEN7_GT_MODE,
6799                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6800
6801        snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6802        snpcr &= ~GEN6_MBC_SNPCR_MASK;
6803        snpcr |= GEN6_MBC_SNPCR_MED;
6804        I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6805
6806        if (!HAS_PCH_NOP(dev))
6807                cpt_init_clock_gating(dev);
6808
6809        gen6_check_mch_setup(dev);
6810}
6811
6812static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6813{
6814        u32 val;
6815
6816        /*
6817        * On driver load, a pipe may be active and driving a DSI display.
6818        * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
6819        * (and never recovering) in this case. intel_dsi_post_disable() will
6820        * clear it when we turn off the display.
6821        */
6822        val = I915_READ(DSPCLK_GATE_D);
6823        val &= DPOUNIT_CLOCK_GATE_DISABLE;
6824        val |= VRHUNIT_CLOCK_GATE_DISABLE;
6825        I915_WRITE(DSPCLK_GATE_D, val);
6826
6827        /*
6828         * Disable trickle feed and enable pnd deadline calculation
6829         */
6830        I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6831        I915_WRITE(CBR1_VLV, 0);
6832}
6833
6834static void valleyview_init_clock_gating(struct drm_device *dev)
6835{
6836        struct drm_i915_private *dev_priv = dev->dev_private;
6837
6838        vlv_init_display_clock_gating(dev_priv);
6839
6840        /* WaDisableEarlyCull:vlv */
6841        I915_WRITE(_3D_CHICKEN3,
6842                   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6843
6844        /* WaDisableBackToBackFlipFix:vlv */
6845        I915_WRITE(IVB_CHICKEN3,
6846                   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6847                   CHICKEN3_DGMG_DONE_FIX_DISABLE);
6848
6849        /* WaPsdDispatchEnable:vlv */
6850        /* WaDisablePSDDualDispatchEnable:vlv */
6851        I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6852                   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6853                                      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6854
6855        /* WaDisable_RenderCache_OperationalFlush:vlv */
6856        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6857
6858        /* WaForceL3Serialization:vlv */
6859        I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6860                   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6861
6862        /* WaDisableDopClockGating:vlv */
6863        I915_WRITE(GEN7_ROW_CHICKEN2,
6864                   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6865
6866        /* This is required by WaCatErrorRejectionIssue:vlv */
6867        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6868                   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6869                   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6870
6871        gen7_setup_fixed_func_scheduler(dev_priv);
6872
6873        /*
6874         * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6875         * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6876         */
6877        I915_WRITE(GEN6_UCGCTL2,
6878                   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6879
6880        /* WaDisableL3Bank2xClockGate:vlv
6881         * Disabling L3 clock gating- MMIO 940c[25] = 1
6882         * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6883        I915_WRITE(GEN7_UCGCTL4,
6884                   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6885
6886        /*
6887         * BSpec says this must be set, even though
6888         * WaDisable4x2SubspanOptimization isn't listed for VLV.
6889         */
6890        I915_WRITE(CACHE_MODE_1,
6891                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6892
6893        /*
6894         * BSpec recommends 8x4 when MSAA is used,
6895         * however in practice 16x4 seems fastest.
6896         *
6897         * Note that PS/WM thread counts depend on the WIZ hashing
6898         * disable bit, which we don't touch here, but it's good
6899         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6900         */
6901        I915_WRITE(GEN7_GT_MODE,
6902                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6903
6904        /*
6905         * WaIncreaseL3CreditsForVLVB0:vlv
6906         * This is the hardware default actually.
6907         */
6908        I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6909
6910        /*
6911         * WaDisableVLVClockGating_VBIIssue:vlv
6912         * Disable clock gating on th GCFG unit to prevent a delay
6913         * in the reporting of vblank events.
6914         */
6915        I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6916}
6917
6918static void cherryview_init_clock_gating(struct drm_device *dev)
6919{
6920        struct drm_i915_private *dev_priv = dev->dev_private;
6921
6922        vlv_init_display_clock_gating(dev_priv);
6923
6924        /* WaVSRefCountFullforceMissDisable:chv */
6925        /* WaDSRefCountFullforceMissDisable:chv */
6926        I915_WRITE(GEN7_FF_THREAD_MODE,
6927                   I915_READ(GEN7_FF_THREAD_MODE) &
6928                   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6929
6930        /* WaDisableSemaphoreAndSyncFlipWait:chv */
6931        I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6932                   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6933
6934        /* WaDisableCSUnitClockGating:chv */
6935        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6936                   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6937
6938        /* WaDisableSDEUnitClockGating:chv */
6939        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6940                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6941
6942        /*
6943         * GTT cache may not work with big pages, so if those
6944         * are ever enabled GTT cache may need to be disabled.
6945         */
6946        I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6947}
6948
6949static void g4x_init_clock_gating(struct drm_device *dev)
6950{
6951        struct drm_i915_private *dev_priv = dev->dev_private;
6952        uint32_t dspclk_gate;
6953
6954        I915_WRITE(RENCLK_GATE_D1, 0);
6955        I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6956                   GS_UNIT_CLOCK_GATE_DISABLE |
6957                   CL_UNIT_CLOCK_GATE_DISABLE);
6958        I915_WRITE(RAMCLK_GATE_D, 0);
6959        dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6960                OVRUNIT_CLOCK_GATE_DISABLE |
6961                OVCUNIT_CLOCK_GATE_DISABLE;
6962        if (IS_GM45(dev))
6963                dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6964        I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6965
6966        /* WaDisableRenderCachePipelinedFlush */
6967        I915_WRITE(CACHE_MODE_0,
6968                   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6969
6970        /* WaDisable_RenderCache_OperationalFlush:g4x */
6971        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6972
6973        g4x_disable_trickle_feed(dev);
6974}
6975
6976static void crestline_init_clock_gating(struct drm_device *dev)
6977{
6978        struct drm_i915_private *dev_priv = dev->dev_private;
6979
6980        I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6981        I915_WRITE(RENCLK_GATE_D2, 0);
6982        I915_WRITE(DSPCLK_GATE_D, 0);
6983        I915_WRITE(RAMCLK_GATE_D, 0);
6984        I915_WRITE16(DEUC, 0);
6985        I915_WRITE(MI_ARB_STATE,
6986                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6987
6988        /* WaDisable_RenderCache_OperationalFlush:gen4 */
6989        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6990}
6991
6992static void broadwater_init_clock_gating(struct drm_device *dev)
6993{
6994        struct drm_i915_private *dev_priv = dev->dev_private;
6995
6996        I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6997                   I965_RCC_CLOCK_GATE_DISABLE |
6998                   I965_RCPB_CLOCK_GATE_DISABLE |
6999                   I965_ISC_CLOCK_GATE_DISABLE |
7000                   I965_FBC_CLOCK_GATE_DISABLE);
7001        I915_WRITE(RENCLK_GATE_D2, 0);
7002        I915_WRITE(MI_ARB_STATE,
7003                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7004
7005        /* WaDisable_RenderCache_OperationalFlush:gen4 */
7006        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7007}
7008
7009static void gen3_init_clock_gating(struct drm_device *dev)
7010{
7011        struct drm_i915_private *dev_priv = dev->dev_private;
7012        u32 dstate = I915_READ(D_STATE);
7013
7014        dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7015                DSTATE_DOT_CLOCK_GATING;
7016        I915_WRITE(D_STATE, dstate);
7017
7018        if (IS_PINEVIEW(dev))
7019                I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7020
7021        /* IIR "flip pending" means done if this bit is set */
7022        I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7023
7024        /* interrupts should cause a wake up from C3 */
7025        I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7026
7027        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7028        I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7029
7030        I915_WRITE(MI_ARB_STATE,
7031                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7032}
7033
7034static void i85x_init_clock_gating(struct drm_device *dev)
7035{
7036        struct drm_i915_private *dev_priv = dev->dev_private;
7037
7038        I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7039
7040        /* interrupts should cause a wake up from C3 */
7041        I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7042                   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7043
7044        I915_WRITE(MEM_MODE,
7045                   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7046}
7047
7048static void i830_init_clock_gating(struct drm_device *dev)
7049{
7050        struct drm_i915_private *dev_priv = dev->dev_private;
7051
7052        I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7053
7054        I915_WRITE(MEM_MODE,
7055                   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7056                   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7057}
7058
7059void intel_init_clock_gating(struct drm_device *dev)
7060{
7061        struct drm_i915_private *dev_priv = dev->dev_private;
7062
7063        if (dev_priv->display.init_clock_gating)
7064                dev_priv->display.init_clock_gating(dev);
7065}
7066
7067void intel_suspend_hw(struct drm_device *dev)
7068{
7069        if (HAS_PCH_LPT(dev))
7070                lpt_suspend_hw(dev);
7071}
7072
7073/* Set up chip specific power management-related functions */
7074void intel_init_pm(struct drm_device *dev)
7075{
7076        struct drm_i915_private *dev_priv = dev->dev_private;
7077
7078        intel_fbc_init(dev_priv);
7079
7080        /* For cxsr */
7081        if (IS_PINEVIEW(dev))
7082                i915_pineview_get_mem_freq(dev);
7083        else if (IS_GEN5(dev))
7084                i915_ironlake_get_mem_freq(dev);
7085
7086        /* For FIFO watermark updates */
7087        if (INTEL_INFO(dev)->gen >= 9) {
7088                skl_setup_wm_latency(dev);
7089
7090                if (IS_BROXTON(dev))
7091                        dev_priv->display.init_clock_gating =
7092                                bxt_init_clock_gating;
7093                dev_priv->display.update_wm = skl_update_wm;
7094                dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7095        } else if (HAS_PCH_SPLIT(dev)) {
7096                ilk_setup_wm_latency(dev);
7097
7098                if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7099                     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7100                    (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7101                     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7102                        dev_priv->display.update_wm = ilk_update_wm;
7103                        dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7104                } else {
7105                        DRM_DEBUG_KMS("Failed to read display plane latency. "
7106                                      "Disable CxSR\n");
7107                }
7108
7109                if (IS_GEN5(dev))
7110                        dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7111                else if (IS_GEN6(dev))
7112                        dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7113                else if (IS_IVYBRIDGE(dev))
7114                        dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7115                else if (IS_HASWELL(dev))
7116                        dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7117                else if (INTEL_INFO(dev)->gen == 8)
7118                        dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7119        } else if (IS_CHERRYVIEW(dev)) {
7120                vlv_setup_wm_latency(dev);
7121
7122                dev_priv->display.update_wm = vlv_update_wm;
7123                dev_priv->display.init_clock_gating =
7124                        cherryview_init_clock_gating;
7125        } else if (IS_VALLEYVIEW(dev)) {
7126                vlv_setup_wm_latency(dev);
7127
7128                dev_priv->display.update_wm = vlv_update_wm;
7129                dev_priv->display.init_clock_gating =
7130                        valleyview_init_clock_gating;
7131        } else if (IS_PINEVIEW(dev)) {
7132                if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7133                                            dev_priv->is_ddr3,
7134                                            dev_priv->fsb_freq,
7135                                            dev_priv->mem_freq)) {
7136                        DRM_INFO("failed to find known CxSR latency "
7137                                 "(found ddr%s fsb freq %d, mem freq %d), "
7138                                 "disabling CxSR\n",
7139                                 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7140                                 dev_priv->fsb_freq, dev_priv->mem_freq);
7141                        /* Disable CxSR and never update its watermark again */
7142                        intel_set_memory_cxsr(dev_priv, false);
7143                        dev_priv->display.update_wm = NULL;
7144                } else
7145                        dev_priv->display.update_wm = pineview_update_wm;
7146                dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7147        } else if (IS_G4X(dev)) {
7148                dev_priv->display.update_wm = g4x_update_wm;
7149                dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7150        } else if (IS_GEN4(dev)) {
7151                dev_priv->display.update_wm = i965_update_wm;
7152                if (IS_CRESTLINE(dev))
7153                        dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7154                else if (IS_BROADWATER(dev))
7155                        dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7156        } else if (IS_GEN3(dev)) {
7157                dev_priv->display.update_wm = i9xx_update_wm;
7158                dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7159                dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7160        } else if (IS_GEN2(dev)) {
7161                if (INTEL_INFO(dev)->num_pipes == 1) {
7162                        dev_priv->display.update_wm = i845_update_wm;
7163                        dev_priv->display.get_fifo_size = i845_get_fifo_size;
7164                } else {
7165                        dev_priv->display.update_wm = i9xx_update_wm;
7166                        dev_priv->display.get_fifo_size = i830_get_fifo_size;
7167                }
7168
7169                if (IS_I85X(dev) || IS_I865G(dev))
7170                        dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7171                else
7172                        dev_priv->display.init_clock_gating = i830_init_clock_gating;
7173        } else {
7174                DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7175        }
7176}
7177
7178int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7179{
7180        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7181
7182        if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7183                DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7184                return -EAGAIN;
7185        }
7186
7187        I915_WRITE(GEN6_PCODE_DATA, *val);
7188        I915_WRITE(GEN6_PCODE_DATA1, 0);
7189        I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7190
7191        if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7192                     500)) {
7193                DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7194                return -ETIMEDOUT;
7195        }
7196
7197        *val = I915_READ(GEN6_PCODE_DATA);
7198        I915_WRITE(GEN6_PCODE_DATA, 0);
7199
7200        return 0;
7201}
7202
7203int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7204{
7205        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7206
7207        if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7208                DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7209                return -EAGAIN;
7210        }
7211
7212        I915_WRITE(GEN6_PCODE_DATA, val);
7213        I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7214
7215        if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7216                     500)) {
7217                DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7218                return -ETIMEDOUT;
7219        }
7220
7221        I915_WRITE(GEN6_PCODE_DATA, 0);
7222
7223        return 0;
7224}
7225
7226static int vlv_gpu_freq_div(unsigned int czclk_freq)
7227{
7228        switch (czclk_freq) {
7229        case 200:
7230                return 10;
7231        case 267:
7232                return 12;
7233        case 320:
7234        case 333:
7235                return 16;
7236        case 400:
7237                return 20;
7238        default:
7239                return -1;
7240        }
7241}
7242
7243static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7244{
7245        int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7246
7247        div = vlv_gpu_freq_div(czclk_freq);
7248        if (div < 0)
7249                return div;
7250
7251        return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7252}
7253
7254static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7255{
7256        int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7257
7258        mul = vlv_gpu_freq_div(czclk_freq);
7259        if (mul < 0)
7260                return mul;
7261
7262        return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7263}
7264
7265static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7266{
7267        int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7268
7269        div = vlv_gpu_freq_div(czclk_freq) / 2;
7270        if (div < 0)
7271                return div;
7272
7273        return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7274}
7275
7276static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7277{
7278        int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7279
7280        mul = vlv_gpu_freq_div(czclk_freq) / 2;
7281        if (mul < 0)
7282                return mul;
7283
7284        /* CHV needs even values */
7285        return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7286}
7287
7288int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7289{
7290        if (IS_GEN9(dev_priv->dev))
7291                return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7292                                         GEN9_FREQ_SCALER);
7293        else if (IS_CHERRYVIEW(dev_priv->dev))
7294                return chv_gpu_freq(dev_priv, val);
7295        else if (IS_VALLEYVIEW(dev_priv->dev))
7296                return byt_gpu_freq(dev_priv, val);
7297        else
7298                return val * GT_FREQUENCY_MULTIPLIER;
7299}
7300
7301int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7302{
7303        if (IS_GEN9(dev_priv->dev))
7304                return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7305                                         GT_FREQUENCY_MULTIPLIER);
7306        else if (IS_CHERRYVIEW(dev_priv->dev))
7307                return chv_freq_opcode(dev_priv, val);
7308        else if (IS_VALLEYVIEW(dev_priv->dev))
7309                return byt_freq_opcode(dev_priv, val);
7310        else
7311                return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7312}
7313
7314struct request_boost {
7315        struct work_struct work;
7316        struct drm_i915_gem_request *req;
7317};
7318
7319static void __intel_rps_boost_work(struct work_struct *work)
7320{
7321        struct request_boost *boost = container_of(work, struct request_boost, work);
7322        struct drm_i915_gem_request *req = boost->req;
7323
7324        if (!i915_gem_request_completed(req, true))
7325                gen6_rps_boost(to_i915(req->ring->dev), NULL,
7326                               req->emitted_jiffies);
7327
7328        i915_gem_request_unreference__unlocked(req);
7329        kfree(boost);
7330}
7331
7332void intel_queue_rps_boost_for_request(struct drm_device *dev,
7333                                       struct drm_i915_gem_request *req)
7334{
7335        struct request_boost *boost;
7336
7337        if (req == NULL || INTEL_INFO(dev)->gen < 6)
7338                return;
7339
7340        if (i915_gem_request_completed(req, true))
7341                return;
7342
7343        boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7344        if (boost == NULL)
7345                return;
7346
7347        i915_gem_request_reference(req);
7348        boost->req = req;
7349
7350        INIT_WORK(&boost->work, __intel_rps_boost_work);
7351        queue_work(to_i915(dev)->wq, &boost->work);
7352}
7353
7354void intel_pm_setup(struct drm_device *dev)
7355{
7356        struct drm_i915_private *dev_priv = dev->dev_private;
7357
7358        mutex_init(&dev_priv->rps.hw_lock);
7359        spin_lock_init(&dev_priv->rps.client_lock);
7360
7361        INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7362                          intel_gen6_powersave_work);
7363        INIT_LIST_HEAD(&dev_priv->rps.clients);
7364        INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7365        INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7366
7367        dev_priv->pm.suspended = false;
7368}
Note: See TracBrowser for help on using the repository browser.