source: src/linux/universal/linux-4.9/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @ 31859

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1Allwinner A10 Display Pipeline
2==============================
3
4The Allwinner A10 Display pipeline is composed of several components
5that are going to be documented below:
6
7TV Encoder
8----------
9
10The TV Encoder supports the composite and VGA output. It is one end of
11the pipeline.
12
13Required properties:
14 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
15 - reg: base address and size of memory-mapped region
16 - clocks: the clocks driving the TV encoder
17 - resets: phandle to the reset controller driving the encoder
18
19- ports: A ports node with endpoint definitions as defined in
20  Documentation/devicetree/bindings/media/video-interfaces.txt. The
21  first port should be the input endpoint.
22
23TCON
24----
25
26The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
27
28Required properties:
29 - compatible: value must be either:
30   * allwinner,sun5i-a13-tcon
31   * allwinner,sun6i-a31-tcon
32   * allwinner,sun6i-a31s-tcon
33   * allwinner,sun8i-a33-tcon
34 - reg: base address and size of memory-mapped region
35 - interrupts: interrupt associated to this IP
36 - clocks: phandles to the clocks feeding the TCON. Three are needed:
37   - 'ahb': the interface clocks
38   - 'tcon-ch0': The clock driving the TCON channel 0
39 - resets: phandles to the reset controllers driving the encoder
40   - "lcd": the reset line for the TCON channel 0
41
42 - clock-names: the clock names mentioned above
43 - reset-names: the reset names mentioned above
44 - clock-output-names: Name of the pixel clock created
45
46- ports: A ports node with endpoint definitions as defined in
47  Documentation/devicetree/bindings/media/video-interfaces.txt. The
48  first port should be the input endpoint, the second one the output
49
50  The output should have two endpoints. The first is the block
51  connected to the TCON channel 0 (usually a panel or a bridge), the
52  second the block connected to the TCON channel 1 (usually the TV
53  encoder)
54
55On SoCs other than the A33, there is one more clock required:
56   - 'tcon-ch1': The clock driving the TCON channel 1
57
58DRC
59---
60
61The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
62(A31, A23, A33), allows to dynamically adjust pixel
63brightness/contrast based on histogram measurements for LCD content
64adaptive backlight control.
65
66
67Required properties:
68  - compatible: value must be one of:
69    * allwinner,sun8i-a33-drc
70  - reg: base address and size of the memory-mapped region.
71  - interrupts: interrupt associated to this IP
72  - clocks: phandles to the clocks feeding the DRC
73    * ahb: the DRC interface clock
74    * mod: the DRC module clock
75    * ram: the DRC DRAM clock
76  - clock-names: the clock names mentioned above
77  - resets: phandles to the reset line driving the DRC
78
79- ports: A ports node with endpoint definitions as defined in
80  Documentation/devicetree/bindings/media/video-interfaces.txt. The
81  first port should be the input endpoints, the second one the outputs
82
83Display Engine Backend
84----------------------
85
86The display engine backend exposes layers and sprites to the
87system.
88
89Required properties:
90  - compatible: value must be one of:
91    * allwinner,sun5i-a13-display-backend
92    * allwinner,sun6i-a31-display-backend
93    * allwinner,sun8i-a33-display-backend
94  - reg: base address and size of the memory-mapped region.
95  - clocks: phandles to the clocks feeding the frontend and backend
96    * ahb: the backend interface clock
97    * mod: the backend module clock
98    * ram: the backend DRAM clock
99  - clock-names: the clock names mentioned above
100  - resets: phandles to the reset controllers driving the backend
101
102- ports: A ports node with endpoint definitions as defined in
103  Documentation/devicetree/bindings/media/video-interfaces.txt. The
104  first port should be the input endpoints, the second one the output
105
106On the A33, some additional properties are required:
107  - reg needs to have an additional region corresponding to the SAT
108  - reg-names need to be set, with "be" and "sat"
109  - clocks and clock-names need to have a phandle to the SAT bus
110    clocks, whose name will be "sat"
111  - resets and reset-names need to have a phandle to the SAT bus
112    resets, whose name will be "sat"
113
114Display Engine Frontend
115-----------------------
116
117The display engine frontend does formats conversion, scaling,
118deinterlacing and color space conversion.
119
120Required properties:
121  - compatible: value must be one of:
122    * allwinner,sun5i-a13-display-frontend
123    * allwinner,sun6i-a31-display-frontend
124    * allwinner,sun8i-a33-display-frontend
125  - reg: base address and size of the memory-mapped region.
126  - interrupts: interrupt associated to this IP
127  - clocks: phandles to the clocks feeding the frontend and backend
128    * ahb: the backend interface clock
129    * mod: the backend module clock
130    * ram: the backend DRAM clock
131  - clock-names: the clock names mentioned above
132  - resets: phandles to the reset controllers driving the backend
133
134- ports: A ports node with endpoint definitions as defined in
135  Documentation/devicetree/bindings/media/video-interfaces.txt. The
136  first port should be the input endpoints, the second one the outputs
137
138
139Display Engine Pipeline
140-----------------------
141
142The display engine pipeline (and its entry point, since it can be
143either directly the backend or the frontend) is represented as an
144extra node.
145
146Required properties:
147  - compatible: value must be one of:
148    * allwinner,sun5i-a13-display-engine
149    * allwinner,sun6i-a31-display-engine
150    * allwinner,sun6i-a31s-display-engine
151    * allwinner,sun8i-a33-display-engine
152
153  - allwinner,pipelines: list of phandle to the display engine
154    frontends available.
155
156Example:
157
158panel: panel {
159        compatible = "olimex,lcd-olinuxino-43-ts";
160        #address-cells = <1>;
161        #size-cells = <0>;
162
163        port {
164                #address-cells = <1>;
165                #size-cells = <0>;
166
167                panel_input: endpoint {
168                        remote-endpoint = <&tcon0_out_panel>;
169                };
170        };
171};
172
173tve0: tv-encoder@01c0a000 {
174        compatible = "allwinner,sun4i-a10-tv-encoder";
175        reg = <0x01c0a000 0x1000>;
176        clocks = <&ahb_gates 34>;
177        resets = <&tcon_ch0_clk 0>;
178
179        port {
180                #address-cells = <1>;
181                #size-cells = <0>;
182
183                tve0_in_tcon0: endpoint@0 {
184                        reg = <0>;
185                        remote-endpoint = <&tcon0_out_tve0>;
186                };
187        };
188};
189
190tcon0: lcd-controller@1c0c000 {
191        compatible = "allwinner,sun5i-a13-tcon";
192        reg = <0x01c0c000 0x1000>;
193        interrupts = <44>;
194        resets = <&tcon_ch0_clk 1>;
195        reset-names = "lcd";
196        clocks = <&ahb_gates 36>,
197                 <&tcon_ch0_clk>,
198                 <&tcon_ch1_clk>;
199        clock-names = "ahb",
200                      "tcon-ch0",
201                      "tcon-ch1";
202        clock-output-names = "tcon-pixel-clock";
203
204        ports {
205                #address-cells = <1>;
206                #size-cells = <0>;
207
208                tcon0_in: port@0 {
209                        #address-cells = <1>;
210                        #size-cells = <0>;
211                        reg = <0>;
212
213                        tcon0_in_be0: endpoint@0 {
214                                reg = <0>;
215                                remote-endpoint = <&be0_out_tcon0>;
216                        };
217                };
218
219                tcon0_out: port@1 {
220                        #address-cells = <1>;
221                        #size-cells = <0>;
222                        reg = <1>;
223
224                        tcon0_out_panel: endpoint@0 {
225                                reg = <0>;
226                                remote-endpoint = <&panel_input>;
227                        };
228
229                        tcon0_out_tve0: endpoint@1 {
230                                reg = <1>;
231                                remote-endpoint = <&tve0_in_tcon0>;
232                        };
233                };
234        };
235};
236
237fe0: display-frontend@1e00000 {
238        compatible = "allwinner,sun5i-a13-display-frontend";
239        reg = <0x01e00000 0x20000>;
240        interrupts = <47>;
241        clocks = <&ahb_gates 46>, <&de_fe_clk>,
242                 <&dram_gates 25>;
243        clock-names = "ahb", "mod",
244                      "ram";
245        resets = <&de_fe_clk>;
246
247        ports {
248                #address-cells = <1>;
249                #size-cells = <0>;
250
251                fe0_out: port@1 {
252                        #address-cells = <1>;
253                        #size-cells = <0>;
254                        reg = <1>;
255
256                        fe0_out_be0: endpoint {
257                                remote-endpoint = <&be0_in_fe0>;
258                        };
259                };
260        };
261};
262
263be0: display-backend@1e60000 {
264        compatible = "allwinner,sun5i-a13-display-backend";
265        reg = <0x01e60000 0x10000>;
266        clocks = <&ahb_gates 44>, <&de_be_clk>,
267                 <&dram_gates 26>;
268        clock-names = "ahb", "mod",
269                      "ram";
270        resets = <&de_be_clk>;
271
272        ports {
273                #address-cells = <1>;
274                #size-cells = <0>;
275
276                be0_in: port@0 {
277                        #address-cells = <1>;
278                        #size-cells = <0>;
279                        reg = <0>;
280
281                        be0_in_fe0: endpoint@0 {
282                                reg = <0>;
283                                remote-endpoint = <&fe0_out_be0>;
284                        };
285                };
286
287                be0_out: port@1 {
288                        #address-cells = <1>;
289                        #size-cells = <0>;
290                        reg = <1>;
291
292                        be0_out_tcon0: endpoint@0 {
293                                reg = <0>;
294                                remote-endpoint = <&tcon0_in_be0>;
295                        };
296                };
297        };
298};
299
300display-engine {
301        compatible = "allwinner,sun5i-a13-display-engine";
302        allwinner,pipelines = <&fe0>;
303};
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