source: src/linux/universal/linux-4.9/arch/powerpc/kernel/setup_64.c @ 31859

Last change on this file since 31859 was 31859, checked in by brainslayer, 3 months ago

kernel update

File size: 17.7 KB
Line 
1/*
2 *
3 * Common boot and setup code.
4 *
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 *      This program is free software; you can redistribute it and/or
8 *      modify it under the terms of the GNU General Public License
9 *      as published by the Free Software Foundation; either version
10 *      2 of the License, or (at your option) any later version.
11 */
12
13#define DEBUG
14
15#include <linux/export.h>
16#include <linux/string.h>
17#include <linux/sched.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/reboot.h>
21#include <linux/delay.h>
22#include <linux/initrd.h>
23#include <linux/seq_file.h>
24#include <linux/ioport.h>
25#include <linux/console.h>
26#include <linux/utsname.h>
27#include <linux/tty.h>
28#include <linux/root_dev.h>
29#include <linux/notifier.h>
30#include <linux/cpu.h>
31#include <linux/unistd.h>
32#include <linux/serial.h>
33#include <linux/serial_8250.h>
34#include <linux/bootmem.h>
35#include <linux/pci.h>
36#include <linux/lockdep.h>
37#include <linux/memblock.h>
38#include <linux/memory.h>
39#include <linux/nmi.h>
40
41#include <asm/io.h>
42#include <asm/kdump.h>
43#include <asm/prom.h>
44#include <asm/processor.h>
45#include <asm/pgtable.h>
46#include <asm/smp.h>
47#include <asm/elf.h>
48#include <asm/machdep.h>
49#include <asm/paca.h>
50#include <asm/time.h>
51#include <asm/cputable.h>
52#include <asm/sections.h>
53#include <asm/btext.h>
54#include <asm/nvram.h>
55#include <asm/setup.h>
56#include <asm/rtas.h>
57#include <asm/iommu.h>
58#include <asm/serial.h>
59#include <asm/cache.h>
60#include <asm/page.h>
61#include <asm/mmu.h>
62#include <asm/firmware.h>
63#include <asm/xmon.h>
64#include <asm/udbg.h>
65#include <asm/kexec.h>
66#include <asm/code-patching.h>
67#include <asm/livepatch.h>
68#include <asm/opal.h>
69#include <asm/cputhreads.h>
70
71#ifdef DEBUG
72#define DBG(fmt...) udbg_printf(fmt)
73#else
74#define DBG(fmt...)
75#endif
76
77int spinning_secondaries;
78u64 ppc64_pft_size;
79
80/* Pick defaults since we might want to patch instructions
81 * before we've read this from the device tree.
82 */
83struct ppc64_caches ppc64_caches = {
84        .dline_size = 0x40,
85        .log_dline_size = 6,
86        .iline_size = 0x40,
87        .log_iline_size = 6
88};
89EXPORT_SYMBOL_GPL(ppc64_caches);
90
91/*
92 * These are used in binfmt_elf.c to put aux entries on the stack
93 * for each elf executable being started.
94 */
95int dcache_bsize;
96int icache_bsize;
97int ucache_bsize;
98
99#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
100void __init setup_tlb_core_data(void)
101{
102        int cpu;
103
104        BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
105
106        for_each_possible_cpu(cpu) {
107                int first = cpu_first_thread_sibling(cpu);
108
109                /*
110                 * If we boot via kdump on a non-primary thread,
111                 * make sure we point at the thread that actually
112                 * set up this TLB.
113                 */
114                if (cpu_first_thread_sibling(boot_cpuid) == first)
115                        first = boot_cpuid;
116
117                paca[cpu].tcd_ptr = &paca[first].tcd;
118
119                /*
120                 * If we have threads, we need either tlbsrx.
121                 * or e6500 tablewalk mode, or else TLB handlers
122                 * will be racy and could produce duplicate entries.
123                 */
124                if (smt_enabled_at_boot >= 2 &&
125                    !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
126                    book3e_htw_mode != PPC_HTW_E6500) {
127                        /* Should we panic instead? */
128                        WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
129                                  __func__);
130                }
131        }
132}
133#endif
134
135#ifdef CONFIG_SMP
136
137static char *smt_enabled_cmdline;
138
139/* Look for ibm,smt-enabled OF option */
140void __init check_smt_enabled(void)
141{
142        struct device_node *dn;
143        const char *smt_option;
144
145        /* Default to enabling all threads */
146        smt_enabled_at_boot = threads_per_core;
147
148        /* Allow the command line to overrule the OF option */
149        if (smt_enabled_cmdline) {
150                if (!strcmp(smt_enabled_cmdline, "on"))
151                        smt_enabled_at_boot = threads_per_core;
152                else if (!strcmp(smt_enabled_cmdline, "off"))
153                        smt_enabled_at_boot = 0;
154                else {
155                        int smt;
156                        int rc;
157
158                        rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
159                        if (!rc)
160                                smt_enabled_at_boot =
161                                        min(threads_per_core, smt);
162                }
163        } else {
164                dn = of_find_node_by_path("/options");
165                if (dn) {
166                        smt_option = of_get_property(dn, "ibm,smt-enabled",
167                                                     NULL);
168
169                        if (smt_option) {
170                                if (!strcmp(smt_option, "on"))
171                                        smt_enabled_at_boot = threads_per_core;
172                                else if (!strcmp(smt_option, "off"))
173                                        smt_enabled_at_boot = 0;
174                        }
175
176                        of_node_put(dn);
177                }
178        }
179}
180
181/* Look for smt-enabled= cmdline option */
182static int __init early_smt_enabled(char *p)
183{
184        smt_enabled_cmdline = p;
185        return 0;
186}
187early_param("smt-enabled", early_smt_enabled);
188
189#endif /* CONFIG_SMP */
190
191/** Fix up paca fields required for the boot cpu */
192static void __init fixup_boot_paca(void)
193{
194        /* The boot cpu is started */
195        get_paca()->cpu_start = 1;
196        /* Allow percpu accesses to work until we setup percpu data */
197        get_paca()->data_offset = 0;
198}
199
200static void __init configure_exceptions(void)
201{
202        /*
203         * Setup the trampolines from the lowmem exception vectors
204         * to the kdump kernel when not using a relocatable kernel.
205         */
206        setup_kdump_trampoline();
207
208        /* Under a PAPR hypervisor, we need hypercalls */
209        if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
210                /* Enable AIL if possible */
211                pseries_enable_reloc_on_exc();
212
213                /*
214                 * Tell the hypervisor that we want our exceptions to
215                 * be taken in little endian mode.
216                 *
217                 * We don't call this for big endian as our calling convention
218                 * makes us always enter in BE, and the call may fail under
219                 * some circumstances with kdump.
220                 */
221#ifdef __LITTLE_ENDIAN__
222                pseries_little_endian_exceptions();
223#endif
224        } else {
225                /* Set endian mode using OPAL */
226                if (firmware_has_feature(FW_FEATURE_OPAL))
227                        opal_configure_cores();
228
229                /* AIL on native is done in cpu_ready_for_interrupts() */
230        }
231}
232
233static void cpu_ready_for_interrupts(void)
234{
235        /*
236         * Enable AIL if supported, and we are in hypervisor mode. This
237         * is called once for every processor.
238         *
239         * If we are not in hypervisor mode the job is done once for
240         * the whole partition in configure_exceptions().
241         */
242        if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
243            early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
244                unsigned long lpcr = mfspr(SPRN_LPCR);
245                mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
246        }
247
248        /*
249         * Fixup HFSCR:TM based on CPU features. The bit is set by our
250         * early asm init because at that point we haven't updated our
251         * CPU features from firmware and device-tree. Here we have,
252         * so let's do it.
253         */
254        if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
255                mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
256
257        /* Set IR and DR in PACA MSR */
258        get_paca()->kernel_msr = MSR_KERNEL;
259}
260
261/*
262 * Early initialization entry point. This is called by head.S
263 * with MMU translation disabled. We rely on the "feature" of
264 * the CPU that ignores the top 2 bits of the address in real
265 * mode so we can access kernel globals normally provided we
266 * only toy with things in the RMO region. From here, we do
267 * some early parsing of the device-tree to setup out MEMBLOCK
268 * data structures, and allocate & initialize the hash table
269 * and segment tables so we can start running with translation
270 * enabled.
271 *
272 * It is this function which will call the probe() callback of
273 * the various platform types and copy the matching one to the
274 * global ppc_md structure. Your platform can eventually do
275 * some very early initializations from the probe() routine, but
276 * this is not recommended, be very careful as, for example, the
277 * device-tree is not accessible via normal means at this point.
278 */
279
280void __init early_setup(unsigned long dt_ptr)
281{
282        static __initdata struct paca_struct boot_paca;
283
284        /* -------- printk is _NOT_ safe to use here ! ------- */
285
286        /* Identify CPU type */
287        identify_cpu(0, mfspr(SPRN_PVR));
288
289        /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
290        initialise_paca(&boot_paca, 0);
291        setup_paca(&boot_paca);
292        fixup_boot_paca();
293
294        /* -------- printk is now safe to use ------- */
295
296        /* Enable early debugging if any specified (see udbg.h) */
297        udbg_early_init();
298
299        DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
300
301        /*
302         * Do early initialization using the flattened device
303         * tree, such as retrieving the physical memory map or
304         * calculating/retrieving the hash table size.
305         */
306        early_init_devtree(__va(dt_ptr));
307
308        /* Now we know the logical id of our boot cpu, setup the paca. */
309        setup_paca(&paca[boot_cpuid]);
310        fixup_boot_paca();
311
312        /*
313         * Configure exception handlers. This include setting up trampolines
314         * if needed, setting exception endian mode, etc...
315         */
316        configure_exceptions();
317
318        /* Apply all the dynamic patching */
319        apply_feature_fixups();
320        setup_feature_keys();
321
322        /* Initialize the hash table or TLB handling */
323        early_init_mmu();
324
325        /*
326         * At this point, we can let interrupts switch to virtual mode
327         * (the MMU has been setup), so adjust the MSR in the PACA to
328         * have IR and DR set and enable AIL if it exists
329         */
330        cpu_ready_for_interrupts();
331
332        DBG(" <- early_setup()\n");
333
334#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
335        /*
336         * This needs to be done *last* (after the above DBG() even)
337         *
338         * Right after we return from this function, we turn on the MMU
339         * which means the real-mode access trick that btext does will
340         * no longer work, it needs to switch to using a real MMU
341         * mapping. This call will ensure that it does
342         */
343        btext_map();
344#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
345}
346
347#ifdef CONFIG_SMP
348void early_setup_secondary(void)
349{
350        /* Mark interrupts disabled in PACA */
351        get_paca()->soft_enabled = 0;
352
353        /* Initialize the hash table or TLB handling */
354        early_init_mmu_secondary();
355
356        /*
357         * At this point, we can let interrupts switch to virtual mode
358         * (the MMU has been setup), so adjust the MSR in the PACA to
359         * have IR and DR set.
360         */
361        cpu_ready_for_interrupts();
362}
363
364#endif /* CONFIG_SMP */
365
366#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
367static bool use_spinloop(void)
368{
369        if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
370                return true;
371
372        /*
373         * When book3e boots from kexec, the ePAPR spin table does
374         * not get used.
375         */
376        return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
377}
378
379void smp_release_cpus(void)
380{
381        unsigned long *ptr;
382        int i;
383
384        if (!use_spinloop())
385                return;
386
387        DBG(" -> smp_release_cpus()\n");
388
389        /* All secondary cpus are spinning on a common spinloop, release them
390         * all now so they can start to spin on their individual paca
391         * spinloops. For non SMP kernels, the secondary cpus never get out
392         * of the common spinloop.
393         */
394
395        ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
396                        - PHYSICAL_START);
397        *ptr = ppc_function_entry(generic_secondary_smp_init);
398
399        /* And wait a bit for them to catch up */
400        for (i = 0; i < 100000; i++) {
401                mb();
402                HMT_low();
403                if (spinning_secondaries == 0)
404                        break;
405                udelay(1);
406        }
407        DBG("spinning_secondaries = %d\n", spinning_secondaries);
408
409        DBG(" <- smp_release_cpus()\n");
410}
411#endif /* CONFIG_SMP || CONFIG_KEXEC */
412
413/*
414 * Initialize some remaining members of the ppc64_caches and systemcfg
415 * structures
416 * (at least until we get rid of them completely). This is mostly some
417 * cache informations about the CPU that will be used by cache flush
418 * routines and/or provided to userland
419 */
420void __init initialize_cache_info(void)
421{
422        struct device_node *np;
423        unsigned long num_cpus = 0;
424
425        DBG(" -> initialize_cache_info()\n");
426
427        for_each_node_by_type(np, "cpu") {
428                num_cpus += 1;
429
430                /*
431                 * We're assuming *all* of the CPUs have the same
432                 * d-cache and i-cache sizes... -Peter
433                 */
434                if (num_cpus == 1) {
435                        const __be32 *sizep, *lsizep;
436                        u32 size, lsize;
437
438                        size = 0;
439                        lsize = cur_cpu_spec->dcache_bsize;
440                        sizep = of_get_property(np, "d-cache-size", NULL);
441                        if (sizep != NULL)
442                                size = be32_to_cpu(*sizep);
443                        lsizep = of_get_property(np, "d-cache-block-size",
444                                                 NULL);
445                        /* fallback if block size missing */
446                        if (lsizep == NULL)
447                                lsizep = of_get_property(np,
448                                                         "d-cache-line-size",
449                                                         NULL);
450                        if (lsizep != NULL)
451                                lsize = be32_to_cpu(*lsizep);
452                        if (sizep == NULL || lsizep == NULL)
453                                DBG("Argh, can't find dcache properties ! "
454                                    "sizep: %p, lsizep: %p\n", sizep, lsizep);
455
456                        ppc64_caches.dsize = size;
457                        ppc64_caches.dline_size = lsize;
458                        ppc64_caches.log_dline_size = __ilog2(lsize);
459                        ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
460
461                        size = 0;
462                        lsize = cur_cpu_spec->icache_bsize;
463                        sizep = of_get_property(np, "i-cache-size", NULL);
464                        if (sizep != NULL)
465                                size = be32_to_cpu(*sizep);
466                        lsizep = of_get_property(np, "i-cache-block-size",
467                                                 NULL);
468                        if (lsizep == NULL)
469                                lsizep = of_get_property(np,
470                                                         "i-cache-line-size",
471                                                         NULL);
472                        if (lsizep != NULL)
473                                lsize = be32_to_cpu(*lsizep);
474                        if (sizep == NULL || lsizep == NULL)
475                                DBG("Argh, can't find icache properties ! "
476                                    "sizep: %p, lsizep: %p\n", sizep, lsizep);
477
478                        ppc64_caches.isize = size;
479                        ppc64_caches.iline_size = lsize;
480                        ppc64_caches.log_iline_size = __ilog2(lsize);
481                        ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
482                }
483        }
484
485        /* For use by binfmt_elf */
486        dcache_bsize = ppc64_caches.dline_size;
487        icache_bsize = ppc64_caches.iline_size;
488
489        DBG(" <- initialize_cache_info()\n");
490}
491
492/* This returns the limit below which memory accesses to the linear
493 * mapping are guarnateed not to cause a TLB or SLB miss. This is
494 * used to allocate interrupt or emergency stacks for which our
495 * exception entry path doesn't deal with being interrupted.
496 */
497static __init u64 safe_stack_limit(void)
498{
499#ifdef CONFIG_PPC_BOOK3E
500        /* Freescale BookE bolts the entire linear mapping */
501        if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
502                return linear_map_top;
503        /* Other BookE, we assume the first GB is bolted */
504        return 1ul << 30;
505#else
506        /* BookS, the first segment is bolted */
507        if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
508                return 1UL << SID_SHIFT_1T;
509        return 1UL << SID_SHIFT;
510#endif
511}
512
513void __init irqstack_early_init(void)
514{
515        u64 limit = safe_stack_limit();
516        unsigned int i;
517
518        /*
519         * Interrupt stacks must be in the first segment since we
520         * cannot afford to take SLB misses on them.
521         */
522        for_each_possible_cpu(i) {
523                softirq_ctx[i] = (struct thread_info *)
524                        __va(memblock_alloc_base(THREAD_SIZE,
525                                            THREAD_SIZE, limit));
526                hardirq_ctx[i] = (struct thread_info *)
527                        __va(memblock_alloc_base(THREAD_SIZE,
528                                            THREAD_SIZE, limit));
529        }
530}
531
532#ifdef CONFIG_PPC_BOOK3E
533void __init exc_lvl_early_init(void)
534{
535        unsigned int i;
536        unsigned long sp;
537
538        for_each_possible_cpu(i) {
539                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
540                critirq_ctx[i] = (struct thread_info *)__va(sp);
541                paca[i].crit_kstack = __va(sp + THREAD_SIZE);
542
543                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
544                dbgirq_ctx[i] = (struct thread_info *)__va(sp);
545                paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
546
547                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
548                mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
549                paca[i].mc_kstack = __va(sp + THREAD_SIZE);
550        }
551
552        if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
553                patch_exception(0x040, exc_debug_debug_book3e);
554}
555#endif
556
557/*
558 * Stack space used when we detect a bad kernel stack pointer, and
559 * early in SMP boots before relocation is enabled. Exclusive emergency
560 * stack for machine checks.
561 */
562void __init emergency_stack_init(void)
563{
564        u64 limit;
565        unsigned int i;
566
567        /*
568         * Emergency stacks must be under 256MB, we cannot afford to take
569         * SLB misses on them. The ABI also requires them to be 128-byte
570         * aligned.
571         *
572         * Since we use these as temporary stacks during secondary CPU
573         * bringup, we need to get at them in real mode. This means they
574         * must also be within the RMO region.
575         */
576        limit = min(safe_stack_limit(), ppc64_rma_size);
577
578        for_each_possible_cpu(i) {
579                struct thread_info *ti;
580                ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
581                klp_init_thread_info(ti);
582                paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
583
584#ifdef CONFIG_PPC_BOOK3S_64
585                /* emergency stack for machine check exception handling. */
586                ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
587                klp_init_thread_info(ti);
588                paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
589#endif
590        }
591}
592
593#ifdef CONFIG_SMP
594#define PCPU_DYN_SIZE           ()
595
596static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
597{
598        return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
599                                    __pa(MAX_DMA_ADDRESS));
600}
601
602static void __init pcpu_fc_free(void *ptr, size_t size)
603{
604        free_bootmem(__pa(ptr), size);
605}
606
607static int pcpu_cpu_distance(unsigned int from, unsigned int to)
608{
609        if (cpu_to_node(from) == cpu_to_node(to))
610                return LOCAL_DISTANCE;
611        else
612                return REMOTE_DISTANCE;
613}
614
615unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
616EXPORT_SYMBOL(__per_cpu_offset);
617
618void __init setup_per_cpu_areas(void)
619{
620        const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
621        size_t atom_size;
622        unsigned long delta;
623        unsigned int cpu;
624        int rc;
625
626        /*
627         * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
628         * to group units.  For larger mappings, use 1M atom which
629         * should be large enough to contain a number of units.
630         */
631        if (mmu_linear_psize == MMU_PAGE_4K)
632                atom_size = PAGE_SIZE;
633        else
634                atom_size = 1 << 20;
635
636        rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
637                                    pcpu_fc_alloc, pcpu_fc_free);
638        if (rc < 0)
639                panic("cannot initialize percpu area (err=%d)", rc);
640
641        delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
642        for_each_possible_cpu(cpu) {
643                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
644                paca[cpu].data_offset = __per_cpu_offset[cpu];
645        }
646}
647#endif
648
649#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
650unsigned long memory_block_size_bytes(void)
651{
652        if (ppc_md.memory_block_size)
653                return ppc_md.memory_block_size();
654
655        return MIN_MEMORY_BLOCK_SIZE;
656}
657#endif
658
659#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
660struct ppc_pci_io ppc_pci_io;
661EXPORT_SYMBOL(ppc_pci_io);
662#endif
663
664#ifdef CONFIG_HARDLOCKUP_DETECTOR
665u64 hw_nmi_get_sample_period(int watchdog_thresh)
666{
667        return ppc_proc_freq * watchdog_thresh;
668}
669
670/*
671 * The hardlockup detector breaks PMU event based branches and is likely
672 * to get false positives in KVM guests, so disable it by default.
673 */
674static int __init disable_hardlockup_detector(void)
675{
676        hardlockup_detector_disable();
677
678        return 0;
679}
680early_initcall(disable_hardlockup_detector);
681#endif
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