source: src/linux/universal/linux-4.9/arch/x86/include/asm/tlbflush.h @ 31662

Last change on this file since 31662 was 31662, checked in by brainslayer, 4 months ago

use new squashfs in all kernels

File size: 8.1 KB
Line 
1#ifndef _ASM_X86_TLBFLUSH_H
2#define _ASM_X86_TLBFLUSH_H
3
4#include <linux/mm.h>
5#include <linux/sched.h>
6
7#include <asm/processor.h>
8#include <asm/cpufeature.h>
9#include <asm/special_insns.h>
10
11static inline void __invpcid(unsigned long pcid, unsigned long addr,
12                             unsigned long type)
13{
14        struct { u64 d[2]; } desc = { { pcid, addr } };
15
16        /*
17         * The memory clobber is because the whole point is to invalidate
18         * stale TLB entries and, especially if we're flushing global
19         * mappings, we don't want the compiler to reorder any subsequent
20         * memory accesses before the TLB flush.
21         *
22         * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
23         * invpcid (%rcx), %rax in long mode.
24         */
25        asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
26                      : : "m" (desc), "a" (type), "c" (&desc) : "memory");
27}
28
29#define INVPCID_TYPE_INDIV_ADDR         0
30#define INVPCID_TYPE_SINGLE_CTXT        1
31#define INVPCID_TYPE_ALL_INCL_GLOBAL    2
32#define INVPCID_TYPE_ALL_NON_GLOBAL     3
33
34/* Flush all mappings for a given pcid and addr, not including globals. */
35static inline void invpcid_flush_one(unsigned long pcid,
36                                     unsigned long addr)
37{
38        __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
39}
40
41/* Flush all mappings for a given PCID, not including globals. */
42static inline void invpcid_flush_single_context(unsigned long pcid)
43{
44        __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
45}
46
47/* Flush all mappings, including globals, for all PCIDs. */
48static inline void invpcid_flush_all(void)
49{
50        __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
51}
52
53/* Flush all mappings for all PCIDs except globals. */
54static inline void invpcid_flush_all_nonglobals(void)
55{
56        __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
57}
58
59#ifdef CONFIG_PARAVIRT
60#include <asm/paravirt.h>
61#else
62#define __flush_tlb() __native_flush_tlb()
63#define __flush_tlb_global() __native_flush_tlb_global()
64#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
65#endif
66
67struct tlb_state {
68#ifdef CONFIG_SMP
69        struct mm_struct *active_mm;
70        int state;
71#endif
72
73        /*
74         * Access to this CR4 shadow and to H/W CR4 is protected by
75         * disabling interrupts when modifying either one.
76         */
77        unsigned long cr4;
78};
79DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
80
81/* Initialize cr4 shadow for this CPU. */
82static inline void cr4_init_shadow(void)
83{
84        this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
85}
86
87/* Set in this cpu's CR4. */
88static inline void cr4_set_bits(unsigned long mask)
89{
90        unsigned long cr4;
91
92        cr4 = this_cpu_read(cpu_tlbstate.cr4);
93        if ((cr4 | mask) != cr4) {
94                cr4 |= mask;
95                this_cpu_write(cpu_tlbstate.cr4, cr4);
96                __write_cr4(cr4);
97        }
98}
99
100/* Clear in this cpu's CR4. */
101static inline void cr4_clear_bits(unsigned long mask)
102{
103        unsigned long cr4;
104
105        cr4 = this_cpu_read(cpu_tlbstate.cr4);
106        if ((cr4 & ~mask) != cr4) {
107                cr4 &= ~mask;
108                this_cpu_write(cpu_tlbstate.cr4, cr4);
109                __write_cr4(cr4);
110        }
111}
112
113/* Read the CR4 shadow. */
114static inline unsigned long cr4_read_shadow(void)
115{
116        return this_cpu_read(cpu_tlbstate.cr4);
117}
118
119/*
120 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
121 * enable and PPro Global page enable), so that any CPU's that boot
122 * up after us can get the correct flags.  This should only be used
123 * during boot on the boot cpu.
124 */
125extern unsigned long mmu_cr4_features;
126extern u32 *trampoline_cr4_features;
127
128static inline void cr4_set_bits_and_update_boot(unsigned long mask)
129{
130        mmu_cr4_features |= mask;
131        if (trampoline_cr4_features)
132                *trampoline_cr4_features = mmu_cr4_features;
133        cr4_set_bits(mask);
134}
135
136static inline void __native_flush_tlb(void)
137{
138        /*
139         * If current->mm == NULL then we borrow a mm which may change during a
140         * task switch and therefore we must not be preempted while we write CR3
141         * back:
142         */
143        preempt_disable();
144        native_write_cr3(native_read_cr3());
145        preempt_enable();
146}
147
148static inline void __native_flush_tlb_global_irq_disabled(void)
149{
150        unsigned long cr4;
151
152        cr4 = this_cpu_read(cpu_tlbstate.cr4);
153        /* clear PGE */
154        native_write_cr4(cr4 & ~X86_CR4_PGE);
155        /* write old PGE again and flush TLBs */
156        native_write_cr4(cr4);
157}
158
159static inline void __native_flush_tlb_global(void)
160{
161        unsigned long flags;
162
163        if (static_cpu_has(X86_FEATURE_INVPCID)) {
164                /*
165                 * Using INVPCID is considerably faster than a pair of writes
166                 * to CR4 sandwiched inside an IRQ flag save/restore.
167                 */
168                invpcid_flush_all();
169                return;
170        }
171
172        /*
173         * Read-modify-write to CR4 - protect it from preemption and
174         * from interrupts. (Use the raw variant because this code can
175         * be called from deep inside debugging code.)
176         */
177        raw_local_irq_save(flags);
178
179        __native_flush_tlb_global_irq_disabled();
180
181        raw_local_irq_restore(flags);
182}
183
184static inline void __native_flush_tlb_single(unsigned long addr)
185{
186        asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
187}
188
189static inline void __flush_tlb_all(void)
190{
191        if (boot_cpu_has(X86_FEATURE_PGE))
192                __flush_tlb_global();
193        else
194                __flush_tlb();
195}
196
197static inline void __flush_tlb_one(unsigned long addr)
198{
199        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
200        __flush_tlb_single(addr);
201}
202
203#define TLB_FLUSH_ALL   -1UL
204
205/*
206 * TLB flushing:
207 *
208 *  - flush_tlb() flushes the current mm struct TLBs
209 *  - flush_tlb_all() flushes all processes TLBs
210 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
211 *  - flush_tlb_page(vma, vmaddr) flushes one page
212 *  - flush_tlb_range(vma, start, end) flushes a range of pages
213 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
214 *  - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
215 *
216 * ..but the i386 has somewhat limited tlb flushing capabilities,
217 * and page-granular flushes are available only on i486 and up.
218 */
219
220#ifndef CONFIG_SMP
221
222/* "_up" is for UniProcessor.
223 *
224 * This is a helper for other header functions.  *Not* intended to be called
225 * directly.  All global TLB flushes need to either call this, or to bump the
226 * vm statistics themselves.
227 */
228static inline void __flush_tlb_up(void)
229{
230        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
231        __flush_tlb();
232}
233
234static inline void flush_tlb_all(void)
235{
236        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
237        __flush_tlb_all();
238}
239
240static inline void flush_tlb(void)
241{
242        __flush_tlb_up();
243}
244
245static inline void local_flush_tlb(void)
246{
247        __flush_tlb_up();
248}
249
250static inline void flush_tlb_mm(struct mm_struct *mm)
251{
252        if (mm == current->active_mm)
253                __flush_tlb_up();
254}
255
256static inline void flush_tlb_page(struct vm_area_struct *vma,
257                                  unsigned long addr)
258{
259        if (vma->vm_mm == current->active_mm)
260                __flush_tlb_one(addr);
261}
262
263static inline void flush_tlb_range(struct vm_area_struct *vma,
264                                   unsigned long start, unsigned long end)
265{
266        if (vma->vm_mm == current->active_mm)
267                __flush_tlb_up();
268}
269
270static inline void flush_tlb_mm_range(struct mm_struct *mm,
271           unsigned long start, unsigned long end, unsigned long vmflag)
272{
273        if (mm == current->active_mm)
274                __flush_tlb_up();
275}
276
277static inline void native_flush_tlb_others(const struct cpumask *cpumask,
278                                           struct mm_struct *mm,
279                                           unsigned long start,
280                                           unsigned long end)
281{
282}
283
284static inline void reset_lazy_tlbstate(void)
285{
286}
287
288static inline void flush_tlb_kernel_range(unsigned long start,
289                                          unsigned long end)
290{
291        flush_tlb_all();
292}
293
294#else  /* SMP */
295
296#include <asm/smp.h>
297
298#define local_flush_tlb() __flush_tlb()
299
300#define flush_tlb_mm(mm)        flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
301
302#define flush_tlb_range(vma, start, end)        \
303                flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
304
305extern void flush_tlb_all(void);
306extern void flush_tlb_current_task(void);
307extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
308extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
309                                unsigned long end, unsigned long vmflag);
310extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
311
312#define flush_tlb()     flush_tlb_current_task()
313
314void native_flush_tlb_others(const struct cpumask *cpumask,
315                                struct mm_struct *mm,
316                                unsigned long start, unsigned long end);
317
318#define TLBSTATE_OK     1
319#define TLBSTATE_LAZY   2
320
321static inline void reset_lazy_tlbstate(void)
322{
323        this_cpu_write(cpu_tlbstate.state, 0);
324        this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
325}
326
327#endif  /* SMP */
328
329#ifndef CONFIG_PARAVIRT
330#define flush_tlb_others(mask, mm, start, end)  \
331        native_flush_tlb_others(mask, mm, start, end)
332#endif
333
334#endif /* _ASM_X86_TLBFLUSH_H */
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