source: src/linux/universal/linux-4.9/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @ 31662

Last change on this file since 31662 was 31662, checked in by brainslayer, 11 days ago

use new squashfs in all kernels

File size: 118.4 KB
Line 
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_11_0_d.h"
36#include "dce/dce_11_0_sh_mask.h"
37#include "dce/dce_11_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48        CRTC0_REGISTER_OFFSET,
49        CRTC1_REGISTER_OFFSET,
50        CRTC2_REGISTER_OFFSET,
51        CRTC3_REGISTER_OFFSET,
52        CRTC4_REGISTER_OFFSET,
53        CRTC5_REGISTER_OFFSET,
54        CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59        HPD0_REGISTER_OFFSET,
60        HPD1_REGISTER_OFFSET,
61        HPD2_REGISTER_OFFSET,
62        HPD3_REGISTER_OFFSET,
63        HPD4_REGISTER_OFFSET,
64        HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68        DIG0_REGISTER_OFFSET,
69        DIG1_REGISTER_OFFSET,
70        DIG2_REGISTER_OFFSET,
71        DIG3_REGISTER_OFFSET,
72        DIG4_REGISTER_OFFSET,
73        DIG5_REGISTER_OFFSET,
74        DIG6_REGISTER_OFFSET,
75        DIG7_REGISTER_OFFSET,
76        DIG8_REGISTER_OFFSET
77};
78
79static const struct {
80        uint32_t        reg;
81        uint32_t        vblank;
82        uint32_t        vline;
83        uint32_t        hpd;
84
85} interrupt_status_offsets[] = { {
86        .reg = mmDISP_INTERRUPT_STATUS,
87        .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88        .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89        .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90}, {
91        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92        .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93        .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94        .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95}, {
96        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97        .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98        .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99        .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100}, {
101        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102        .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103        .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104        .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105}, {
106        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107        .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108        .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109        .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110}, {
111        .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112        .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113        .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114        .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115} };
116
117static const u32 cz_golden_settings_a11[] =
118{
119        mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120        mmFBC_MISC, 0x1f311fff, 0x14300000,
121};
122
123static const u32 cz_mgcg_cgcg_init[] =
124{
125        mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126        mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
129static const u32 stoney_golden_settings_a11[] =
130{
131        mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132        mmFBC_MISC, 0x1f311fff, 0x14302000,
133};
134
135static const u32 polaris11_golden_settings_a11[] =
136{
137        mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138        mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139        mmFBC_DEBUG1, 0xffffffff, 0x00000008,
140        mmFBC_MISC, 0x9f313fff, 0x14302008,
141        mmHDMI_CONTROL, 0x313f031f, 0x00000011,
142};
143
144static const u32 polaris10_golden_settings_a11[] =
145{
146        mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
147        mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
148        mmFBC_MISC, 0x9f313fff, 0x14302008,
149        mmHDMI_CONTROL, 0x313f031f, 0x00000011,
150};
151
152static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
153{
154        switch (adev->asic_type) {
155        case CHIP_CARRIZO:
156                amdgpu_program_register_sequence(adev,
157                                                 cz_mgcg_cgcg_init,
158                                                 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
159                amdgpu_program_register_sequence(adev,
160                                                 cz_golden_settings_a11,
161                                                 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
162                break;
163        case CHIP_STONEY:
164                amdgpu_program_register_sequence(adev,
165                                                 stoney_golden_settings_a11,
166                                                 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
167                break;
168        case CHIP_POLARIS11:
169                amdgpu_program_register_sequence(adev,
170                                                 polaris11_golden_settings_a11,
171                                                 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
172                break;
173        case CHIP_POLARIS10:
174                amdgpu_program_register_sequence(adev,
175                                                 polaris10_golden_settings_a11,
176                                                 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
177                break;
178        default:
179                break;
180        }
181}
182
183static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
184                                     u32 block_offset, u32 reg)
185{
186        unsigned long flags;
187        u32 r;
188
189        spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191        r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
192        spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
193
194        return r;
195}
196
197static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
198                                      u32 block_offset, u32 reg, u32 v)
199{
200        unsigned long flags;
201
202        spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204        WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
205        spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
206}
207
208static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
209{
210        if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
211                        CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
212                return true;
213        else
214                return false;
215}
216
217static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
218{
219        u32 pos1, pos2;
220
221        pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
222        pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
223
224        if (pos1 != pos2)
225                return true;
226        else
227                return false;
228}
229
230/**
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
232 *
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
235 *
236 * Wait for vblank on the requested crtc (evergreen+).
237 */
238static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
239{
240        unsigned i = 100;
241
242        if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
243                return;
244
245        if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
246                return;
247
248        /* depending on when we hit vblank, we may be close to active; if so,
249         * wait for another frame.
250         */
251        while (dce_v11_0_is_in_vblank(adev, crtc)) {
252                if (i++ == 100) {
253                        i = 0;
254                        if (!dce_v11_0_is_counter_moving(adev, crtc))
255                                break;
256                }
257        }
258
259        while (!dce_v11_0_is_in_vblank(adev, crtc)) {
260                if (i++ == 100) {
261                        i = 0;
262                        if (!dce_v11_0_is_counter_moving(adev, crtc))
263                                break;
264                }
265        }
266}
267
268static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
269{
270        if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
271                return 0;
272        else
273                return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
274}
275
276static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
277{
278        unsigned i;
279
280        /* Enable pflip interrupts */
281        for (i = 0; i < adev->mode_info.num_crtc; i++)
282                amdgpu_irq_get(adev, &adev->pageflip_irq, i);
283}
284
285static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
286{
287        unsigned i;
288
289        /* Disable pflip interrupts */
290        for (i = 0; i < adev->mode_info.num_crtc; i++)
291                amdgpu_irq_put(adev, &adev->pageflip_irq, i);
292}
293
294/**
295 * dce_v11_0_page_flip - pageflip callback.
296 *
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
300 *
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
303 */
304static void dce_v11_0_page_flip(struct amdgpu_device *adev,
305                                int crtc_id, u64 crtc_base, bool async)
306{
307        struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
308        u32 tmp;
309
310        /* flip immediate for async, default is vsync */
311        tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
312        tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
313                            GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
314        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
315        /* update the scanout addresses */
316        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
317               upper_32_bits(crtc_base));
318        /* writing to the low address triggers the update */
319        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
320               lower_32_bits(crtc_base));
321        /* post the write */
322        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
323}
324
325static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
326                                        u32 *vbl, u32 *position)
327{
328        if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
329                return -EINVAL;
330
331        *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
332        *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
333
334        return 0;
335}
336
337/**
338 * dce_v11_0_hpd_sense - hpd sense callback.
339 *
340 * @adev: amdgpu_device pointer
341 * @hpd: hpd (hotplug detect) pin
342 *
343 * Checks if a digital monitor is connected (evergreen+).
344 * Returns true if connected, false if not connected.
345 */
346static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
347                               enum amdgpu_hpd_id hpd)
348{
349        int idx;
350        bool connected = false;
351
352        switch (hpd) {
353        case AMDGPU_HPD_1:
354                idx = 0;
355                break;
356        case AMDGPU_HPD_2:
357                idx = 1;
358                break;
359        case AMDGPU_HPD_3:
360                idx = 2;
361                break;
362        case AMDGPU_HPD_4:
363                idx = 3;
364                break;
365        case AMDGPU_HPD_5:
366                idx = 4;
367                break;
368        case AMDGPU_HPD_6:
369                idx = 5;
370                break;
371        default:
372                return connected;
373        }
374
375        if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
376            DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
377                connected = true;
378
379        return connected;
380}
381
382/**
383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
384 *
385 * @adev: amdgpu_device pointer
386 * @hpd: hpd (hotplug detect) pin
387 *
388 * Set the polarity of the hpd pin (evergreen+).
389 */
390static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
391                                      enum amdgpu_hpd_id hpd)
392{
393        u32 tmp;
394        bool connected = dce_v11_0_hpd_sense(adev, hpd);
395        int idx;
396
397        switch (hpd) {
398        case AMDGPU_HPD_1:
399                idx = 0;
400                break;
401        case AMDGPU_HPD_2:
402                idx = 1;
403                break;
404        case AMDGPU_HPD_3:
405                idx = 2;
406                break;
407        case AMDGPU_HPD_4:
408                idx = 3;
409                break;
410        case AMDGPU_HPD_5:
411                idx = 4;
412                break;
413        case AMDGPU_HPD_6:
414                idx = 5;
415                break;
416        default:
417                return;
418        }
419
420        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
421        if (connected)
422                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
423        else
424                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
425        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
426}
427
428/**
429 * dce_v11_0_hpd_init - hpd setup callback.
430 *
431 * @adev: amdgpu_device pointer
432 *
433 * Setup the hpd pins used by the card (evergreen+).
434 * Enable the pin, set the polarity, and enable the hpd interrupts.
435 */
436static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
437{
438        struct drm_device *dev = adev->ddev;
439        struct drm_connector *connector;
440        u32 tmp;
441        int idx;
442
443        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
444                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
445
446                switch (amdgpu_connector->hpd.hpd) {
447                case AMDGPU_HPD_1:
448                        idx = 0;
449                        break;
450                case AMDGPU_HPD_2:
451                        idx = 1;
452                        break;
453                case AMDGPU_HPD_3:
454                        idx = 2;
455                        break;
456                case AMDGPU_HPD_4:
457                        idx = 3;
458                        break;
459                case AMDGPU_HPD_5:
460                        idx = 4;
461                        break;
462                case AMDGPU_HPD_6:
463                        idx = 5;
464                        break;
465                default:
466                        continue;
467                }
468
469                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
470                    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
471                        /* don't try to enable hpd on eDP or LVDS avoid breaking the
472                         * aux dp channel on imac and help (but not completely fix)
473                         * https://bugzilla.redhat.com/show_bug.cgi?id=726143
474                         * also avoid interrupt storms during dpms.
475                         */
476                        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
477                        tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
478                        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
479                        continue;
480                }
481
482                tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
483                tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
484                WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
485
486                tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
487                tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
488                                    DC_HPD_CONNECT_INT_DELAY,
489                                    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
490                tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
491                                    DC_HPD_DISCONNECT_INT_DELAY,
492                                    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
493                WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
494
495                dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
496                amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
497        }
498}
499
500/**
501 * dce_v11_0_hpd_fini - hpd tear down callback.
502 *
503 * @adev: amdgpu_device pointer
504 *
505 * Tear down the hpd pins used by the card (evergreen+).
506 * Disable the hpd interrupts.
507 */
508static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
509{
510        struct drm_device *dev = adev->ddev;
511        struct drm_connector *connector;
512        u32 tmp;
513        int idx;
514
515        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
516                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517
518                switch (amdgpu_connector->hpd.hpd) {
519                case AMDGPU_HPD_1:
520                        idx = 0;
521                        break;
522                case AMDGPU_HPD_2:
523                        idx = 1;
524                        break;
525                case AMDGPU_HPD_3:
526                        idx = 2;
527                        break;
528                case AMDGPU_HPD_4:
529                        idx = 3;
530                        break;
531                case AMDGPU_HPD_5:
532                        idx = 4;
533                        break;
534                case AMDGPU_HPD_6:
535                        idx = 5;
536                        break;
537                default:
538                        continue;
539                }
540
541                tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
542                tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
543                WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
544
545                amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
546        }
547}
548
549static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
550{
551        return mmDC_GPIO_HPD_A;
552}
553
554static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
555{
556        u32 crtc_hung = 0;
557        u32 crtc_status[6];
558        u32 i, j, tmp;
559
560        for (i = 0; i < adev->mode_info.num_crtc; i++) {
561                tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
562                if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
563                        crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
564                        crtc_hung |= (1 << i);
565                }
566        }
567
568        for (j = 0; j < 10; j++) {
569                for (i = 0; i < adev->mode_info.num_crtc; i++) {
570                        if (crtc_hung & (1 << i)) {
571                                tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
572                                if (tmp != crtc_status[i])
573                                        crtc_hung &= ~(1 << i);
574                        }
575                }
576                if (crtc_hung == 0)
577                        return false;
578                udelay(100);
579        }
580
581        return true;
582}
583
584static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
585                                     struct amdgpu_mode_mc_save *save)
586{
587        u32 crtc_enabled, tmp;
588        int i;
589
590        save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
591        save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
592
593        /* disable VGA render */
594        tmp = RREG32(mmVGA_RENDER_CONTROL);
595        tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
596        WREG32(mmVGA_RENDER_CONTROL, tmp);
597
598        /* blank the display controllers */
599        for (i = 0; i < adev->mode_info.num_crtc; i++) {
600                crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
601                                             CRTC_CONTROL, CRTC_MASTER_EN);
602                if (crtc_enabled) {
603#if 1
604                        save->crtc_enabled[i] = true;
605                        tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
606                        if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
607                                /*it is correct only for RGB ; black is 0*/
608                                WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
609                                tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
610                                WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
611                        }
612#else
613                        /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
614                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
615                        tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
616                        tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
617                        WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
618                        WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
619                        save->crtc_enabled[i] = false;
620                        /* ***** */
621#endif
622                } else {
623                        save->crtc_enabled[i] = false;
624                }
625        }
626}
627
628static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
629                                       struct amdgpu_mode_mc_save *save)
630{
631        u32 tmp;
632        int i;
633
634        /* update crtc base addresses */
635        for (i = 0; i < adev->mode_info.num_crtc; i++) {
636                WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
637                       upper_32_bits(adev->mc.vram_start));
638                WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
639                       (u32)adev->mc.vram_start);
640
641                if (save->crtc_enabled[i]) {
642                        tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
643                        tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
644                        WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
645                }
646        }
647
648        WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
649        WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
650
651        /* Unlock vga access */
652        WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
653        mdelay(1);
654        WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
655}
656
657static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
658                                           bool render)
659{
660        u32 tmp;
661
662        /* Lockout access through VGA aperture*/
663        tmp = RREG32(mmVGA_HDP_CONTROL);
664        if (render)
665                tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
666        else
667                tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
668        WREG32(mmVGA_HDP_CONTROL, tmp);
669
670        /* disable VGA render */
671        tmp = RREG32(mmVGA_RENDER_CONTROL);
672        if (render)
673                tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
674        else
675                tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
676        WREG32(mmVGA_RENDER_CONTROL, tmp);
677}
678
679static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
680{
681        int num_crtc = 0;
682
683        switch (adev->asic_type) {
684        case CHIP_CARRIZO:
685                num_crtc = 3;
686                break;
687        case CHIP_STONEY:
688                num_crtc = 2;
689                break;
690        case CHIP_POLARIS10:
691                num_crtc = 6;
692                break;
693        case CHIP_POLARIS11:
694                num_crtc = 5;
695                break;
696        default:
697                num_crtc = 0;
698        }
699        return num_crtc;
700}
701
702void dce_v11_0_disable_dce(struct amdgpu_device *adev)
703{
704        /*Disable VGA render and enabled crtc, if has DCE engine*/
705        if (amdgpu_atombios_has_dce_engine_info(adev)) {
706                u32 tmp;
707                int crtc_enabled, i;
708
709                dce_v11_0_set_vga_render_state(adev, false);
710
711                /*Disable crtc*/
712                for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
713                        crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
714                                                                         CRTC_CONTROL, CRTC_MASTER_EN);
715                        if (crtc_enabled) {
716                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
717                                tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
718                                tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
719                                WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
720                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
721                        }
722                }
723        }
724}
725
726static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
727{
728        struct drm_device *dev = encoder->dev;
729        struct amdgpu_device *adev = dev->dev_private;
730        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
731        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
732        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
733        int bpc = 0;
734        u32 tmp = 0;
735        enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
736
737        if (connector) {
738                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
739                bpc = amdgpu_connector_get_monitor_bpc(connector);
740                dither = amdgpu_connector->dither;
741        }
742
743        /* LVDS/eDP FMT is set up by atom */
744        if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
745                return;
746
747        /* not needed for analog */
748        if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
749            (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
750                return;
751
752        if (bpc == 0)
753                return;
754
755        switch (bpc) {
756        case 6:
757                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
758                        /* XXX sort out optimal dither settings */
759                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
760                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
761                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
762                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
763                } else {
764                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
765                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
766                }
767                break;
768        case 8:
769                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
770                        /* XXX sort out optimal dither settings */
771                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
772                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
773                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
774                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
775                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
776                } else {
777                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
778                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
779                }
780                break;
781        case 10:
782                if (dither == AMDGPU_FMT_DITHER_ENABLE) {
783                        /* XXX sort out optimal dither settings */
784                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
785                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
786                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
787                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
788                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
789                } else {
790                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
791                        tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
792                }
793                break;
794        default:
795                /* not needed */
796                break;
797        }
798
799        WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
800}
801
802
803/* display watermark setup */
804/**
805 * dce_v11_0_line_buffer_adjust - Set up the line buffer
806 *
807 * @adev: amdgpu_device pointer
808 * @amdgpu_crtc: the selected display controller
809 * @mode: the current display mode on the selected display
810 * controller
811 *
812 * Setup up the line buffer allocation for
813 * the selected display controller (CIK).
814 * Returns the line buffer size in pixels.
815 */
816static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
817                                       struct amdgpu_crtc *amdgpu_crtc,
818                                       struct drm_display_mode *mode)
819{
820        u32 tmp, buffer_alloc, i, mem_cfg;
821        u32 pipe_offset = amdgpu_crtc->crtc_id;
822        /*
823         * Line Buffer Setup
824         * There are 6 line buffers, one for each display controllers.
825         * There are 3 partitions per LB. Select the number of partitions
826         * to enable based on the display width.  For display widths larger
827         * than 4096, you need use to use 2 display controllers and combine
828         * them using the stereo blender.
829         */
830        if (amdgpu_crtc->base.enabled && mode) {
831                if (mode->crtc_hdisplay < 1920) {
832                        mem_cfg = 1;
833                        buffer_alloc = 2;
834                } else if (mode->crtc_hdisplay < 2560) {
835                        mem_cfg = 2;
836                        buffer_alloc = 2;
837                } else if (mode->crtc_hdisplay < 4096) {
838                        mem_cfg = 0;
839                        buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
840                } else {
841                        DRM_DEBUG_KMS("Mode too big for LB!\n");
842                        mem_cfg = 0;
843                        buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
844                }
845        } else {
846                mem_cfg = 1;
847                buffer_alloc = 0;
848        }
849
850        tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
851        tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
852        WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
853
854        tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
855        tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
856        WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
857
858        for (i = 0; i < adev->usec_timeout; i++) {
859                tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
860                if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
861                        break;
862                udelay(1);
863        }
864
865        if (amdgpu_crtc->base.enabled && mode) {
866                switch (mem_cfg) {
867                case 0:
868                default:
869                        return 4096 * 2;
870                case 1:
871                        return 1920 * 2;
872                case 2:
873                        return 2560 * 2;
874                }
875        }
876
877        /* controller not enabled, so no lb used */
878        return 0;
879}
880
881/**
882 * cik_get_number_of_dram_channels - get the number of dram channels
883 *
884 * @adev: amdgpu_device pointer
885 *
886 * Look up the number of video ram channels (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the number of dram channels
889 */
890static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
891{
892        u32 tmp = RREG32(mmMC_SHARED_CHMAP);
893
894        switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
895        case 0:
896        default:
897                return 1;
898        case 1:
899                return 2;
900        case 2:
901                return 4;
902        case 3:
903                return 8;
904        case 4:
905                return 3;
906        case 5:
907                return 6;
908        case 6:
909                return 10;
910        case 7:
911                return 12;
912        case 8:
913                return 16;
914        }
915}
916
917struct dce10_wm_params {
918        u32 dram_channels; /* number of dram channels */
919        u32 yclk;          /* bandwidth per dram data pin in kHz */
920        u32 sclk;          /* engine clock in kHz */
921        u32 disp_clk;      /* display clock in kHz */
922        u32 src_width;     /* viewport width */
923        u32 active_time;   /* active display time in ns */
924        u32 blank_time;    /* blank time in ns */
925        bool interlaced;    /* mode is interlaced */
926        fixed20_12 vsc;    /* vertical scale ratio */
927        u32 num_heads;     /* number of active crtcs */
928        u32 bytes_per_pixel; /* bytes per pixel display + overlay */
929        u32 lb_size;       /* line buffer allocated to pipe */
930        u32 vtaps;         /* vertical scaler taps */
931};
932
933/**
934 * dce_v11_0_dram_bandwidth - get the dram bandwidth
935 *
936 * @wm: watermark calculation data
937 *
938 * Calculate the raw dram bandwidth (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns the dram bandwidth in MBytes/s
941 */
942static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
943{
944        /* Calculate raw DRAM Bandwidth */
945        fixed20_12 dram_efficiency; /* 0.7 */
946        fixed20_12 yclk, dram_channels, bandwidth;
947        fixed20_12 a;
948
949        a.full = dfixed_const(1000);
950        yclk.full = dfixed_const(wm->yclk);
951        yclk.full = dfixed_div(yclk, a);
952        dram_channels.full = dfixed_const(wm->dram_channels * 4);
953        a.full = dfixed_const(10);
954        dram_efficiency.full = dfixed_const(7);
955        dram_efficiency.full = dfixed_div(dram_efficiency, a);
956        bandwidth.full = dfixed_mul(dram_channels, yclk);
957        bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
958
959        return dfixed_trunc(bandwidth);
960}
961
962/**
963 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
964 *
965 * @wm: watermark calculation data
966 *
967 * Calculate the dram bandwidth used for display (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns the dram bandwidth for display in MBytes/s
970 */
971static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
972{
973        /* Calculate DRAM Bandwidth and the part allocated to display. */
974        fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
975        fixed20_12 yclk, dram_channels, bandwidth;
976        fixed20_12 a;
977
978        a.full = dfixed_const(1000);
979        yclk.full = dfixed_const(wm->yclk);
980        yclk.full = dfixed_div(yclk, a);
981        dram_channels.full = dfixed_const(wm->dram_channels * 4);
982        a.full = dfixed_const(10);
983        disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
984        disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
985        bandwidth.full = dfixed_mul(dram_channels, yclk);
986        bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
987
988        return dfixed_trunc(bandwidth);
989}
990
991/**
992 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
993 *
994 * @wm: watermark calculation data
995 *
996 * Calculate the data return bandwidth used for display (CIK).
997 * Used for display watermark bandwidth calculations
998 * Returns the data return bandwidth in MBytes/s
999 */
1000static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
1001{
1002        /* Calculate the display Data return Bandwidth */
1003        fixed20_12 return_efficiency; /* 0.8 */
1004        fixed20_12 sclk, bandwidth;
1005        fixed20_12 a;
1006
1007        a.full = dfixed_const(1000);
1008        sclk.full = dfixed_const(wm->sclk);
1009        sclk.full = dfixed_div(sclk, a);
1010        a.full = dfixed_const(10);
1011        return_efficiency.full = dfixed_const(8);
1012        return_efficiency.full = dfixed_div(return_efficiency, a);
1013        a.full = dfixed_const(32);
1014        bandwidth.full = dfixed_mul(a, sclk);
1015        bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1016
1017        return dfixed_trunc(bandwidth);
1018}
1019
1020/**
1021 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
1022 *
1023 * @wm: watermark calculation data
1024 *
1025 * Calculate the dmif bandwidth used for display (CIK).
1026 * Used for display watermark bandwidth calculations
1027 * Returns the dmif bandwidth in MBytes/s
1028 */
1029static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1030{
1031        /* Calculate the DMIF Request Bandwidth */
1032        fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1033        fixed20_12 disp_clk, bandwidth;
1034        fixed20_12 a, b;
1035
1036        a.full = dfixed_const(1000);
1037        disp_clk.full = dfixed_const(wm->disp_clk);
1038        disp_clk.full = dfixed_div(disp_clk, a);
1039        a.full = dfixed_const(32);
1040        b.full = dfixed_mul(a, disp_clk);
1041
1042        a.full = dfixed_const(10);
1043        disp_clk_request_efficiency.full = dfixed_const(8);
1044        disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1045
1046        bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1047
1048        return dfixed_trunc(bandwidth);
1049}
1050
1051/**
1052 * dce_v11_0_available_bandwidth - get the min available bandwidth
1053 *
1054 * @wm: watermark calculation data
1055 *
1056 * Calculate the min available bandwidth used for display (CIK).
1057 * Used for display watermark bandwidth calculations
1058 * Returns the min available bandwidth in MBytes/s
1059 */
1060static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1061{
1062        /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1063        u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1064        u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1065        u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1066
1067        return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1068}
1069
1070/**
1071 * dce_v11_0_average_bandwidth - get the average available bandwidth
1072 *
1073 * @wm: watermark calculation data
1074 *
1075 * Calculate the average available bandwidth used for display (CIK).
1076 * Used for display watermark bandwidth calculations
1077 * Returns the average available bandwidth in MBytes/s
1078 */
1079static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1080{
1081        /* Calculate the display mode Average Bandwidth
1082         * DisplayMode should contain the source and destination dimensions,
1083         * timing, etc.
1084         */
1085        fixed20_12 bpp;
1086        fixed20_12 line_time;
1087        fixed20_12 src_width;
1088        fixed20_12 bandwidth;
1089        fixed20_12 a;
1090
1091        a.full = dfixed_const(1000);
1092        line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1093        line_time.full = dfixed_div(line_time, a);
1094        bpp.full = dfixed_const(wm->bytes_per_pixel);
1095        src_width.full = dfixed_const(wm->src_width);
1096        bandwidth.full = dfixed_mul(src_width, bpp);
1097        bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1098        bandwidth.full = dfixed_div(bandwidth, line_time);
1099
1100        return dfixed_trunc(bandwidth);
1101}
1102
1103/**
1104 * dce_v11_0_latency_watermark - get the latency watermark
1105 *
1106 * @wm: watermark calculation data
1107 *
1108 * Calculate the latency watermark (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns the latency watermark in ns
1111 */
1112static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1113{
1114        /* First calculate the latency in ns */
1115        u32 mc_latency = 2000; /* 2000 ns. */
1116        u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1117        u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1118        u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1119        u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1120        u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1121                (wm->num_heads * cursor_line_pair_return_time);
1122        u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1123        u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1124        u32 tmp, dmif_size = 12288;
1125        fixed20_12 a, b, c;
1126
1127        if (wm->num_heads == 0)
1128                return 0;
1129
1130        a.full = dfixed_const(2);
1131        b.full = dfixed_const(1);
1132        if ((wm->vsc.full > a.full) ||
1133            ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1134            (wm->vtaps >= 5) ||
1135            ((wm->vsc.full >= a.full) && wm->interlaced))
1136                max_src_lines_per_dst_line = 4;
1137        else
1138                max_src_lines_per_dst_line = 2;
1139
1140        a.full = dfixed_const(available_bandwidth);
1141        b.full = dfixed_const(wm->num_heads);
1142        a.full = dfixed_div(a, b);
1143
1144        b.full = dfixed_const(mc_latency + 512);
1145        c.full = dfixed_const(wm->disp_clk);
1146        b.full = dfixed_div(b, c);
1147
1148        c.full = dfixed_const(dmif_size);
1149        b.full = dfixed_div(c, b);
1150
1151        tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1152
1153        b.full = dfixed_const(1000);
1154        c.full = dfixed_const(wm->disp_clk);
1155        b.full = dfixed_div(c, b);
1156        c.full = dfixed_const(wm->bytes_per_pixel);
1157        b.full = dfixed_mul(b, c);
1158
1159        lb_fill_bw = min(tmp, dfixed_trunc(b));
1160
1161        a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1162        b.full = dfixed_const(1000);
1163        c.full = dfixed_const(lb_fill_bw);
1164        b.full = dfixed_div(c, b);
1165        a.full = dfixed_div(a, b);
1166        line_fill_time = dfixed_trunc(a);
1167
1168        if (line_fill_time < wm->active_time)
1169                return latency;
1170        else
1171                return latency + (line_fill_time - wm->active_time);
1172
1173}
1174
1175/**
1176 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1177 * average and available dram bandwidth
1178 *
1179 * @wm: watermark calculation data
1180 *
1181 * Check if the display average bandwidth fits in the display
1182 * dram bandwidth (CIK).
1183 * Used for display watermark bandwidth calculations
1184 * Returns true if the display fits, false if not.
1185 */
1186static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1187{
1188        if (dce_v11_0_average_bandwidth(wm) <=
1189            (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1190                return true;
1191        else
1192                return false;
1193}
1194
1195/**
1196 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1197 * average and available bandwidth
1198 *
1199 * @wm: watermark calculation data
1200 *
1201 * Check if the display average bandwidth fits in the display
1202 * available bandwidth (CIK).
1203 * Used for display watermark bandwidth calculations
1204 * Returns true if the display fits, false if not.
1205 */
1206static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1207{
1208        if (dce_v11_0_average_bandwidth(wm) <=
1209            (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1210                return true;
1211        else
1212                return false;
1213}
1214
1215/**
1216 * dce_v11_0_check_latency_hiding - check latency hiding
1217 *
1218 * @wm: watermark calculation data
1219 *
1220 * Check latency hiding (CIK).
1221 * Used for display watermark bandwidth calculations
1222 * Returns true if the display fits, false if not.
1223 */
1224static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1225{
1226        u32 lb_partitions = wm->lb_size / wm->src_width;
1227        u32 line_time = wm->active_time + wm->blank_time;
1228        u32 latency_tolerant_lines;
1229        u32 latency_hiding;
1230        fixed20_12 a;
1231
1232        a.full = dfixed_const(1);
1233        if (wm->vsc.full > a.full)
1234                latency_tolerant_lines = 1;
1235        else {
1236                if (lb_partitions <= (wm->vtaps + 1))
1237                        latency_tolerant_lines = 1;
1238                else
1239                        latency_tolerant_lines = 2;
1240        }
1241
1242        latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1243
1244        if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1245                return true;
1246        else
1247                return false;
1248}
1249
1250/**
1251 * dce_v11_0_program_watermarks - program display watermarks
1252 *
1253 * @adev: amdgpu_device pointer
1254 * @amdgpu_crtc: the selected display controller
1255 * @lb_size: line buffer size
1256 * @num_heads: number of display controllers in use
1257 *
1258 * Calculate and program the display watermarks for the
1259 * selected display controller (CIK).
1260 */
1261static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1262                                        struct amdgpu_crtc *amdgpu_crtc,
1263                                        u32 lb_size, u32 num_heads)
1264{
1265        struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1266        struct dce10_wm_params wm_low, wm_high;
1267        u32 pixel_period;
1268        u32 line_time = 0;
1269        u32 latency_watermark_a = 0, latency_watermark_b = 0;
1270        u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1271
1272        if (amdgpu_crtc->base.enabled && num_heads && mode) {
1273                pixel_period = 1000000 / (u32)mode->clock;
1274                line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1275
1276                /* watermark for high clocks */
1277                if (adev->pm.dpm_enabled) {
1278                        wm_high.yclk =
1279                                amdgpu_dpm_get_mclk(adev, false) * 10;
1280                        wm_high.sclk =
1281                                amdgpu_dpm_get_sclk(adev, false) * 10;
1282                } else {
1283                        wm_high.yclk = adev->pm.current_mclk * 10;
1284                        wm_high.sclk = adev->pm.current_sclk * 10;
1285                }
1286
1287                wm_high.disp_clk = mode->clock;
1288                wm_high.src_width = mode->crtc_hdisplay;
1289                wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1290                wm_high.blank_time = line_time - wm_high.active_time;
1291                wm_high.interlaced = false;
1292                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1293                        wm_high.interlaced = true;
1294                wm_high.vsc = amdgpu_crtc->vsc;
1295                wm_high.vtaps = 1;
1296                if (amdgpu_crtc->rmx_type != RMX_OFF)
1297                        wm_high.vtaps = 2;
1298                wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1299                wm_high.lb_size = lb_size;
1300                wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1301                wm_high.num_heads = num_heads;
1302
1303                /* set for high clocks */
1304                latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1305
1306                /* possibly force display priority to high */
1307                /* should really do this at mode validation time... */
1308                if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1309                    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1310                    !dce_v11_0_check_latency_hiding(&wm_high) ||
1311                    (adev->mode_info.disp_priority == 2)) {
1312                        DRM_DEBUG_KMS("force priority to high\n");
1313                }
1314
1315                /* watermark for low clocks */
1316                if (adev->pm.dpm_enabled) {
1317                        wm_low.yclk =
1318                                amdgpu_dpm_get_mclk(adev, true) * 10;
1319                        wm_low.sclk =
1320                                amdgpu_dpm_get_sclk(adev, true) * 10;
1321                } else {
1322                        wm_low.yclk = adev->pm.current_mclk * 10;
1323                        wm_low.sclk = adev->pm.current_sclk * 10;
1324                }
1325
1326                wm_low.disp_clk = mode->clock;
1327                wm_low.src_width = mode->crtc_hdisplay;
1328                wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1329                wm_low.blank_time = line_time - wm_low.active_time;
1330                wm_low.interlaced = false;
1331                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1332                        wm_low.interlaced = true;
1333                wm_low.vsc = amdgpu_crtc->vsc;
1334                wm_low.vtaps = 1;
1335                if (amdgpu_crtc->rmx_type != RMX_OFF)
1336                        wm_low.vtaps = 2;
1337                wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1338                wm_low.lb_size = lb_size;
1339                wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1340                wm_low.num_heads = num_heads;
1341
1342                /* set for low clocks */
1343                latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1344
1345                /* possibly force display priority to high */
1346                /* should really do this at mode validation time... */
1347                if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1348                    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1349                    !dce_v11_0_check_latency_hiding(&wm_low) ||
1350                    (adev->mode_info.disp_priority == 2)) {
1351                        DRM_DEBUG_KMS("force priority to high\n");
1352                }
1353                lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1354        }
1355
1356        /* select wm A */
1357        wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1358        tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1359        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1360        tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1361        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1362        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1363        WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1364        /* select wm B */
1365        tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1366        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1367        tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1368        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1369        tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1370        WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1371        /* restore original selection */
1372        WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1373
1374        /* save values for DPM */
1375        amdgpu_crtc->line_time = line_time;
1376        amdgpu_crtc->wm_high = latency_watermark_a;
1377        amdgpu_crtc->wm_low = latency_watermark_b;
1378        /* Save number of lines the linebuffer leads before the scanout */
1379        amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1380}
1381
1382/**
1383 * dce_v11_0_bandwidth_update - program display watermarks
1384 *
1385 * @adev: amdgpu_device pointer
1386 *
1387 * Calculate and program the display watermarks and line
1388 * buffer allocation (CIK).
1389 */
1390static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1391{
1392        struct drm_display_mode *mode = NULL;
1393        u32 num_heads = 0, lb_size;
1394        int i;
1395
1396        amdgpu_update_display_priority(adev);
1397
1398        for (i = 0; i < adev->mode_info.num_crtc; i++) {
1399                if (adev->mode_info.crtcs[i]->base.enabled)
1400                        num_heads++;
1401        }
1402        for (i = 0; i < adev->mode_info.num_crtc; i++) {
1403                mode = &adev->mode_info.crtcs[i]->base.mode;
1404                lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1405                dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1406                                            lb_size, num_heads);
1407        }
1408}
1409
1410static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1411{
1412        int i;
1413        u32 offset, tmp;
1414
1415        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1416                offset = adev->mode_info.audio.pin[i].offset;
1417                tmp = RREG32_AUDIO_ENDPT(offset,
1418                                         ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1419                if (((tmp &
1420                AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1421                AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1422                        adev->mode_info.audio.pin[i].connected = false;
1423                else
1424                        adev->mode_info.audio.pin[i].connected = true;
1425        }
1426}
1427
1428static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1429{
1430        int i;
1431
1432        dce_v11_0_audio_get_connected_pins(adev);
1433
1434        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1435                if (adev->mode_info.audio.pin[i].connected)
1436                        return &adev->mode_info.audio.pin[i];
1437        }
1438        DRM_ERROR("No connected audio pins found!\n");
1439        return NULL;
1440}
1441
1442static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1443{
1444        struct amdgpu_device *adev = encoder->dev->dev_private;
1445        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1446        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1447        u32 tmp;
1448
1449        if (!dig || !dig->afmt || !dig->afmt->pin)
1450                return;
1451
1452        tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1453        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1454        WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1455}
1456
1457static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1458                                                struct drm_display_mode *mode)
1459{
1460        struct amdgpu_device *adev = encoder->dev->dev_private;
1461        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1462        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1463        struct drm_connector *connector;
1464        struct amdgpu_connector *amdgpu_connector = NULL;
1465        u32 tmp;
1466        int interlace = 0;
1467
1468        if (!dig || !dig->afmt || !dig->afmt->pin)
1469                return;
1470
1471        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1472                if (connector->encoder == encoder) {
1473                        amdgpu_connector = to_amdgpu_connector(connector);
1474                        break;
1475                }
1476        }
1477
1478        if (!amdgpu_connector) {
1479                DRM_ERROR("Couldn't find encoder's connector\n");
1480                return;
1481        }
1482
1483        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1484                interlace = 1;
1485        if (connector->latency_present[interlace]) {
1486                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1487                                    VIDEO_LIPSYNC, connector->video_latency[interlace]);
1488                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1489                                    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1490        } else {
1491                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1492                                    VIDEO_LIPSYNC, 0);
1493                tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1494                                    AUDIO_LIPSYNC, 0);
1495        }
1496        WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1497                           ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1498}
1499
1500static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1501{
1502        struct amdgpu_device *adev = encoder->dev->dev_private;
1503        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1504        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1505        struct drm_connector *connector;
1506        struct amdgpu_connector *amdgpu_connector = NULL;
1507        u32 tmp;
1508        u8 *sadb = NULL;
1509        int sad_count;
1510
1511        if (!dig || !dig->afmt || !dig->afmt->pin)
1512                return;
1513
1514        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1515                if (connector->encoder == encoder) {
1516                        amdgpu_connector = to_amdgpu_connector(connector);
1517                        break;
1518                }
1519        }
1520
1521        if (!amdgpu_connector) {
1522                DRM_ERROR("Couldn't find encoder's connector\n");
1523                return;
1524        }
1525
1526        sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1527        if (sad_count < 0) {
1528                DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1529                sad_count = 0;
1530        }
1531
1532        /* program the speaker allocation */
1533        tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1534                                 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1535        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1536                            DP_CONNECTION, 0);
1537        /* set HDMI mode */
1538        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1539                            HDMI_CONNECTION, 1);
1540        if (sad_count)
1541                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1542                                    SPEAKER_ALLOCATION, sadb[0]);
1543        else
1544                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1545                                    SPEAKER_ALLOCATION, 5); /* stereo */
1546        WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1547                           ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1548
1549        kfree(sadb);
1550}
1551
1552static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1553{
1554        struct amdgpu_device *adev = encoder->dev->dev_private;
1555        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1556        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1557        struct drm_connector *connector;
1558        struct amdgpu_connector *amdgpu_connector = NULL;
1559        struct cea_sad *sads;
1560        int i, sad_count;
1561
1562        static const u16 eld_reg_to_type[][2] = {
1563                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1564                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1565                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1566                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1567                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1568                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1569                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1570                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1571                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1572                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1573                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1574                { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1575        };
1576
1577        if (!dig || !dig->afmt || !dig->afmt->pin)
1578                return;
1579
1580        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1581                if (connector->encoder == encoder) {
1582                        amdgpu_connector = to_amdgpu_connector(connector);
1583                        break;
1584                }
1585        }
1586
1587        if (!amdgpu_connector) {
1588                DRM_ERROR("Couldn't find encoder's connector\n");
1589                return;
1590        }
1591
1592        sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1593        if (sad_count <= 0) {
1594                DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1595                return;
1596        }
1597        BUG_ON(!sads);
1598
1599        for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1600                u32 tmp = 0;
1601                u8 stereo_freqs = 0;
1602                int max_channels = -1;
1603                int j;
1604
1605                for (j = 0; j < sad_count; j++) {
1606                        struct cea_sad *sad = &sads[j];
1607
1608                        if (sad->format == eld_reg_to_type[i][1]) {
1609                                if (sad->channels > max_channels) {
1610                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1611                                                            MAX_CHANNELS, sad->channels);
1612                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1613                                                            DESCRIPTOR_BYTE_2, sad->byte2);
1614                                        tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1615                                                            SUPPORTED_FREQUENCIES, sad->freq);
1616                                        max_channels = sad->channels;
1617                                }
1618
1619                                if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1620                                        stereo_freqs |= sad->freq;
1621                                else
1622                                        break;
1623                        }
1624                }
1625
1626                tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1627                                    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1628                WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1629        }
1630
1631        kfree(sads);
1632}
1633
1634static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1635                                  struct amdgpu_audio_pin *pin,
1636                                  bool enable)
1637{
1638        if (!pin)
1639                return;
1640
1641        WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1642                           enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1643}
1644
1645static const u32 pin_offsets[] =
1646{
1647        AUD0_REGISTER_OFFSET,
1648        AUD1_REGISTER_OFFSET,
1649        AUD2_REGISTER_OFFSET,
1650        AUD3_REGISTER_OFFSET,
1651        AUD4_REGISTER_OFFSET,
1652        AUD5_REGISTER_OFFSET,
1653        AUD6_REGISTER_OFFSET,
1654        AUD7_REGISTER_OFFSET,
1655};
1656
1657static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1658{
1659        int i;
1660
1661        if (!amdgpu_audio)
1662                return 0;
1663
1664        adev->mode_info.audio.enabled = true;
1665
1666        switch (adev->asic_type) {
1667        case CHIP_CARRIZO:
1668        case CHIP_STONEY:
1669                adev->mode_info.audio.num_pins = 7;
1670                break;
1671        case CHIP_POLARIS10:
1672                adev->mode_info.audio.num_pins = 8;
1673                break;
1674        case CHIP_POLARIS11:
1675                adev->mode_info.audio.num_pins = 6;
1676                break;
1677        default:
1678                return -EINVAL;
1679        }
1680
1681        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1682                adev->mode_info.audio.pin[i].channels = -1;
1683                adev->mode_info.audio.pin[i].rate = -1;
1684                adev->mode_info.audio.pin[i].bits_per_sample = -1;
1685                adev->mode_info.audio.pin[i].status_bits = 0;
1686                adev->mode_info.audio.pin[i].category_code = 0;
1687                adev->mode_info.audio.pin[i].connected = false;
1688                adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1689                adev->mode_info.audio.pin[i].id = i;
1690                /* disable audio.  it will be set up later */
1691                /* XXX remove once we switch to ip funcs */
1692                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1693        }
1694
1695        return 0;
1696}
1697
1698static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1699{
1700        int i;
1701
1702        if (!amdgpu_audio)
1703                return;
1704
1705        if (!adev->mode_info.audio.enabled)
1706                return;
1707
1708        for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1709                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1710
1711        adev->mode_info.audio.enabled = false;
1712}
1713
1714/*
1715 * update the N and CTS parameters for a given pixel clock rate
1716 */
1717static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1718{
1719        struct drm_device *dev = encoder->dev;
1720        struct amdgpu_device *adev = dev->dev_private;
1721        struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1722        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1723        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1724        u32 tmp;
1725
1726        tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1727        tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1728        WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1729        tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1730        tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1731        WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1732
1733        tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1734        tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1735        WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1736        tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1737        tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1738        WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1739
1740        tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1741        tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1742        WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1743        tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1744        tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1745        WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1746
1747}
1748
1749/*
1750 * build a HDMI Video Info Frame
1751 */
1752static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1753                                               void *buffer, size_t size)
1754{
1755        struct drm_device *dev = encoder->dev;
1756        struct amdgpu_device *adev = dev->dev_private;
1757        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1758        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1759        uint8_t *frame = buffer + 3;
1760        uint8_t *header = buffer;
1761
1762        WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1763                frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1764        WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1765                frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1766        WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1767                frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1768        WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1769                frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1770}
1771
1772static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1773{
1774        struct drm_device *dev = encoder->dev;
1775        struct amdgpu_device *adev = dev->dev_private;
1776        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1777        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1778        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1779        u32 dto_phase = 24 * 1000;
1780        u32 dto_modulo = clock;
1781        u32 tmp;
1782
1783        if (!dig || !dig->afmt)
1784                return;
1785
1786        /* XXX two dtos; generally use dto0 for hdmi */
1787        /* Express [24MHz / target pixel clock] as an exact rational
1788         * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1789         * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1790         */
1791        tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1792        tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1793                            amdgpu_crtc->crtc_id);
1794        WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1795        WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1796        WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1797}
1798
1799/*
1800 * update the info frames with the data from the current display mode
1801 */
1802static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1803                                  struct drm_display_mode *mode)
1804{
1805        struct drm_device *dev = encoder->dev;
1806        struct amdgpu_device *adev = dev->dev_private;
1807        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1808        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1809        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1810        u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1811        struct hdmi_avi_infoframe frame;
1812        ssize_t err;
1813        u32 tmp;
1814        int bpc = 8;
1815
1816        if (!dig || !dig->afmt)
1817                return;
1818
1819        /* Silent, r600_hdmi_enable will raise WARN for us */
1820        if (!dig->afmt->enabled)
1821                return;
1822
1823        /* hdmi deep color mode general control packets setup, if bpc > 8 */
1824        if (encoder->crtc) {
1825                struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1826                bpc = amdgpu_crtc->bpc;
1827        }
1828
1829        /* disable audio prior to setting up hw */
1830        dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1831        dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1832
1833        dce_v11_0_audio_set_dto(encoder, mode->clock);
1834
1835        tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1836        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1837        WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1838
1839        WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1840
1841        tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1842        switch (bpc) {
1843        case 0:
1844        case 6:
1845        case 8:
1846        case 16:
1847        default:
1848                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1849                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1850                DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1851                          connector->name, bpc);
1852                break;
1853        case 10:
1854                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1855                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1856                DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1857                          connector->name);
1858                break;
1859        case 12:
1860                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1861                tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1862                DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1863                          connector->name);
1864                break;
1865        }
1866        WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1867
1868        tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1869        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1870        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1871        tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1872        WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1873
1874        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1875        /* enable audio info frames (frames won't be set until audio is enabled) */
1876        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1877        /* required for audio info values to be updated */
1878        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1879        WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1880
1881        tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1882        /* required for audio info values to be updated */
1883        tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1884        WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1885
1886        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1887        /* anything other than 0 */
1888        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1889        WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1890
1891        WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1892
1893        tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1894        /* set the default audio delay */
1895        tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1896        /* should be suffient for all audio modes and small enough for all hblanks */
1897        tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1898        WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1899
1900        tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1901        /* allow 60958 channel status fields to be updated */
1902        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1903        WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1904
1905        tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1906        if (bpc > 8)
1907                /* clear SW CTS value */
1908                tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1909        else
1910                /* select SW CTS value */
1911                tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1912        /* allow hw to sent ACR packets when required */
1913        tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1914        WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1915
1916        dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1917
1918        tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1919        tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1920        WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1921
1922        tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1923        tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1924        WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1925
1926        tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1927        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1928        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1929        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1930        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1931        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1932        tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1933        WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1934
1935        dce_v11_0_audio_write_speaker_allocation(encoder);
1936
1937        WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1938               (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1939
1940        dce_v11_0_afmt_audio_select_pin(encoder);
1941        dce_v11_0_audio_write_sad_regs(encoder);
1942        dce_v11_0_audio_write_latency_fields(encoder, mode);
1943
1944        err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1945        if (err < 0) {
1946                DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1947                return;
1948        }
1949
1950        err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1951        if (err < 0) {
1952                DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1953                return;
1954        }
1955
1956        dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1957
1958        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1959        /* enable AVI info frames */
1960        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1961        /* required for audio info values to be updated */
1962        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1963        WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1964
1965        tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1966        tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1967        WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1968
1969        tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1970        /* send audio packets */
1971        tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1972        WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1973
1974        WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1975        WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1976        WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1977        WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1978
1979        /* enable audio after to setting up hw */
1980        dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1981}
1982
1983static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1984{
1985        struct drm_device *dev = encoder->dev;
1986        struct amdgpu_device *adev = dev->dev_private;
1987        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1988        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1989
1990        if (!dig || !dig->afmt)
1991                return;
1992
1993        /* Silent, r600_hdmi_enable will raise WARN for us */
1994        if (enable && dig->afmt->enabled)
1995                return;
1996        if (!enable && !dig->afmt->enabled)
1997                return;
1998
1999        if (!enable && dig->afmt->pin) {
2000                dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
2001                dig->afmt->pin = NULL;
2002        }
2003
2004        dig->afmt->enabled = enable;
2005
2006        DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2007                  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2008}
2009
2010static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
2011{
2012        int i;
2013
2014        for (i = 0; i < adev->mode_info.num_dig; i++)
2015                adev->mode_info.afmt[i] = NULL;
2016
2017        /* DCE11 has audio blocks tied to DIG encoders */
2018        for (i = 0; i < adev->mode_info.num_dig; i++) {
2019                adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2020                if (adev->mode_info.afmt[i]) {
2021                        adev->mode_info.afmt[i]->offset = dig_offsets[i];
2022                        adev->mode_info.afmt[i]->id = i;
2023                } else {
2024                        int j;
2025                        for (j = 0; j < i; j++) {
2026                                kfree(adev->mode_info.afmt[j]);
2027                                adev->mode_info.afmt[j] = NULL;
2028                        }
2029                        return -ENOMEM;
2030                }
2031        }
2032        return 0;
2033}
2034
2035static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
2036{
2037        int i;
2038
2039        for (i = 0; i < adev->mode_info.num_dig; i++) {
2040                kfree(adev->mode_info.afmt[i]);
2041                adev->mode_info.afmt[i] = NULL;
2042        }
2043}
2044
2045static const u32 vga_control_regs[6] =
2046{
2047        mmD1VGA_CONTROL,
2048        mmD2VGA_CONTROL,
2049        mmD3VGA_CONTROL,
2050        mmD4VGA_CONTROL,
2051        mmD5VGA_CONTROL,
2052        mmD6VGA_CONTROL,
2053};
2054
2055static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2056{
2057        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2058        struct drm_device *dev = crtc->dev;
2059        struct amdgpu_device *adev = dev->dev_private;
2060        u32 vga_control;
2061
2062        vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2063        if (enable)
2064                WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2065        else
2066                WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2067}
2068
2069static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2070{
2071        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2072        struct drm_device *dev = crtc->dev;
2073        struct amdgpu_device *adev = dev->dev_private;
2074
2075        if (enable)
2076                WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2077        else
2078                WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2079}
2080
2081static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2082                                     struct drm_framebuffer *fb,
2083                                     int x, int y, int atomic)
2084{
2085        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2086        struct drm_device *dev = crtc->dev;
2087        struct amdgpu_device *adev = dev->dev_private;
2088        struct amdgpu_framebuffer *amdgpu_fb;
2089        struct drm_framebuffer *target_fb;
2090        struct drm_gem_object *obj;
2091        struct amdgpu_bo *abo;
2092        uint64_t fb_location, tiling_flags;
2093        uint32_t fb_format, fb_pitch_pixels;
2094        u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2095        u32 pipe_config;
2096        u32 tmp, viewport_w, viewport_h;
2097        int r;
2098        bool bypass_lut = false;
2099        char *format_name;
2100
2101        /* no fb bound */
2102        if (!atomic && !crtc->primary->fb) {
2103                DRM_DEBUG_KMS("No FB bound\n");
2104                return 0;
2105        }
2106
2107        if (atomic) {
2108                amdgpu_fb = to_amdgpu_framebuffer(fb);
2109                target_fb = fb;
2110        } else {
2111                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2112                target_fb = crtc->primary->fb;
2113        }
2114
2115        /* If atomic, assume fb object is pinned & idle & fenced and
2116         * just update base pointers
2117         */
2118        obj = amdgpu_fb->obj;
2119        abo = gem_to_amdgpu_bo(obj);
2120        r = amdgpu_bo_reserve(abo, false);
2121        if (unlikely(r != 0))
2122                return r;
2123
2124        if (atomic) {
2125                fb_location = amdgpu_bo_gpu_offset(abo);
2126        } else {
2127                r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2128                if (unlikely(r != 0)) {
2129                        amdgpu_bo_unreserve(abo);
2130                        return -EINVAL;
2131                }
2132        }
2133
2134        amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2135        amdgpu_bo_unreserve(abo);
2136
2137        pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2138
2139        switch (target_fb->pixel_format) {
2140        case DRM_FORMAT_C8:
2141                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2142                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2143                break;
2144        case DRM_FORMAT_XRGB4444:
2145        case DRM_FORMAT_ARGB4444:
2146                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2147                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2148#ifdef __BIG_ENDIAN
2149                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2150                                        ENDIAN_8IN16);
2151#endif
2152                break;
2153        case DRM_FORMAT_XRGB1555:
2154        case DRM_FORMAT_ARGB1555:
2155                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2156                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2157#ifdef __BIG_ENDIAN
2158                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2159                                        ENDIAN_8IN16);
2160#endif
2161                break;
2162        case DRM_FORMAT_BGRX5551:
2163        case DRM_FORMAT_BGRA5551:
2164                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2165                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2166#ifdef __BIG_ENDIAN
2167                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2168                                        ENDIAN_8IN16);
2169#endif
2170                break;
2171        case DRM_FORMAT_RGB565:
2172                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2173                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2174#ifdef __BIG_ENDIAN
2175                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2176                                        ENDIAN_8IN16);
2177#endif
2178                break;
2179        case DRM_FORMAT_XRGB8888:
2180        case DRM_FORMAT_ARGB8888:
2181                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2182                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2183#ifdef __BIG_ENDIAN
2184                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2185                                        ENDIAN_8IN32);
2186#endif
2187                break;
2188        case DRM_FORMAT_XRGB2101010:
2189        case DRM_FORMAT_ARGB2101010:
2190                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2191                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2192#ifdef __BIG_ENDIAN
2193                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2194                                        ENDIAN_8IN32);
2195#endif
2196                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2197                bypass_lut = true;
2198                break;
2199        case DRM_FORMAT_BGRX1010102:
2200        case DRM_FORMAT_BGRA1010102:
2201                fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2202                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2203#ifdef __BIG_ENDIAN
2204                fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2205                                        ENDIAN_8IN32);
2206#endif
2207                /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2208                bypass_lut = true;
2209                break;
2210        default:
2211                format_name = drm_get_format_name(target_fb->pixel_format);
2212                DRM_ERROR("Unsupported screen format %s\n", format_name);
2213                kfree(format_name);
2214                return -EINVAL;
2215        }
2216
2217        if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2218                unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2219
2220                bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2221                bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2222                mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2223                tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2224                num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2225
2226                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2227                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2228                                          ARRAY_2D_TILED_THIN1);
2229                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2230                                          tile_split);
2231                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2232                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2233                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2234                                          mtaspect);
2235                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2236                                          ADDR_SURF_MICRO_TILING_DISPLAY);
2237        } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2238                fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2239                                          ARRAY_1D_TILED_THIN1);
2240        }
2241
2242        fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2243                                  pipe_config);
2244
2245        dce_v11_0_vga_enable(crtc, false);
2246
2247        /* Make sure surface address is updated at vertical blank rather than
2248         * horizontal blank
2249         */
2250        tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2251        tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2252                            GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2253        WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2254
2255        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2256               upper_32_bits(fb_location));
2257        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2258               upper_32_bits(fb_location));
2259        WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2260               (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2261        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2262               (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2263        WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2264        WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2265
2266        /*
2267         * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2268         * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2269         * retain the full precision throughout the pipeline.
2270         */
2271        tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2272        if (bypass_lut)
2273                tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2274        else
2275                tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2276        WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2277
2278        if (bypass_lut)
2279                DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2280
2281        WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2282        WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2283        WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2284        WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2285        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2286        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2287
2288        fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2289        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2290
2291        dce_v11_0_grph_enable(crtc, true);
2292
2293        WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2294               target_fb->height);
2295
2296        x &= ~3;
2297        y &= ~1;
2298        WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2299               (x << 16) | y);
2300        viewport_w = crtc->mode.hdisplay;
2301        viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2302        WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2303               (viewport_w << 16) | viewport_h);
2304
2305        /* set pageflip to happen anywhere in vblank interval */
2306        WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2307
2308        if (!atomic && fb && fb != crtc->primary->fb) {
2309                amdgpu_fb = to_amdgpu_framebuffer(fb);
2310                abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2311                r = amdgpu_bo_reserve(abo, false);
2312                if (unlikely(r != 0))
2313                        return r;
2314                amdgpu_bo_unpin(abo);
2315                amdgpu_bo_unreserve(abo);
2316        }
2317
2318        /* Bytes per pixel may have changed */
2319        dce_v11_0_bandwidth_update(adev);
2320
2321        return 0;
2322}
2323
2324static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2325                                     struct drm_display_mode *mode)
2326{
2327        struct drm_device *dev = crtc->dev;
2328        struct amdgpu_device *adev = dev->dev_private;
2329        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2330        u32 tmp;
2331
2332        tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2333        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2334                tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2335        else
2336                tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2337        WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2338}
2339
2340static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2341{
2342        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2343        struct drm_device *dev = crtc->dev;
2344        struct amdgpu_device *adev = dev->dev_private;
2345        int i;
2346        u32 tmp;
2347
2348        DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2349
2350        tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2351        tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2352        WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353
2354        tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2355        tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2356        WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2357
2358        tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2359        tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2360        WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2361
2362        WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2363
2364        WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2365        WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2366        WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2367
2368        WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2369        WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2370        WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2371
2372        WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2373        WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2374
2375        WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2376        for (i = 0; i < 256; i++) {
2377                WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2378                       (amdgpu_crtc->lut_r[i] << 20) |
2379                       (amdgpu_crtc->lut_g[i] << 10) |
2380                       (amdgpu_crtc->lut_b[i] << 0));
2381        }
2382
2383        tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2384        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2385        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2386        tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2387        WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2388
2389        tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2390        tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2391        WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2392
2393        tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2394        tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2395        WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2396
2397        tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2398        tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2399        WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2400
2401        /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2402        WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2403        /* XXX this only needs to be programmed once per crtc at startup,
2404         * not sure where the best place for it is
2405         */
2406        tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2407        tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2408        WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2409}
2410
2411static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2412{
2413        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2414        struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2415
2416        switch (amdgpu_encoder->encoder_id) {
2417        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2418                if (dig->linkb)
2419                        return 1;
2420                else
2421                        return 0;
2422                break;
2423        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2424                if (dig->linkb)
2425                        return 3;
2426                else
2427                        return 2;
2428                break;
2429        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2430                if (dig->linkb)
2431                        return 5;
2432                else
2433                        return 4;
2434                break;
2435        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2436                return 6;
2437                break;
2438        default:
2439                DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2440                return 0;
2441        }
2442}
2443
2444/**
2445 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2446 *
2447 * @crtc: drm crtc
2448 *
2449 * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2450 * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2451 * monitors a dedicated PPLL must be used.  If a particular board has
2452 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2453 * as there is no need to program the PLL itself.  If we are not able to
2454 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2455 * avoid messing up an existing monitor.
2456 *
2457 * Asic specific PLL information
2458 *
2459 * DCE 10.x
2460 * Tonga
2461 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2462 * CI
2463 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2464 *
2465 */
2466static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2467{
2468        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2469        struct drm_device *dev = crtc->dev;
2470        struct amdgpu_device *adev = dev->dev_private;
2471        u32 pll_in_use;
2472        int pll;
2473
2474        if ((adev->asic_type == CHIP_POLARIS10) ||
2475            (adev->asic_type == CHIP_POLARIS11)) {
2476                struct amdgpu_encoder *amdgpu_encoder =
2477                        to_amdgpu_encoder(amdgpu_crtc->encoder);
2478                struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2479
2480                if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2481                        return ATOM_DP_DTO;
2482
2483                switch (amdgpu_encoder->encoder_id) {
2484                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2485                        if (dig->linkb)
2486                                return ATOM_COMBOPHY_PLL1;
2487                        else
2488                                return ATOM_COMBOPHY_PLL0;
2489                        break;
2490                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2491                        if (dig->linkb)
2492                                return ATOM_COMBOPHY_PLL3;
2493                        else
2494                                return ATOM_COMBOPHY_PLL2;
2495                        break;
2496                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2497                        if (dig->linkb)
2498                                return ATOM_COMBOPHY_PLL5;
2499                        else
2500                                return ATOM_COMBOPHY_PLL4;
2501                        break;
2502                default:
2503                        DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2504                        return ATOM_PPLL_INVALID;
2505                }
2506        }
2507
2508        if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2509                if (adev->clock.dp_extclk)
2510                        /* skip PPLL programming if using ext clock */
2511                        return ATOM_PPLL_INVALID;
2512                else {
2513                        /* use the same PPLL for all DP monitors */
2514                        pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2515                        if (pll != ATOM_PPLL_INVALID)
2516                                return pll;
2517                }
2518        } else {
2519                /* use the same PPLL for all monitors with the same clock */
2520                pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2521                if (pll != ATOM_PPLL_INVALID)
2522                        return pll;
2523        }
2524
2525        /* XXX need to determine what plls are available on each DCE11 part */
2526        pll_in_use = amdgpu_pll_get_use_mask(crtc);
2527        if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2528                if (!(pll_in_use & (1 << ATOM_PPLL1)))
2529                        return ATOM_PPLL1;
2530                if (!(pll_in_use & (1 << ATOM_PPLL0)))
2531                        return ATOM_PPLL0;
2532                DRM_ERROR("unable to allocate a PPLL\n");
2533                return ATOM_PPLL_INVALID;
2534        } else {
2535                if (!(pll_in_use & (1 << ATOM_PPLL2)))
2536                        return ATOM_PPLL2;
2537                if (!(pll_in_use & (1 << ATOM_PPLL1)))
2538                        return ATOM_PPLL1;
2539                if (!(pll_in_use & (1 << ATOM_PPLL0)))
2540                        return ATOM_PPLL0;
2541                DRM_ERROR("unable to allocate a PPLL\n");
2542                return ATOM_PPLL_INVALID;
2543        }
2544        return ATOM_PPLL_INVALID;
2545}
2546
2547static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2548{
2549        struct amdgpu_device *adev = crtc->dev->dev_private;
2550        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2551        uint32_t cur_lock;
2552
2553        cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2554        if (lock)
2555                cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2556        else
2557                cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2558        WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2559}
2560
2561static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2562{
2563        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2564        struct amdgpu_device *adev = crtc->dev->dev_private;
2565        u32 tmp;
2566
2567        tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2568        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2569        WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2570}
2571
2572static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2573{
2574        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2575        struct amdgpu_device *adev = crtc->dev->dev_private;
2576        u32 tmp;
2577
2578        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2579               upper_32_bits(amdgpu_crtc->cursor_addr));
2580        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2581               lower_32_bits(amdgpu_crtc->cursor_addr));
2582
2583        tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2584        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2585        tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2586        WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2587}
2588
2589static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2590                                        int x, int y)
2591{
2592        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2593        struct amdgpu_device *adev = crtc->dev->dev_private;
2594        int xorigin = 0, yorigin = 0;
2595
2596        amdgpu_crtc->cursor_x = x;
2597        amdgpu_crtc->cursor_y = y;
2598
2599        /* avivo cursor are offset into the total surface */
2600        x += crtc->x;
2601        y += crtc->y;
2602        DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2603
2604        if (x < 0) {
2605                xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2606                x = 0;
2607        }
2608        if (y < 0) {
2609                yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2610                y = 0;
2611        }
2612
2613        WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2614        WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2615        WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2616               ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2617
2618        return 0;
2619}
2620
2621static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2622                                      int x, int y)
2623{
2624        int ret;
2625
2626        dce_v11_0_lock_cursor(crtc, true);
2627        ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2628        dce_v11_0_lock_cursor(crtc, false);
2629
2630        return ret;
2631}
2632
2633static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2634                                      struct drm_file *file_priv,
2635                                      uint32_t handle,
2636                                      uint32_t width,
2637                                      uint32_t height,
2638                                      int32_t hot_x,
2639                                      int32_t hot_y)
2640{
2641        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2642        struct drm_gem_object *obj;
2643        struct amdgpu_bo *aobj;
2644        int ret;
2645
2646        if (!handle) {
2647                /* turn off cursor */
2648                dce_v11_0_hide_cursor(crtc);
2649                obj = NULL;
2650                goto unpin;
2651        }
2652
2653        if ((width > amdgpu_crtc->max_cursor_width) ||
2654            (height > amdgpu_crtc->max_cursor_height)) {
2655                DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2656                return -EINVAL;
2657        }
2658
2659        obj = drm_gem_object_lookup(file_priv, handle);
2660        if (!obj) {
2661                DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2662                return -ENOENT;
2663        }
2664
2665        aobj = gem_to_amdgpu_bo(obj);
2666        ret = amdgpu_bo_reserve(aobj, false);
2667        if (ret != 0) {
2668                drm_gem_object_unreference_unlocked(obj);
2669                return ret;
2670        }
2671
2672        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2673        amdgpu_bo_unreserve(aobj);
2674        if (ret) {
2675                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2676                drm_gem_object_unreference_unlocked(obj);
2677                return ret;
2678        }
2679
2680        dce_v11_0_lock_cursor(crtc, true);
2681
2682        if (width != amdgpu_crtc->cursor_width ||
2683            height != amdgpu_crtc->cursor_height ||
2684            hot_x != amdgpu_crtc->cursor_hot_x ||
2685            hot_y != amdgpu_crtc->cursor_hot_y) {
2686                int x, y;
2687
2688                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2689                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2690
2691                dce_v11_0_cursor_move_locked(crtc, x, y);
2692
2693                amdgpu_crtc->cursor_width = width;
2694                amdgpu_crtc->cursor_height = height;
2695                amdgpu_crtc->cursor_hot_x = hot_x;
2696                amdgpu_crtc->cursor_hot_y = hot_y;
2697        }
2698
2699        dce_v11_0_show_cursor(crtc);
2700        dce_v11_0_lock_cursor(crtc, false);
2701
2702unpin:
2703        if (amdgpu_crtc->cursor_bo) {
2704                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2705                ret = amdgpu_bo_reserve(aobj, false);
2706                if (likely(ret == 0)) {
2707                        amdgpu_bo_unpin(aobj);
2708                        amdgpu_bo_unreserve(aobj);
2709                }
2710                drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2711        }
2712
2713        amdgpu_crtc->cursor_bo = obj;
2714        return 0;
2715}
2716
2717static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2718{
2719        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2720
2721        if (amdgpu_crtc->cursor_bo) {
2722                dce_v11_0_lock_cursor(crtc, true);
2723
2724                dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2725                                             amdgpu_crtc->cursor_y);
2726
2727                dce_v11_0_show_cursor(crtc);
2728
2729                dce_v11_0_lock_cursor(crtc, false);
2730        }
2731}
2732
2733static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2734                                    u16 *blue, uint32_t size)
2735{
2736        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2737        int i;
2738
2739        /* userspace palettes are always correct as is */
2740        for (i = 0; i < size; i++) {
2741                amdgpu_crtc->lut_r[i] = red[i] >> 6;
2742                amdgpu_crtc->lut_g[i] = green[i] >> 6;
2743                amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2744        }
2745        dce_v11_0_crtc_load_lut(crtc);
2746
2747        return 0;
2748}
2749
2750static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2751{
2752        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2753
2754        drm_crtc_cleanup(crtc);
2755        kfree(amdgpu_crtc);
2756}
2757
2758static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2759        .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2760        .cursor_move = dce_v11_0_crtc_cursor_move,
2761        .gamma_set = dce_v11_0_crtc_gamma_set,
2762        .set_config = amdgpu_crtc_set_config,
2763        .destroy = dce_v11_0_crtc_destroy,
2764        .page_flip_target = amdgpu_crtc_page_flip_target,
2765};
2766
2767static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2768{
2769        struct drm_device *dev = crtc->dev;
2770        struct amdgpu_device *adev = dev->dev_private;
2771        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2772        unsigned type;
2773
2774        switch (mode) {
2775        case DRM_MODE_DPMS_ON:
2776                amdgpu_crtc->enabled = true;
2777                amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2778                dce_v11_0_vga_enable(crtc, true);
2779                amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2780                dce_v11_0_vga_enable(crtc, false);
2781                /* Make sure VBLANK and PFLIP interrupts are still enabled */
2782                type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2783                amdgpu_irq_update(adev, &adev->crtc_irq, type);
2784                amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2785                drm_crtc_vblank_on(crtc);
2786                dce_v11_0_crtc_load_lut(crtc);
2787                break;
2788        case DRM_MODE_DPMS_STANDBY:
2789        case DRM_MODE_DPMS_SUSPEND:
2790        case DRM_MODE_DPMS_OFF:
2791                drm_crtc_vblank_off(crtc);
2792                if (amdgpu_crtc->enabled) {
2793                        dce_v11_0_vga_enable(crtc, true);
2794                        amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2795                        dce_v11_0_vga_enable(crtc, false);
2796                }
2797                amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2798                amdgpu_crtc->enabled = false;
2799                break;
2800        }
2801        /* adjust pm to dpms */
2802        amdgpu_pm_compute_clocks(adev);
2803}
2804
2805static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2806{
2807        /* disable crtc pair power gating before programming */
2808        amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2809        amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2810        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2811}
2812
2813static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2814{
2815        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2816        amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2817}
2818
2819static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2820{
2821        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2822        struct drm_device *dev = crtc->dev;
2823        struct amdgpu_device *adev = dev->dev_private;
2824        struct amdgpu_atom_ss ss;
2825        int i;
2826
2827        dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2828        if (crtc->primary->fb) {
2829                int r;
2830                struct amdgpu_framebuffer *amdgpu_fb;
2831                struct amdgpu_bo *abo;
2832
2833                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2834                abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2835                r = amdgpu_bo_reserve(abo, false);
2836                if (unlikely(r))
2837                        DRM_ERROR("failed to reserve abo before unpin\n");
2838                else {
2839                        amdgpu_bo_unpin(abo);
2840                        amdgpu_bo_unreserve(abo);
2841                }
2842        }
2843        /* disable the GRPH */
2844        dce_v11_0_grph_enable(crtc, false);
2845
2846        amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2847
2848        for (i = 0; i < adev->mode_info.num_crtc; i++) {
2849                if (adev->mode_info.crtcs[i] &&
2850                    adev->mode_info.crtcs[i]->enabled &&
2851                    i != amdgpu_crtc->crtc_id &&
2852                    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2853                        /* one other crtc is using this pll don't turn
2854                         * off the pll
2855                         */
2856                        goto done;
2857                }
2858        }
2859
2860        switch (amdgpu_crtc->pll_id) {
2861        case ATOM_PPLL0:
2862        case ATOM_PPLL1:
2863        case ATOM_PPLL2:
2864                /* disable the ppll */
2865                amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2866                                                 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2867                break;
2868        case ATOM_COMBOPHY_PLL0:
2869        case ATOM_COMBOPHY_PLL1:
2870        case ATOM_COMBOPHY_PLL2:
2871        case ATOM_COMBOPHY_PLL3:
2872        case ATOM_COMBOPHY_PLL4:
2873        case ATOM_COMBOPHY_PLL5:
2874                /* disable the ppll */
2875                amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2876                                                 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2877                break;
2878        default:
2879                break;
2880        }
2881done:
2882        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2883        amdgpu_crtc->adjusted_clock = 0;
2884        amdgpu_crtc->encoder = NULL;
2885        amdgpu_crtc->connector = NULL;
2886}
2887
2888static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2889                                  struct drm_display_mode *mode,
2890                                  struct drm_display_mode *adjusted_mode,
2891                                  int x, int y, struct drm_framebuffer *old_fb)
2892{
2893        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2894        struct drm_device *dev = crtc->dev;
2895        struct amdgpu_device *adev = dev->dev_private;
2896
2897        if (!amdgpu_crtc->adjusted_clock)
2898                return -EINVAL;
2899
2900        if ((adev->asic_type == CHIP_POLARIS10) ||
2901            (adev->asic_type == CHIP_POLARIS11)) {
2902                struct amdgpu_encoder *amdgpu_encoder =
2903                        to_amdgpu_encoder(amdgpu_crtc->encoder);
2904                int encoder_mode =
2905                        amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2906
2907                /* SetPixelClock calculates the plls and ss values now */
2908                amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2909                                                 amdgpu_crtc->pll_id,
2910                                                 encoder_mode, amdgpu_encoder->encoder_id,
2911                                                 adjusted_mode->clock, 0, 0, 0, 0,
2912                                                 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2913        } else {
2914                amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2915        }
2916        amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2917        dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2918        amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2919        amdgpu_atombios_crtc_scaler_setup(crtc);
2920        dce_v11_0_cursor_reset(crtc);
2921        /* update the hw version fpr dpm */
2922        amdgpu_crtc->hw_mode = *adjusted_mode;
2923
2924        return 0;
2925}
2926
2927static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2928                                     const struct drm_display_mode *mode,
2929                                     struct drm_display_mode *adjusted_mode)
2930{
2931        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2932        struct drm_device *dev = crtc->dev;
2933        struct drm_encoder *encoder;
2934
2935        /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2936        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2937                if (encoder->crtc == crtc) {
2938                        amdgpu_crtc->encoder = encoder;
2939                        amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2940                        break;
2941                }
2942        }
2943        if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2944                amdgpu_crtc->encoder = NULL;
2945                amdgpu_crtc->connector = NULL;
2946                return false;
2947        }
2948        if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2949                return false;
2950        if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2951                return false;
2952        /* pick pll */
2953        amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2954        /* if we can't get a PPLL for a non-DP encoder, fail */
2955        if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2956            !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2957                return false;
2958
2959        return true;
2960}
2961
2962static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2963                                  struct drm_framebuffer *old_fb)
2964{
2965        return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2966}
2967
2968static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2969                                         struct drm_framebuffer *fb,
2970                                         int x, int y, enum mode_set_atomic state)
2971{
2972       return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2973}
2974
2975static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2976        .dpms = dce_v11_0_crtc_dpms,
2977        .mode_fixup = dce_v11_0_crtc_mode_fixup,
2978        .mode_set = dce_v11_0_crtc_mode_set,
2979        .mode_set_base = dce_v11_0_crtc_set_base,
2980        .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2981        .prepare = dce_v11_0_crtc_prepare,
2982        .commit = dce_v11_0_crtc_commit,
2983        .load_lut = dce_v11_0_crtc_load_lut,
2984        .disable = dce_v11_0_crtc_disable,
2985};
2986
2987static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2988{
2989        struct amdgpu_crtc *amdgpu_crtc;
2990        int i;
2991
2992        amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2993                              (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2994        if (amdgpu_crtc == NULL)
2995                return -ENOMEM;
2996
2997        drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2998
2999        drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
3000        amdgpu_crtc->crtc_id = index;
3001        adev->mode_info.crtcs[index] = amdgpu_crtc;
3002
3003        amdgpu_crtc->max_cursor_width = 128;
3004        amdgpu_crtc->max_cursor_height = 128;
3005        adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
3006        adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
3007
3008        for (i = 0; i < 256; i++) {
3009                amdgpu_crtc->lut_r[i] = i << 2;
3010                amdgpu_crtc->lut_g[i] = i << 2;
3011                amdgpu_crtc->lut_b[i] = i << 2;
3012        }
3013
3014        switch (amdgpu_crtc->crtc_id) {
3015        case 0:
3016        default:
3017                amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
3018                break;
3019        case 1:
3020                amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
3021                break;
3022        case 2:
3023                amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
3024                break;
3025        case 3:
3026                amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
3027                break;
3028        case 4:
3029                amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
3030                break;
3031        case 5:
3032                amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
3033                break;
3034        }
3035
3036        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
3037        amdgpu_crtc->adjusted_clock = 0;
3038        amdgpu_crtc->encoder = NULL;
3039        amdgpu_crtc->connector = NULL;
3040        drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
3041
3042        return 0;
3043}
3044
3045static int dce_v11_0_early_init(void *handle)
3046{
3047        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3048
3049        adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
3050        adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
3051
3052        dce_v11_0_set_display_funcs(adev);
3053        dce_v11_0_set_irq_funcs(adev);
3054
3055        adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
3056
3057        switch (adev->asic_type) {
3058        case CHIP_CARRIZO:
3059                adev->mode_info.num_hpd = 6;
3060                adev->mode_info.num_dig = 9;
3061                break;
3062        case CHIP_STONEY:
3063                adev->mode_info.num_hpd = 6;
3064                adev->mode_info.num_dig = 9;
3065                break;
3066        case CHIP_POLARIS10:
3067                adev->mode_info.num_hpd = 6;
3068                adev->mode_info.num_dig = 6;
3069                break;
3070        case CHIP_POLARIS11:
3071                adev->mode_info.num_hpd = 5;
3072                adev->mode_info.num_dig = 5;
3073                break;
3074        default:
3075                /* FIXME: not supported yet */
3076                return -EINVAL;
3077        }
3078
3079        return 0;
3080}
3081
3082static int dce_v11_0_sw_init(void *handle)
3083{
3084        int r, i;
3085        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3086
3087        for (i = 0; i < adev->mode_info.num_crtc; i++) {
3088                r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3089                if (r)
3090                        return r;
3091        }
3092
3093        for (i = 8; i < 20; i += 2) {
3094                r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3095                if (r)
3096                        return r;
3097        }
3098
3099        /* HPD hotplug */
3100        r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3101        if (r)
3102                return r;
3103
3104        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3105
3106        adev->ddev->mode_config.async_page_flip = true;
3107
3108        adev->ddev->mode_config.max_width = 16384;
3109        adev->ddev->mode_config.max_height = 16384;
3110
3111        adev->ddev->mode_config.preferred_depth = 24;
3112        adev->ddev->mode_config.prefer_shadow = 1;
3113
3114        adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3115
3116        r = amdgpu_modeset_create_props(adev);
3117        if (r)
3118                return r;
3119
3120        adev->ddev->mode_config.max_width = 16384;
3121        adev->ddev->mode_config.max_height = 16384;
3122
3123
3124        /* allocate crtcs */
3125        for (i = 0; i < adev->mode_info.num_crtc; i++) {
3126                r = dce_v11_0_crtc_init(adev, i);
3127                if (r)
3128                        return r;
3129        }
3130
3131        if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3132                amdgpu_print_display_setup(adev->ddev);
3133        else
3134                return -EINVAL;
3135
3136        /* setup afmt */
3137        r = dce_v11_0_afmt_init(adev);
3138        if (r)
3139                return r;
3140
3141        r = dce_v11_0_audio_init(adev);
3142        if (r)
3143                return r;
3144
3145        drm_kms_helper_poll_init(adev->ddev);
3146
3147        adev->mode_info.mode_config_initialized = true;
3148        return 0;
3149}
3150
3151static int dce_v11_0_sw_fini(void *handle)
3152{
3153        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3154
3155        kfree(adev->mode_info.bios_hardcoded_edid);
3156
3157        drm_kms_helper_poll_fini(adev->ddev);
3158
3159        dce_v11_0_audio_fini(adev);
3160
3161        dce_v11_0_afmt_fini(adev);
3162
3163        drm_mode_config_cleanup(adev->ddev);
3164        adev->mode_info.mode_config_initialized = false;
3165
3166        return 0;
3167}
3168
3169static int dce_v11_0_hw_init(void *handle)
3170{
3171        int i;
3172        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3173
3174        dce_v11_0_init_golden_registers(adev);
3175
3176        /* init dig PHYs, disp eng pll */
3177        amdgpu_atombios_crtc_powergate_init(adev);
3178        amdgpu_atombios_encoder_init_dig(adev);
3179        if ((adev->asic_type == CHIP_POLARIS10) ||
3180            (adev->asic_type == CHIP_POLARIS11)) {
3181                amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3182                                                   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3183                amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3184                                                   DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3185        } else {
3186                amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3187        }
3188
3189        /* initialize hpd */
3190        dce_v11_0_hpd_init(adev);
3191
3192        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3193                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3194        }
3195
3196        dce_v11_0_pageflip_interrupt_init(adev);
3197
3198        return 0;
3199}
3200
3201static int dce_v11_0_hw_fini(void *handle)
3202{
3203        int i;
3204        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3205
3206        dce_v11_0_hpd_fini(adev);
3207
3208        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3209                dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3210        }
3211
3212        dce_v11_0_pageflip_interrupt_fini(adev);
3213
3214        return 0;
3215}
3216
3217static int dce_v11_0_suspend(void *handle)
3218{
3219        return dce_v11_0_hw_fini(handle);
3220}
3221
3222static int dce_v11_0_resume(void *handle)
3223{
3224        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3225        int ret;
3226
3227        ret = dce_v11_0_hw_init(handle);
3228
3229        /* turn on the BL */
3230        if (adev->mode_info.bl_encoder) {
3231                u8 bl_level = amdgpu_display_backlight_get_level(adev,
3232                                                                  adev->mode_info.bl_encoder);
3233                amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3234                                                    bl_level);
3235        }
3236
3237        return ret;
3238}
3239
3240static bool dce_v11_0_is_idle(void *handle)
3241{
3242        return true;
3243}
3244
3245static int dce_v11_0_wait_for_idle(void *handle)
3246{
3247        return 0;
3248}
3249
3250static int dce_v11_0_soft_reset(void *handle)
3251{
3252        u32 srbm_soft_reset = 0, tmp;
3253        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3254
3255        if (dce_v11_0_is_display_hung(adev))
3256                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3257
3258        if (srbm_soft_reset) {
3259                tmp = RREG32(mmSRBM_SOFT_RESET);
3260                tmp |= srbm_soft_reset;
3261                dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3262                WREG32(mmSRBM_SOFT_RESET, tmp);
3263                tmp = RREG32(mmSRBM_SOFT_RESET);
3264
3265                udelay(50);
3266
3267                tmp &= ~srbm_soft_reset;
3268                WREG32(mmSRBM_SOFT_RESET, tmp);
3269                tmp = RREG32(mmSRBM_SOFT_RESET);
3270
3271                /* Wait a little for things to settle down */
3272                udelay(50);
3273        }
3274        return 0;
3275}
3276
3277static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3278                                                     int crtc,
3279                                                     enum amdgpu_interrupt_state state)
3280{
3281        u32 lb_interrupt_mask;
3282
3283        if (crtc >= adev->mode_info.num_crtc) {
3284                DRM_DEBUG("invalid crtc %d\n", crtc);
3285                return;
3286        }
3287
3288        switch (state) {
3289        case AMDGPU_IRQ_STATE_DISABLE:
3290                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3291                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3292                                                  VBLANK_INTERRUPT_MASK, 0);
3293                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3294                break;
3295        case AMDGPU_IRQ_STATE_ENABLE:
3296                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3297                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3298                                                  VBLANK_INTERRUPT_MASK, 1);
3299                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3300                break;
3301        default:
3302                break;
3303        }
3304}
3305
3306static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3307                                                    int crtc,
3308                                                    enum amdgpu_interrupt_state state)
3309{
3310        u32 lb_interrupt_mask;
3311
3312        if (crtc >= adev->mode_info.num_crtc) {
3313                DRM_DEBUG("invalid crtc %d\n", crtc);
3314                return;
3315        }
3316
3317        switch (state) {
3318        case AMDGPU_IRQ_STATE_DISABLE:
3319                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3320                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3321                                                  VLINE_INTERRUPT_MASK, 0);
3322                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3323                break;
3324        case AMDGPU_IRQ_STATE_ENABLE:
3325                lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3326                lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3327                                                  VLINE_INTERRUPT_MASK, 1);
3328                WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3329                break;
3330        default:
3331                break;
3332        }
3333}
3334
3335static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3336                                        struct amdgpu_irq_src *source,
3337                                        unsigned hpd,
3338                                        enum amdgpu_interrupt_state state)
3339{
3340        u32 tmp;
3341
3342        if (hpd >= adev->mode_info.num_hpd) {
3343                DRM_DEBUG("invalid hdp %d\n", hpd);
3344                return 0;
3345        }
3346
3347        switch (state) {
3348        case AMDGPU_IRQ_STATE_DISABLE:
3349                tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3350                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3351                WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3352                break;
3353        case AMDGPU_IRQ_STATE_ENABLE:
3354                tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3355                tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3356                WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3357                break;
3358        default:
3359                break;
3360        }
3361
3362        return 0;
3363}
3364
3365static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3366                                        struct amdgpu_irq_src *source,
3367                                        unsigned type,
3368                                        enum amdgpu_interrupt_state state)
3369{
3370        switch (type) {
3371        case AMDGPU_CRTC_IRQ_VBLANK1:
3372                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3373                break;
3374        case AMDGPU_CRTC_IRQ_VBLANK2:
3375                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3376                break;
3377        case AMDGPU_CRTC_IRQ_VBLANK3:
3378                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3379                break;
3380        case AMDGPU_CRTC_IRQ_VBLANK4:
3381                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3382                break;
3383        case AMDGPU_CRTC_IRQ_VBLANK5:
3384                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3385                break;
3386        case AMDGPU_CRTC_IRQ_VBLANK6:
3387                dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3388                break;
3389        case AMDGPU_CRTC_IRQ_VLINE1:
3390                dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3391                break;
3392        case AMDGPU_CRTC_IRQ_VLINE2:
3393                dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3394                break;
3395        case AMDGPU_CRTC_IRQ_VLINE3:
3396                dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3397                break;
3398        case AMDGPU_CRTC_IRQ_VLINE4:
3399                dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3400                break;
3401        case AMDGPU_CRTC_IRQ_VLINE5:
3402                dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3403                break;
3404         case AMDGPU_CRTC_IRQ_VLINE6:
3405                dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3406                break;
3407        default:
3408                break;
3409        }
3410        return 0;
3411}
3412
3413static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3414                                            struct amdgpu_irq_src *src,
3415                                            unsigned type,
3416                                            enum amdgpu_interrupt_state state)
3417{
3418        u32 reg;
3419
3420        if (type >= adev->mode_info.num_crtc) {
3421                DRM_ERROR("invalid pageflip crtc %d\n", type);
3422                return -EINVAL;
3423        }
3424
3425        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3426        if (state == AMDGPU_IRQ_STATE_DISABLE)
3427                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3428                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3429        else
3430                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3431                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3432
3433        return 0;
3434}
3435
3436static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3437                                  struct amdgpu_irq_src *source,
3438                                  struct amdgpu_iv_entry *entry)
3439{
3440        unsigned long flags;
3441        unsigned crtc_id;
3442        struct amdgpu_crtc *amdgpu_crtc;
3443        struct amdgpu_flip_work *works;
3444
3445        crtc_id = (entry->src_id - 8) >> 1;
3446        amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3447
3448        if (crtc_id >= adev->mode_info.num_crtc) {
3449                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3450                return -EINVAL;
3451        }
3452
3453        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3454            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3455                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3456                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3457
3458        /* IRQ could occur when in initial stage */
3459        if(amdgpu_crtc == NULL)
3460                return 0;
3461
3462        spin_lock_irqsave(&adev->ddev->event_lock, flags);
3463        works = amdgpu_crtc->pflip_works;
3464        if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3465                DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3466                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3467                                                 amdgpu_crtc->pflip_status,
3468                                                 AMDGPU_FLIP_SUBMITTED);
3469                spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3470                return 0;
3471        }
3472
3473        /* page flip completed. clean up */
3474        amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3475        amdgpu_crtc->pflip_works = NULL;
3476
3477        /* wakeup usersapce */
3478        if(works->event)
3479                drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3480
3481        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3482
3483        drm_crtc_vblank_put(&amdgpu_crtc->base);
3484        schedule_work(&works->unpin_work);
3485
3486        return 0;
3487}
3488
3489static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3490                                  int hpd)
3491{
3492        u32 tmp;
3493
3494        if (hpd >= adev->mode_info.num_hpd) {
3495                DRM_DEBUG("invalid hdp %d\n", hpd);
3496                return;
3497        }
3498
3499        tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3500        tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3501        WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3502}
3503
3504static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3505                                          int crtc)
3506{
3507        u32 tmp;
3508
3509        if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3510                DRM_DEBUG("invalid crtc %d\n", crtc);
3511                return;
3512        }
3513
3514        tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3515        tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3516        WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3517}
3518
3519static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3520                                         int crtc)
3521{
3522        u32 tmp;
3523
3524        if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3525                DRM_DEBUG("invalid crtc %d\n", crtc);
3526                return;
3527        }
3528
3529        tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3530        tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3531        WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3532}
3533
3534static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3535                                struct amdgpu_irq_src *source,
3536                                struct amdgpu_iv_entry *entry)
3537{
3538        unsigned crtc = entry->src_id - 1;
3539        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3540        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3541
3542        switch (entry->src_data) {
3543        case 0: /* vblank */
3544                if (disp_int & interrupt_status_offsets[crtc].vblank)
3545                        dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3546                else
3547                        DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3548
3549                if (amdgpu_irq_enabled(adev, source, irq_type)) {
3550                        drm_handle_vblank(adev->ddev, crtc);
3551                }
3552                DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3553
3554                break;
3555        case 1: /* vline */
3556                if (disp_int & interrupt_status_offsets[crtc].vline)
3557                        dce_v11_0_crtc_vline_int_ack(adev, crtc);
3558                else
3559                        DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3560
3561                DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3562
3563                break;
3564        default:
3565                DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3566                break;
3567        }
3568
3569        return 0;
3570}
3571
3572static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3573                             struct amdgpu_irq_src *source,
3574                             struct amdgpu_iv_entry *entry)
3575{
3576        uint32_t disp_int, mask;
3577        unsigned hpd;
3578
3579        if (entry->src_data >= adev->mode_info.num_hpd) {
3580                DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3581                return 0;
3582        }
3583
3584        hpd = entry->src_data;
3585        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3586        mask = interrupt_status_offsets[hpd].hpd;
3587
3588        if (disp_int & mask) {
3589                dce_v11_0_hpd_int_ack(adev, hpd);
3590                schedule_work(&adev->hotplug_work);
3591                DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3592        }
3593
3594        return 0;
3595}
3596
3597static int dce_v11_0_set_clockgating_state(void *handle,
3598                                          enum amd_clockgating_state state)
3599{
3600        return 0;
3601}
3602
3603static int dce_v11_0_set_powergating_state(void *handle,
3604                                          enum amd_powergating_state state)
3605{
3606        return 0;
3607}
3608
3609const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3610        .name = "dce_v11_0",
3611        .early_init = dce_v11_0_early_init,
3612        .late_init = NULL,
3613        .sw_init = dce_v11_0_sw_init,
3614        .sw_fini = dce_v11_0_sw_fini,
3615        .hw_init = dce_v11_0_hw_init,
3616        .hw_fini = dce_v11_0_hw_fini,
3617        .suspend = dce_v11_0_suspend,
3618        .resume = dce_v11_0_resume,
3619        .is_idle = dce_v11_0_is_idle,
3620        .wait_for_idle = dce_v11_0_wait_for_idle,
3621        .soft_reset = dce_v11_0_soft_reset,
3622        .set_clockgating_state = dce_v11_0_set_clockgating_state,
3623        .set_powergating_state = dce_v11_0_set_powergating_state,
3624};
3625
3626static void
3627dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3628                          struct drm_display_mode *mode,
3629                          struct drm_display_mode *adjusted_mode)
3630{
3631        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3632
3633        amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3634
3635        /* need to call this here rather than in prepare() since we need some crtc info */
3636        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3637
3638        /* set scaler clears this on some chips */
3639        dce_v11_0_set_interleave(encoder->crtc, mode);
3640
3641        if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3642                dce_v11_0_afmt_enable(encoder, true);
3643                dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3644        }
3645}
3646
3647static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3648{
3649        struct amdgpu_device *adev = encoder->dev->dev_private;
3650        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3651        struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3652
3653        if ((amdgpu_encoder->active_device &
3654             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3655            (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3656             ENCODER_OBJECT_ID_NONE)) {
3657                struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3658                if (dig) {
3659                        dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3660                        if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3661                                dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3662                }
3663        }
3664
3665        amdgpu_atombios_scratch_regs_lock(adev, true);
3666
3667        if (connector) {
3668                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3669
3670                /* select the clock/data port if it uses a router */
3671                if (amdgpu_connector->router.cd_valid)
3672                        amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3673
3674                /* turn eDP panel on for mode set */
3675                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3676                        amdgpu_atombios_encoder_set_edp_panel_power(connector,
3677                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
3678        }
3679
3680        /* this is needed for the pll/ss setup to work correctly in some cases */
3681        amdgpu_atombios_encoder_set_crtc_source(encoder);
3682        /* set up the FMT blocks */
3683        dce_v11_0_program_fmt(encoder);
3684}
3685
3686static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3687{
3688        struct drm_device *dev = encoder->dev;
3689        struct amdgpu_device *adev = dev->dev_private;
3690
3691        /* need to call this here as we need the crtc set up */
3692        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3693        amdgpu_atombios_scratch_regs_lock(adev, false);
3694}
3695
3696static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3697{
3698        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3699        struct amdgpu_encoder_atom_dig *dig;
3700
3701        amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3702
3703        if (amdgpu_atombios_encoder_is_digital(encoder)) {
3704                if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3705                        dce_v11_0_afmt_enable(encoder, false);
3706                dig = amdgpu_encoder->enc_priv;
3707                dig->dig_encoder = -1;
3708        }
3709        amdgpu_encoder->active_device = 0;
3710}
3711
3712/* these are handled by the primary encoders */
3713static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3714{
3715
3716}
3717
3718static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3719{
3720
3721}
3722
3723static void
3724dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3725                      struct drm_display_mode *mode,
3726                      struct drm_display_mode *adjusted_mode)
3727{
3728
3729}
3730
3731static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3732{
3733
3734}
3735
3736static void
3737dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3738{
3739
3740}
3741
3742static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3743        .dpms = dce_v11_0_ext_dpms,
3744        .prepare = dce_v11_0_ext_prepare,
3745        .mode_set = dce_v11_0_ext_mode_set,
3746        .commit = dce_v11_0_ext_commit,
3747        .disable = dce_v11_0_ext_disable,
3748        /* no detect for TMDS/LVDS yet */
3749};
3750
3751static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3752        .dpms = amdgpu_atombios_encoder_dpms,
3753        .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3754        .prepare = dce_v11_0_encoder_prepare,
3755        .mode_set = dce_v11_0_encoder_mode_set,
3756        .commit = dce_v11_0_encoder_commit,
3757        .disable = dce_v11_0_encoder_disable,
3758        .detect = amdgpu_atombios_encoder_dig_detect,
3759};
3760
3761static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3762        .dpms = amdgpu_atombios_encoder_dpms,
3763        .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3764        .prepare = dce_v11_0_encoder_prepare,
3765        .mode_set = dce_v11_0_encoder_mode_set,
3766        .commit = dce_v11_0_encoder_commit,
3767        .detect = amdgpu_atombios_encoder_dac_detect,
3768};
3769
3770static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3771{
3772        struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3773        if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3774                amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3775        kfree(amdgpu_encoder->enc_priv);
3776        drm_encoder_cleanup(encoder);
3777        kfree(amdgpu_encoder);
3778}
3779
3780static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3781        .destroy = dce_v11_0_encoder_destroy,
3782};
3783
3784static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3785                                 uint32_t encoder_enum,
3786                                 uint32_t supported_device,
3787                                 u16 caps)
3788{
3789        struct drm_device *dev = adev->ddev;
3790        struct drm_encoder *encoder;
3791        struct amdgpu_encoder *amdgpu_encoder;
3792
3793        /* see if we already added it */
3794        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3795                amdgpu_encoder = to_amdgpu_encoder(encoder);
3796                if (amdgpu_encoder->encoder_enum == encoder_enum) {
3797                        amdgpu_encoder->devices |= supported_device;
3798                        return;
3799                }
3800
3801        }
3802
3803        /* add a new one */
3804        amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3805        if (!amdgpu_encoder)
3806                return;
3807
3808        encoder = &amdgpu_encoder->base;
3809        switch (adev->mode_info.num_crtc) {
3810        case 1:
3811                encoder->possible_crtcs = 0x1;
3812                break;
3813        case 2:
3814        default:
3815                encoder->possible_crtcs = 0x3;
3816                break;
3817        case 3:
3818                encoder->possible_crtcs = 0x7;
3819                break;
3820        case 4:
3821                encoder->possible_crtcs = 0xf;
3822                break;
3823        case 5:
3824                encoder->possible_crtcs = 0x1f;
3825                break;
3826        case 6:
3827                encoder->possible_crtcs = 0x3f;
3828                break;
3829        }
3830
3831        amdgpu_encoder->enc_priv = NULL;
3832
3833        amdgpu_encoder->encoder_enum = encoder_enum;
3834        amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3835        amdgpu_encoder->devices = supported_device;
3836        amdgpu_encoder->rmx_type = RMX_OFF;
3837        amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3838        amdgpu_encoder->is_ext_encoder = false;
3839        amdgpu_encoder->caps = caps;
3840
3841        switch (amdgpu_encoder->encoder_id) {
3842        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3843        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3844                drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3845                                 DRM_MODE_ENCODER_DAC, NULL);
3846                drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3847                break;
3848        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3849        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3850        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3851        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3852        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3853                if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3854                        amdgpu_encoder->rmx_type = RMX_FULL;
3855                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3856                                         DRM_MODE_ENCODER_LVDS, NULL);
3857                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3858                } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3859                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3860                                         DRM_MODE_ENCODER_DAC, NULL);
3861                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3862                } else {
3863                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3864                                         DRM_MODE_ENCODER_TMDS, NULL);
3865                        amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3866                }
3867                drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3868                break;
3869        case ENCODER_OBJECT_ID_SI170B:
3870        case ENCODER_OBJECT_ID_CH7303:
3871        case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3872        case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3873        case ENCODER_OBJECT_ID_TITFP513:
3874        case ENCODER_OBJECT_ID_VT1623:
3875        case ENCODER_OBJECT_ID_HDMI_SI1930:
3876        case ENCODER_OBJECT_ID_TRAVIS:
3877        case ENCODER_OBJECT_ID_NUTMEG:
3878                /* these are handled by the primary encoders */
3879                amdgpu_encoder->is_ext_encoder = true;
3880                if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3881                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3882                                         DRM_MODE_ENCODER_LVDS, NULL);
3883                else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3884                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3885                                         DRM_MODE_ENCODER_DAC, NULL);
3886                else
3887                        drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3888                                         DRM_MODE_ENCODER_TMDS, NULL);
3889                drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3890                break;
3891        }
3892}
3893
3894static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3895        .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3896        .bandwidth_update = &dce_v11_0_bandwidth_update,
3897        .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3898        .vblank_wait = &dce_v11_0_vblank_wait,
3899        .is_display_hung = &dce_v11_0_is_display_hung,
3900        .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3901        .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3902        .hpd_sense = &dce_v11_0_hpd_sense,
3903        .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3904        .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3905        .page_flip = &dce_v11_0_page_flip,
3906        .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3907        .add_encoder = &dce_v11_0_encoder_add,
3908        .add_connector = &amdgpu_connector_add,
3909        .stop_mc_access = &dce_v11_0_stop_mc_access,
3910        .resume_mc_access = &dce_v11_0_resume_mc_access,
3911};
3912
3913static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3914{
3915        if (adev->mode_info.funcs == NULL)
3916                adev->mode_info.funcs = &dce_v11_0_display_funcs;
3917}
3918
3919static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3920        .set = dce_v11_0_set_crtc_irq_state,
3921        .process = dce_v11_0_crtc_irq,
3922};
3923
3924static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3925        .set = dce_v11_0_set_pageflip_irq_state,
3926        .process = dce_v11_0_pageflip_irq,
3927};
3928
3929static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3930        .set = dce_v11_0_set_hpd_irq_state,
3931        .process = dce_v11_0_hpd_irq,
3932};
3933
3934static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3935{
3936        adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3937        adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3938
3939        adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3940        adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3941
3942        adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3943        adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3944}
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