source: src/linux/universal/linux-4.9/drivers/gpu/drm/i915/i915_drv.h @ 31884

Last change on this file since 31884 was 31884, checked in by brainslayer, 6 weeks ago

update kernels

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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <linux/backlight.h>
40#include <linux/hashtable.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43#include <linux/pm_qos.h>
44#include <linux/shmem_fs.h>
45
46#include <drm/drmP.h>
47#include <drm/intel-gtt.h>
48#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49#include <drm/drm_gem.h>
50#include <drm/drm_auth.h>
51
52#include "i915_params.h"
53#include "i915_reg.h"
54
55#include "intel_bios.h"
56#include "intel_dpll_mgr.h"
57#include "intel_guc.h"
58#include "intel_lrc.h"
59#include "intel_ringbuffer.h"
60
61#include "i915_gem.h"
62#include "i915_gem_gtt.h"
63#include "i915_gem_render_state.h"
64#include "i915_gem_request.h"
65
66#include "intel_gvt.h"
67
68/* General customization:
69 */
70
71#define DRIVER_NAME             "i915"
72#define DRIVER_DESC             "Intel Graphics"
73#define DRIVER_DATE             "20160919"
74
75#undef WARN_ON
76/* Many gcc seem to no see through this and fall over :( */
77#if 0
78#define WARN_ON(x) ({ \
79        bool __i915_warn_cond = (x); \
80        if (__builtin_constant_p(__i915_warn_cond)) \
81                BUILD_BUG_ON(__i915_warn_cond); \
82        WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83#else
84#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
85#endif
86
87#undef WARN_ON_ONCE
88#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89
90#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91                             (long) (x), __func__);
92
93/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem.  This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
98 * spam.
99 */
100#define I915_STATE_WARN(condition, format...) ({                        \
101        int __ret_warn_on = !!(condition);                              \
102        if (unlikely(__ret_warn_on))                                    \
103                if (!WARN(i915.verbose_state_checks, format))           \
104                        DRM_ERROR(format);                              \
105        unlikely(__ret_warn_on);                                        \
106})
107
108#define I915_STATE_WARN_ON(x)                                           \
109        I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110
111bool __i915_inject_load_failure(const char *func, int line);
112#define i915_inject_load_failure() \
113        __i915_inject_load_failure(__func__, __LINE__)
114
115static inline const char *yesno(bool v)
116{
117        return v ? "yes" : "no";
118}
119
120static inline const char *onoff(bool v)
121{
122        return v ? "on" : "off";
123}
124
125enum pipe {
126        INVALID_PIPE = -1,
127        PIPE_A = 0,
128        PIPE_B,
129        PIPE_C,
130        _PIPE_EDP,
131        I915_MAX_PIPES = _PIPE_EDP
132};
133#define pipe_name(p) ((p) + 'A')
134
135enum transcoder {
136        TRANSCODER_A = 0,
137        TRANSCODER_B,
138        TRANSCODER_C,
139        TRANSCODER_EDP,
140        TRANSCODER_DSI_A,
141        TRANSCODER_DSI_C,
142        I915_MAX_TRANSCODERS
143};
144
145static inline const char *transcoder_name(enum transcoder transcoder)
146{
147        switch (transcoder) {
148        case TRANSCODER_A:
149                return "A";
150        case TRANSCODER_B:
151                return "B";
152        case TRANSCODER_C:
153                return "C";
154        case TRANSCODER_EDP:
155                return "EDP";
156        case TRANSCODER_DSI_A:
157                return "DSI A";
158        case TRANSCODER_DSI_C:
159                return "DSI C";
160        default:
161                return "<invalid>";
162        }
163}
164
165static inline bool transcoder_is_dsi(enum transcoder transcoder)
166{
167        return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
168}
169
170/*
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC.  Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
175 */
176enum plane {
177        PLANE_A = 0,
178        PLANE_B,
179        PLANE_C,
180        PLANE_CURSOR,
181        I915_MAX_PLANES,
182};
183#define plane_name(p) ((p) + 'A')
184
185#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
186
187enum port {
188        PORT_A = 0,
189        PORT_B,
190        PORT_C,
191        PORT_D,
192        PORT_E,
193        I915_MAX_PORTS
194};
195#define port_name(p) ((p) + 'A')
196
197#define I915_NUM_PHYS_VLV 2
198
199enum dpio_channel {
200        DPIO_CH0,
201        DPIO_CH1
202};
203
204enum dpio_phy {
205        DPIO_PHY0,
206        DPIO_PHY1
207};
208
209enum intel_display_power_domain {
210        POWER_DOMAIN_PIPE_A,
211        POWER_DOMAIN_PIPE_B,
212        POWER_DOMAIN_PIPE_C,
213        POWER_DOMAIN_PIPE_A_PANEL_FITTER,
214        POWER_DOMAIN_PIPE_B_PANEL_FITTER,
215        POWER_DOMAIN_PIPE_C_PANEL_FITTER,
216        POWER_DOMAIN_TRANSCODER_A,
217        POWER_DOMAIN_TRANSCODER_B,
218        POWER_DOMAIN_TRANSCODER_C,
219        POWER_DOMAIN_TRANSCODER_EDP,
220        POWER_DOMAIN_TRANSCODER_DSI_A,
221        POWER_DOMAIN_TRANSCODER_DSI_C,
222        POWER_DOMAIN_PORT_DDI_A_LANES,
223        POWER_DOMAIN_PORT_DDI_B_LANES,
224        POWER_DOMAIN_PORT_DDI_C_LANES,
225        POWER_DOMAIN_PORT_DDI_D_LANES,
226        POWER_DOMAIN_PORT_DDI_E_LANES,
227        POWER_DOMAIN_PORT_DSI,
228        POWER_DOMAIN_PORT_CRT,
229        POWER_DOMAIN_PORT_OTHER,
230        POWER_DOMAIN_VGA,
231        POWER_DOMAIN_AUDIO,
232        POWER_DOMAIN_PLLS,
233        POWER_DOMAIN_AUX_A,
234        POWER_DOMAIN_AUX_B,
235        POWER_DOMAIN_AUX_C,
236        POWER_DOMAIN_AUX_D,
237        POWER_DOMAIN_GMBUS,
238        POWER_DOMAIN_MODESET,
239        POWER_DOMAIN_INIT,
240
241        POWER_DOMAIN_NUM,
242};
243
244#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246                ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247#define POWER_DOMAIN_TRANSCODER(tran) \
248        ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249         (tran) + POWER_DOMAIN_TRANSCODER_A)
250
251enum hpd_pin {
252        HPD_NONE = 0,
253        HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
254        HPD_CRT,
255        HPD_SDVO_B,
256        HPD_SDVO_C,
257        HPD_PORT_A,
258        HPD_PORT_B,
259        HPD_PORT_C,
260        HPD_PORT_D,
261        HPD_PORT_E,
262        HPD_NUM_PINS
263};
264
265#define for_each_hpd_pin(__pin) \
266        for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267
268struct i915_hotplug {
269        struct work_struct hotplug_work;
270
271        struct {
272                unsigned long last_jiffies;
273                int count;
274                enum {
275                        HPD_ENABLED = 0,
276                        HPD_DISABLED = 1,
277                        HPD_MARK_DISABLED = 2
278                } state;
279        } stats[HPD_NUM_PINS];
280        u32 event_bits;
281        struct delayed_work reenable_work;
282
283        struct intel_digital_port *irq_port[I915_MAX_PORTS];
284        u32 long_port_mask;
285        u32 short_port_mask;
286        struct work_struct dig_port_work;
287
288        struct work_struct poll_init_work;
289        bool poll_enabled;
290
291        /*
292         * if we get a HPD irq from DP and a HPD irq from non-DP
293         * the non-DP HPD could block the workqueue on a mode config
294         * mutex getting, that userspace may have taken. However
295         * userspace is waiting on the DP workqueue to run which is
296         * blocked behind the non-DP one.
297         */
298        struct workqueue_struct *dp_wq;
299};
300
301#define I915_GEM_GPU_DOMAINS \
302        (I915_GEM_DOMAIN_RENDER | \
303         I915_GEM_DOMAIN_SAMPLER | \
304         I915_GEM_DOMAIN_COMMAND | \
305         I915_GEM_DOMAIN_INSTRUCTION | \
306         I915_GEM_DOMAIN_VERTEX)
307
308#define for_each_pipe(__dev_priv, __p) \
309        for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310#define for_each_pipe_masked(__dev_priv, __p, __mask) \
311        for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312                for_each_if ((__mask) & (1 << (__p)))
313#define for_each_plane(__dev_priv, __pipe, __p)                         \
314        for ((__p) = 0;                                                 \
315             (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
316             (__p)++)
317#define for_each_sprite(__dev_priv, __p, __s)                           \
318        for ((__s) = 0;                                                 \
319             (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
320             (__s)++)
321
322#define for_each_port_masked(__port, __ports_mask) \
323        for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
324                for_each_if ((__ports_mask) & (1 << (__port)))
325
326#define for_each_crtc(dev, crtc) \
327        list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
328
329#define for_each_intel_plane(dev, intel_plane) \
330        list_for_each_entry(intel_plane,                        \
331                            &(dev)->mode_config.plane_list,     \
332                            base.head)
333
334#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
335        list_for_each_entry(intel_plane,                                \
336                            &(dev)->mode_config.plane_list,             \
337                            base.head)                                  \
338                for_each_if ((plane_mask) &                             \
339                             (1 << drm_plane_index(&intel_plane->base)))
340
341#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
342        list_for_each_entry(intel_plane,                                \
343                            &(dev)->mode_config.plane_list,             \
344                            base.head)                                  \
345                for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
346
347#define for_each_intel_crtc(dev, intel_crtc)                            \
348        list_for_each_entry(intel_crtc,                                 \
349                            &(dev)->mode_config.crtc_list,              \
350                            base.head)
351
352#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
353        list_for_each_entry(intel_crtc,                                 \
354                            &(dev)->mode_config.crtc_list,              \
355                            base.head)                                  \
356                for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
357
358#define for_each_intel_encoder(dev, intel_encoder)              \
359        list_for_each_entry(intel_encoder,                      \
360                            &(dev)->mode_config.encoder_list,   \
361                            base.head)
362
363#define for_each_intel_connector(dev, intel_connector)          \
364        list_for_each_entry(intel_connector,                    \
365                            &(dev)->mode_config.connector_list, \
366                            base.head)
367
368#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369        list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370                for_each_if ((intel_encoder)->base.crtc == (__crtc))
371
372#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373        list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374                for_each_if ((intel_connector)->base.encoder == (__encoder))
375
376#define for_each_power_domain(domain, mask)                             \
377        for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
378                for_each_if ((1 << (domain)) & (mask))
379
380struct drm_i915_private;
381struct i915_mm_struct;
382struct i915_mmu_object;
383
384struct drm_i915_file_private {
385        struct drm_i915_private *dev_priv;
386        struct drm_file *file;
387
388        struct {
389                spinlock_t lock;
390                struct list_head request_list;
391/* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
395 */
396#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
397        } mm;
398        struct idr context_idr;
399
400        struct intel_rps_client {
401                struct list_head link;
402                unsigned boosts;
403        } rps;
404
405        unsigned int bsd_engine;
406};
407
408/* Used by dp and fdi links */
409struct intel_link_m_n {
410        uint32_t        tu;
411        uint32_t        gmch_m;
412        uint32_t        gmch_n;
413        uint32_t        link_m;
414        uint32_t        link_n;
415};
416
417void intel_link_compute_m_n(int bpp, int nlanes,
418                            int pixel_clock, int link_clock,
419                            struct intel_link_m_n *m_n);
420
421/* Interface history:
422 *
423 * 1.1: Original.
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 *      - Support vertical blank on secondary display pipe
430 */
431#define DRIVER_MAJOR            1
432#define DRIVER_MINOR            6
433#define DRIVER_PATCHLEVEL       0
434
435struct opregion_header;
436struct opregion_acpi;
437struct opregion_swsci;
438struct opregion_asle;
439
440struct intel_opregion {
441        struct opregion_header *header;
442        struct opregion_acpi *acpi;
443        struct opregion_swsci *swsci;
444        u32 swsci_gbda_sub_functions;
445        u32 swsci_sbcb_sub_functions;
446        struct opregion_asle *asle;
447        void *rvda;
448        const void *vbt;
449        u32 vbt_size;
450        u32 *lid_state;
451        struct work_struct asle_work;
452};
453#define OPREGION_SIZE            (8*1024)
454
455struct intel_overlay;
456struct intel_overlay_error_state;
457
458struct drm_i915_fence_reg {
459        struct list_head link;
460        struct drm_i915_private *i915;
461        struct i915_vma *vma;
462        int pin_count;
463        int id;
464        /**
465         * Whether the tiling parameters for the currently
466         * associated fence register have changed. Note that
467         * for the purposes of tracking tiling changes we also
468         * treat the unfenced register, the register slot that
469         * the object occupies whilst it executes a fenced
470         * command (such as BLT on gen2/3), as a "fence".
471         */
472        bool dirty;
473};
474
475struct sdvo_device_mapping {
476        u8 initialized;
477        u8 dvo_port;
478        u8 slave_addr;
479        u8 dvo_wiring;
480        u8 i2c_pin;
481        u8 ddc_pin;
482};
483
484struct intel_connector;
485struct intel_encoder;
486struct intel_crtc_state;
487struct intel_initial_plane_config;
488struct intel_crtc;
489struct intel_limit;
490struct dpll;
491
492struct drm_i915_display_funcs {
493        int (*get_display_clock_speed)(struct drm_device *dev);
494        int (*get_fifo_size)(struct drm_device *dev, int plane);
495        int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
496        int (*compute_intermediate_wm)(struct drm_device *dev,
497                                       struct intel_crtc *intel_crtc,
498                                       struct intel_crtc_state *newstate);
499        void (*initial_watermarks)(struct intel_crtc_state *cstate);
500        void (*optimize_watermarks)(struct intel_crtc_state *cstate);
501        int (*compute_global_watermarks)(struct drm_atomic_state *state);
502        void (*update_wm)(struct drm_crtc *crtc);
503        int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
504        void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
505        /* Returns the active state of the crtc, and if the crtc is active,
506         * fills out the pipe-config with the hw state. */
507        bool (*get_pipe_config)(struct intel_crtc *,
508                                struct intel_crtc_state *);
509        void (*get_initial_plane_config)(struct intel_crtc *,
510                                         struct intel_initial_plane_config *);
511        int (*crtc_compute_clock)(struct intel_crtc *crtc,
512                                  struct intel_crtc_state *crtc_state);
513        void (*crtc_enable)(struct intel_crtc_state *pipe_config,
514                            struct drm_atomic_state *old_state);
515        void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
516                             struct drm_atomic_state *old_state);
517        void (*update_crtcs)(struct drm_atomic_state *state,
518                             unsigned int *crtc_vblank_mask);
519        void (*audio_codec_enable)(struct drm_connector *connector,
520                                   struct intel_encoder *encoder,
521                                   const struct drm_display_mode *adjusted_mode);
522        void (*audio_codec_disable)(struct intel_encoder *encoder);
523        void (*fdi_link_train)(struct drm_crtc *crtc);
524        void (*init_clock_gating)(struct drm_device *dev);
525        int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
526                          struct drm_framebuffer *fb,
527                          struct drm_i915_gem_object *obj,
528                          struct drm_i915_gem_request *req,
529                          uint32_t flags);
530        void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
531        /* clock updates for mode set */
532        /* cursor updates */
533        /* render clock increase/decrease */
534        /* display clock increase/decrease */
535        /* pll clock increase/decrease */
536
537        void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
538        void (*load_luts)(struct drm_crtc_state *crtc_state);
539};
540
541enum forcewake_domain_id {
542        FW_DOMAIN_ID_RENDER = 0,
543        FW_DOMAIN_ID_BLITTER,
544        FW_DOMAIN_ID_MEDIA,
545
546        FW_DOMAIN_ID_COUNT
547};
548
549enum forcewake_domains {
550        FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
551        FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
552        FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
553        FORCEWAKE_ALL = (FORCEWAKE_RENDER |
554                         FORCEWAKE_BLITTER |
555                         FORCEWAKE_MEDIA)
556};
557
558#define FW_REG_READ  (1)
559#define FW_REG_WRITE (2)
560
561enum forcewake_domains
562intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
563                               i915_reg_t reg, unsigned int op);
564
565struct intel_uncore_funcs {
566        void (*force_wake_get)(struct drm_i915_private *dev_priv,
567                                                        enum forcewake_domains domains);
568        void (*force_wake_put)(struct drm_i915_private *dev_priv,
569                                                        enum forcewake_domains domains);
570
571        uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
572        uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
573        uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
574        uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
575
576        void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
577                                uint8_t val, bool trace);
578        void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
579                                uint16_t val, bool trace);
580        void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
581                                uint32_t val, bool trace);
582};
583
584struct intel_uncore {
585        spinlock_t lock; /** lock is also taken in irq contexts. */
586
587        struct intel_uncore_funcs funcs;
588
589        unsigned fifo_count;
590        enum forcewake_domains fw_domains;
591
592        struct intel_uncore_forcewake_domain {
593                struct drm_i915_private *i915;
594                enum forcewake_domain_id id;
595                enum forcewake_domains mask;
596                unsigned wake_count;
597                struct hrtimer timer;
598                i915_reg_t reg_set;
599                u32 val_set;
600                u32 val_clear;
601                i915_reg_t reg_ack;
602                i915_reg_t reg_post;
603                u32 val_reset;
604        } fw_domain[FW_DOMAIN_ID_COUNT];
605
606        int unclaimed_mmio_check;
607};
608
609/* Iterate over initialised fw domains */
610#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
611        for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
612             (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
613             (domain__)++) \
614                for_each_if ((mask__) & (domain__)->mask)
615
616#define for_each_fw_domain(domain__, dev_priv__) \
617        for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
618
619#define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
620#define CSR_VERSION_MAJOR(version)      ((version) >> 16)
621#define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
622
623struct intel_csr {
624        struct work_struct work;
625        const char *fw_path;
626        uint32_t *dmc_payload;
627        uint32_t dmc_fw_size;
628        uint32_t version;
629        uint32_t mmio_count;
630        i915_reg_t mmioaddr[8];
631        uint32_t mmiodata[8];
632        uint32_t dc_state;
633        uint32_t allowed_dc_mask;
634};
635
636#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
637        func(is_mobile) sep \
638        func(is_i85x) sep \
639        func(is_i915g) sep \
640        func(is_i945gm) sep \
641        func(is_g33) sep \
642        func(hws_needs_physical) sep \
643        func(is_g4x) sep \
644        func(is_pineview) sep \
645        func(is_broadwater) sep \
646        func(is_crestline) sep \
647        func(is_ivybridge) sep \
648        func(is_valleyview) sep \
649        func(is_cherryview) sep \
650        func(is_haswell) sep \
651        func(is_broadwell) sep \
652        func(is_skylake) sep \
653        func(is_broxton) sep \
654        func(is_kabylake) sep \
655        func(is_preliminary) sep \
656        func(has_fbc) sep \
657        func(has_psr) sep \
658        func(has_runtime_pm) sep \
659        func(has_csr) sep \
660        func(has_resource_streamer) sep \
661        func(has_rc6) sep \
662        func(has_rc6p) sep \
663        func(has_dp_mst) sep \
664        func(has_gmbus_irq) sep \
665        func(has_hw_contexts) sep \
666        func(has_logical_ring_contexts) sep \
667        func(has_l3_dpf) sep \
668        func(has_gmch_display) sep \
669        func(has_guc) sep \
670        func(has_pipe_cxsr) sep \
671        func(has_hotplug) sep \
672        func(cursor_needs_physical) sep \
673        func(has_overlay) sep \
674        func(overlay_needs_physical) sep \
675        func(supports_tv) sep \
676        func(has_llc) sep \
677        func(has_snoop) sep \
678        func(has_ddi) sep \
679        func(has_fpga_dbg) sep \
680        func(has_pooled_eu)
681
682#define DEFINE_FLAG(name) u8 name:1
683#define SEP_SEMICOLON ;
684
685struct sseu_dev_info {
686        u8 slice_mask;
687        u8 subslice_mask;
688        u8 eu_total;
689        u8 eu_per_subslice;
690        u8 min_eu_in_pool;
691        /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
692        u8 subslice_7eu[3];
693        u8 has_slice_pg:1;
694        u8 has_subslice_pg:1;
695        u8 has_eu_pg:1;
696};
697
698static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
699{
700        return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
701}
702
703struct intel_device_info {
704        u32 display_mmio_offset;
705        u16 device_id;
706        u8 num_pipes;
707        u8 num_sprites[I915_MAX_PIPES];
708        u8 gen;
709        u16 gen_mask;
710        u8 ring_mask; /* Rings supported by the HW */
711        u8 num_rings;
712        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
713        u16 ddb_size; /* in blocks */
714        /* Register offsets for the various display pipes and transcoders */
715        int pipe_offsets[I915_MAX_TRANSCODERS];
716        int trans_offsets[I915_MAX_TRANSCODERS];
717        int palette_offsets[I915_MAX_PIPES];
718        int cursor_offsets[I915_MAX_PIPES];
719
720        /* Slice/subslice/EU info */
721        struct sseu_dev_info sseu;
722
723        struct color_luts {
724                u16 degamma_lut_size;
725                u16 gamma_lut_size;
726        } color;
727};
728
729#undef DEFINE_FLAG
730#undef SEP_SEMICOLON
731
732struct intel_display_error_state;
733
734struct drm_i915_error_state {
735        struct kref ref;
736        struct timeval time;
737
738        char error_msg[128];
739        bool simulated;
740        int iommu;
741        u32 reset_count;
742        u32 suspend_count;
743        struct intel_device_info device_info;
744
745        /* Generic register state */
746        u32 eir;
747        u32 pgtbl_er;
748        u32 ier;
749        u32 gtier[4];
750        u32 ccid;
751        u32 derrmr;
752        u32 forcewake;
753        u32 error; /* gen6+ */
754        u32 err_int; /* gen7 */
755        u32 fault_data0; /* gen8, gen9 */
756        u32 fault_data1; /* gen8, gen9 */
757        u32 done_reg;
758        u32 gac_eco;
759        u32 gam_ecochk;
760        u32 gab_ctl;
761        u32 gfx_mode;
762        u32 extra_instdone[I915_NUM_INSTDONE_REG];
763        u64 fence[I915_MAX_NUM_FENCES];
764        struct intel_overlay_error_state *overlay;
765        struct intel_display_error_state *display;
766        struct drm_i915_error_object *semaphore;
767
768        struct drm_i915_error_engine {
769                int engine_id;
770                /* Software tracked state */
771                bool waiting;
772                int num_waiters;
773                int hangcheck_score;
774                enum intel_engine_hangcheck_action hangcheck_action;
775                struct i915_address_space *vm;
776                int num_requests;
777
778                /* our own tracking of ring head and tail */
779                u32 cpu_ring_head;
780                u32 cpu_ring_tail;
781
782                u32 last_seqno;
783                u32 semaphore_seqno[I915_NUM_ENGINES - 1];
784
785                /* Register state */
786                u32 start;
787                u32 tail;
788                u32 head;
789                u32 ctl;
790                u32 mode;
791                u32 hws;
792                u32 ipeir;
793                u32 ipehr;
794                u32 instdone;
795                u32 bbstate;
796                u32 instpm;
797                u32 instps;
798                u32 seqno;
799                u64 bbaddr;
800                u64 acthd;
801                u32 fault_reg;
802                u64 faddr;
803                u32 rc_psmi; /* sleep state */
804                u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
805
806                struct drm_i915_error_object {
807                        int page_count;
808                        u64 gtt_offset;
809                        u64 gtt_size;
810                        u32 *pages[0];
811                } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
812
813                struct drm_i915_error_object *wa_ctx;
814
815                struct drm_i915_error_request {
816                        long jiffies;
817                        pid_t pid;
818                        u32 seqno;
819                        u32 head;
820                        u32 tail;
821                } *requests;
822
823                struct drm_i915_error_waiter {
824                        char comm[TASK_COMM_LEN];
825                        pid_t pid;
826                        u32 seqno;
827                } *waiters;
828
829                struct {
830                        u32 gfx_mode;
831                        union {
832                                u64 pdp[4];
833                                u32 pp_dir_base;
834                        };
835                } vm_info;
836
837                pid_t pid;
838                char comm[TASK_COMM_LEN];
839        } engine[I915_NUM_ENGINES];
840
841        struct drm_i915_error_buffer {
842                u32 size;
843                u32 name;
844                u32 rseqno[I915_NUM_ENGINES], wseqno;
845                u64 gtt_offset;
846                u32 read_domains;
847                u32 write_domain;
848                s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
849                u32 tiling:2;
850                u32 dirty:1;
851                u32 purgeable:1;
852                u32 userptr:1;
853                s32 engine:4;
854                u32 cache_level:3;
855        } *active_bo[I915_NUM_ENGINES], *pinned_bo;
856        u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
857        struct i915_address_space *active_vm[I915_NUM_ENGINES];
858};
859
860enum i915_cache_level {
861        I915_CACHE_NONE = 0,
862        I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
863        I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
864                              caches, eg sampler/render caches, and the
865                              large Last-Level-Cache. LLC is coherent with
866                              the CPU, but L3 is only visible to the GPU. */
867        I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
868};
869
870struct i915_ctx_hang_stats {
871        /* This context had batch pending when hang was declared */
872        unsigned batch_pending;
873
874        /* This context had batch active when hang was declared */
875        unsigned batch_active;
876
877        /* Time when this context was last blamed for a GPU reset */
878        unsigned long guilty_ts;
879
880        /* If the contexts causes a second GPU hang within this time,
881         * it is permanently banned from submitting any more work.
882         */
883        unsigned long ban_period_seconds;
884
885        /* This context is banned to submit more work */
886        bool banned;
887};
888
889/* This must match up with the value previously used for execbuf2.rsvd1. */
890#define DEFAULT_CONTEXT_HANDLE 0
891
892/**
893 * struct i915_gem_context - as the name implies, represents a context.
894 * @ref: reference count.
895 * @user_handle: userspace tracking identity for this context.
896 * @remap_slice: l3 row remapping information.
897 * @flags: context specific flags:
898 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
899 * @file_priv: filp associated with this context (NULL for global default
900 *             context).
901 * @hang_stats: information about the role of this context in possible GPU
902 *              hangs.
903 * @ppgtt: virtual memory space used by this context.
904 * @legacy_hw_ctx: render context backing object and whether it is correctly
905 *                initialized (legacy ring submission mechanism only).
906 * @link: link in the global list of contexts.
907 *
908 * Contexts are memory images used by the hardware to store copies of their
909 * internal state.
910 */
911struct i915_gem_context {
912        struct kref ref;
913        struct drm_i915_private *i915;
914        struct drm_i915_file_private *file_priv;
915        struct i915_hw_ppgtt *ppgtt;
916        struct pid *pid;
917
918        struct i915_ctx_hang_stats hang_stats;
919
920        unsigned long flags;
921#define CONTEXT_NO_ZEROMAP              BIT(0)
922#define CONTEXT_NO_ERROR_CAPTURE        BIT(1)
923
924        /* Unique identifier for this context, used by the hw for tracking */
925        unsigned int hw_id;
926        u32 user_handle;
927
928        u32 ggtt_alignment;
929
930        struct intel_context {
931                struct i915_vma *state;
932                struct intel_ring *ring;
933                uint32_t *lrc_reg_state;
934                u64 lrc_desc;
935                int pin_count;
936                bool initialised;
937        } engine[I915_NUM_ENGINES];
938        u32 ring_size;
939        u32 desc_template;
940        struct atomic_notifier_head status_notifier;
941        bool execlists_force_single_submission;
942
943        struct list_head link;
944
945        u8 remap_slice;
946        bool closed:1;
947};
948
949enum fb_op_origin {
950        ORIGIN_GTT,
951        ORIGIN_CPU,
952        ORIGIN_CS,
953        ORIGIN_FLIP,
954        ORIGIN_DIRTYFB,
955};
956
957struct intel_fbc {
958        /* This is always the inner lock when overlapping with struct_mutex and
959         * it's the outer lock when overlapping with stolen_lock. */
960        struct mutex lock;
961        unsigned threshold;
962        unsigned int possible_framebuffer_bits;
963        unsigned int busy_bits;
964        unsigned int visible_pipes_mask;
965        struct intel_crtc *crtc;
966
967        struct drm_mm_node compressed_fb;
968        struct drm_mm_node *compressed_llb;
969
970        bool false_color;
971
972        bool enabled;
973        bool active;
974
975        struct intel_fbc_state_cache {
976                struct {
977                        unsigned int mode_flags;
978                        uint32_t hsw_bdw_pixel_rate;
979                } crtc;
980
981                struct {
982                        unsigned int rotation;
983                        int src_w;
984                        int src_h;
985                        bool visible;
986                } plane;
987
988                struct {
989                        u64 ilk_ggtt_offset;
990                        uint32_t pixel_format;
991                        unsigned int stride;
992                        int fence_reg;
993                        unsigned int tiling_mode;
994                } fb;
995        } state_cache;
996
997        struct intel_fbc_reg_params {
998                struct {
999                        enum pipe pipe;
1000                        enum plane plane;
1001                        unsigned int fence_y_offset;
1002                } crtc;
1003
1004                struct {
1005                        u64 ggtt_offset;
1006                        uint32_t pixel_format;
1007                        unsigned int stride;
1008                        int fence_reg;
1009                } fb;
1010
1011                int cfb_size;
1012        } params;
1013
1014        struct intel_fbc_work {
1015                bool scheduled;
1016                u32 scheduled_vblank;
1017                struct work_struct work;
1018        } work;
1019
1020        const char *no_fbc_reason;
1021};
1022
1023/**
1024 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1025 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1026 * parsing for same resolution.
1027 */
1028enum drrs_refresh_rate_type {
1029        DRRS_HIGH_RR,
1030        DRRS_LOW_RR,
1031        DRRS_MAX_RR, /* RR count */
1032};
1033
1034enum drrs_support_type {
1035        DRRS_NOT_SUPPORTED = 0,
1036        STATIC_DRRS_SUPPORT = 1,
1037        SEAMLESS_DRRS_SUPPORT = 2
1038};
1039
1040struct intel_dp;
1041struct i915_drrs {
1042        struct mutex mutex;
1043        struct delayed_work work;
1044        struct intel_dp *dp;
1045        unsigned busy_frontbuffer_bits;
1046        enum drrs_refresh_rate_type refresh_rate_type;
1047        enum drrs_support_type type;
1048};
1049
1050struct i915_psr {
1051        struct mutex lock;
1052        bool sink_support;
1053        bool source_ok;
1054        struct intel_dp *enabled;
1055        bool active;
1056        struct delayed_work work;
1057        unsigned busy_frontbuffer_bits;
1058        bool psr2_support;
1059        bool aux_frame_sync;
1060        bool link_standby;
1061};
1062
1063enum intel_pch {
1064        PCH_NONE = 0,   /* No PCH present */
1065        PCH_IBX,        /* Ibexpeak PCH */
1066        PCH_CPT,        /* Cougarpoint PCH */
1067        PCH_LPT,        /* Lynxpoint PCH */
1068        PCH_SPT,        /* Sunrisepoint PCH */
1069        PCH_KBP,        /* Kabypoint PCH */
1070        PCH_NOP,
1071};
1072
1073enum intel_sbi_destination {
1074        SBI_ICLK,
1075        SBI_MPHY,
1076};
1077
1078#define QUIRK_PIPEA_FORCE (1<<0)
1079#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1080#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1081#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1082#define QUIRK_PIPEB_FORCE (1<<4)
1083#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1084
1085struct intel_fbdev;
1086struct intel_fbc_work;
1087
1088struct intel_gmbus {
1089        struct i2c_adapter adapter;
1090#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1091        u32 force_bit;
1092        u32 reg0;
1093        i915_reg_t gpio_reg;
1094        struct i2c_algo_bit_data bit_algo;
1095        struct drm_i915_private *dev_priv;
1096};
1097
1098struct i915_suspend_saved_registers {
1099        u32 saveDSPARB;
1100        u32 saveFBC_CONTROL;
1101        u32 saveCACHE_MODE_0;
1102        u32 saveMI_ARB_STATE;
1103        u32 saveSWF0[16];
1104        u32 saveSWF1[16];
1105        u32 saveSWF3[3];
1106        uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1107        u32 savePCH_PORT_HOTPLUG;
1108        u16 saveGCDGMBUS;
1109};
1110
1111struct vlv_s0ix_state {
1112        /* GAM */
1113        u32 wr_watermark;
1114        u32 gfx_prio_ctrl;
1115        u32 arb_mode;
1116        u32 gfx_pend_tlb0;
1117        u32 gfx_pend_tlb1;
1118        u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1119        u32 media_max_req_count;
1120        u32 gfx_max_req_count;
1121        u32 render_hwsp;
1122        u32 ecochk;
1123        u32 bsd_hwsp;
1124        u32 blt_hwsp;
1125        u32 tlb_rd_addr;
1126
1127        /* MBC */
1128        u32 g3dctl;
1129        u32 gsckgctl;
1130        u32 mbctl;
1131
1132        /* GCP */
1133        u32 ucgctl1;
1134        u32 ucgctl3;
1135        u32 rcgctl1;
1136        u32 rcgctl2;
1137        u32 rstctl;
1138        u32 misccpctl;
1139
1140        /* GPM */
1141        u32 gfxpause;
1142        u32 rpdeuhwtc;
1143        u32 rpdeuc;
1144        u32 ecobus;
1145        u32 pwrdwnupctl;
1146        u32 rp_down_timeout;
1147        u32 rp_deucsw;
1148        u32 rcubmabdtmr;
1149        u32 rcedata;
1150        u32 spare2gh;
1151
1152        /* Display 1 CZ domain */
1153        u32 gt_imr;
1154        u32 gt_ier;
1155        u32 pm_imr;
1156        u32 pm_ier;
1157        u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1158
1159        /* GT SA CZ domain */
1160        u32 tilectl;
1161        u32 gt_fifoctl;
1162        u32 gtlc_wake_ctrl;
1163        u32 gtlc_survive;
1164        u32 pmwgicz;
1165
1166        /* Display 2 CZ domain */
1167        u32 gu_ctl0;
1168        u32 gu_ctl1;
1169        u32 pcbr;
1170        u32 clock_gate_dis2;
1171};
1172
1173struct intel_rps_ei {
1174        u32 cz_clock;
1175        u32 render_c0;
1176        u32 media_c0;
1177};
1178
1179struct intel_gen6_power_mgmt {
1180        /*
1181         * work, interrupts_enabled and pm_iir are protected by
1182         * dev_priv->irq_lock
1183         */
1184        struct work_struct work;
1185        bool interrupts_enabled;
1186        u32 pm_iir;
1187
1188        /* PM interrupt bits that should never be masked */
1189        u32 pm_intr_keep;
1190
1191        /* Frequencies are stored in potentially platform dependent multiples.
1192         * In other words, *_freq needs to be multiplied by X to be interesting.
1193         * Soft limits are those which are used for the dynamic reclocking done
1194         * by the driver (raise frequencies under heavy loads, and lower for
1195         * lighter loads). Hard limits are those imposed by the hardware.
1196         *
1197         * A distinction is made for overclocking, which is never enabled by
1198         * default, and is considered to be above the hard limit if it's
1199         * possible at all.
1200         */
1201        u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1202        u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1203        u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1204        u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1205        u8 min_freq;            /* AKA RPn. Minimum frequency */
1206        u8 boost_freq;          /* Frequency to request when wait boosting */
1207        u8 idle_freq;           /* Frequency to request when we are idle */
1208        u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1209        u8 rp1_freq;            /* "less than" RP0 power/freqency */
1210        u8 rp0_freq;            /* Non-overclocked max frequency. */
1211        u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
1212
1213        u8 up_threshold; /* Current %busy required to uplock */
1214        u8 down_threshold; /* Current %busy required to downclock */
1215
1216        int last_adj;
1217        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1218
1219        spinlock_t client_lock;
1220        struct list_head clients;
1221        bool client_boost;
1222
1223        bool enabled;
1224        struct delayed_work autoenable_work;
1225        unsigned boosts;
1226
1227        /* manual wa residency calculations */
1228        struct intel_rps_ei ei;
1229
1230        /*
1231         * Protects RPS/RC6 register access and PCU communication.
1232         * Must be taken after struct_mutex if nested. Note that
1233         * this lock may be held for long periods of time when
1234         * talking to hw - so only take it when talking to hw!
1235         */
1236        struct mutex hw_lock;
1237};
1238
1239/* defined intel_pm.c */
1240extern spinlock_t mchdev_lock;
1241
1242struct intel_ilk_power_mgmt {
1243        u8 cur_delay;
1244        u8 min_delay;
1245        u8 max_delay;
1246        u8 fmax;
1247        u8 fstart;
1248
1249        u64 last_count1;
1250        unsigned long last_time1;
1251        unsigned long chipset_power;
1252        u64 last_count2;
1253        u64 last_time2;
1254        unsigned long gfx_power;
1255        u8 corr;
1256
1257        int c_m;
1258        int r_t;
1259};
1260
1261struct drm_i915_private;
1262struct i915_power_well;
1263
1264struct i915_power_well_ops {
1265        /*
1266         * Synchronize the well's hw state to match the current sw state, for
1267         * example enable/disable it based on the current refcount. Called
1268         * during driver init and resume time, possibly after first calling
1269         * the enable/disable handlers.
1270         */
1271        void (*sync_hw)(struct drm_i915_private *dev_priv,
1272                        struct i915_power_well *power_well);
1273        /*
1274         * Enable the well and resources that depend on it (for example
1275         * interrupts located on the well). Called after the 0->1 refcount
1276         * transition.
1277         */
1278        void (*enable)(struct drm_i915_private *dev_priv,
1279                       struct i915_power_well *power_well);
1280        /*
1281         * Disable the well and resources that depend on it. Called after
1282         * the 1->0 refcount transition.
1283         */
1284        void (*disable)(struct drm_i915_private *dev_priv,
1285                        struct i915_power_well *power_well);
1286        /* Returns the hw enabled state. */
1287        bool (*is_enabled)(struct drm_i915_private *dev_priv,
1288                           struct i915_power_well *power_well);
1289};
1290
1291/* Power well structure for haswell */
1292struct i915_power_well {
1293        const char *name;
1294        bool always_on;
1295        /* power well enable/disable usage count */
1296        int count;
1297        /* cached hw enabled state */
1298        bool hw_enabled;
1299        unsigned long domains;
1300        unsigned long data;
1301        const struct i915_power_well_ops *ops;
1302};
1303
1304struct i915_power_domains {
1305        /*
1306         * Power wells needed for initialization at driver init and suspend
1307         * time are on. They are kept on until after the first modeset.
1308         */
1309        bool init_power_on;
1310        bool initializing;
1311        int power_well_count;
1312
1313        struct mutex lock;
1314        int domain_use_count[POWER_DOMAIN_NUM];
1315        struct i915_power_well *power_wells;
1316};
1317
1318#define MAX_L3_SLICES 2
1319struct intel_l3_parity {
1320        u32 *remap_info[MAX_L3_SLICES];
1321        struct work_struct error_work;
1322        int which_slice;
1323};
1324
1325struct i915_gem_mm {
1326        /** Memory allocator for GTT stolen memory */
1327        struct drm_mm stolen;
1328        /** Protects the usage of the GTT stolen memory allocator. This is
1329         * always the inner lock when overlapping with struct_mutex. */
1330        struct mutex stolen_lock;
1331
1332        /** List of all objects in gtt_space. Used to restore gtt
1333         * mappings on resume */
1334        struct list_head bound_list;
1335        /**
1336         * List of objects which are not bound to the GTT (thus
1337         * are idle and not used by the GPU) but still have
1338         * (presumably uncached) pages still attached.
1339         */
1340        struct list_head unbound_list;
1341
1342        /** Usable portion of the GTT for GEM */
1343        unsigned long stolen_base; /* limited to low memory (32-bit) */
1344
1345        /** PPGTT used for aliasing the PPGTT with the GTT */
1346        struct i915_hw_ppgtt *aliasing_ppgtt;
1347
1348        struct notifier_block oom_notifier;
1349        struct notifier_block vmap_notifier;
1350        struct shrinker shrinker;
1351
1352        /** LRU list of objects with fence regs on them. */
1353        struct list_head fence_list;
1354
1355        /**
1356         * Are we in a non-interruptible section of code like
1357         * modesetting?
1358         */
1359        bool interruptible;
1360
1361        /* the indicator for dispatch video commands on two BSD rings */
1362        atomic_t bsd_engine_dispatch_index;
1363
1364        /** Bit 6 swizzling required for X tiling */
1365        uint32_t bit_6_swizzle_x;
1366        /** Bit 6 swizzling required for Y tiling */
1367        uint32_t bit_6_swizzle_y;
1368
1369        /* accounting, useful for userland debugging */
1370        spinlock_t object_stat_lock;
1371        size_t object_memory;
1372        u32 object_count;
1373};
1374
1375struct drm_i915_error_state_buf {
1376        struct drm_i915_private *i915;
1377        unsigned bytes;
1378        unsigned size;
1379        int err;
1380        u8 *buf;
1381        loff_t start;
1382        loff_t pos;
1383};
1384
1385struct i915_error_state_file_priv {
1386        struct drm_device *dev;
1387        struct drm_i915_error_state *error;
1388};
1389
1390struct i915_gpu_error {
1391        /* For hangcheck timer */
1392#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1393#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1394        /* Hang gpu twice in this window and your context gets banned */
1395#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1396
1397        struct delayed_work hangcheck_work;
1398
1399        /* For reset and error_state handling. */
1400        spinlock_t lock;
1401        /* Protected by the above dev->gpu_error.lock. */
1402        struct drm_i915_error_state *first_error;
1403
1404        unsigned long missed_irq_rings;
1405
1406        /**
1407         * State variable controlling the reset flow and count
1408         *
1409         * This is a counter which gets incremented when reset is triggered,
1410         *
1411         * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1412         * meaning that any waiters holding onto the struct_mutex should
1413         * relinquish the lock immediately in order for the reset to start.
1414         *
1415         * If reset is not completed succesfully, the I915_WEDGE bit is
1416         * set meaning that hardware is terminally sour and there is no
1417         * recovery. All waiters on the reset_queue will be woken when
1418         * that happens.
1419         *
1420         * This counter is used by the wait_seqno code to notice that reset
1421         * event happened and it needs to restart the entire ioctl (since most
1422         * likely the seqno it waited for won't ever signal anytime soon).
1423         *
1424         * This is important for lock-free wait paths, where no contended lock
1425         * naturally enforces the correct ordering between the bail-out of the
1426         * waiter and the gpu reset work code.
1427         */
1428        unsigned long reset_count;
1429
1430        unsigned long flags;
1431#define I915_RESET_IN_PROGRESS  0
1432#define I915_WEDGED             (BITS_PER_LONG - 1)
1433
1434        /**
1435         * Waitqueue to signal when a hang is detected. Used to for waiters
1436         * to release the struct_mutex for the reset to procede.
1437         */
1438        wait_queue_head_t wait_queue;
1439
1440        /**
1441         * Waitqueue to signal when the reset has completed. Used by clients
1442         * that wait for dev_priv->mm.wedged to settle.
1443         */
1444        wait_queue_head_t reset_queue;
1445
1446        /* For missed irq/seqno simulation. */
1447        unsigned long test_irq_rings;
1448};
1449
1450enum modeset_restore {
1451        MODESET_ON_LID_OPEN,
1452        MODESET_DONE,
1453        MODESET_SUSPENDED,
1454};
1455
1456#define DP_AUX_A 0x40
1457#define DP_AUX_B 0x10
1458#define DP_AUX_C 0x20
1459#define DP_AUX_D 0x30
1460
1461#define DDC_PIN_B  0x05
1462#define DDC_PIN_C  0x04
1463#define DDC_PIN_D  0x06
1464
1465struct ddi_vbt_port_info {
1466        /*
1467         * This is an index in the HDMI/DVI DDI buffer translation table.
1468         * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1469         * populate this field.
1470         */
1471#define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1472        uint8_t hdmi_level_shift;
1473
1474        uint8_t supports_dvi:1;
1475        uint8_t supports_hdmi:1;
1476        uint8_t supports_dp:1;
1477
1478        uint8_t alternate_aux_channel;
1479        uint8_t alternate_ddc_pin;
1480
1481        uint8_t dp_boost_level;
1482        uint8_t hdmi_boost_level;
1483};
1484
1485enum psr_lines_to_wait {
1486        PSR_0_LINES_TO_WAIT = 0,
1487        PSR_1_LINE_TO_WAIT,
1488        PSR_4_LINES_TO_WAIT,
1489        PSR_8_LINES_TO_WAIT
1490};
1491
1492struct intel_vbt_data {
1493        struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1494        struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1495
1496        /* Feature bits */
1497        unsigned int int_tv_support:1;
1498        unsigned int lvds_dither:1;
1499        unsigned int lvds_vbt:1;
1500        unsigned int int_crt_support:1;
1501        unsigned int lvds_use_ssc:1;
1502        unsigned int display_clock_mode:1;
1503        unsigned int fdi_rx_polarity_inverted:1;
1504        unsigned int panel_type:4;
1505        int lvds_ssc_freq;
1506        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1507
1508        enum drrs_support_type drrs_type;
1509
1510        struct {
1511                int rate;
1512                int lanes;
1513                int preemphasis;
1514                int vswing;
1515                bool low_vswing;
1516                bool initialized;
1517                bool support;
1518                int bpp;
1519                struct edp_power_seq pps;
1520        } edp;
1521
1522        struct {
1523                bool full_link;
1524                bool require_aux_wakeup;
1525                int idle_frames;
1526                enum psr_lines_to_wait lines_to_wait;
1527                int tp1_wakeup_time;
1528                int tp2_tp3_wakeup_time;
1529        } psr;
1530
1531        struct {
1532                u16 pwm_freq_hz;
1533                bool present;
1534                bool active_low_pwm;
1535                u8 min_brightness;      /* min_brightness/255 of max */
1536                enum intel_backlight_type type;
1537        } backlight;
1538
1539        /* MIPI DSI */
1540        struct {
1541                u16 panel_id;
1542                struct mipi_config *config;
1543                struct mipi_pps_data *pps;
1544                u8 seq_version;
1545                u32 size;
1546                u8 *data;
1547                const u8 *sequence[MIPI_SEQ_MAX];
1548        } dsi;
1549
1550        int crt_ddc_pin;
1551
1552        int child_dev_num;
1553        union child_device_config *child_dev;
1554
1555        struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1556        struct sdvo_device_mapping sdvo_mappings[2];
1557};
1558
1559enum intel_ddb_partitioning {
1560        INTEL_DDB_PART_1_2,
1561        INTEL_DDB_PART_5_6, /* IVB+ */
1562};
1563
1564struct intel_wm_level {
1565        bool enable;
1566        uint32_t pri_val;
1567        uint32_t spr_val;
1568        uint32_t cur_val;
1569        uint32_t fbc_val;
1570};
1571
1572struct ilk_wm_values {
1573        uint32_t wm_pipe[3];
1574        uint32_t wm_lp[3];
1575        uint32_t wm_lp_spr[3];
1576        uint32_t wm_linetime[3];
1577        bool enable_fbc_wm;
1578        enum intel_ddb_partitioning partitioning;
1579};
1580
1581struct vlv_pipe_wm {
1582        uint16_t primary;
1583        uint16_t sprite[2];
1584        uint8_t cursor;
1585};
1586
1587struct vlv_sr_wm {
1588        uint16_t plane;
1589        uint8_t cursor;
1590};
1591
1592struct vlv_wm_values {
1593        struct vlv_pipe_wm pipe[3];
1594        struct vlv_sr_wm sr;
1595        struct {
1596                uint8_t cursor;
1597                uint8_t sprite[2];
1598                uint8_t primary;
1599        } ddl[3];
1600        uint8_t level;
1601        bool cxsr;
1602};
1603
1604struct skl_ddb_entry {
1605        uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1606};
1607
1608static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1609{
1610        return entry->end - entry->start;
1611}
1612
1613static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1614                                       const struct skl_ddb_entry *e2)
1615{
1616        if (e1->start == e2->start && e1->end == e2->end)
1617                return true;
1618
1619        return false;
1620}
1621
1622struct skl_ddb_allocation {
1623        struct skl_ddb_entry pipe[I915_MAX_PIPES];
1624        struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1625        struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1626};
1627
1628struct skl_wm_values {
1629        unsigned dirty_pipes;
1630        struct skl_ddb_allocation ddb;
1631        uint32_t wm_linetime[I915_MAX_PIPES];
1632        uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1633        uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1634};
1635
1636struct skl_wm_level {
1637        bool plane_en[I915_MAX_PLANES];
1638        uint16_t plane_res_b[I915_MAX_PLANES];
1639        uint8_t plane_res_l[I915_MAX_PLANES];
1640};
1641
1642/*
1643 * This struct helps tracking the state needed for runtime PM, which puts the
1644 * device in PCI D3 state. Notice that when this happens, nothing on the
1645 * graphics device works, even register access, so we don't get interrupts nor
1646 * anything else.
1647 *
1648 * Every piece of our code that needs to actually touch the hardware needs to
1649 * either call intel_runtime_pm_get or call intel_display_power_get with the
1650 * appropriate power domain.
1651 *
1652 * Our driver uses the autosuspend delay feature, which means we'll only really
1653 * suspend if we stay with zero refcount for a certain amount of time. The
1654 * default value is currently very conservative (see intel_runtime_pm_enable), but
1655 * it can be changed with the standard runtime PM files from sysfs.
1656 *
1657 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1658 * goes back to false exactly before we reenable the IRQs. We use this variable
1659 * to check if someone is trying to enable/disable IRQs while they're supposed
1660 * to be disabled. This shouldn't happen and we'll print some error messages in
1661 * case it happens.
1662 *
1663 * For more, read the Documentation/power/runtime_pm.txt.
1664 */
1665struct i915_runtime_pm {
1666        atomic_t wakeref_count;
1667        atomic_t atomic_seq;
1668        bool suspended;
1669        bool irqs_enabled;
1670};
1671
1672enum intel_pipe_crc_source {
1673        INTEL_PIPE_CRC_SOURCE_NONE,
1674        INTEL_PIPE_CRC_SOURCE_PLANE1,
1675        INTEL_PIPE_CRC_SOURCE_PLANE2,
1676        INTEL_PIPE_CRC_SOURCE_PF,
1677        INTEL_PIPE_CRC_SOURCE_PIPE,
1678        /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1679        INTEL_PIPE_CRC_SOURCE_TV,
1680        INTEL_PIPE_CRC_SOURCE_DP_B,
1681        INTEL_PIPE_CRC_SOURCE_DP_C,
1682        INTEL_PIPE_CRC_SOURCE_DP_D,
1683        INTEL_PIPE_CRC_SOURCE_AUTO,
1684        INTEL_PIPE_CRC_SOURCE_MAX,
1685};
1686
1687struct intel_pipe_crc_entry {
1688        uint32_t frame;
1689        uint32_t crc[5];
1690};
1691
1692#define INTEL_PIPE_CRC_ENTRIES_NR       128
1693struct intel_pipe_crc {
1694        spinlock_t lock;
1695        bool opened;            /* exclusive access to the result file */
1696        struct intel_pipe_crc_entry *entries;
1697        enum intel_pipe_crc_source source;
1698        int head, tail;
1699        wait_queue_head_t wq;
1700};
1701
1702struct i915_frontbuffer_tracking {
1703        spinlock_t lock;
1704
1705        /*
1706         * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1707         * scheduled flips.
1708         */
1709        unsigned busy_bits;
1710        unsigned flip_bits;
1711};
1712
1713struct i915_wa_reg {
1714        i915_reg_t addr;
1715        u32 value;
1716        /* bitmask representing WA bits */
1717        u32 mask;
1718};
1719
1720/*
1721 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1722 * allowing it for RCS as we don't foresee any requirement of having
1723 * a whitelist for other engines. When it is really required for
1724 * other engines then the limit need to be increased.
1725 */
1726#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1727
1728struct i915_workarounds {
1729        struct i915_wa_reg reg[I915_MAX_WA_REGS];
1730        u32 count;
1731        u32 hw_whitelist_count[I915_NUM_ENGINES];
1732};
1733
1734struct i915_virtual_gpu {
1735        bool active;
1736};
1737
1738/* used in computing the new watermarks state */
1739struct intel_wm_config {
1740        unsigned int num_pipes_active;
1741        bool sprites_enabled;
1742        bool sprites_scaled;
1743};
1744
1745struct drm_i915_private {
1746        struct drm_device drm;
1747
1748        struct kmem_cache *objects;
1749        struct kmem_cache *vmas;
1750        struct kmem_cache *requests;
1751
1752        const struct intel_device_info info;
1753
1754        void __iomem *regs;
1755
1756        struct intel_uncore uncore;
1757
1758        struct i915_virtual_gpu vgpu;
1759
1760        struct intel_gvt gvt;
1761
1762        struct intel_guc guc;
1763
1764        struct intel_csr csr;
1765
1766        struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1767
1768        /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1769         * controller on different i2c buses. */
1770        struct mutex gmbus_mutex;
1771
1772        /**
1773         * Base address of the gmbus and gpio block.
1774         */
1775        uint32_t gpio_mmio_base;
1776
1777        /* MMIO base address for MIPI regs */
1778        uint32_t mipi_mmio_base;
1779
1780        uint32_t psr_mmio_base;
1781
1782        uint32_t pps_mmio_base;
1783
1784        wait_queue_head_t gmbus_wait_queue;
1785
1786        struct pci_dev *bridge_dev;
1787        struct i915_gem_context *kernel_context;
1788        struct intel_engine_cs engine[I915_NUM_ENGINES];
1789        struct i915_vma *semaphore;
1790        u32 next_seqno;
1791
1792        struct drm_dma_handle *status_page_dmah;
1793        struct resource mch_res;
1794
1795        /* protects the irq masks */
1796        spinlock_t irq_lock;
1797
1798        /* protects the mmio flip data */
1799        spinlock_t mmio_flip_lock;
1800
1801        bool display_irqs_enabled;
1802
1803        /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1804        struct pm_qos_request pm_qos;
1805
1806        /* Sideband mailbox protection */
1807        struct mutex sb_lock;
1808
1809        /** Cached value of IMR to avoid reads in updating the bitfield */
1810        union {
1811                u32 irq_mask;
1812                u32 de_irq_mask[I915_MAX_PIPES];
1813        };
1814        u32 gt_irq_mask;
1815        u32 pm_irq_mask;
1816        u32 pm_rps_events;
1817        u32 pipestat_irq_mask[I915_MAX_PIPES];
1818
1819        struct i915_hotplug hotplug;
1820        struct intel_fbc fbc;
1821        struct i915_drrs drrs;
1822        struct intel_opregion opregion;
1823        struct intel_vbt_data vbt;
1824
1825        bool preserve_bios_swizzle;
1826
1827        /* overlay */
1828        struct intel_overlay *overlay;
1829
1830        /* backlight registers and fields in struct intel_panel */
1831        struct mutex backlight_lock;
1832
1833        /* LVDS info */
1834        bool no_aux_handshake;
1835
1836        /* protects panel power sequencer state */
1837        struct mutex pps_mutex;
1838
1839        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1840        int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1841
1842        unsigned int fsb_freq, mem_freq, is_ddr3;
1843        unsigned int skl_preferred_vco_freq;
1844        unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1845        unsigned int max_dotclk_freq;
1846        unsigned int rawclk_freq;
1847        unsigned int hpll_freq;
1848        unsigned int czclk_freq;
1849
1850        struct {
1851                unsigned int vco, ref;
1852        } cdclk_pll;
1853
1854        /**
1855         * wq - Driver workqueue for GEM.
1856         *
1857         * NOTE: Work items scheduled here are not allowed to grab any modeset
1858         * locks, for otherwise the flushing done in the pageflip code will
1859         * result in deadlocks.
1860         */
1861        struct workqueue_struct *wq;
1862
1863        /* Display functions */
1864        struct drm_i915_display_funcs display;
1865
1866        /* PCH chipset type */
1867        enum intel_pch pch_type;
1868        unsigned short pch_id;
1869
1870        unsigned long quirks;
1871
1872        enum modeset_restore modeset_restore;
1873        struct mutex modeset_restore_lock;
1874        struct drm_atomic_state *modeset_restore_state;
1875        struct drm_modeset_acquire_ctx reset_ctx;
1876
1877        struct list_head vm_list; /* Global list of all address spaces */
1878        struct i915_ggtt ggtt; /* VM representing the global address space */
1879
1880        struct i915_gem_mm mm;
1881        DECLARE_HASHTABLE(mm_structs, 7);
1882        struct mutex mm_lock;
1883
1884        /* The hw wants to have a stable context identifier for the lifetime
1885         * of the context (for OA, PASID, faults, etc). This is limited
1886         * in execlists to 21 bits.
1887         */
1888        struct ida context_hw_ida;
1889#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1890
1891        /* Kernel Modesetting */
1892
1893        struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1894        struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1895        wait_queue_head_t pending_flip_queue;
1896
1897#ifdef CONFIG_DEBUG_FS
1898        struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1899#endif
1900
1901        /* dpll and cdclk state is protected by connection_mutex */
1902        int num_shared_dpll;
1903        struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1904        const struct intel_dpll_mgr *dpll_mgr;
1905
1906        /*
1907         * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1908         * Must be global rather than per dpll, because on some platforms
1909         * plls share registers.
1910         */
1911        struct mutex dpll_lock;
1912
1913        unsigned int active_crtcs;
1914        unsigned int min_pixclk[I915_MAX_PIPES];
1915
1916        int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1917
1918        struct i915_workarounds workarounds;
1919
1920        struct i915_frontbuffer_tracking fb_tracking;
1921
1922        u16 orig_clock;
1923
1924        bool mchbar_need_disable;
1925
1926        struct intel_l3_parity l3_parity;
1927
1928        /* Cannot be determined by PCIID. You must always read a register. */
1929        u32 edram_cap;
1930
1931        /* gen6+ rps state */
1932        struct intel_gen6_power_mgmt rps;
1933
1934        /* ilk-only ips/rps state. Everything in here is protected by the global
1935         * mchdev_lock in intel_pm.c */
1936        struct intel_ilk_power_mgmt ips;
1937
1938        struct i915_power_domains power_domains;
1939
1940        struct i915_psr psr;
1941
1942        struct i915_gpu_error gpu_error;
1943
1944        struct drm_i915_gem_object *vlv_pctx;
1945
1946#ifdef CONFIG_DRM_FBDEV_EMULATION
1947        /* list of fbdev register on this device */
1948        struct intel_fbdev *fbdev;
1949        struct work_struct fbdev_suspend_work;
1950#endif
1951
1952        struct drm_property *broadcast_rgb_property;
1953        struct drm_property *force_audio_property;
1954
1955        /* hda/i915 audio component */
1956        struct i915_audio_component *audio_component;
1957        bool audio_component_registered;
1958        /**
1959         * av_mutex - mutex for audio/video sync
1960         *
1961         */
1962        struct mutex av_mutex;
1963
1964        uint32_t hw_context_size;
1965        struct list_head context_list;
1966
1967        u32 fdi_rx_config;
1968
1969        /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1970        u32 chv_phy_control;
1971        /*
1972         * Shadows for CHV DPLL_MD regs to keep the state
1973         * checker somewhat working in the presence hardware
1974         * crappiness (can't read out DPLL_MD for pipes B & C).
1975         */
1976        u32 chv_dpll_md[I915_MAX_PIPES];
1977        u32 bxt_phy_grc;
1978
1979        u32 suspend_count;
1980        bool suspended_to_idle;
1981        struct i915_suspend_saved_registers regfile;
1982        struct vlv_s0ix_state vlv_s0ix_state;
1983
1984        enum {
1985                I915_SAGV_UNKNOWN = 0,
1986                I915_SAGV_DISABLED,
1987                I915_SAGV_ENABLED,
1988                I915_SAGV_NOT_CONTROLLED
1989        } sagv_status;
1990
1991        struct {
1992                /*
1993                 * Raw watermark latency values:
1994                 * in 0.1us units for WM0,
1995                 * in 0.5us units for WM1+.
1996                 */
1997                /* primary */
1998                uint16_t pri_latency[5];
1999                /* sprite */
2000                uint16_t spr_latency[5];
2001                /* cursor */
2002                uint16_t cur_latency[5];
2003                /*
2004                 * Raw watermark memory latency values
2005                 * for SKL for all 8 levels
2006                 * in 1us units.
2007                 */
2008                uint16_t skl_latency[8];
2009
2010                /*
2011                 * The skl_wm_values structure is a bit too big for stack
2012                 * allocation, so we keep the staging struct where we store
2013                 * intermediate results here instead.
2014                 */
2015                struct skl_wm_values skl_results;
2016
2017                /* current hardware state */
2018                union {
2019                        struct ilk_wm_values hw;
2020                        struct skl_wm_values skl_hw;
2021                        struct vlv_wm_values vlv;
2022                };
2023
2024                uint8_t max_level;
2025
2026                /*
2027                 * Should be held around atomic WM register writing; also
2028                 * protects * intel_crtc->wm.active and
2029                 * cstate->wm.need_postvbl_update.
2030                 */
2031                struct mutex wm_mutex;
2032
2033                /*
2034                 * Set during HW readout of watermarks/DDB.  Some platforms
2035                 * need to know when we're still using BIOS-provided values
2036                 * (which we don't fully trust).
2037                 */
2038                bool distrust_bios_wm;
2039        } wm;
2040
2041        struct i915_runtime_pm pm;
2042
2043        /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2044        struct {
2045                void (*resume)(struct drm_i915_private *);
2046                void (*cleanup_engine)(struct intel_engine_cs *engine);
2047
2048                /**
2049                 * Is the GPU currently considered idle, or busy executing
2050                 * userspace requests? Whilst idle, we allow runtime power
2051                 * management to power down the hardware and display clocks.
2052                 * In order to reduce the effect on performance, there
2053                 * is a slight delay before we do so.
2054                 */
2055                unsigned int active_engines;
2056                bool awake;
2057
2058                /**
2059                 * We leave the user IRQ off as much as possible,
2060                 * but this means that requests will finish and never
2061                 * be retired once the system goes idle. Set a timer to
2062                 * fire periodically while the ring is running. When it
2063                 * fires, go retire requests.
2064                 */
2065                struct delayed_work retire_work;
2066
2067                /**
2068                 * When we detect an idle GPU, we want to turn on
2069                 * powersaving features. So once we see that there
2070                 * are no more requests outstanding and no more
2071                 * arrive within a small period of time, we fire
2072                 * off the idle_work.
2073                 */
2074                struct delayed_work idle_work;
2075        } gt;
2076
2077        /* perform PHY state sanity checks? */
2078        bool chv_phy_assert[2];
2079
2080        struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2081
2082        /*
2083         * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2084         * will be rejected. Instead look for a better place.
2085         */
2086};
2087
2088static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2089{
2090        return container_of(dev, struct drm_i915_private, drm);
2091}
2092
2093static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2094{
2095        return to_i915(dev_get_drvdata(kdev));
2096}
2097
2098static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2099{
2100        return container_of(guc, struct drm_i915_private, guc);
2101}
2102
2103/* Simple iterator over all initialised engines */
2104#define for_each_engine(engine__, dev_priv__) \
2105        for ((engine__) = &(dev_priv__)->engine[0]; \
2106             (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2107             (engine__)++) \
2108                for_each_if (intel_engine_initialized(engine__))
2109
2110/* Iterator with engine_id */
2111#define for_each_engine_id(engine__, dev_priv__, id__) \
2112        for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2113             (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2114             (engine__)++) \
2115                for_each_if (((id__) = (engine__)->id, \
2116                              intel_engine_initialized(engine__)))
2117
2118#define __mask_next_bit(mask) ({                                        \
2119        int __idx = ffs(mask) - 1;                                      \
2120        mask &= ~BIT(__idx);                                            \
2121        __idx;                                                          \
2122})
2123
2124/* Iterator over subset of engines selected by mask */
2125#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2126        for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;        \
2127             tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2128
2129enum hdmi_force_audio {
2130        HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2131        HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2132        HDMI_AUDIO_AUTO,                /* trust EDID */
2133        HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2134};
2135
2136#define I915_GTT_OFFSET_NONE ((u32)-1)
2137
2138struct drm_i915_gem_object_ops {
2139        unsigned int flags;
2140#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2141
2142        /* Interface between the GEM object and its backing storage.
2143         * get_pages() is called once prior to the use of the associated set
2144         * of pages before to binding them into the GTT, and put_pages() is
2145         * called after we no longer need them. As we expect there to be
2146         * associated cost with migrating pages between the backing storage
2147         * and making them available for the GPU (e.g. clflush), we may hold
2148         * onto the pages after they are no longer referenced by the GPU
2149         * in case they may be used again shortly (for example migrating the
2150         * pages to a different memory domain within the GTT). put_pages()
2151         * will therefore most likely be called when the object itself is
2152         * being released or under memory pressure (where we attempt to
2153         * reap pages for the shrinker).
2154         */
2155        int (*get_pages)(struct drm_i915_gem_object *);
2156        void (*put_pages)(struct drm_i915_gem_object *);
2157
2158        int (*dmabuf_export)(struct drm_i915_gem_object *);
2159        void (*release)(struct drm_i915_gem_object *);
2160};
2161
2162/*
2163 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2164 * considered to be the frontbuffer for the given plane interface-wise. This
2165 * doesn't mean that the hw necessarily already scans it out, but that any
2166 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2167 *
2168 * We have one bit per pipe and per scanout plane type.
2169 */
2170#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2171#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2172#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2173        (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2174#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2175        (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2176#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2177        (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2178#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2179        (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2180#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2181        (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2182
2183struct drm_i915_gem_object {
2184        struct drm_gem_object base;
2185
2186        const struct drm_i915_gem_object_ops *ops;
2187
2188        /** List of VMAs backed by this object */
2189        struct list_head vma_list;
2190
2191        /** Stolen memory for this object, instead of being backed by shmem. */
2192        struct drm_mm_node *stolen;
2193        struct list_head global_list;
2194
2195        /** Used in execbuf to temporarily hold a ref */
2196        struct list_head obj_exec_link;
2197
2198        struct list_head batch_pool_link;
2199
2200        unsigned long flags;
2201        /**
2202         * This is set if the object is on the active lists (has pending
2203         * rendering and so a non-zero seqno), and is not set if it i s on
2204         * inactive (ready to be unbound) list.
2205         */
2206#define I915_BO_ACTIVE_SHIFT 0
2207#define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2208#define __I915_BO_ACTIVE(bo) \
2209        ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2210
2211        /**
2212         * This is set if the object has been written to since last bound
2213         * to the GTT
2214         */
2215        unsigned int dirty:1;
2216
2217        /**
2218         * Advice: are the backing pages purgeable?
2219         */
2220        unsigned int madv:2;
2221
2222        /**
2223         * Whether the current gtt mapping needs to be mappable (and isn't just
2224         * mappable by accident). Track pin and fault separate for a more
2225         * accurate mappable working set.
2226         */
2227        unsigned int fault_mappable:1;
2228
2229        /*
2230         * Is the object to be mapped as read-only to the GPU
2231         * Only honoured if hardware has relevant pte bit
2232         */
2233        unsigned long gt_ro:1;
2234        unsigned int cache_level:3;
2235        unsigned int cache_dirty:1;
2236
2237        atomic_t frontbuffer_bits;
2238        unsigned int frontbuffer_ggtt_origin; /* write once */
2239
2240        /** Current tiling stride for the object, if it's tiled. */
2241        unsigned int tiling_and_stride;
2242#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2243#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2244#define STRIDE_MASK (~TILING_MASK)
2245
2246        /** Count of VMA actually bound by this object */
2247        unsigned int bind_count;
2248        unsigned int pin_display;
2249
2250        struct sg_table *pages;
2251        int pages_pin_count;
2252        struct get_page {
2253                struct scatterlist *sg;
2254                int last;
2255        } get_page;
2256        void *mapping;
2257
2258        /** Breadcrumb of last rendering to the buffer.
2259         * There can only be one writer, but we allow for multiple readers.
2260         * If there is a writer that necessarily implies that all other
2261         * read requests are complete - but we may only be lazily clearing
2262         * the read requests. A read request is naturally the most recent
2263         * request on a ring, so we may have two different write and read
2264         * requests on one ring where the write request is older than the
2265         * read request. This allows for the CPU to read from an active
2266         * buffer by only waiting for the write to complete.
2267         */
2268        struct i915_gem_active last_read[I915_NUM_ENGINES];
2269        struct i915_gem_active last_write;
2270
2271        /** References from framebuffers, locks out tiling changes. */
2272        unsigned long framebuffer_references;
2273
2274        /** Record of address bit 17 of each page at last unbind. */
2275        unsigned long *bit_17;
2276
2277        struct i915_gem_userptr {
2278                uintptr_t ptr;
2279                unsigned read_only :1;
2280                unsigned workers :4;
2281#define I915_GEM_USERPTR_MAX_WORKERS 15
2282
2283                struct i915_mm_struct *mm;
2284                struct i915_mmu_object *mmu_object;
2285                struct work_struct *work;
2286        } userptr;
2287
2288        /** for phys allocated objects */
2289        struct drm_dma_handle *phys_handle;
2290};
2291
2292static inline struct drm_i915_gem_object *
2293to_intel_bo(struct drm_gem_object *gem)
2294{
2295        /* Assert that to_intel_bo(NULL) == NULL */
2296        BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2297
2298        return container_of(gem, struct drm_i915_gem_object, base);
2299}
2300
2301static inline struct drm_i915_gem_object *
2302i915_gem_object_lookup(struct drm_file *file, u32 handle)
2303{
2304        return to_intel_bo(drm_gem_object_lookup(file, handle));
2305}
2306
2307__deprecated
2308extern struct drm_gem_object *
2309drm_gem_object_lookup(struct drm_file *file, u32 handle);
2310
2311__attribute__((nonnull))
2312static inline struct drm_i915_gem_object *
2313i915_gem_object_get(struct drm_i915_gem_object *obj)
2314{
2315        drm_gem_object_reference(&obj->base);
2316        return obj;
2317}
2318
2319__deprecated
2320extern void drm_gem_object_reference(struct drm_gem_object *);
2321
2322__attribute__((nonnull))
2323static inline void
2324i915_gem_object_put(struct drm_i915_gem_object *obj)
2325{
2326        drm_gem_object_unreference(&obj->base);
2327}
2328
2329__deprecated
2330extern void drm_gem_object_unreference(struct drm_gem_object *);
2331
2332__attribute__((nonnull))
2333static inline void
2334i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2335{
2336        drm_gem_object_unreference_unlocked(&obj->base);
2337}
2338
2339__deprecated
2340extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2341
2342static inline bool
2343i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2344{
2345        return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2346}
2347
2348static inline unsigned long
2349i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2350{
2351        return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2352}
2353
2354static inline bool
2355i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2356{
2357        return i915_gem_object_get_active(obj);
2358}
2359
2360static inline void
2361i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2362{
2363        obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2364}
2365
2366static inline void
2367i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2368{
2369        obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2370}
2371
2372static inline bool
2373i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2374                                  int engine)
2375{
2376        return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2377}
2378
2379static inline unsigned int
2380i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2381{
2382        return obj->tiling_and_stride & TILING_MASK;
2383}
2384
2385static inline bool
2386i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2387{
2388        return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2389}
2390
2391static inline unsigned int
2392i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2393{
2394        return obj->tiling_and_stride & STRIDE_MASK;
2395}
2396
2397static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
2398{
2399        i915_gem_object_get(vma->obj);
2400        return vma;
2401}
2402
2403static inline void i915_vma_put(struct i915_vma *vma)
2404{
2405        lockdep_assert_held(&vma->vm->dev->struct_mutex);
2406        i915_gem_object_put(vma->obj);
2407}
2408
2409/*
2410 * Optimised SGL iterator for GEM objects
2411 */
2412static __always_inline struct sgt_iter {
2413        struct scatterlist *sgp;
2414        union {
2415                unsigned long pfn;
2416                dma_addr_t dma;
2417        };
2418        unsigned int curr;
2419        unsigned int max;
2420} __sgt_iter(struct scatterlist *sgl, bool dma) {
2421        struct sgt_iter s = { .sgp = sgl };
2422
2423        if (s.sgp) {
2424                s.max = s.curr = s.sgp->offset;
2425                s.max += s.sgp->length;
2426                if (dma)
2427                        s.dma = sg_dma_address(s.sgp);
2428                else
2429                        s.pfn = page_to_pfn(sg_page(s.sgp));
2430        }
2431
2432        return s;
2433}
2434
2435/**
2436 * __sg_next - return the next scatterlist entry in a list
2437 * @sg:         The current sg entry
2438 *
2439 * Description:
2440 *   If the entry is the last, return NULL; otherwise, step to the next
2441 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2442 *   otherwise just return the pointer to the current element.
2443 **/
2444static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2445{
2446#ifdef CONFIG_DEBUG_SG
2447        BUG_ON(sg->sg_magic != SG_MAGIC);
2448#endif
2449        return sg_is_last(sg) ? NULL :
2450                likely(!sg_is_chain(++sg)) ? sg :
2451                sg_chain_ptr(sg);
2452}
2453
2454/**
2455 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2456 * @__dmap:     DMA address (output)
2457 * @__iter:     'struct sgt_iter' (iterator state, internal)
2458 * @__sgt:      sg_table to iterate over (input)
2459 */
2460#define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2461        for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2462             ((__dmap) = (__iter).dma + (__iter).curr);                 \
2463             (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2464             ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2465
2466/**
2467 * for_each_sgt_page - iterate over the pages of the given sg_table
2468 * @__pp:       page pointer (output)
2469 * @__iter:     'struct sgt_iter' (iterator state, internal)
2470 * @__sgt:      sg_table to iterate over (input)
2471 */
2472#define for_each_sgt_page(__pp, __iter, __sgt)                          \
2473        for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2474             ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2475              pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2476             (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2477             ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2478
2479/*
2480 * A command that requires special handling by the command parser.
2481 */
2482struct drm_i915_cmd_descriptor {
2483        /*
2484         * Flags describing how the command parser processes the command.
2485         *
2486         * CMD_DESC_FIXED: The command has a fixed length if this is set,
2487         *                 a length mask if not set
2488         * CMD_DESC_SKIP: The command is allowed but does not follow the
2489         *                standard length encoding for the opcode range in
2490         *                which it falls
2491         * CMD_DESC_REJECT: The command is never allowed
2492         * CMD_DESC_REGISTER: The command should be checked against the
2493         *                    register whitelist for the appropriate ring
2494         * CMD_DESC_MASTER: The command is allowed if the submitting process
2495         *                  is the DRM master
2496         */
2497        u32 flags;
2498#define CMD_DESC_FIXED    (1<<0)
2499#define CMD_DESC_SKIP     (1<<1)
2500#define CMD_DESC_REJECT   (1<<2)
2501#define CMD_DESC_REGISTER (1<<3)
2502#define CMD_DESC_BITMASK  (1<<4)
2503#define CMD_DESC_MASTER   (1<<5)
2504
2505        /*
2506         * The command's unique identification bits and the bitmask to get them.
2507         * This isn't strictly the opcode field as defined in the spec and may
2508         * also include type, subtype, and/or subop fields.
2509         */
2510        struct {
2511                u32 value;
2512                u32 mask;
2513        } cmd;
2514
2515        /*
2516         * The command's length. The command is either fixed length (i.e. does
2517         * not include a length field) or has a length field mask. The flag
2518         * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2519         * a length mask. All command entries in a command table must include
2520         * length information.
2521         */
2522        union {
2523                u32 fixed;
2524                u32 mask;
2525        } length;
2526
2527        /*
2528         * Describes where to find a register address in the command to check
2529         * against the ring's register whitelist. Only valid if flags has the
2530         * CMD_DESC_REGISTER bit set.
2531         *
2532         * A non-zero step value implies that the command may access multiple
2533         * registers in sequence (e.g. LRI), in that case step gives the
2534         * distance in dwords between individual offset fields.
2535         */
2536        struct {
2537                u32 offset;
2538                u32 mask;
2539                u32 step;
2540        } reg;
2541
2542#define MAX_CMD_DESC_BITMASKS 3
2543        /*
2544         * Describes command checks where a particular dword is masked and
2545         * compared against an expected value. If the command does not match
2546         * the expected value, the parser rejects it. Only valid if flags has
2547         * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2548         * are valid.
2549         *
2550         * If the check specifies a non-zero condition_mask then the parser
2551         * only performs the check when the bits specified by condition_mask
2552         * are non-zero.
2553         */
2554        struct {
2555                u32 offset;
2556                u32 mask;
2557                u32 expected;
2558                u32 condition_offset;
2559                u32 condition_mask;
2560        } bits[MAX_CMD_DESC_BITMASKS];
2561};
2562
2563/*
2564 * A table of commands requiring special handling by the command parser.
2565 *
2566 * Each engine has an array of tables. Each table consists of an array of
2567 * command descriptors, which must be sorted with command opcodes in
2568 * ascending order.
2569 */
2570struct drm_i915_cmd_table {
2571        const struct drm_i915_cmd_descriptor *table;
2572        int count;
2573};
2574
2575/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2576#define __I915__(p) ({ \
2577        struct drm_i915_private *__p; \
2578        if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2579                __p = (struct drm_i915_private *)p; \
2580        else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2581                __p = to_i915((struct drm_device *)p); \
2582        else \
2583                BUILD_BUG(); \
2584        __p; \
2585})
2586#define INTEL_INFO(p)   (&__I915__(p)->info)
2587#define INTEL_GEN(p)    (INTEL_INFO(p)->gen)
2588#define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
2589
2590#define REVID_FOREVER           0xff
2591#define INTEL_REVID(p)  (__I915__(p)->drm.pdev->revision)
2592
2593#define GEN_FOREVER (0)
2594/*
2595 * Returns true if Gen is in inclusive range [Start, End].
2596 *
2597 * Use GEN_FOREVER for unbound start and or end.
2598 */
2599#define IS_GEN(p, s, e) ({ \
2600        unsigned int __s = (s), __e = (e); \
2601        BUILD_BUG_ON(!__builtin_constant_p(s)); \
2602        BUILD_BUG_ON(!__builtin_constant_p(e)); \
2603        if ((__s) != GEN_FOREVER) \
2604                __s = (s) - 1; \
2605        if ((__e) == GEN_FOREVER) \
2606                __e = BITS_PER_LONG - 1; \
2607        else \
2608                __e = (e) - 1; \
2609        !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2610})
2611
2612/*
2613 * Return true if revision is in range [since,until] inclusive.
2614 *
2615 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2616 */
2617#define IS_REVID(p, since, until) \
2618        (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2619
2620#define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
2621#define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
2622#define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
2623#define IS_I865G(dev)           (INTEL_DEVID(dev) == 0x2572)
2624#define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
2625#define IS_I915GM(dev)          (INTEL_DEVID(dev) == 0x2592)
2626#define IS_I945G(dev)           (INTEL_DEVID(dev) == 0x2772)
2627#define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
2628#define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
2629#define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
2630#define IS_GM45(dev)            (INTEL_DEVID(dev) == 0x2A42)
2631#define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
2632#define IS_PINEVIEW_G(dev)      (INTEL_DEVID(dev) == 0xa001)
2633#define IS_PINEVIEW_M(dev)      (INTEL_DEVID(dev) == 0xa011)
2634#define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
2635#define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
2636#define IS_IRONLAKE_M(dev)      (INTEL_DEVID(dev) == 0x0046)
2637#define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
2638#define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
2639                                 INTEL_DEVID(dev) == 0x0152 || \
2640                                 INTEL_DEVID(dev) == 0x015a)
2641#define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
2642#define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_cherryview)
2643#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2644#define IS_BROADWELL(dev)       (INTEL_INFO(dev)->is_broadwell)
2645#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2646#define IS_BROXTON(dev)         (INTEL_INFO(dev)->is_broxton)
2647#define IS_KABYLAKE(dev)        (INTEL_INFO(dev)->is_kabylake)
2648#define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
2649#define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
2650                                 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2651#define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
2652                                 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||    \
2653                                 (INTEL_DEVID(dev) & 0xf) == 0xb ||     \
2654                                 (INTEL_DEVID(dev) & 0xf) == 0xe))
2655/* ULX machines are also considered ULT. */
2656#define IS_BDW_ULX(dev)         (IS_BROADWELL(dev) && \
2657                                 (INTEL_DEVID(dev) & 0xf) == 0xe)
2658#define IS_BDW_GT3(dev)         (IS_BROADWELL(dev) && \
2659                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2660#define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
2661                                 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2662#define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
2663                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2664/* ULX machines are also considered ULT. */
2665#define IS_HSW_ULX(dev)         (INTEL_DEVID(dev) == 0x0A0E || \
2666                                 INTEL_DEVID(dev) == 0x0A1E)
2667#define IS_SKL_ULT(dev)         (INTEL_DEVID(dev) == 0x1906 || \
2668                                 INTEL_DEVID(dev) == 0x1913 || \
2669                                 INTEL_DEVID(dev) == 0x1916 || \
2670                                 INTEL_DEVID(dev) == 0x1921 || \
2671                                 INTEL_DEVID(dev) == 0x1926)
2672#define IS_SKL_ULX(dev)         (INTEL_DEVID(dev) == 0x190E || \
2673                                 INTEL_DEVID(dev) == 0x1915 || \
2674                                 INTEL_DEVID(dev) == 0x191E)
2675#define IS_KBL_ULT(dev)         (INTEL_DEVID(dev) == 0x5906 || \
2676                                 INTEL_DEVID(dev) == 0x5913 || \
2677                                 INTEL_DEVID(dev) == 0x5916 || \
2678                                 INTEL_DEVID(dev) == 0x5921 || \
2679                                 INTEL_DEVID(dev) == 0x5926)
2680#define IS_KBL_ULX(dev)         (INTEL_DEVID(dev) == 0x590E || \
2681                                 INTEL_DEVID(dev) == 0x5915 || \
2682                                 INTEL_DEVID(dev) == 0x591E)
2683#define IS_SKL_GT3(dev)         (IS_SKYLAKE(dev) && \
2684                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2685#define IS_SKL_GT4(dev)         (IS_SKYLAKE(dev) && \
2686                                 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2687
2688#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2689
2690#define SKL_REVID_A0            0x0
2691#define SKL_REVID_B0            0x1
2692#define SKL_REVID_C0            0x2
2693#define SKL_REVID_D0            0x3
2694#define SKL_REVID_E0            0x4
2695#define SKL_REVID_F0            0x5
2696#define SKL_REVID_G0            0x6
2697#define SKL_REVID_H0            0x7
2698
2699#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2700
2701#define BXT_REVID_A0            0x0
2702#define BXT_REVID_A1            0x1
2703#define BXT_REVID_B0            0x3
2704#define BXT_REVID_C0            0x9
2705
2706#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2707
2708#define KBL_REVID_A0            0x0
2709#define KBL_REVID_B0            0x1
2710#define KBL_REVID_C0            0x2
2711#define KBL_REVID_D0            0x3
2712#define KBL_REVID_E0            0x4
2713
2714#define IS_KBL_REVID(p, since, until) \
2715        (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2716
2717/*
2718 * The genX designation typically refers to the render engine, so render
2719 * capability related checks should use IS_GEN, while display and other checks
2720 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2721 * chips, etc.).
2722 */
2723#define IS_GEN2(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2724#define IS_GEN3(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2725#define IS_GEN4(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2726#define IS_GEN5(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2727#define IS_GEN6(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2728#define IS_GEN7(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2729#define IS_GEN8(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2730#define IS_GEN9(dev)    (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2731
2732#define ENGINE_MASK(id) BIT(id)
2733#define RENDER_RING     ENGINE_MASK(RCS)
2734#define BSD_RING        ENGINE_MASK(VCS)
2735#define BLT_RING        ENGINE_MASK(BCS)
2736#define VEBOX_RING      ENGINE_MASK(VECS)
2737#define BSD2_RING       ENGINE_MASK(VCS2)
2738#define ALL_ENGINES     (~0)
2739
2740#define HAS_ENGINE(dev_priv, id) \
2741        (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2742
2743#define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2744#define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2745#define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2746#define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2747
2748#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
2749#define HAS_SNOOP(dev)          (INTEL_INFO(dev)->has_snoop)
2750#define HAS_EDRAM(dev)          (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2751#define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2752                                 HAS_EDRAM(dev))
2753#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2754
2755#define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->has_hw_contexts)
2756#define HAS_LOGICAL_RING_CONTEXTS(dev)  (INTEL_INFO(dev)->has_logical_ring_contexts)
2757#define USES_PPGTT(dev)         (i915.enable_ppgtt)
2758#define USES_FULL_PPGTT(dev)    (i915.enable_ppgtt >= 2)
2759#define USES_FULL_48BIT_PPGTT(dev)      (i915.enable_ppgtt == 3)
2760
2761#define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
2762#define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
2763
2764/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2765#define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
2766
2767/* WaRsDisableCoarsePowerGating:skl,bxt */
2768#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2769        (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2770         IS_SKL_GT3(dev_priv) || \
2771         IS_SKL_GT4(dev_priv))
2772
2773/*
2774 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2775 * even when in MSI mode. This results in spurious interrupt warnings if the
2776 * legacy irq no. is shared with another device. The kernel then disables that
2777 * interrupt source and so prevents the other device from working properly.
2778 */
2779#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2780#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2781
2782/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2783 * rows, which changed the alignment requirements and fence programming.
2784 */
2785#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2786                                                      IS_I915GM(dev)))
2787#define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
2788#define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
2789
2790#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2791#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2792#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2793
2794#define HAS_IPS(dev)            (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2795
2796#define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
2797
2798#define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
2799#define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
2800#define HAS_PSR(dev)            (INTEL_INFO(dev)->has_psr)
2801#define HAS_RUNTIME_PM(dev)     (INTEL_INFO(dev)->has_runtime_pm)
2802#define HAS_RC6(dev)            (INTEL_INFO(dev)->has_rc6)
2803#define HAS_RC6p(dev)           (INTEL_INFO(dev)->has_rc6p)
2804
2805#define HAS_CSR(dev)    (INTEL_INFO(dev)->has_csr)
2806
2807/*
2808 * For now, anything with a GuC requires uCode loading, and then supports
2809 * command submission once loaded. But these are logically independent
2810 * properties, so we have separate macros to test them.
2811 */
2812#define HAS_GUC(dev)            (INTEL_INFO(dev)->has_guc)
2813#define HAS_GUC_UCODE(dev)      (HAS_GUC(dev))
2814#define HAS_GUC_SCHED(dev)      (HAS_GUC(dev))
2815
2816#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2817
2818#define HAS_POOLED_EU(dev)      (INTEL_INFO(dev)->has_pooled_eu)
2819
2820#define INTEL_PCH_DEVICE_ID_MASK                0xff00
2821#define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2822#define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2823#define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2824#define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2825#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2826#define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2827#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2828#define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA200
2829#define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2830#define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2831#define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2832
2833#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2834#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2835#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2836#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2837#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2838#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2839#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2840#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2841#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2842#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2843
2844#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
2845
2846/* DPF == dynamic parity feature */
2847#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
2848#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2849
2850#define GT_FREQUENCY_MULTIPLIER 50
2851#define GEN9_FREQ_SCALER 3
2852
2853#include "i915_trace.h"
2854
2855static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2856{
2857#ifdef CONFIG_INTEL_IOMMU
2858        if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2859                return true;
2860#endif
2861        return false;
2862}
2863
2864extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2865extern int i915_resume_switcheroo(struct drm_device *dev);
2866
2867int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2868                                int enable_ppgtt);
2869
2870bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2871
2872/* i915_drv.c */
2873void __printf(3, 4)
2874__i915_printk(struct drm_i915_private *dev_priv, const char *level,
2875              const char *fmt, ...);
2876
2877#define i915_report_error(dev_priv, fmt, ...)                              \
2878        __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2879
2880#ifdef CONFIG_COMPAT
2881extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2882                              unsigned long arg);
2883#endif
2884extern const struct dev_pm_ops i915_pm_ops;
2885
2886extern int i915_driver_load(struct pci_dev *pdev,
2887                            const struct pci_device_id *ent);
2888extern void i915_driver_unload(struct drm_device *dev);
2889extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2890extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2891extern void i915_reset(struct drm_i915_private *dev_priv);
2892extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2893extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2894extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2895extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2896extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2897extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2898int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2899
2900/* intel_hotplug.c */
2901void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2902                           u32 pin_mask, u32 long_mask);
2903void intel_hpd_init(struct drm_i915_private *dev_priv);
2904void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2905void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2906bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2907bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2908void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2909
2910/* i915_irq.c */
2911static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2912{
2913        unsigned long delay;
2914
2915        if (unlikely(!i915.enable_hangcheck))
2916                return;
2917
2918        /* Don't continually defer the hangcheck so that it is always run at
2919         * least once after work has been scheduled on any ring. Otherwise,
2920         * we will ignore a hung ring if a second ring is kept busy.
2921         */
2922
2923        delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2924        queue_delayed_work(system_long_wq,
2925                           &dev_priv->gpu_error.hangcheck_work, delay);
2926}
2927
2928__printf(3, 4)
2929void i915_handle_error(struct drm_i915_private *dev_priv,
2930                       u32 engine_mask,
2931                       const char *fmt, ...);
2932
2933extern void intel_irq_init(struct drm_i915_private *dev_priv);
2934int intel_irq_install(struct drm_i915_private *dev_priv);
2935void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2936
2937extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2938extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2939                                        bool restore_forcewake);
2940extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2941extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2942extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2943extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2944extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2945                                         bool restore);
2946const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2947void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2948                                enum forcewake_domains domains);
2949void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2950                                enum forcewake_domains domains);
2951/* Like above but the caller must manage the uncore.lock itself.
2952 * Must be used with I915_READ_FW and friends.
2953 */
2954void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2955                                        enum forcewake_domains domains);
2956void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2957                                        enum forcewake_domains domains);
2958u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2959
2960void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2961
2962int intel_wait_for_register(struct drm_i915_private *dev_priv,
2963                            i915_reg_t reg,
2964                            const u32 mask,
2965                            const u32 value,
2966                            const unsigned long timeout_ms);
2967int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2968                               i915_reg_t reg,
2969                               const u32 mask,
2970                               const u32 value,
2971                               const unsigned long timeout_ms);
2972
2973static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2974{
2975        return dev_priv->gvt.initialized;
2976}
2977
2978static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2979{
2980        return dev_priv->vgpu.active;
2981}
2982
2983void
2984i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2985                     u32 status_mask);
2986
2987void
2988i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2989                      u32 status_mask);
2990
2991void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2992void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2993void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2994                                   uint32_t mask,
2995                                   uint32_t bits);
2996void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2997                            uint32_t interrupt_mask,
2998                            uint32_t enabled_irq_mask);
2999static inline void
3000ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3001{
3002        ilk_update_display_irq(dev_priv, bits, bits);
3003}
3004static inline void
3005ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3006{
3007        ilk_update_display_irq(dev_priv, bits, 0);
3008}
3009void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3010                         enum pipe pipe,
3011                         uint32_t interrupt_mask,
3012                         uint32_t enabled_irq_mask);
3013static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3014                                       enum pipe pipe, uint32_t bits)
3015{
3016        bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3017}
3018static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3019                                        enum pipe pipe, uint32_t bits)
3020{
3021        bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3022}
3023void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3024                                  uint32_t interrupt_mask,
3025                                  uint32_t enabled_irq_mask);
3026static inline void
3027ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3028{
3029        ibx_display_interrupt_update(dev_priv, bits, bits);
3030}
3031static inline void
3032ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3033{
3034        ibx_display_interrupt_update(dev_priv, bits, 0);
3035}
3036
3037/* i915_gem.c */
3038int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3039                          struct drm_file *file_priv);
3040int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3041                         struct drm_file *file_priv);
3042int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3043                          struct drm_file *file_priv);
3044int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3045                        struct drm_file *file_priv);
3046int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3047                        struct drm_file *file_priv);
3048int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3049                              struct drm_file *file_priv);
3050int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3051                             struct drm_file *file_priv);
3052int i915_gem_execbuffer(struct drm_device *dev, void *data,
3053                        struct drm_file *file_priv);
3054int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3055                         struct drm_file *file_priv);
3056int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3057                        struct drm_file *file_priv);
3058int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3059                               struct drm_file *file);
3060int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3061                               struct drm_file *file);
3062int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3063                            struct drm_file *file_priv);
3064int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3065                           struct drm_file *file_priv);
3066int i915_gem_set_tiling(struct drm_device *dev, void *data,
3067                        struct drm_file *file_priv);
3068int i915_gem_get_tiling(struct drm_device *dev, void *data,
3069                        struct drm_file *file_priv);
3070void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3071int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3072                           struct drm_file *file);
3073int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3074                                struct drm_file *file_priv);
3075int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3076                        struct drm_file *file_priv);
3077void i915_gem_load_init(struct drm_device *dev);
3078void i915_gem_load_cleanup(struct drm_device *dev);
3079void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3080int i915_gem_freeze(struct drm_i915_private *dev_priv);
3081int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3082
3083void *i915_gem_object_alloc(struct drm_device *dev);
3084void i915_gem_object_free(struct drm_i915_gem_object *obj);
3085void i915_gem_object_init(struct drm_i915_gem_object *obj,
3086                         const struct drm_i915_gem_object_ops *ops);
3087struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3088                                                  size_t size);
3089struct drm_i915_gem_object *i915_gem_object_create_from_data(
3090                struct drm_device *dev, const void *data, size_t size);
3091void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3092void i915_gem_free_object(struct drm_gem_object *obj);
3093
3094struct i915_vma * __must_check
3095i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3096                         const struct i915_ggtt_view *view,
3097                         u64 size,
3098                         u64 alignment,
3099                         u64 flags);
3100
3101int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3102                  u32 flags);
3103void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3104int __must_check i915_vma_unbind(struct i915_vma *vma);
3105void i915_vma_close(struct i915_vma *vma);
3106void i915_vma_destroy(struct i915_vma *vma);
3107
3108int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3109int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3110void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3111void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3112
3113int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3114
3115static inline int __sg_page_count(struct scatterlist *sg)
3116{
3117        return sg->length >> PAGE_SHIFT;
3118}
3119
3120struct page *
3121i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3122
3123static inline dma_addr_t
3124i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3125{
3126        if (n < obj->get_page.last) {
3127                obj->get_page.sg = obj->pages->sgl;
3128                obj->get_page.last = 0;
3129        }
3130
3131        while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3132                obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3133                if (unlikely(sg_is_chain(obj->get_page.sg)))
3134                        obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3135        }
3136
3137        return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3138}
3139
3140static inline struct page *
3141i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3142{
3143        if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3144                return NULL;
3145
3146        if (n < obj->get_page.last) {
3147                obj->get_page.sg = obj->pages->sgl;
3148                obj->get_page.last = 0;
3149        }
3150
3151        while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3152                obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3153                if (unlikely(sg_is_chain(obj->get_page.sg)))
3154                        obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3155        }
3156
3157        return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3158}
3159
3160static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3161{
3162        BUG_ON(obj->pages == NULL);
3163        obj->pages_pin_count++;
3164}
3165
3166static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3167{
3168        BUG_ON(obj->pages_pin_count == 0);
3169        obj->pages_pin_count--;
3170}
3171
3172enum i915_map_type {
3173        I915_MAP_WB = 0,
3174        I915_MAP_WC,
3175};
3176
3177/**
3178 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3179 * @obj - the object to map into kernel address space
3180 * @type - the type of mapping, used to select pgprot_t
3181 *
3182 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3183 * pages and then returns a contiguous mapping of the backing storage into
3184 * the kernel address space. Based on the @type of mapping, the PTE will be
3185 * set to either WriteBack or WriteCombine (via pgprot_t).
3186 *
3187 * The caller must hold the struct_mutex, and is responsible for calling
3188 * i915_gem_object_unpin_map() when the mapping is no longer required.
3189 *
3190 * Returns the pointer through which to access the mapped object, or an
3191 * ERR_PTR() on error.
3192 */
3193void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3194                                           enum i915_map_type type);
3195
3196/**
3197 * i915_gem_object_unpin_map - releases an earlier mapping
3198 * @obj - the object to unmap
3199 *
3200 * After pinning the object and mapping its pages, once you are finished
3201 * with your access, call i915_gem_object_unpin_map() to release the pin
3202 * upon the mapping. Once the pin count reaches zero, that mapping may be
3203 * removed.
3204 *
3205 * The caller must hold the struct_mutex.
3206 */
3207static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3208{
3209        lockdep_assert_held(&obj->base.dev->struct_mutex);
3210        i915_gem_object_unpin_pages(obj);
3211}
3212
3213int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3214                                    unsigned int *needs_clflush);
3215int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3216                                     unsigned int *needs_clflush);
3217#define CLFLUSH_BEFORE 0x1
3218#define CLFLUSH_AFTER 0x2
3219#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3220
3221static inline void
3222i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3223{
3224        i915_gem_object_unpin_pages(obj);
3225}
3226
3227int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3228void i915_vma_move_to_active(struct i915_vma *vma,
3229                             struct drm_i915_gem_request *req,
3230                             unsigned int flags);
3231int i915_gem_dumb_create(struct drm_file *file_priv,
3232                         struct drm_device *dev,
3233                         struct drm_mode_create_dumb *args);
3234int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3235                      uint32_t handle, uint64_t *offset);
3236int i915_gem_mmap_gtt_version(void);
3237
3238void i915_gem_track_fb(struct drm_i915_gem_object *old,
3239                       struct drm_i915_gem_object *new,
3240                       unsigned frontbuffer_bits);
3241
3242int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3243
3244struct drm_i915_gem_request *
3245i915_gem_find_active_request(struct intel_engine_cs *engine);
3246
3247void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3248
3249static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3250{
3251        return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3252}
3253
3254static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3255{
3256        return unlikely(test_bit(I915_WEDGED, &error->flags));
3257}
3258
3259static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3260{
3261        return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3262}
3263
3264static inline u32 i915_reset_count(struct i915_gpu_error *error)
3265{
3266        return READ_ONCE(error->reset_count);
3267}
3268
3269void i915_gem_reset(struct drm_i915_private *dev_priv);
3270void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3271bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3272int __must_check i915_gem_init(struct drm_device *dev);
3273int __must_check i915_gem_init_hw(struct drm_device *dev);
3274void i915_gem_init_swizzling(struct drm_device *dev);
3275void i915_gem_cleanup_engines(struct drm_device *dev);
3276int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3277                                        unsigned int flags);
3278int __must_check i915_gem_suspend(struct drm_device *dev);
3279void i915_gem_resume(struct drm_device *dev);
3280int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3281int __must_check
3282i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3283                               bool readonly);
3284int __must_check
3285i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3286                                  bool write);
3287int __must_check
3288i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3289struct i915_vma * __must_check
3290i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3291                                     u32 alignment,
3292                                     const struct i915_ggtt_view *view);
3293void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3294int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3295                                int align);
3296int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3297void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3298
3299u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3300                           int tiling_mode);
3301u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3302                                int tiling_mode, bool fenced);
3303
3304int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3305                                    enum i915_cache_level cache_level);
3306
3307struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3308                                struct dma_buf *dma_buf);
3309
3310struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3311                                struct drm_gem_object *gem_obj, int flags);
3312
3313struct i915_vma *
3314i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3315                     struct i915_address_space *vm,
3316                     const struct i915_ggtt_view *view);
3317
3318struct i915_vma *
3319i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3320                                  struct i915_address_space *vm,
3321                                  const struct i915_ggtt_view *view);
3322
3323static inline struct i915_hw_ppgtt *
3324i915_vm_to_ppgtt(struct i915_address_space *vm)
3325{
3326        return container_of(vm, struct i915_hw_ppgtt, base);
3327}
3328
3329static inline struct i915_vma *
3330i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3331                        const struct i915_ggtt_view *view)
3332{
3333        return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3334}
3335
3336static inline unsigned long
3337i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3338                            const struct i915_ggtt_view *view)
3339{
3340        return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3341}
3342
3343/* i915_gem_fence.c */
3344int __must_check i915_vma_get_fence(struct i915_vma *vma);
3345int __must_check i915_vma_put_fence(struct i915_vma *vma);
3346
3347/**
3348 * i915_vma_pin_fence - pin fencing state
3349 * @vma: vma to pin fencing for
3350 *
3351 * This pins the fencing state (whether tiled or untiled) to make sure the
3352 * vma (and its object) is ready to be used as a scanout target. Fencing
3353 * status must be synchronize first by calling i915_vma_get_fence():
3354 *
3355 * The resulting fence pin reference must be released again with
3356 * i915_vma_unpin_fence().
3357 *
3358 * Returns:
3359 *
3360 * True if the vma has a fence, false otherwise.
3361 */
3362static inline bool
3363i915_vma_pin_fence(struct i915_vma *vma)
3364{
3365        if (vma->fence) {
3366                vma->fence->pin_count++;
3367                return true;
3368        } else
3369                return false;
3370}
3371
3372/**
3373 * i915_vma_unpin_fence - unpin fencing state
3374 * @vma: vma to unpin fencing for
3375 *
3376 * This releases the fence pin reference acquired through
3377 * i915_vma_pin_fence. It will handle both objects with and without an
3378 * attached fence correctly, callers do not need to distinguish this.
3379 */
3380static inline void
3381i915_vma_unpin_fence(struct i915_vma *vma)
3382{
3383        if (vma->fence) {
3384                GEM_BUG_ON(vma->fence->pin_count <= 0);
3385                vma->fence->pin_count--;
3386        }
3387}
3388
3389void i915_gem_restore_fences(struct drm_device *dev);
3390
3391void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3392void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3393void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3394
3395/* i915_gem_context.c */
3396int __must_check i915_gem_context_init(struct drm_device *dev);
3397void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3398void i915_gem_context_fini(struct drm_device *dev);
3399int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3400void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3401int i915_switch_context(struct drm_i915_gem_request *req);
3402int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3403void i915_gem_context_free(struct kref *ctx_ref);
3404struct drm_i915_gem_object *
3405i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3406struct i915_gem_context *
3407i915_gem_context_create_gvt(struct drm_device *dev);
3408
3409static inline struct i915_gem_context *
3410i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3411{
3412        struct i915_gem_context *ctx;
3413
3414        lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3415
3416        ctx = idr_find(&file_priv->context_idr, id);
3417        if (!ctx)
3418                return ERR_PTR(-ENOENT);
3419
3420        return ctx;
3421}
3422
3423static inline struct i915_gem_context *
3424i915_gem_context_get(struct i915_gem_context *ctx)
3425{
3426        kref_get(&ctx->ref);
3427        return ctx;
3428}
3429
3430static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3431{
3432        lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3433        kref_put(&ctx->ref, i915_gem_context_free);
3434}
3435
3436static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3437{
3438        return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3439}
3440
3441int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3442                                  struct drm_file *file);
3443int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3444                                   struct drm_file *file);
3445int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3446                                    struct drm_file *file_priv);
3447int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3448                                    struct drm_file *file_priv);
3449int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3450                                       struct drm_file *file);
3451
3452/* i915_gem_evict.c */
3453int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3454                                          u64 min_size, u64 alignment,
3455                                          unsigned cache_level,
3456                                          u64 start, u64 end,
3457                                          unsigned flags);
3458int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3459int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3460
3461/* belongs in i915_gem_gtt.h */
3462static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3463{
3464        wmb();
3465        if (INTEL_GEN(dev_priv) < 6)
3466                intel_gtt_chipset_flush();
3467}
3468
3469/* i915_gem_stolen.c */
3470int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3471                                struct drm_mm_node *node, u64 size,
3472                                unsigned alignment);
3473int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3474                                         struct drm_mm_node *node, u64 size,
3475                                         unsigned alignment, u64 start,
3476                                         u64 end);
3477void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3478                                 struct drm_mm_node *node);
3479int i915_gem_init_stolen(struct drm_device *dev);
3480void i915_gem_cleanup_stolen(struct drm_device *dev);
3481struct drm_i915_gem_object *
3482i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3483struct drm_i915_gem_object *
3484i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3485                                               u32 stolen_offset,
3486                                               u32 gtt_offset,
3487                                               u32 size);
3488
3489/* i915_gem_shrinker.c */
3490unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3491                              unsigned long target,
3492                              unsigned flags);
3493#define I915_SHRINK_PURGEABLE 0x1
3494#define I915_SHRINK_UNBOUND 0x2
3495#define I915_SHRINK_BOUND 0x4
3496#define I915_SHRINK_ACTIVE 0x8
3497#define I915_SHRINK_VMAPS 0x10
3498unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3499void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3500void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3501
3502
3503/* i915_gem_tiling.c */
3504static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3505{
3506        struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3507
3508        return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3509                i915_gem_object_is_tiled(obj);
3510}
3511
3512/* i915_debugfs.c */
3513#ifdef CONFIG_DEBUG_FS
3514int i915_debugfs_register(struct drm_i915_private *dev_priv);
3515void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3516int i915_debugfs_connector_add(struct drm_connector *connector);
3517void intel_display_crc_init(struct drm_i915_private *dev_priv);
3518#else
3519static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3520static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3521static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3522{ return 0; }
3523static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3524#endif
3525
3526/* i915_gpu_error.c */
3527__printf(2, 3)
3528void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3529int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3530                            const struct i915_error_state_file_priv *error);
3531int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3532                              struct drm_i915_private *i915,
3533                              size_t count, loff_t pos);
3534static inline void i915_error_state_buf_release(
3535        struct drm_i915_error_state_buf *eb)
3536{
3537        kfree(eb->buf);
3538}
3539void i915_capture_error_state(struct drm_i915_private *dev_priv,
3540                              u32 engine_mask,
3541                              const char *error_msg);
3542void i915_error_state_get(struct drm_device *dev,
3543                          struct i915_error_state_file_priv *error_priv);
3544void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3545void i915_destroy_error_state(struct drm_device *dev);
3546
3547void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3548const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3549
3550/* i915_cmd_parser.c */
3551int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3552void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3553void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3554bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3555int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3556                            struct drm_i915_gem_object *batch_obj,
3557                            struct drm_i915_gem_object *shadow_batch_obj,
3558                            u32 batch_start_offset,
3559                            u32 batch_len,
3560                            bool is_master);
3561
3562/* i915_suspend.c */
3563extern int i915_save_state(struct drm_device *dev);
3564extern int i915_restore_state(struct drm_device *dev);
3565
3566/* i915_sysfs.c */
3567void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3568void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3569
3570/* intel_i2c.c */
3571extern int intel_setup_gmbus(struct drm_device *dev);
3572extern void intel_teardown_gmbus(struct drm_device *dev);
3573extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3574                                     unsigned int pin);
3575
3576extern struct i2c_adapter *
3577intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3578extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3579extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3580static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3581{
3582        return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3583}
3584extern void intel_i2c_reset(struct drm_device *dev);
3585
3586/* intel_bios.c */
3587int intel_bios_init(struct drm_i915_private *dev_priv);
3588bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3589bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3590bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3591bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3592bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3593bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3594bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3595bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3596                                     enum port port);
3597
3598/* intel_opregion.c */
3599#ifdef CONFIG_ACPI
3600extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3601extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3602extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3603extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3604extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3605                                         bool enable);
3606extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3607                                         pci_power_t state);
3608extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3609#else
3610static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3611static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3612static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3613static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3614{
3615}
3616static inline int
3617intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3618{
3619        return 0;
3620}
3621static inline int
3622intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3623{
3624        return 0;
3625}
3626static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3627{
3628        return -ENODEV;
3629}
3630#endif
3631
3632/* intel_acpi.c */
3633#ifdef CONFIG_ACPI
3634extern void intel_register_dsm_handler(void);
3635extern void intel_unregister_dsm_handler(void);
3636#else
3637static inline void intel_register_dsm_handler(void) { return; }
3638static inline void intel_unregister_dsm_handler(void) { return; }
3639#endif /* CONFIG_ACPI */
3640
3641/* intel_device_info.c */
3642static inline struct intel_device_info *
3643mkwrite_device_info(struct drm_i915_private *dev_priv)
3644{
3645        return (struct intel_device_info *)&dev_priv->info;
3646}
3647
3648void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3649void intel_device_info_dump(struct drm_i915_private *dev_priv);
3650
3651/* modesetting */
3652extern void intel_modeset_init_hw(struct drm_device *dev);
3653extern void intel_modeset_init(struct drm_device *dev);
3654extern void intel_modeset_gem_init(struct drm_device *dev);
3655extern void intel_modeset_cleanup(struct drm_device *dev);
3656extern int intel_connector_register(struct drm_connector *);
3657extern void intel_connector_unregister(struct drm_connector *);
3658extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3659extern void intel_display_resume(struct drm_device *dev);
3660extern void i915_redisable_vga(struct drm_device *dev);
3661extern void i915_redisable_vga_power_on(struct drm_device *dev);
3662extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3663extern void intel_init_pch_refclk(struct drm_device *dev);
3664extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3665extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3666                                  bool enable);
3667
3668int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3669                        struct drm_file *file);
3670
3671/* overlay */
3672extern struct intel_overlay_error_state *
3673intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3674extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3675                                            struct intel_overlay_error_state *error);
3676
3677extern struct intel_display_error_state *
3678intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3679extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3680                                            struct drm_device *dev,
3681                                            struct intel_display_error_state *error);
3682
3683int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3684int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3685int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3686                      u32 reply_mask, u32 reply, int timeout_base_ms);
3687
3688/* intel_sideband.c */
3689u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3690void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3691u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3692u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3693void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3694u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3695void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3696u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3697void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3698u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3699void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3700u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3701void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3702u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3703                   enum intel_sbi_destination destination);
3704void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3705                     enum intel_sbi_destination destination);
3706u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3707void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3708
3709/* intel_dpio_phy.c */
3710void chv_set_phy_signal_level(struct intel_encoder *encoder,
3711                              u32 deemph_reg_value, u32 margin_reg_value,
3712                              bool uniq_trans_scale);
3713void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3714                              bool reset);
3715void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3716void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3717void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3718void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3719
3720void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3721                              u32 demph_reg_value, u32 preemph_reg_value,
3722                              u32 uniqtranscale_reg_value, u32 tx3_demph);
3723void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3724void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3725void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3726
3727int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3728int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3729
3730#define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3731#define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3732
3733#define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3734#define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3735#define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3736#define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3737
3738#define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3739#define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3740#define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3741#define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3742
3743/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3744 * will be implemented using 2 32-bit writes in an arbitrary order with
3745 * an arbitrary delay between them. This can cause the hardware to
3746 * act upon the intermediate value, possibly leading to corruption and
3747 * machine death. For this reason we do not support I915_WRITE64, or
3748 * dev_priv->uncore.funcs.mmio_writeq.
3749 *
3750 * When reading a 64-bit value as two 32-bit values, the delay may cause
3751 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3752 * occasionally a 64-bit register does not actualy support a full readq
3753 * and must be read using two 32-bit reads.
3754 *
3755 * You have been warned.
3756 */
3757#define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3758
3759#define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3760        u32 upper, lower, old_upper, loop = 0;                          \
3761        upper = I915_READ(upper_reg);                                   \
3762        do {                                                            \
3763                old_upper = upper;                                      \
3764                lower = I915_READ(lower_reg);                           \
3765                upper = I915_READ(upper_reg);                           \
3766        } while (upper != old_upper && loop++ < 2);                     \
3767        (u64)upper << 32 | lower; })
3768
3769#define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3770#define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3771
3772#define __raw_read(x, s) \
3773static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3774                                             i915_reg_t reg) \
3775{ \
3776        return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3777}
3778
3779#define __raw_write(x, s) \
3780static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3781                                       i915_reg_t reg, uint##x##_t val) \
3782{ \
3783        write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3784}
3785__raw_read(8, b)
3786__raw_read(16, w)
3787__raw_read(32, l)
3788__raw_read(64, q)
3789
3790__raw_write(8, b)
3791__raw_write(16, w)
3792__raw_write(32, l)
3793__raw_write(64, q)
3794
3795#undef __raw_read
3796#undef __raw_write
3797
3798/* These are untraced mmio-accessors that are only valid to be used inside
3799 * critical sections inside IRQ handlers where forcewake is explicitly
3800 * controlled.
3801 * Think twice, and think again, before using these.
3802 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3803 * intel_uncore_forcewake_irqunlock().
3804 */
3805#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3806#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3807#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3808#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3809
3810/* "Broadcast RGB" property */
3811#define INTEL_BROADCAST_RGB_AUTO 0
3812#define INTEL_BROADCAST_RGB_FULL 1
3813#define INTEL_BROADCAST_RGB_LIMITED 2
3814
3815static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3816{
3817        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3818                return VLV_VGACNTRL;
3819        else if (INTEL_INFO(dev)->gen >= 5)
3820                return CPU_VGACNTRL;
3821        else
3822                return VGACNTRL;
3823}
3824
3825static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3826{
3827        unsigned long j = msecs_to_jiffies(m);
3828
3829        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3830}
3831
3832static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3833{
3834        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3835}
3836
3837static inline unsigned long
3838timespec_to_jiffies_timeout(const struct timespec *value)
3839{
3840        unsigned long j = timespec_to_jiffies(value);
3841
3842        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3843}
3844
3845/*
3846 * If you need to wait X milliseconds between events A and B, but event B
3847 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3848 * when event A happened, then just before event B you call this function and
3849 * pass the timestamp as the first argument, and X as the second argument.
3850 */
3851static inline void
3852wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3853{
3854        unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3855
3856        /*
3857         * Don't re-read the value of "jiffies" every time since it may change
3858         * behind our back and break the math.
3859         */
3860        tmp_jiffies = jiffies;
3861        target_jiffies = timestamp_jiffies +
3862                         msecs_to_jiffies_timeout(to_wait_ms);
3863
3864        if (time_after(target_jiffies, tmp_jiffies)) {
3865                remaining_jiffies = target_jiffies - tmp_jiffies;
3866                while (remaining_jiffies)
3867                        remaining_jiffies =
3868                            schedule_timeout_uninterruptible(remaining_jiffies);
3869        }
3870}
3871
3872static inline bool
3873__i915_request_irq_complete(struct drm_i915_gem_request *req)
3874{
3875        struct intel_engine_cs *engine = req->engine;
3876
3877        /* Before we do the heavier coherent read of the seqno,
3878         * check the value (hopefully) in the CPU cacheline.
3879         */
3880        if (i915_gem_request_completed(req))
3881                return true;
3882
3883        /* Ensure our read of the seqno is coherent so that we
3884         * do not "miss an interrupt" (i.e. if this is the last
3885         * request and the seqno write from the GPU is not visible
3886         * by the time the interrupt fires, we will see that the
3887         * request is incomplete and go back to sleep awaiting
3888         * another interrupt that will never come.)
3889         *
3890         * Strictly, we only need to do this once after an interrupt,
3891         * but it is easier and safer to do it every time the waiter
3892         * is woken.
3893         */
3894        if (engine->irq_seqno_barrier &&
3895            rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3896            cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3897                struct task_struct *tsk;
3898
3899                /* The ordering of irq_posted versus applying the barrier
3900                 * is crucial. The clearing of the current irq_posted must
3901                 * be visible before we perform the barrier operation,
3902                 * such that if a subsequent interrupt arrives, irq_posted
3903                 * is reasserted and our task rewoken (which causes us to
3904                 * do another __i915_request_irq_complete() immediately
3905                 * and reapply the barrier). Conversely, if the clear
3906                 * occurs after the barrier, then an interrupt that arrived
3907                 * whilst we waited on the barrier would not trigger a
3908                 * barrier on the next pass, and the read may not see the
3909                 * seqno update.
3910                 */
3911                engine->irq_seqno_barrier(engine);
3912
3913                /* If we consume the irq, but we are no longer the bottom-half,
3914                 * the real bottom-half may not have serialised their own
3915                 * seqno check with the irq-barrier (i.e. may have inspected
3916                 * the seqno before we believe it coherent since they see
3917                 * irq_posted == false but we are still running).
3918                 */
3919                rcu_read_lock();
3920                tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3921                if (tsk && tsk != current)
3922                        /* Note that if the bottom-half is changed as we
3923                         * are sending the wake-up, the new bottom-half will
3924                         * be woken by whomever made the change. We only have
3925                         * to worry about when we steal the irq-posted for
3926                         * ourself.
3927                         */
3928                        wake_up_process(tsk);
3929                rcu_read_unlock();
3930
3931                if (i915_gem_request_completed(req))
3932                        return true;
3933        }
3934
3935        return false;
3936}
3937
3938void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3939bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3940
3941/* i915_mm.c */
3942int remap_io_mapping(struct vm_area_struct *vma,
3943                     unsigned long addr, unsigned long pfn, unsigned long size,
3944                     struct io_mapping *iomap);
3945
3946#define ptr_mask_bits(ptr) ({                                           \
3947        unsigned long __v = (unsigned long)(ptr);                       \
3948        (typeof(ptr))(__v & PAGE_MASK);                                 \
3949})
3950
3951#define ptr_unpack_bits(ptr, bits) ({                                   \
3952        unsigned long __v = (unsigned long)(ptr);                       \
3953        (bits) = __v & ~PAGE_MASK;                                      \
3954        (typeof(ptr))(__v & PAGE_MASK);                                 \
3955})
3956
3957#define ptr_pack_bits(ptr, bits)                                        \
3958        ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3959
3960#define fetch_and_zero(ptr) ({                                          \
3961        typeof(*ptr) __T = *(ptr);                                      \
3962        *(ptr) = (typeof(*ptr))0;                                       \
3963        __T;                                                            \
3964})
3965
3966#endif
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