source: src/linux/universal/linux-4.9/drivers/gpu/drm/i915/i915_irq.c @ 31884

Last change on this file since 31884 was 31884, checked in by brainslayer, 3 months ago

update kernels

File size: 129.4 KB
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1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/sysrq.h>
32#include <linux/slab.h>
33#include <linux/circ_buf.h>
34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include "intel_drv.h"
39
40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48static const u32 hpd_ilk[HPD_NUM_PINS] = {
49        [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50};
51
52static const u32 hpd_ivb[HPD_NUM_PINS] = {
53        [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54};
55
56static const u32 hpd_bdw[HPD_NUM_PINS] = {
57        [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58};
59
60static const u32 hpd_ibx[HPD_NUM_PINS] = {
61        [HPD_CRT] = SDE_CRT_HOTPLUG,
62        [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63        [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64        [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65        [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66};
67
68static const u32 hpd_cpt[HPD_NUM_PINS] = {
69        [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70        [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71        [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72        [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73        [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74};
75
76static const u32 hpd_spt[HPD_NUM_PINS] = {
77        [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78        [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79        [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80        [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81        [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82};
83
84static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85        [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86        [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87        [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88        [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89        [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90        [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91};
92
93static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94        [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95        [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96        [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97        [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98        [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99        [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100};
101
102static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103        [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104        [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105        [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106        [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107        [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108        [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109};
110
111/* BXT hpd list */
112static const u32 hpd_bxt[HPD_NUM_PINS] = {
113        [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114        [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115        [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116};
117
118/* IIR can theoretically queue up two events. Be paranoid. */
119#define GEN8_IRQ_RESET_NDX(type, which) do { \
120        I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121        POSTING_READ(GEN8_##type##_IMR(which)); \
122        I915_WRITE(GEN8_##type##_IER(which), 0); \
123        I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124        POSTING_READ(GEN8_##type##_IIR(which)); \
125        I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126        POSTING_READ(GEN8_##type##_IIR(which)); \
127} while (0)
128
129#define GEN5_IRQ_RESET(type) do { \
130        I915_WRITE(type##IMR, 0xffffffff); \
131        POSTING_READ(type##IMR); \
132        I915_WRITE(type##IER, 0); \
133        I915_WRITE(type##IIR, 0xffffffff); \
134        POSTING_READ(type##IIR); \
135        I915_WRITE(type##IIR, 0xffffffff); \
136        POSTING_READ(type##IIR); \
137} while (0)
138
139/*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
142static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143                                    i915_reg_t reg)
144{
145        u32 val = I915_READ(reg);
146
147        if (val == 0)
148                return;
149
150        WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151             i915_mmio_reg_offset(reg), val);
152        I915_WRITE(reg, 0xffffffff);
153        POSTING_READ(reg);
154        I915_WRITE(reg, 0xffffffff);
155        POSTING_READ(reg);
156}
157
158#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159        gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160        I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161        I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162        POSTING_READ(GEN8_##type##_IMR(which)); \
163} while (0)
164
165#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166        gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167        I915_WRITE(type##IER, (ier_val)); \
168        I915_WRITE(type##IMR, (imr_val)); \
169        POSTING_READ(type##IMR); \
170} while (0)
171
172static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173
174/* For display hotplug interrupt */
175static inline void
176i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
177                                     uint32_t mask,
178                                     uint32_t bits)
179{
180        uint32_t val;
181
182        assert_spin_locked(&dev_priv->irq_lock);
183        WARN_ON(bits & ~mask);
184
185        val = I915_READ(PORT_HOTPLUG_EN);
186        val &= ~mask;
187        val |= bits;
188        I915_WRITE(PORT_HOTPLUG_EN, val);
189}
190
191/**
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
202 */
203void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
204                                   uint32_t mask,
205                                   uint32_t bits)
206{
207        spin_lock_irq(&dev_priv->irq_lock);
208        i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209        spin_unlock_irq(&dev_priv->irq_lock);
210}
211
212/**
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
217 */
218void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219                            uint32_t interrupt_mask,
220                            uint32_t enabled_irq_mask)
221{
222        uint32_t new_val;
223
224        assert_spin_locked(&dev_priv->irq_lock);
225
226        WARN_ON(enabled_irq_mask & ~interrupt_mask);
227
228        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
229                return;
230
231        new_val = dev_priv->irq_mask;
232        new_val &= ~interrupt_mask;
233        new_val |= (~enabled_irq_mask & interrupt_mask);
234
235        if (new_val != dev_priv->irq_mask) {
236                dev_priv->irq_mask = new_val;
237                I915_WRITE(DEIMR, dev_priv->irq_mask);
238                POSTING_READ(DEIMR);
239        }
240}
241
242/**
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
247 */
248static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249                              uint32_t interrupt_mask,
250                              uint32_t enabled_irq_mask)
251{
252        assert_spin_locked(&dev_priv->irq_lock);
253
254        WARN_ON(enabled_irq_mask & ~interrupt_mask);
255
256        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
257                return;
258
259        dev_priv->gt_irq_mask &= ~interrupt_mask;
260        dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261        I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262}
263
264void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
265{
266        ilk_update_gt_irq(dev_priv, mask, mask);
267        POSTING_READ_FW(GTIMR);
268}
269
270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
271{
272        ilk_update_gt_irq(dev_priv, mask, 0);
273}
274
275static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
276{
277        return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
278}
279
280static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
281{
282        return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
283}
284
285static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
286{
287        return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
288}
289
290/**
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
295 */
296static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297                              uint32_t interrupt_mask,
298                              uint32_t enabled_irq_mask)
299{
300        uint32_t new_val;
301
302        WARN_ON(enabled_irq_mask & ~interrupt_mask);
303
304        assert_spin_locked(&dev_priv->irq_lock);
305
306        new_val = dev_priv->pm_irq_mask;
307        new_val &= ~interrupt_mask;
308        new_val |= (~enabled_irq_mask & interrupt_mask);
309
310        if (new_val != dev_priv->pm_irq_mask) {
311                dev_priv->pm_irq_mask = new_val;
312                I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313                POSTING_READ(gen6_pm_imr(dev_priv));
314        }
315}
316
317void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
318{
319        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
320                return;
321
322        snb_update_pm_irq(dev_priv, mask, mask);
323}
324
325static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
326                                  uint32_t mask)
327{
328        snb_update_pm_irq(dev_priv, mask, 0);
329}
330
331void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
332{
333        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334                return;
335
336        __gen6_disable_pm_irq(dev_priv, mask);
337}
338
339void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
340{
341        i915_reg_t reg = gen6_pm_iir(dev_priv);
342
343        spin_lock_irq(&dev_priv->irq_lock);
344        I915_WRITE(reg, dev_priv->pm_rps_events);
345        I915_WRITE(reg, dev_priv->pm_rps_events);
346        POSTING_READ(reg);
347        dev_priv->rps.pm_iir = 0;
348        spin_unlock_irq(&dev_priv->irq_lock);
349}
350
351void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
352{
353        if (READ_ONCE(dev_priv->rps.interrupts_enabled))
354                return;
355
356        spin_lock_irq(&dev_priv->irq_lock);
357        WARN_ON_ONCE(dev_priv->rps.pm_iir);
358        WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
359        dev_priv->rps.interrupts_enabled = true;
360        I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
361                                dev_priv->pm_rps_events);
362        gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
363
364        spin_unlock_irq(&dev_priv->irq_lock);
365}
366
367u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
368{
369        return (mask & ~dev_priv->rps.pm_intr_keep);
370}
371
372void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
373{
374        if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
375                return;
376
377        spin_lock_irq(&dev_priv->irq_lock);
378        dev_priv->rps.interrupts_enabled = false;
379
380        I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
381
382        __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
383        I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
384                                ~dev_priv->pm_rps_events);
385
386        spin_unlock_irq(&dev_priv->irq_lock);
387        synchronize_irq(dev_priv->drm.irq);
388
389        /* Now that we will not be generating any more work, flush any
390         * outsanding tasks. As we are called on the RPS idle path,
391         * we will reset the GPU to minimum frequencies, so the current
392         * state of the worker can be discarded.
393         */
394        cancel_work_sync(&dev_priv->rps.work);
395        gen6_reset_rps_interrupts(dev_priv);
396}
397
398/**
399 * bdw_update_port_irq - update DE port interrupt
400 * @dev_priv: driver private
401 * @interrupt_mask: mask of interrupt bits to update
402 * @enabled_irq_mask: mask of interrupt bits to enable
403 */
404static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
405                                uint32_t interrupt_mask,
406                                uint32_t enabled_irq_mask)
407{
408        uint32_t new_val;
409        uint32_t old_val;
410
411        assert_spin_locked(&dev_priv->irq_lock);
412
413        WARN_ON(enabled_irq_mask & ~interrupt_mask);
414
415        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
416                return;
417
418        old_val = I915_READ(GEN8_DE_PORT_IMR);
419
420        new_val = old_val;
421        new_val &= ~interrupt_mask;
422        new_val |= (~enabled_irq_mask & interrupt_mask);
423
424        if (new_val != old_val) {
425                I915_WRITE(GEN8_DE_PORT_IMR, new_val);
426                POSTING_READ(GEN8_DE_PORT_IMR);
427        }
428}
429
430/**
431 * bdw_update_pipe_irq - update DE pipe interrupt
432 * @dev_priv: driver private
433 * @pipe: pipe whose interrupt to update
434 * @interrupt_mask: mask of interrupt bits to update
435 * @enabled_irq_mask: mask of interrupt bits to enable
436 */
437void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
438                         enum pipe pipe,
439                         uint32_t interrupt_mask,
440                         uint32_t enabled_irq_mask)
441{
442        uint32_t new_val;
443
444        assert_spin_locked(&dev_priv->irq_lock);
445
446        WARN_ON(enabled_irq_mask & ~interrupt_mask);
447
448        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
449                return;
450
451        new_val = dev_priv->de_irq_mask[pipe];
452        new_val &= ~interrupt_mask;
453        new_val |= (~enabled_irq_mask & interrupt_mask);
454
455        if (new_val != dev_priv->de_irq_mask[pipe]) {
456                dev_priv->de_irq_mask[pipe] = new_val;
457                I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
458                POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
459        }
460}
461
462/**
463 * ibx_display_interrupt_update - update SDEIMR
464 * @dev_priv: driver private
465 * @interrupt_mask: mask of interrupt bits to update
466 * @enabled_irq_mask: mask of interrupt bits to enable
467 */
468void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
469                                  uint32_t interrupt_mask,
470                                  uint32_t enabled_irq_mask)
471{
472        uint32_t sdeimr = I915_READ(SDEIMR);
473        sdeimr &= ~interrupt_mask;
474        sdeimr |= (~enabled_irq_mask & interrupt_mask);
475
476        WARN_ON(enabled_irq_mask & ~interrupt_mask);
477
478        assert_spin_locked(&dev_priv->irq_lock);
479
480        if (WARN_ON(!intel_irqs_enabled(dev_priv)))
481                return;
482
483        I915_WRITE(SDEIMR, sdeimr);
484        POSTING_READ(SDEIMR);
485}
486
487static void
488__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
489                       u32 enable_mask, u32 status_mask)
490{
491        i915_reg_t reg = PIPESTAT(pipe);
492        u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
493
494        assert_spin_locked(&dev_priv->irq_lock);
495        WARN_ON(!intel_irqs_enabled(dev_priv));
496
497        if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
498                      status_mask & ~PIPESTAT_INT_STATUS_MASK,
499                      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
500                      pipe_name(pipe), enable_mask, status_mask))
501                return;
502
503        if ((pipestat & enable_mask) == enable_mask)
504                return;
505
506        dev_priv->pipestat_irq_mask[pipe] |= status_mask;
507
508        /* Enable the interrupt, clear any pending status */
509        pipestat |= enable_mask | status_mask;
510        I915_WRITE(reg, pipestat);
511        POSTING_READ(reg);
512}
513
514static void
515__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
516                        u32 enable_mask, u32 status_mask)
517{
518        i915_reg_t reg = PIPESTAT(pipe);
519        u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
520
521        assert_spin_locked(&dev_priv->irq_lock);
522        WARN_ON(!intel_irqs_enabled(dev_priv));
523
524        if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
525                      status_mask & ~PIPESTAT_INT_STATUS_MASK,
526                      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
527                      pipe_name(pipe), enable_mask, status_mask))
528                return;
529
530        if ((pipestat & enable_mask) == 0)
531                return;
532
533        dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
534
535        pipestat &= ~enable_mask;
536        I915_WRITE(reg, pipestat);
537        POSTING_READ(reg);
538}
539
540static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
541{
542        u32 enable_mask = status_mask << 16;
543
544        /*
545         * On pipe A we don't support the PSR interrupt yet,
546         * on pipe B and C the same bit MBZ.
547         */
548        if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
549                return 0;
550        /*
551         * On pipe B and C we don't support the PSR interrupt yet, on pipe
552         * A the same bit is for perf counters which we don't use either.
553         */
554        if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
555                return 0;
556
557        enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
558                         SPRITE0_FLIP_DONE_INT_EN_VLV |
559                         SPRITE1_FLIP_DONE_INT_EN_VLV);
560        if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
561                enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
562        if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
563                enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
564
565        return enable_mask;
566}
567
568void
569i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
570                     u32 status_mask)
571{
572        u32 enable_mask;
573
574        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
575                enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
576                                                           status_mask);
577        else
578                enable_mask = status_mask << 16;
579        __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
580}
581
582void
583i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
584                      u32 status_mask)
585{
586        u32 enable_mask;
587
588        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
589                enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
590                                                           status_mask);
591        else
592                enable_mask = status_mask << 16;
593        __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
594}
595
596/**
597 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
598 * @dev_priv: i915 device private
599 */
600static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
601{
602        if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
603                return;
604
605        spin_lock_irq(&dev_priv->irq_lock);
606
607        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
608        if (INTEL_GEN(dev_priv) >= 4)
609                i915_enable_pipestat(dev_priv, PIPE_A,
610                                     PIPE_LEGACY_BLC_EVENT_STATUS);
611
612        spin_unlock_irq(&dev_priv->irq_lock);
613}
614
615/*
616 * This timing diagram depicts the video signal in and
617 * around the vertical blanking period.
618 *
619 * Assumptions about the fictitious mode used in this example:
620 *  vblank_start >= 3
621 *  vsync_start = vblank_start + 1
622 *  vsync_end = vblank_start + 2
623 *  vtotal = vblank_start + 3
624 *
625 *           start of vblank:
626 *           latch double buffered registers
627 *           increment frame counter (ctg+)
628 *           generate start of vblank interrupt (gen4+)
629 *           |
630 *           |          frame start:
631 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
632 *           |          may be shifted forward 1-3 extra lines via PIPECONF
633 *           |          |
634 *           |          |  start of vsync:
635 *           |          |  generate vsync interrupt
636 *           |          |  |
637 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
638 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
639 * ----va---> <-----------------vb--------------------> <--------va-------------
640 *       |          |       <----vs----->                     |
641 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
642 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
643 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
644 *       |          |                                         |
645 *       last visible pixel                                   first visible pixel
646 *                  |                                         increment frame counter (gen3/4)
647 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
648 *
649 * x  = horizontal active
650 * _  = horizontal blanking
651 * hs = horizontal sync
652 * va = vertical active
653 * vb = vertical blanking
654 * vs = vertical sync
655 * vbs = vblank_start (number)
656 *
657 * Summary:
658 * - most events happen at the start of horizontal sync
659 * - frame start happens at the start of horizontal blank, 1-4 lines
660 *   (depending on PIPECONF settings) after the start of vblank
661 * - gen3/4 pixel and frame counter are synchronized with the start
662 *   of horizontal active on the first line of vertical active
663 */
664
665/* Called from drm generic code, passed a 'crtc', which
666 * we use as a pipe index
667 */
668static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
669{
670        struct drm_i915_private *dev_priv = to_i915(dev);
671        i915_reg_t high_frame, low_frame;
672        u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
673        struct intel_crtc *intel_crtc =
674                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
675        const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
676
677        htotal = mode->crtc_htotal;
678        hsync_start = mode->crtc_hsync_start;
679        vbl_start = mode->crtc_vblank_start;
680        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
681                vbl_start = DIV_ROUND_UP(vbl_start, 2);
682
683        /* Convert to pixel count */
684        vbl_start *= htotal;
685
686        /* Start of vblank event occurs at start of hsync */
687        vbl_start -= htotal - hsync_start;
688
689        high_frame = PIPEFRAME(pipe);
690        low_frame = PIPEFRAMEPIXEL(pipe);
691
692        /*
693         * High & low register fields aren't synchronized, so make sure
694         * we get a low value that's stable across two reads of the high
695         * register.
696         */
697        do {
698                high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
699                low   = I915_READ(low_frame);
700                high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
701        } while (high1 != high2);
702
703        high1 >>= PIPE_FRAME_HIGH_SHIFT;
704        pixel = low & PIPE_PIXEL_MASK;
705        low >>= PIPE_FRAME_LOW_SHIFT;
706
707        /*
708         * The frame counter increments at beginning of active.
709         * Cook up a vblank counter by also checking the pixel
710         * counter against vblank start.
711         */
712        return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
713}
714
715static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
716{
717        struct drm_i915_private *dev_priv = to_i915(dev);
718
719        return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
720}
721
722/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
723static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
724{
725        struct drm_device *dev = crtc->base.dev;
726        struct drm_i915_private *dev_priv = to_i915(dev);
727        const struct drm_display_mode *mode = &crtc->base.hwmode;
728        enum pipe pipe = crtc->pipe;
729        int position, vtotal;
730
731        vtotal = mode->crtc_vtotal;
732        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
733                vtotal /= 2;
734
735        if (IS_GEN2(dev_priv))
736                position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
737        else
738                position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
739
740        /*
741         * On HSW, the DSL reg (0x70000) appears to return 0 if we
742         * read it just before the start of vblank.  So try it again
743         * so we don't accidentally end up spanning a vblank frame
744         * increment, causing the pipe_update_end() code to squak at us.
745         *
746         * The nature of this problem means we can't simply check the ISR
747         * bit and return the vblank start value; nor can we use the scanline
748         * debug register in the transcoder as it appears to have the same
749         * problem.  We may need to extend this to include other platforms,
750         * but so far testing only shows the problem on HSW.
751         */
752        if (HAS_DDI(dev_priv) && !position) {
753                int i, temp;
754
755                for (i = 0; i < 100; i++) {
756                        udelay(1);
757                        temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
758                                DSL_LINEMASK_GEN3;
759                        if (temp != position) {
760                                position = temp;
761                                break;
762                        }
763                }
764        }
765
766        /*
767         * See update_scanline_offset() for the details on the
768         * scanline_offset adjustment.
769         */
770        return (position + crtc->scanline_offset) % vtotal;
771}
772
773static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
774                                    unsigned int flags, int *vpos, int *hpos,
775                                    ktime_t *stime, ktime_t *etime,
776                                    const struct drm_display_mode *mode)
777{
778        struct drm_i915_private *dev_priv = to_i915(dev);
779        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
780        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
781        int position;
782        int vbl_start, vbl_end, hsync_start, htotal, vtotal;
783        bool in_vbl = true;
784        int ret = 0;
785        unsigned long irqflags;
786
787        if (WARN_ON(!mode->crtc_clock)) {
788                DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
789                                 "pipe %c\n", pipe_name(pipe));
790                return 0;
791        }
792
793        htotal = mode->crtc_htotal;
794        hsync_start = mode->crtc_hsync_start;
795        vtotal = mode->crtc_vtotal;
796        vbl_start = mode->crtc_vblank_start;
797        vbl_end = mode->crtc_vblank_end;
798
799        if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
800                vbl_start = DIV_ROUND_UP(vbl_start, 2);
801                vbl_end /= 2;
802                vtotal /= 2;
803        }
804
805        ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
806
807        /*
808         * Lock uncore.lock, as we will do multiple timing critical raw
809         * register reads, potentially with preemption disabled, so the
810         * following code must not block on uncore.lock.
811         */
812        spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
813
814        /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815
816        /* Get optional system timestamp before query. */
817        if (stime)
818                *stime = ktime_get();
819
820        if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
821                /* No obvious pixelcount register. Only query vertical
822                 * scanout position from Display scan line register.
823                 */
824                position = __intel_get_crtc_scanline(intel_crtc);
825        } else {
826                /* Have access to pixelcount since start of frame.
827                 * We can split this into vertical and horizontal
828                 * scanout position.
829                 */
830                position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
831
832                /* convert to pixel counts */
833                vbl_start *= htotal;
834                vbl_end *= htotal;
835                vtotal *= htotal;
836
837                /*
838                 * In interlaced modes, the pixel counter counts all pixels,
839                 * so one field will have htotal more pixels. In order to avoid
840                 * the reported position from jumping backwards when the pixel
841                 * counter is beyond the length of the shorter field, just
842                 * clamp the position the length of the shorter field. This
843                 * matches how the scanline counter based position works since
844                 * the scanline counter doesn't count the two half lines.
845                 */
846                if (position >= vtotal)
847                        position = vtotal - 1;
848
849                /*
850                 * Start of vblank interrupt is triggered at start of hsync,
851                 * just prior to the first active line of vblank. However we
852                 * consider lines to start at the leading edge of horizontal
853                 * active. So, should we get here before we've crossed into
854                 * the horizontal active of the first line in vblank, we would
855                 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
856                 * always add htotal-hsync_start to the current pixel position.
857                 */
858                position = (position + htotal - hsync_start) % vtotal;
859        }
860
861        /* Get optional system timestamp after query. */
862        if (etime)
863                *etime = ktime_get();
864
865        /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
866
867        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
868
869        in_vbl = position >= vbl_start && position < vbl_end;
870
871        /*
872         * While in vblank, position will be negative
873         * counting up towards 0 at vbl_end. And outside
874         * vblank, position will be positive counting
875         * up since vbl_end.
876         */
877        if (position >= vbl_start)
878                position -= vbl_end;
879        else
880                position += vtotal - vbl_end;
881
882        if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
883                *vpos = position;
884                *hpos = 0;
885        } else {
886                *vpos = position / htotal;
887                *hpos = position - (*vpos * htotal);
888        }
889
890        /* In vblank? */
891        if (in_vbl)
892                ret |= DRM_SCANOUTPOS_IN_VBLANK;
893
894        return ret;
895}
896
897int intel_get_crtc_scanline(struct intel_crtc *crtc)
898{
899        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
900        unsigned long irqflags;
901        int position;
902
903        spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
904        position = __intel_get_crtc_scanline(crtc);
905        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
906
907        return position;
908}
909
910static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
911                              int *max_error,
912                              struct timeval *vblank_time,
913                              unsigned flags)
914{
915        struct drm_crtc *crtc;
916
917        if (pipe >= INTEL_INFO(dev)->num_pipes) {
918                DRM_ERROR("Invalid crtc %u\n", pipe);
919                return -EINVAL;
920        }
921
922        /* Get drm_crtc to timestamp: */
923        crtc = intel_get_crtc_for_pipe(dev, pipe);
924        if (crtc == NULL) {
925                DRM_ERROR("Invalid crtc %u\n", pipe);
926                return -EINVAL;
927        }
928
929        if (!crtc->hwmode.crtc_clock) {
930                DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
931                return -EBUSY;
932        }
933
934        /* Helper routine in DRM core does all the work: */
935        return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
936                                                     vblank_time, flags,
937                                                     &crtc->hwmode);
938}
939
940static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
941{
942        u32 busy_up, busy_down, max_avg, min_avg;
943        u8 new_delay;
944
945        spin_lock(&mchdev_lock);
946
947        I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
948
949        new_delay = dev_priv->ips.cur_delay;
950
951        I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
952        busy_up = I915_READ(RCPREVBSYTUPAVG);
953        busy_down = I915_READ(RCPREVBSYTDNAVG);
954        max_avg = I915_READ(RCBMAXAVG);
955        min_avg = I915_READ(RCBMINAVG);
956
957        /* Handle RCS change request from hw */
958        if (busy_up > max_avg) {
959                if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
960                        new_delay = dev_priv->ips.cur_delay - 1;
961                if (new_delay < dev_priv->ips.max_delay)
962                        new_delay = dev_priv->ips.max_delay;
963        } else if (busy_down < min_avg) {
964                if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
965                        new_delay = dev_priv->ips.cur_delay + 1;
966                if (new_delay > dev_priv->ips.min_delay)
967                        new_delay = dev_priv->ips.min_delay;
968        }
969
970        if (ironlake_set_drps(dev_priv, new_delay))
971                dev_priv->ips.cur_delay = new_delay;
972
973        spin_unlock(&mchdev_lock);
974
975        return;
976}
977
978static void notify_ring(struct intel_engine_cs *engine)
979{
980        smp_store_mb(engine->breadcrumbs.irq_posted, true);
981        if (intel_engine_wakeup(engine))
982                trace_i915_gem_request_notify(engine);
983}
984
985static void vlv_c0_read(struct drm_i915_private *dev_priv,
986                        struct intel_rps_ei *ei)
987{
988        ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
989        ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
990        ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
991}
992
993void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
994{
995        memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
996}
997
998static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
999{
1000        const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1001        struct intel_rps_ei now;
1002        u32 events = 0;
1003
1004        if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1005                return 0;
1006
1007        vlv_c0_read(dev_priv, &now);
1008        if (now.cz_clock == 0)
1009                return 0;
1010
1011        if (prev->cz_clock) {
1012                u64 time, c0;
1013                unsigned int mul;
1014
1015                mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
1016                if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1017                        mul <<= 8;
1018
1019                time = now.cz_clock - prev->cz_clock;
1020                time *= dev_priv->czclk_freq;
1021
1022                /* Workload can be split between render + media,
1023                 * e.g. SwapBuffers being blitted in X after being rendered in
1024                 * mesa. To account for this we need to combine both engines
1025                 * into our activity counter.
1026                 */
1027                c0 = now.render_c0 - prev->render_c0;
1028                c0 += now.media_c0 - prev->media_c0;
1029                c0 *= mul;
1030
1031                if (c0 > time * dev_priv->rps.up_threshold)
1032                        events = GEN6_PM_RP_UP_THRESHOLD;
1033                else if (c0 < time * dev_priv->rps.down_threshold)
1034                        events = GEN6_PM_RP_DOWN_THRESHOLD;
1035        }
1036
1037        dev_priv->rps.ei = now;
1038        return events;
1039}
1040
1041static bool any_waiters(struct drm_i915_private *dev_priv)
1042{
1043        struct intel_engine_cs *engine;
1044
1045        for_each_engine(engine, dev_priv)
1046                if (intel_engine_has_waiter(engine))
1047                        return true;
1048
1049        return false;
1050}
1051
1052static void gen6_pm_rps_work(struct work_struct *work)
1053{
1054        struct drm_i915_private *dev_priv =
1055                container_of(work, struct drm_i915_private, rps.work);
1056        bool client_boost;
1057        int new_delay, adj, min, max;
1058        u32 pm_iir;
1059
1060        spin_lock_irq(&dev_priv->irq_lock);
1061        /* Speed up work cancelation during disabling rps interrupts. */
1062        if (!dev_priv->rps.interrupts_enabled) {
1063                spin_unlock_irq(&dev_priv->irq_lock);
1064                return;
1065        }
1066
1067        pm_iir = dev_priv->rps.pm_iir;
1068        dev_priv->rps.pm_iir = 0;
1069        /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1070        gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1071        client_boost = dev_priv->rps.client_boost;
1072        dev_priv->rps.client_boost = false;
1073        spin_unlock_irq(&dev_priv->irq_lock);
1074
1075        /* Make sure we didn't queue anything we're not going to process. */
1076        WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1077
1078        if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1079                return;
1080
1081        mutex_lock(&dev_priv->rps.hw_lock);
1082
1083        pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1084
1085        adj = dev_priv->rps.last_adj;
1086        new_delay = dev_priv->rps.cur_freq;
1087        min = dev_priv->rps.min_freq_softlimit;
1088        max = dev_priv->rps.max_freq_softlimit;
1089        if (client_boost || any_waiters(dev_priv))
1090                max = dev_priv->rps.max_freq;
1091        if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1092                new_delay = dev_priv->rps.boost_freq;
1093                adj = 0;
1094        } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1095                if (adj > 0)
1096                        adj *= 2;
1097                else /* CHV needs even encode values */
1098                        adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1099                /*
1100                 * For better performance, jump directly
1101                 * to RPe if we're below it.
1102                 */
1103                if (new_delay < dev_priv->rps.efficient_freq - adj) {
1104                        new_delay = dev_priv->rps.efficient_freq;
1105                        adj = 0;
1106                }
1107        } else if (client_boost || any_waiters(dev_priv)) {
1108                adj = 0;
1109        } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1110                if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1111                        new_delay = dev_priv->rps.efficient_freq;
1112                else
1113                        new_delay = dev_priv->rps.min_freq_softlimit;
1114                adj = 0;
1115        } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1116                if (adj < 0)
1117                        adj *= 2;
1118                else /* CHV needs even encode values */
1119                        adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1120        } else { /* unknown event */
1121                adj = 0;
1122        }
1123
1124        dev_priv->rps.last_adj = adj;
1125
1126        /* sysfs frequency interfaces may have snuck in while servicing the
1127         * interrupt
1128         */
1129        new_delay += adj;
1130        new_delay = clamp_t(int, new_delay, min, max);
1131
1132        intel_set_rps(dev_priv, new_delay);
1133
1134        mutex_unlock(&dev_priv->rps.hw_lock);
1135}
1136
1137
1138/**
1139 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1140 * occurred.
1141 * @work: workqueue struct
1142 *
1143 * Doesn't actually do anything except notify userspace. As a consequence of
1144 * this event, userspace should try to remap the bad rows since statistically
1145 * it is likely the same row is more likely to go bad again.
1146 */
1147static void ivybridge_parity_work(struct work_struct *work)
1148{
1149        struct drm_i915_private *dev_priv =
1150                container_of(work, struct drm_i915_private, l3_parity.error_work);
1151        u32 error_status, row, bank, subbank;
1152        char *parity_event[6];
1153        uint32_t misccpctl;
1154        uint8_t slice = 0;
1155
1156        /* We must turn off DOP level clock gating to access the L3 registers.
1157         * In order to prevent a get/put style interface, acquire struct mutex
1158         * any time we access those registers.
1159         */
1160        mutex_lock(&dev_priv->drm.struct_mutex);
1161
1162        /* If we've screwed up tracking, just let the interrupt fire again */
1163        if (WARN_ON(!dev_priv->l3_parity.which_slice))
1164                goto out;
1165
1166        misccpctl = I915_READ(GEN7_MISCCPCTL);
1167        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1168        POSTING_READ(GEN7_MISCCPCTL);
1169
1170        while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1171                i915_reg_t reg;
1172
1173                slice--;
1174                if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1175                        break;
1176
1177                dev_priv->l3_parity.which_slice &= ~(1<<slice);
1178
1179                reg = GEN7_L3CDERRST1(slice);
1180
1181                error_status = I915_READ(reg);
1182                row = GEN7_PARITY_ERROR_ROW(error_status);
1183                bank = GEN7_PARITY_ERROR_BANK(error_status);
1184                subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1185
1186                I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1187                POSTING_READ(reg);
1188
1189                parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1190                parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1191                parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1192                parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1193                parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1194                parity_event[5] = NULL;
1195
1196                kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1197                                   KOBJ_CHANGE, parity_event);
1198
1199                DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1200                          slice, row, bank, subbank);
1201
1202                kfree(parity_event[4]);
1203                kfree(parity_event[3]);
1204                kfree(parity_event[2]);
1205                kfree(parity_event[1]);
1206        }
1207
1208        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1209
1210out:
1211        WARN_ON(dev_priv->l3_parity.which_slice);
1212        spin_lock_irq(&dev_priv->irq_lock);
1213        gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1214        spin_unlock_irq(&dev_priv->irq_lock);
1215
1216        mutex_unlock(&dev_priv->drm.struct_mutex);
1217}
1218
1219static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1220                                               u32 iir)
1221{
1222        if (!HAS_L3_DPF(dev_priv))
1223                return;
1224
1225        spin_lock(&dev_priv->irq_lock);
1226        gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1227        spin_unlock(&dev_priv->irq_lock);
1228
1229        iir &= GT_PARITY_ERROR(dev_priv);
1230        if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1231                dev_priv->l3_parity.which_slice |= 1 << 1;
1232
1233        if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1234                dev_priv->l3_parity.which_slice |= 1 << 0;
1235
1236        queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1237}
1238
1239static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1240                               u32 gt_iir)
1241{
1242        if (gt_iir & GT_RENDER_USER_INTERRUPT)
1243                notify_ring(&dev_priv->engine[RCS]);
1244        if (gt_iir & ILK_BSD_USER_INTERRUPT)
1245                notify_ring(&dev_priv->engine[VCS]);
1246}
1247
1248static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1249                               u32 gt_iir)
1250{
1251        if (gt_iir & GT_RENDER_USER_INTERRUPT)
1252                notify_ring(&dev_priv->engine[RCS]);
1253        if (gt_iir & GT_BSD_USER_INTERRUPT)
1254                notify_ring(&dev_priv->engine[VCS]);
1255        if (gt_iir & GT_BLT_USER_INTERRUPT)
1256                notify_ring(&dev_priv->engine[BCS]);
1257
1258        if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1259                      GT_BSD_CS_ERROR_INTERRUPT |
1260                      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1261                DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1262
1263        if (gt_iir & GT_PARITY_ERROR(dev_priv))
1264                ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1265}
1266
1267static __always_inline void
1268gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1269{
1270        if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1271                notify_ring(engine);
1272        if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1273                tasklet_schedule(&engine->irq_tasklet);
1274}
1275
1276static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1277                                   u32 master_ctl,
1278                                   u32 gt_iir[4])
1279{
1280        irqreturn_t ret = IRQ_NONE;
1281
1282        if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1283                gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1284                if (gt_iir[0]) {
1285                        I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1286                        ret = IRQ_HANDLED;
1287                } else
1288                        DRM_ERROR("The master control interrupt lied (GT0)!\n");
1289        }
1290
1291        if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1292                gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1293                if (gt_iir[1]) {
1294                        I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1295                        ret = IRQ_HANDLED;
1296                } else
1297                        DRM_ERROR("The master control interrupt lied (GT1)!\n");
1298        }
1299
1300        if (master_ctl & GEN8_GT_VECS_IRQ) {
1301                gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1302                if (gt_iir[3]) {
1303                        I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1304                        ret = IRQ_HANDLED;
1305                } else
1306                        DRM_ERROR("The master control interrupt lied (GT3)!\n");
1307        }
1308
1309        if (master_ctl & GEN8_GT_PM_IRQ) {
1310                gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1311                if (gt_iir[2] & dev_priv->pm_rps_events) {
1312                        I915_WRITE_FW(GEN8_GT_IIR(2),
1313                                      gt_iir[2] & dev_priv->pm_rps_events);
1314                        ret = IRQ_HANDLED;
1315                } else
1316                        DRM_ERROR("The master control interrupt lied (PM)!\n");
1317        }
1318
1319        return ret;
1320}
1321
1322static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1323                                u32 gt_iir[4])
1324{
1325        if (gt_iir[0]) {
1326                gen8_cs_irq_handler(&dev_priv->engine[RCS],
1327                                    gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1328                gen8_cs_irq_handler(&dev_priv->engine[BCS],
1329                                    gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1330        }
1331
1332        if (gt_iir[1]) {
1333                gen8_cs_irq_handler(&dev_priv->engine[VCS],
1334                                    gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1335                gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1336                                    gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1337        }
1338
1339        if (gt_iir[3])
1340                gen8_cs_irq_handler(&dev_priv->engine[VECS],
1341                                    gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1342
1343        if (gt_iir[2] & dev_priv->pm_rps_events)
1344                gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1345}
1346
1347static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1348{
1349        switch (port) {
1350        case PORT_A:
1351                return val & PORTA_HOTPLUG_LONG_DETECT;
1352        case PORT_B:
1353                return val & PORTB_HOTPLUG_LONG_DETECT;
1354        case PORT_C:
1355                return val & PORTC_HOTPLUG_LONG_DETECT;
1356        default:
1357                return false;
1358        }
1359}
1360
1361static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1362{
1363        switch (port) {
1364        case PORT_E:
1365                return val & PORTE_HOTPLUG_LONG_DETECT;
1366        default:
1367                return false;
1368        }
1369}
1370
1371static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1372{
1373        switch (port) {
1374        case PORT_A:
1375                return val & PORTA_HOTPLUG_LONG_DETECT;
1376        case PORT_B:
1377                return val & PORTB_HOTPLUG_LONG_DETECT;
1378        case PORT_C:
1379                return val & PORTC_HOTPLUG_LONG_DETECT;
1380        case PORT_D:
1381                return val & PORTD_HOTPLUG_LONG_DETECT;
1382        default:
1383                return false;
1384        }
1385}
1386
1387static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1388{
1389        switch (port) {
1390        case PORT_A:
1391                return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1392        default:
1393                return false;
1394        }
1395}
1396
1397static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1398{
1399        switch (port) {
1400        case PORT_B:
1401                return val & PORTB_HOTPLUG_LONG_DETECT;
1402        case PORT_C:
1403                return val & PORTC_HOTPLUG_LONG_DETECT;
1404        case PORT_D:
1405                return val & PORTD_HOTPLUG_LONG_DETECT;
1406        default:
1407                return false;
1408        }
1409}
1410
1411static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1412{
1413        switch (port) {
1414        case PORT_B:
1415                return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1416        case PORT_C:
1417                return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1418        case PORT_D:
1419                return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1420        default:
1421                return false;
1422        }
1423}
1424
1425/*
1426 * Get a bit mask of pins that have triggered, and which ones may be long.
1427 * This can be called multiple times with the same masks to accumulate
1428 * hotplug detection results from several registers.
1429 *
1430 * Note that the caller is expected to zero out the masks initially.
1431 */
1432static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1433                             u32 hotplug_trigger, u32 dig_hotplug_reg,
1434                             const u32 hpd[HPD_NUM_PINS],
1435                             bool long_pulse_detect(enum port port, u32 val))
1436{
1437        enum port port;
1438        int i;
1439
1440        for_each_hpd_pin(i) {
1441                if ((hpd[i] & hotplug_trigger) == 0)
1442                        continue;
1443
1444                *pin_mask |= BIT(i);
1445
1446                if (!intel_hpd_pin_to_port(i, &port))
1447                        continue;
1448
1449                if (long_pulse_detect(port, dig_hotplug_reg))
1450                        *long_mask |= BIT(i);
1451        }
1452
1453        DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1454                         hotplug_trigger, dig_hotplug_reg, *pin_mask);
1455
1456}
1457
1458static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1459{
1460        wake_up_all(&dev_priv->gmbus_wait_queue);
1461}
1462
1463static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1464{
1465        wake_up_all(&dev_priv->gmbus_wait_queue);
1466}
1467
1468#if defined(CONFIG_DEBUG_FS)
1469static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1470                                         enum pipe pipe,
1471                                         uint32_t crc0, uint32_t crc1,
1472                                         uint32_t crc2, uint32_t crc3,
1473                                         uint32_t crc4)
1474{
1475        struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1476        struct intel_pipe_crc_entry *entry;
1477        int head, tail;
1478
1479        spin_lock(&pipe_crc->lock);
1480
1481        if (!pipe_crc->entries) {
1482                spin_unlock(&pipe_crc->lock);
1483                DRM_DEBUG_KMS("spurious interrupt\n");
1484                return;
1485        }
1486
1487        head = pipe_crc->head;
1488        tail = pipe_crc->tail;
1489
1490        if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1491                spin_unlock(&pipe_crc->lock);
1492                DRM_ERROR("CRC buffer overflowing\n");
1493                return;
1494        }
1495
1496        entry = &pipe_crc->entries[head];
1497
1498        entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1499                                                                 pipe);
1500        entry->crc[0] = crc0;
1501        entry->crc[1] = crc1;
1502        entry->crc[2] = crc2;
1503        entry->crc[3] = crc3;
1504        entry->crc[4] = crc4;
1505
1506        head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1507        pipe_crc->head = head;
1508
1509        spin_unlock(&pipe_crc->lock);
1510
1511        wake_up_interruptible(&pipe_crc->wq);
1512}
1513#else
1514static inline void
1515display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1516                             enum pipe pipe,
1517                             uint32_t crc0, uint32_t crc1,
1518                             uint32_t crc2, uint32_t crc3,
1519                             uint32_t crc4) {}
1520#endif
1521
1522
1523static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1524                                     enum pipe pipe)
1525{
1526        display_pipe_crc_irq_handler(dev_priv, pipe,
1527                                     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1528                                     0, 0, 0, 0);
1529}
1530
1531static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1532                                     enum pipe pipe)
1533{
1534        display_pipe_crc_irq_handler(dev_priv, pipe,
1535                                     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1536                                     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1537                                     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1538                                     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1539                                     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1540}
1541
1542static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1543                                      enum pipe pipe)
1544{
1545        uint32_t res1, res2;
1546
1547        if (INTEL_GEN(dev_priv) >= 3)
1548                res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1549        else
1550                res1 = 0;
1551
1552        if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1553                res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1554        else
1555                res2 = 0;
1556
1557        display_pipe_crc_irq_handler(dev_priv, pipe,
1558                                     I915_READ(PIPE_CRC_RES_RED(pipe)),
1559                                     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1560                                     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1561                                     res1, res2);
1562}
1563
1564/* The RPS events need forcewake, so we add them to a work queue and mask their
1565 * IMR bits until the work is done. Other interrupts can be processed without
1566 * the work queue. */
1567static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1568{
1569        if (pm_iir & dev_priv->pm_rps_events) {
1570                spin_lock(&dev_priv->irq_lock);
1571                gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1572                if (dev_priv->rps.interrupts_enabled) {
1573                        dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1574                        schedule_work(&dev_priv->rps.work);
1575                }
1576                spin_unlock(&dev_priv->irq_lock);
1577        }
1578
1579        if (INTEL_INFO(dev_priv)->gen >= 8)
1580                return;
1581
1582        if (HAS_VEBOX(dev_priv)) {
1583                if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1584                        notify_ring(&dev_priv->engine[VECS]);
1585
1586                if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1587                        DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1588        }
1589}
1590
1591static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1592                                     enum pipe pipe)
1593{
1594        bool ret;
1595
1596        ret = drm_handle_vblank(&dev_priv->drm, pipe);
1597        if (ret)
1598                intel_finish_page_flip_mmio(dev_priv, pipe);
1599
1600        return ret;
1601}
1602
1603static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1604                                        u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1605{
1606        int pipe;
1607
1608        spin_lock(&dev_priv->irq_lock);
1609
1610        if (!dev_priv->display_irqs_enabled) {
1611                spin_unlock(&dev_priv->irq_lock);
1612                return;
1613        }
1614
1615        for_each_pipe(dev_priv, pipe) {
1616                i915_reg_t reg;
1617                u32 mask, iir_bit = 0;
1618
1619                /*
1620                 * PIPESTAT bits get signalled even when the interrupt is
1621                 * disabled with the mask bits, and some of the status bits do
1622                 * not generate interrupts at all (like the underrun bit). Hence
1623                 * we need to be careful that we only handle what we want to
1624                 * handle.
1625                 */
1626
1627                /* fifo underruns are filterered in the underrun handler. */
1628                mask = PIPE_FIFO_UNDERRUN_STATUS;
1629
1630                switch (pipe) {
1631                case PIPE_A:
1632                        iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1633                        break;
1634                case PIPE_B:
1635                        iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1636                        break;
1637                case PIPE_C:
1638                        iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1639                        break;
1640                }
1641                if (iir & iir_bit)
1642                        mask |= dev_priv->pipestat_irq_mask[pipe];
1643
1644                if (!mask)
1645                        continue;
1646
1647                reg = PIPESTAT(pipe);
1648                mask |= PIPESTAT_INT_ENABLE_MASK;
1649                pipe_stats[pipe] = I915_READ(reg) & mask;
1650
1651                /*
1652                 * Clear the PIPE*STAT regs before the IIR
1653                 */
1654                if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1655                                        PIPESTAT_INT_STATUS_MASK))
1656                        I915_WRITE(reg, pipe_stats[pipe]);
1657        }
1658        spin_unlock(&dev_priv->irq_lock);
1659}
1660
1661static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1662                                            u32 pipe_stats[I915_MAX_PIPES])
1663{
1664        enum pipe pipe;
1665
1666        for_each_pipe(dev_priv, pipe) {
1667                if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1668                    intel_pipe_handle_vblank(dev_priv, pipe))
1669                        intel_check_page_flip(dev_priv, pipe);
1670
1671                if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1672                        intel_finish_page_flip_cs(dev_priv, pipe);
1673
1674                if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1675                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1676
1677                if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1678                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1679        }
1680
1681        if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1682                gmbus_irq_handler(dev_priv);
1683}
1684
1685static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1686{
1687        u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1688
1689        if (hotplug_status)
1690                I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1691
1692        return hotplug_status;
1693}
1694
1695static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1696                                 u32 hotplug_status)
1697{
1698        u32 pin_mask = 0, long_mask = 0;
1699
1700        if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1701            IS_CHERRYVIEW(dev_priv)) {
1702                u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1703
1704                if (hotplug_trigger) {
1705                        intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1706                                           hotplug_trigger, hpd_status_g4x,
1707                                           i9xx_port_hotplug_long_detect);
1708
1709                        intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1710                }
1711
1712                if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1713                        dp_aux_irq_handler(dev_priv);
1714        } else {
1715                u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1716
1717                if (hotplug_trigger) {
1718                        intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1719                                           hotplug_trigger, hpd_status_i915,
1720                                           i9xx_port_hotplug_long_detect);
1721                        intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1722                }
1723        }
1724}
1725
1726static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1727{
1728        struct drm_device *dev = arg;
1729        struct drm_i915_private *dev_priv = to_i915(dev);
1730        irqreturn_t ret = IRQ_NONE;
1731
1732        if (!intel_irqs_enabled(dev_priv))
1733                return IRQ_NONE;
1734
1735        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1736        disable_rpm_wakeref_asserts(dev_priv);
1737
1738        do {
1739                u32 iir, gt_iir, pm_iir;
1740                u32 pipe_stats[I915_MAX_PIPES] = {};
1741                u32 hotplug_status = 0;
1742                u32 ier = 0;
1743
1744                gt_iir = I915_READ(GTIIR);
1745                pm_iir = I915_READ(GEN6_PMIIR);
1746                iir = I915_READ(VLV_IIR);
1747
1748                if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1749                        break;
1750
1751                ret = IRQ_HANDLED;
1752
1753                /*
1754                 * Theory on interrupt generation, based on empirical evidence:
1755                 *
1756                 * x = ((VLV_IIR & VLV_IER) ||
1757                 *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1758                 *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1759                 *
1760                 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1761                 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1762                 * guarantee the CPU interrupt will be raised again even if we
1763                 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1764                 * bits this time around.
1765                 */
1766                I915_WRITE(VLV_MASTER_IER, 0);
1767                ier = I915_READ(VLV_IER);
1768                I915_WRITE(VLV_IER, 0);
1769
1770                if (gt_iir)
1771                        I915_WRITE(GTIIR, gt_iir);
1772                if (pm_iir)
1773                        I915_WRITE(GEN6_PMIIR, pm_iir);
1774
1775                if (iir & I915_DISPLAY_PORT_INTERRUPT)
1776                        hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1777
1778                /* Call regardless, as some status bits might not be
1779                 * signalled in iir */
1780                valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1781
1782                /*
1783                 * VLV_IIR is single buffered, and reflects the level
1784                 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1785                 */
1786                if (iir)
1787                        I915_WRITE(VLV_IIR, iir);
1788
1789                I915_WRITE(VLV_IER, ier);
1790                I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1791                POSTING_READ(VLV_MASTER_IER);
1792
1793                if (gt_iir)
1794                        snb_gt_irq_handler(dev_priv, gt_iir);
1795                if (pm_iir)
1796                        gen6_rps_irq_handler(dev_priv, pm_iir);
1797
1798                if (hotplug_status)
1799                        i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1800
1801                valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1802        } while (0);
1803
1804        enable_rpm_wakeref_asserts(dev_priv);
1805
1806        return ret;
1807}
1808
1809static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1810{
1811        struct drm_device *dev = arg;
1812        struct drm_i915_private *dev_priv = to_i915(dev);
1813        irqreturn_t ret = IRQ_NONE;
1814
1815        if (!intel_irqs_enabled(dev_priv))
1816                return IRQ_NONE;
1817
1818        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1819        disable_rpm_wakeref_asserts(dev_priv);
1820
1821        do {
1822                u32 master_ctl, iir;
1823                u32 gt_iir[4] = {};
1824                u32 pipe_stats[I915_MAX_PIPES] = {};
1825                u32 hotplug_status = 0;
1826                u32 ier = 0;
1827
1828                master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1829                iir = I915_READ(VLV_IIR);
1830
1831                if (master_ctl == 0 && iir == 0)
1832                        break;
1833
1834                ret = IRQ_HANDLED;
1835
1836                /*
1837                 * Theory on interrupt generation, based on empirical evidence:
1838                 *
1839                 * x = ((VLV_IIR & VLV_IER) ||
1840                 *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1841                 *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1842                 *
1843                 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1844                 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1845                 * guarantee the CPU interrupt will be raised again even if we
1846                 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1847                 * bits this time around.
1848                 */
1849                I915_WRITE(GEN8_MASTER_IRQ, 0);
1850                ier = I915_READ(VLV_IER);
1851                I915_WRITE(VLV_IER, 0);
1852
1853                gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1854
1855                if (iir & I915_DISPLAY_PORT_INTERRUPT)
1856                        hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1857
1858                /* Call regardless, as some status bits might not be
1859                 * signalled in iir */
1860                valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1861
1862                /*
1863                 * VLV_IIR is single buffered, and reflects the level
1864                 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1865                 */
1866                if (iir)
1867                        I915_WRITE(VLV_IIR, iir);
1868
1869                I915_WRITE(VLV_IER, ier);
1870                I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1871                POSTING_READ(GEN8_MASTER_IRQ);
1872
1873                gen8_gt_irq_handler(dev_priv, gt_iir);
1874
1875                if (hotplug_status)
1876                        i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1877
1878                valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1879        } while (0);
1880
1881        enable_rpm_wakeref_asserts(dev_priv);
1882
1883        return ret;
1884}
1885
1886static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1887                                u32 hotplug_trigger,
1888                                const u32 hpd[HPD_NUM_PINS])
1889{
1890        u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1891
1892        /*
1893         * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1894         * unless we touch the hotplug register, even if hotplug_trigger is
1895         * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1896         * errors.
1897         */
1898        dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1899        if (!hotplug_trigger) {
1900                u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1901                        PORTD_HOTPLUG_STATUS_MASK |
1902                        PORTC_HOTPLUG_STATUS_MASK |
1903                        PORTB_HOTPLUG_STATUS_MASK;
1904                dig_hotplug_reg &= ~mask;
1905        }
1906
1907        I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1908        if (!hotplug_trigger)
1909                return;
1910
1911        intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1912                           dig_hotplug_reg, hpd,
1913                           pch_port_hotplug_long_detect);
1914
1915        intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1916}
1917
1918static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1919{
1920        int pipe;
1921        u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1922
1923        ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1924
1925        if (pch_iir & SDE_AUDIO_POWER_MASK) {
1926                int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1927                               SDE_AUDIO_POWER_SHIFT);
1928                DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1929                                 port_name(port));
1930        }
1931
1932        if (pch_iir & SDE_AUX_MASK)
1933                dp_aux_irq_handler(dev_priv);
1934
1935        if (pch_iir & SDE_GMBUS)
1936                gmbus_irq_handler(dev_priv);
1937
1938        if (pch_iir & SDE_AUDIO_HDCP_MASK)
1939                DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1940
1941        if (pch_iir & SDE_AUDIO_TRANS_MASK)
1942                DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1943
1944        if (pch_iir & SDE_POISON)
1945                DRM_ERROR("PCH poison interrupt\n");
1946
1947        if (pch_iir & SDE_FDI_MASK)
1948                for_each_pipe(dev_priv, pipe)
1949                        DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1950                                         pipe_name(pipe),
1951                                         I915_READ(FDI_RX_IIR(pipe)));
1952
1953        if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1954                DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1955
1956        if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1957                DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1958
1959        if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1960                intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1961
1962        if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1963                intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1964}
1965
1966static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1967{
1968        u32 err_int = I915_READ(GEN7_ERR_INT);
1969        enum pipe pipe;
1970
1971        if (err_int & ERR_INT_POISON)
1972                DRM_ERROR("Poison interrupt\n");
1973
1974        for_each_pipe(dev_priv, pipe) {
1975                if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1976                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1977
1978                if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1979                        if (IS_IVYBRIDGE(dev_priv))
1980                                ivb_pipe_crc_irq_handler(dev_priv, pipe);
1981                        else
1982                                hsw_pipe_crc_irq_handler(dev_priv, pipe);
1983                }
1984        }
1985
1986        I915_WRITE(GEN7_ERR_INT, err_int);
1987}
1988
1989static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1990{
1991        u32 serr_int = I915_READ(SERR_INT);
1992
1993        if (serr_int & SERR_INT_POISON)
1994                DRM_ERROR("PCH poison interrupt\n");
1995
1996        if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1997                intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1998
1999        if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2000                intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2001
2002        if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2003                intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2004
2005        I915_WRITE(SERR_INT, serr_int);
2006}
2007
2008static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2009{
2010        int pipe;
2011        u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2012
2013        ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2014
2015        if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2016                int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2017                               SDE_AUDIO_POWER_SHIFT_CPT);
2018                DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2019                                 port_name(port));
2020        }
2021
2022        if (pch_iir & SDE_AUX_MASK_CPT)
2023                dp_aux_irq_handler(dev_priv);
2024
2025        if (pch_iir & SDE_GMBUS_CPT)
2026                gmbus_irq_handler(dev_priv);
2027
2028        if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2029                DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2030
2031        if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2032                DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2033
2034        if (pch_iir & SDE_FDI_MASK_CPT)
2035                for_each_pipe(dev_priv, pipe)
2036                        DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2037                                         pipe_name(pipe),
2038                                         I915_READ(FDI_RX_IIR(pipe)));
2039
2040        if (pch_iir & SDE_ERROR_CPT)
2041                cpt_serr_int_handler(dev_priv);
2042}
2043
2044static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2045{
2046        u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2047                ~SDE_PORTE_HOTPLUG_SPT;
2048        u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2049        u32 pin_mask = 0, long_mask = 0;
2050
2051        if (hotplug_trigger) {
2052                u32 dig_hotplug_reg;
2053
2054                dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2055                I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2056
2057                intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2058                                   dig_hotplug_reg, hpd_spt,
2059                                   spt_port_hotplug_long_detect);
2060        }
2061
2062        if (hotplug2_trigger) {
2063                u32 dig_hotplug_reg;
2064
2065                dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2066                I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2067
2068                intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2069                                   dig_hotplug_reg, hpd_spt,
2070                                   spt_port_hotplug2_long_detect);
2071        }
2072
2073        if (pin_mask)
2074                intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2075
2076        if (pch_iir & SDE_GMBUS_CPT)
2077                gmbus_irq_handler(dev_priv);
2078}
2079
2080static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2081                                u32 hotplug_trigger,
2082                                const u32 hpd[HPD_NUM_PINS])
2083{
2084        u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2085
2086        dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2087        I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2088
2089        intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2090                           dig_hotplug_reg, hpd,
2091                           ilk_port_hotplug_long_detect);
2092
2093        intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2094}
2095
2096static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2097                                    u32 de_iir)
2098{
2099        enum pipe pipe;
2100        u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2101
2102        if (hotplug_trigger)
2103                ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2104
2105        if (de_iir & DE_AUX_CHANNEL_A)
2106                dp_aux_irq_handler(dev_priv);
2107
2108        if (de_iir & DE_GSE)
2109                intel_opregion_asle_intr(dev_priv);
2110
2111        if (de_iir & DE_POISON)
2112                DRM_ERROR("Poison interrupt\n");
2113
2114        for_each_pipe(dev_priv, pipe) {
2115                if (de_iir & DE_PIPE_VBLANK(pipe) &&
2116                    intel_pipe_handle_vblank(dev_priv, pipe))
2117                        intel_check_page_flip(dev_priv, pipe);
2118
2119                if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2120                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2121
2122                if (de_iir & DE_PIPE_CRC_DONE(pipe))
2123                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2124
2125                /* plane/pipes map 1:1 on ilk+ */
2126                if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2127                        intel_finish_page_flip_cs(dev_priv, pipe);
2128        }
2129
2130        /* check event from PCH */
2131        if (de_iir & DE_PCH_EVENT) {
2132                u32 pch_iir = I915_READ(SDEIIR);
2133
2134                if (HAS_PCH_CPT(dev_priv))
2135                        cpt_irq_handler(dev_priv, pch_iir);
2136                else
2137                        ibx_irq_handler(dev_priv, pch_iir);
2138
2139                /* should clear PCH hotplug event before clear CPU irq */
2140                I915_WRITE(SDEIIR, pch_iir);
2141        }
2142
2143        if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2144                ironlake_rps_change_irq_handler(dev_priv);
2145}
2146
2147static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2148                                    u32 de_iir)
2149{
2150        enum pipe pipe;
2151        u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2152
2153        if (hotplug_trigger)
2154                ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2155
2156        if (de_iir & DE_ERR_INT_IVB)
2157                ivb_err_int_handler(dev_priv);
2158
2159        if (de_iir & DE_AUX_CHANNEL_A_IVB)
2160                dp_aux_irq_handler(dev_priv);
2161
2162        if (de_iir & DE_GSE_IVB)
2163                intel_opregion_asle_intr(dev_priv);
2164
2165        for_each_pipe(dev_priv, pipe) {
2166                if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2167                    intel_pipe_handle_vblank(dev_priv, pipe))
2168                        intel_check_page_flip(dev_priv, pipe);
2169
2170                /* plane/pipes map 1:1 on ilk+ */
2171                if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2172                        intel_finish_page_flip_cs(dev_priv, pipe);
2173        }
2174
2175        /* check event from PCH */
2176        if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2177                u32 pch_iir = I915_READ(SDEIIR);
2178
2179                cpt_irq_handler(dev_priv, pch_iir);
2180
2181                /* clear PCH hotplug event before clear CPU irq */
2182                I915_WRITE(SDEIIR, pch_iir);
2183        }
2184}
2185
2186/*
2187 * To handle irqs with the minimum potential races with fresh interrupts, we:
2188 * 1 - Disable Master Interrupt Control.
2189 * 2 - Find the source(s) of the interrupt.
2190 * 3 - Clear the Interrupt Identity bits (IIR).
2191 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2192 * 5 - Re-enable Master Interrupt Control.
2193 */
2194static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2195{
2196        struct drm_device *dev = arg;
2197        struct drm_i915_private *dev_priv = to_i915(dev);
2198        u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2199        irqreturn_t ret = IRQ_NONE;
2200
2201        if (!intel_irqs_enabled(dev_priv))
2202                return IRQ_NONE;
2203
2204        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2205        disable_rpm_wakeref_asserts(dev_priv);
2206
2207        /* disable master interrupt before clearing iir  */
2208        de_ier = I915_READ(DEIER);
2209        I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2210        POSTING_READ(DEIER);
2211
2212        /* Disable south interrupts. We'll only write to SDEIIR once, so further
2213         * interrupts will will be stored on its back queue, and then we'll be
2214         * able to process them after we restore SDEIER (as soon as we restore
2215         * it, we'll get an interrupt if SDEIIR still has something to process
2216         * due to its back queue). */
2217        if (!HAS_PCH_NOP(dev_priv)) {
2218                sde_ier = I915_READ(SDEIER);
2219                I915_WRITE(SDEIER, 0);
2220                POSTING_READ(SDEIER);
2221        }
2222
2223        /* Find, clear, then process each source of interrupt */
2224
2225        gt_iir = I915_READ(GTIIR);
2226        if (gt_iir) {
2227                I915_WRITE(GTIIR, gt_iir);
2228                ret = IRQ_HANDLED;
2229                if (INTEL_GEN(dev_priv) >= 6)
2230                        snb_gt_irq_handler(dev_priv, gt_iir);
2231                else
2232                        ilk_gt_irq_handler(dev_priv, gt_iir);
2233        }
2234
2235        de_iir = I915_READ(DEIIR);
2236        if (de_iir) {
2237                I915_WRITE(DEIIR, de_iir);
2238                ret = IRQ_HANDLED;
2239                if (INTEL_GEN(dev_priv) >= 7)
2240                        ivb_display_irq_handler(dev_priv, de_iir);
2241                else
2242                        ilk_display_irq_handler(dev_priv, de_iir);
2243        }
2244
2245        if (INTEL_GEN(dev_priv) >= 6) {
2246                u32 pm_iir = I915_READ(GEN6_PMIIR);
2247                if (pm_iir) {
2248                        I915_WRITE(GEN6_PMIIR, pm_iir);
2249                        ret = IRQ_HANDLED;
2250                        gen6_rps_irq_handler(dev_priv, pm_iir);
2251                }
2252        }
2253
2254        I915_WRITE(DEIER, de_ier);
2255        POSTING_READ(DEIER);
2256        if (!HAS_PCH_NOP(dev_priv)) {
2257                I915_WRITE(SDEIER, sde_ier);
2258                POSTING_READ(SDEIER);
2259        }
2260
2261        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2262        enable_rpm_wakeref_asserts(dev_priv);
2263
2264        return ret;
2265}
2266
2267static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2268                                u32 hotplug_trigger,
2269                                const u32 hpd[HPD_NUM_PINS])
2270{
2271        u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2272
2273        dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2274        I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2275
2276        intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2277                           dig_hotplug_reg, hpd,
2278                           bxt_port_hotplug_long_detect);
2279
2280        intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2281}
2282
2283static irqreturn_t
2284gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2285{
2286        irqreturn_t ret = IRQ_NONE;
2287        u32 iir;
2288        enum pipe pipe;
2289
2290        if (master_ctl & GEN8_DE_MISC_IRQ) {
2291                iir = I915_READ(GEN8_DE_MISC_IIR);
2292                if (iir) {
2293                        I915_WRITE(GEN8_DE_MISC_IIR, iir);
2294                        ret = IRQ_HANDLED;
2295                        if (iir & GEN8_DE_MISC_GSE)
2296                                intel_opregion_asle_intr(dev_priv);
2297                        else
2298                                DRM_ERROR("Unexpected DE Misc interrupt\n");
2299                }
2300                else
2301                        DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2302        }
2303
2304        if (master_ctl & GEN8_DE_PORT_IRQ) {
2305                iir = I915_READ(GEN8_DE_PORT_IIR);
2306                if (iir) {
2307                        u32 tmp_mask;
2308                        bool found = false;
2309
2310                        I915_WRITE(GEN8_DE_PORT_IIR, iir);
2311                        ret = IRQ_HANDLED;
2312
2313                        tmp_mask = GEN8_AUX_CHANNEL_A;
2314                        if (INTEL_INFO(dev_priv)->gen >= 9)
2315                                tmp_mask |= GEN9_AUX_CHANNEL_B |
2316                                            GEN9_AUX_CHANNEL_C |
2317                                            GEN9_AUX_CHANNEL_D;
2318
2319                        if (iir & tmp_mask) {
2320                                dp_aux_irq_handler(dev_priv);
2321                                found = true;
2322                        }
2323
2324                        if (IS_BROXTON(dev_priv)) {
2325                                tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2326                                if (tmp_mask) {
2327                                        bxt_hpd_irq_handler(dev_priv, tmp_mask,
2328                                                            hpd_bxt);
2329                                        found = true;
2330                                }
2331                        } else if (IS_BROADWELL(dev_priv)) {
2332                                tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2333                                if (tmp_mask) {
2334                                        ilk_hpd_irq_handler(dev_priv,
2335                                                            tmp_mask, hpd_bdw);
2336                                        found = true;
2337                                }
2338                        }
2339
2340                        if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2341                                gmbus_irq_handler(dev_priv);
2342                                found = true;
2343                        }
2344
2345                        if (!found)
2346                                DRM_ERROR("Unexpected DE Port interrupt\n");
2347                }
2348                else
2349                        DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2350        }
2351
2352        for_each_pipe(dev_priv, pipe) {
2353                u32 flip_done, fault_errors;
2354
2355                if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2356                        continue;
2357
2358                iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2359                if (!iir) {
2360                        DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2361                        continue;
2362                }
2363
2364                ret = IRQ_HANDLED;
2365                I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2366
2367                if (iir & GEN8_PIPE_VBLANK &&
2368                    intel_pipe_handle_vblank(dev_priv, pipe))
2369                        intel_check_page_flip(dev_priv, pipe);
2370
2371                flip_done = iir;
2372                if (INTEL_INFO(dev_priv)->gen >= 9)
2373                        flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2374                else
2375                        flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2376
2377                if (flip_done)
2378                        intel_finish_page_flip_cs(dev_priv, pipe);
2379
2380                if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2381                        hsw_pipe_crc_irq_handler(dev_priv, pipe);
2382
2383                if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2384                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2385
2386                fault_errors = iir;
2387                if (INTEL_INFO(dev_priv)->gen >= 9)
2388                        fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2389                else
2390                        fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2391
2392                if (fault_errors)
2393                        DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2394                                  pipe_name(pipe),
2395                                  fault_errors);
2396        }
2397
2398        if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2399            master_ctl & GEN8_DE_PCH_IRQ) {
2400                /*
2401                 * FIXME(BDW): Assume for now that the new interrupt handling
2402                 * scheme also closed the SDE interrupt handling race we've seen
2403                 * on older pch-split platforms. But this needs testing.
2404                 */
2405                iir = I915_READ(SDEIIR);
2406                if (iir) {
2407                        I915_WRITE(SDEIIR, iir);
2408                        ret = IRQ_HANDLED;
2409
2410                        if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2411                                spt_irq_handler(dev_priv, iir);
2412                        else
2413                                cpt_irq_handler(dev_priv, iir);
2414                } else {
2415                        /*
2416                         * Like on previous PCH there seems to be something
2417                         * fishy going on with forwarding PCH interrupts.
2418                         */
2419                        DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2420                }
2421        }
2422
2423        return ret;
2424}
2425
2426static irqreturn_t gen8_irq_handler(int irq, void *arg)
2427{
2428        struct drm_device *dev = arg;
2429        struct drm_i915_private *dev_priv = to_i915(dev);
2430        u32 master_ctl;
2431        u32 gt_iir[4] = {};
2432        irqreturn_t ret;
2433
2434        if (!intel_irqs_enabled(dev_priv))
2435                return IRQ_NONE;
2436
2437        master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2438        master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2439        if (!master_ctl)
2440                return IRQ_NONE;
2441
2442        I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2443
2444        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2445        disable_rpm_wakeref_asserts(dev_priv);
2446
2447        /* Find, clear, then process each source of interrupt */
2448        ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2449        gen8_gt_irq_handler(dev_priv, gt_iir);
2450        ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2451
2452        I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2453        POSTING_READ_FW(GEN8_MASTER_IRQ);
2454
2455        enable_rpm_wakeref_asserts(dev_priv);
2456
2457        return ret;
2458}
2459
2460static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2461{
2462        /*
2463         * Notify all waiters for GPU completion events that reset state has
2464         * been changed, and that they need to restart their wait after
2465         * checking for potential errors (and bail out to drop locks if there is
2466         * a gpu reset pending so that i915_error_work_func can acquire them).
2467         */
2468
2469        /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2470        wake_up_all(&dev_priv->gpu_error.wait_queue);
2471
2472        /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2473        wake_up_all(&dev_priv->pending_flip_queue);
2474}
2475
2476/**
2477 * i915_reset_and_wakeup - do process context error handling work
2478 * @dev_priv: i915 device private
2479 *
2480 * Fire an error uevent so userspace can see that a hang or error
2481 * was detected.
2482 */
2483static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2484{
2485        struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2486        char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2487        char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2488        char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2489
2490        kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2491
2492        DRM_DEBUG_DRIVER("resetting chip\n");
2493        kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2494
2495        /*
2496         * In most cases it's guaranteed that we get here with an RPM
2497         * reference held, for example because there is a pending GPU
2498         * request that won't finish until the reset is done. This
2499         * isn't the case at least when we get here by doing a
2500         * simulated reset via debugs, so get an RPM reference.
2501         */
2502        intel_runtime_pm_get(dev_priv);
2503        intel_prepare_reset(dev_priv);
2504
2505        do {
2506                /*
2507                 * All state reset _must_ be completed before we update the
2508                 * reset counter, for otherwise waiters might miss the reset
2509                 * pending state and not properly drop locks, resulting in
2510                 * deadlocks with the reset work.
2511                 */
2512                if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2513                        i915_reset(dev_priv);
2514                        mutex_unlock(&dev_priv->drm.struct_mutex);
2515                }
2516
2517                /* We need to wait for anyone holding the lock to wakeup */
2518        } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2519                                     I915_RESET_IN_PROGRESS,
2520                                     TASK_UNINTERRUPTIBLE,
2521                                     HZ));
2522
2523        intel_finish_reset(dev_priv);
2524        intel_runtime_pm_put(dev_priv);
2525
2526        if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2527                kobject_uevent_env(kobj,
2528                                   KOBJ_CHANGE, reset_done_event);
2529
2530        /*
2531         * Note: The wake_up also serves as a memory barrier so that
2532         * waiters see the updated value of the dev_priv->gpu_error.
2533         */
2534        wake_up_all(&dev_priv->gpu_error.reset_queue);
2535}
2536
2537static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2538{
2539        uint32_t instdone[I915_NUM_INSTDONE_REG];
2540        u32 eir = I915_READ(EIR);
2541        int pipe, i;
2542
2543        if (!eir)
2544                return;
2545
2546        pr_err("render error detected, EIR: 0x%08x\n", eir);
2547
2548        i915_get_extra_instdone(dev_priv, instdone);
2549
2550        if (IS_G4X(dev_priv)) {
2551                if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2552                        u32 ipeir = I915_READ(IPEIR_I965);
2553
2554                        pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2555                        pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2556                        for (i = 0; i < ARRAY_SIZE(instdone); i++)
2557                                pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2558                        pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2559                        pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2560                        I915_WRITE(IPEIR_I965, ipeir);
2561                        POSTING_READ(IPEIR_I965);
2562                }
2563                if (eir & GM45_ERROR_PAGE_TABLE) {
2564                        u32 pgtbl_err = I915_READ(PGTBL_ER);
2565                        pr_err("page table error\n");
2566                        pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2567                        I915_WRITE(PGTBL_ER, pgtbl_err);
2568                        POSTING_READ(PGTBL_ER);
2569                }
2570        }
2571
2572        if (!IS_GEN2(dev_priv)) {
2573                if (eir & I915_ERROR_PAGE_TABLE) {
2574                        u32 pgtbl_err = I915_READ(PGTBL_ER);
2575                        pr_err("page table error\n");
2576                        pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2577                        I915_WRITE(PGTBL_ER, pgtbl_err);
2578                        POSTING_READ(PGTBL_ER);
2579                }
2580        }
2581
2582        if (eir & I915_ERROR_MEMORY_REFRESH) {
2583                pr_err("memory refresh error:\n");
2584                for_each_pipe(dev_priv, pipe)
2585                        pr_err("pipe %c stat: 0x%08x\n",
2586                               pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2587                /* pipestat has already been acked */
2588        }
2589        if (eir & I915_ERROR_INSTRUCTION) {
2590                pr_err("instruction error\n");
2591                pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2592                for (i = 0; i < ARRAY_SIZE(instdone); i++)
2593                        pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2594                if (INTEL_GEN(dev_priv) < 4) {
2595                        u32 ipeir = I915_READ(IPEIR);
2596
2597                        pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2598                        pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2599                        pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2600                        I915_WRITE(IPEIR, ipeir);
2601                        POSTING_READ(IPEIR);
2602                } else {
2603                        u32 ipeir = I915_READ(IPEIR_I965);
2604
2605                        pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2606                        pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2607                        pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2608                        pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2609                        I915_WRITE(IPEIR_I965, ipeir);
2610                        POSTING_READ(IPEIR_I965);
2611                }
2612        }
2613
2614        I915_WRITE(EIR, eir);
2615        POSTING_READ(EIR);
2616        eir = I915_READ(EIR);
2617        if (eir) {
2618                /*
2619                 * some errors might have become stuck,
2620                 * mask them.
2621                 */
2622                DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2623                I915_WRITE(EMR, I915_READ(EMR) | eir);
2624                I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2625        }
2626}
2627
2628/**
2629 * i915_handle_error - handle a gpu error
2630 * @dev_priv: i915 device private
2631 * @engine_mask: mask representing engines that are hung
2632 * Do some basic checking of register state at error time and
2633 * dump it to the syslog.  Also call i915_capture_error_state() to make
2634 * sure we get a record and make it available in debugfs.  Fire a uevent
2635 * so userspace knows something bad happened (should trigger collection
2636 * of a ring dump etc.).
2637 * @fmt: Error message format string
2638 */
2639void i915_handle_error(struct drm_i915_private *dev_priv,
2640                       u32 engine_mask,
2641                       const char *fmt, ...)
2642{
2643        va_list args;
2644        char error_msg[80];
2645
2646        va_start(args, fmt);
2647        vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2648        va_end(args);
2649
2650        i915_capture_error_state(dev_priv, engine_mask, error_msg);
2651        i915_report_and_clear_eir(dev_priv);
2652
2653        if (!engine_mask)
2654                return;
2655
2656        if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2657                             &dev_priv->gpu_error.flags))
2658                return;
2659
2660        /*
2661         * Wakeup waiting processes so that the reset function
2662         * i915_reset_and_wakeup doesn't deadlock trying to grab
2663         * various locks. By bumping the reset counter first, the woken
2664         * processes will see a reset in progress and back off,
2665         * releasing their locks and then wait for the reset completion.
2666         * We must do this for _all_ gpu waiters that might hold locks
2667         * that the reset work needs to acquire.
2668         *
2669         * Note: The wake_up also provides a memory barrier to ensure that the
2670         * waiters see the updated value of the reset flags.
2671         */
2672        i915_error_wake_up(dev_priv);
2673
2674        i915_reset_and_wakeup(dev_priv);
2675}
2676
2677/* Called from drm generic code, passed 'crtc' which
2678 * we use as a pipe index
2679 */
2680static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2681{
2682        struct drm_i915_private *dev_priv = to_i915(dev);
2683        unsigned long irqflags;
2684
2685        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2686        if (INTEL_INFO(dev)->gen >= 4)
2687                i915_enable_pipestat(dev_priv, pipe,
2688                                     PIPE_START_VBLANK_INTERRUPT_STATUS);
2689        else
2690                i915_enable_pipestat(dev_priv, pipe,
2691                                     PIPE_VBLANK_INTERRUPT_STATUS);
2692        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2693
2694        return 0;
2695}
2696
2697static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2698{
2699        struct drm_i915_private *dev_priv = to_i915(dev);
2700        unsigned long irqflags;
2701        uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2702                                                     DE_PIPE_VBLANK(pipe);
2703
2704        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2705        ilk_enable_display_irq(dev_priv, bit);
2706        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2707
2708        return 0;
2709}
2710
2711static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2712{
2713        struct drm_i915_private *dev_priv = to_i915(dev);
2714        unsigned long irqflags;
2715
2716        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2717        i915_enable_pipestat(dev_priv, pipe,
2718                             PIPE_START_VBLANK_INTERRUPT_STATUS);
2719        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2720
2721        return 0;
2722}
2723
2724static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2725{
2726        struct drm_i915_private *dev_priv = to_i915(dev);
2727        unsigned long irqflags;
2728
2729        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2730        bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2731        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2732
2733        return 0;
2734}
2735
2736/* Called from drm generic code, passed 'crtc' which
2737 * we use as a pipe index
2738 */
2739static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2740{
2741        struct drm_i915_private *dev_priv = to_i915(dev);
2742        unsigned long irqflags;
2743
2744        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2745        i915_disable_pipestat(dev_priv, pipe,
2746                              PIPE_VBLANK_INTERRUPT_STATUS |
2747                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2748        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2749}
2750
2751static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2752{
2753        struct drm_i915_private *dev_priv = to_i915(dev);
2754        unsigned long irqflags;
2755        uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2756                                                     DE_PIPE_VBLANK(pipe);
2757
2758        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2759        ilk_disable_display_irq(dev_priv, bit);
2760        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2761}
2762
2763static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2764{
2765        struct drm_i915_private *dev_priv = to_i915(dev);
2766        unsigned long irqflags;
2767
2768        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2769        i915_disable_pipestat(dev_priv, pipe,
2770                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2771        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2772}
2773
2774static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2775{
2776        struct drm_i915_private *dev_priv = to_i915(dev);
2777        unsigned long irqflags;
2778
2779        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2780        bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2781        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2782}
2783
2784static bool
2785ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2786{
2787        if (INTEL_GEN(engine->i915) >= 8) {
2788                return (ipehr >> 23) == 0x1c;
2789        } else {
2790                ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2791                return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2792                                 MI_SEMAPHORE_REGISTER);
2793        }
2794}
2795
2796static struct intel_engine_cs *
2797semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2798                                 u64 offset)
2799{
2800        struct drm_i915_private *dev_priv = engine->i915;
2801        struct intel_engine_cs *signaller;
2802
2803        if (INTEL_GEN(dev_priv) >= 8) {
2804                for_each_engine(signaller, dev_priv) {
2805                        if (engine == signaller)
2806                                continue;
2807
2808                        if (offset == signaller->semaphore.signal_ggtt[engine->hw_id])
2809                                return signaller;
2810                }
2811        } else {
2812                u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2813
2814                for_each_engine(signaller, dev_priv) {
2815                        if(engine == signaller)
2816                                continue;
2817
2818                        if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
2819                                return signaller;
2820                }
2821        }
2822
2823        DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n",
2824                         engine->name, ipehr, offset);
2825
2826        return ERR_PTR(-ENODEV);
2827}
2828
2829static struct intel_engine_cs *
2830semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2831{
2832        struct drm_i915_private *dev_priv = engine->i915;
2833        void __iomem *vaddr;
2834        u32 cmd, ipehr, head;
2835        u64 offset = 0;
2836        int i, backwards;
2837
2838        /*
2839         * This function does not support execlist mode - any attempt to
2840         * proceed further into this function will result in a kernel panic
2841         * when dereferencing ring->buffer, which is not set up in execlist
2842         * mode.
2843         *
2844         * The correct way of doing it would be to derive the currently
2845         * executing ring buffer from the current context, which is derived
2846         * from the currently running request. Unfortunately, to get the
2847         * current request we would have to grab the struct_mutex before doing
2848         * anything else, which would be ill-advised since some other thread
2849         * might have grabbed it already and managed to hang itself, causing
2850         * the hang checker to deadlock.
2851         *
2852         * Therefore, this function does not support execlist mode in its
2853         * current form. Just return NULL and move on.
2854         */
2855        if (engine->buffer == NULL)
2856                return NULL;
2857
2858        ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2859        if (!ipehr_is_semaphore_wait(engine, ipehr))
2860                return NULL;
2861
2862        /*
2863         * HEAD is likely pointing to the dword after the actual command,
2864         * so scan backwards until we find the MBOX. But limit it to just 3
2865         * or 4 dwords depending on the semaphore wait command size.
2866         * Note that we don't care about ACTHD here since that might
2867         * point at at batch, and semaphores are always emitted into the
2868         * ringbuffer itself.
2869         */
2870        head = I915_READ_HEAD(engine) & HEAD_ADDR;
2871        backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2872        vaddr = (void __iomem *)engine->buffer->vaddr;
2873
2874        for (i = backwards; i; --i) {
2875                /*
2876                 * Be paranoid and presume the hw has gone off into the wild -
2877                 * our ring is smaller than what the hardware (and hence
2878                 * HEAD_ADDR) allows. Also handles wrap-around.
2879                 */
2880                head &= engine->buffer->size - 1;
2881
2882                /* This here seems to blow up */
2883                cmd = ioread32(vaddr + head);
2884                if (cmd == ipehr)
2885                        break;
2886
2887                head -= 4;
2888        }
2889
2890        if (!i)
2891                return NULL;
2892
2893        *seqno = ioread32(vaddr + head + 4) + 1;
2894        if (INTEL_GEN(dev_priv) >= 8) {
2895                offset = ioread32(vaddr + head + 12);
2896                offset <<= 32;
2897                offset |= ioread32(vaddr + head + 8);
2898        }
2899        return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2900}
2901
2902static int semaphore_passed(struct intel_engine_cs *engine)
2903{
2904        struct drm_i915_private *dev_priv = engine->i915;
2905        struct intel_engine_cs *signaller;
2906        u32 seqno;
2907
2908        engine->hangcheck.deadlock++;
2909
2910        signaller = semaphore_waits_for(engine, &seqno);
2911        if (signaller == NULL)
2912                return -1;
2913
2914        if (IS_ERR(signaller))
2915                return 0;
2916
2917        /* Prevent pathological recursion due to driver bugs */
2918        if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2919                return -1;
2920
2921        if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2922                return 1;
2923
2924        /* cursory check for an unkickable deadlock */
2925        if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2926            semaphore_passed(signaller) < 0)
2927                return -1;
2928
2929        return 0;
2930}
2931
2932static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2933{
2934        struct intel_engine_cs *engine;
2935
2936        for_each_engine(engine, dev_priv)
2937                engine->hangcheck.deadlock = 0;
2938}
2939
2940static bool subunits_stuck(struct intel_engine_cs *engine)
2941{
2942        u32 instdone[I915_NUM_INSTDONE_REG];
2943        bool stuck;
2944        int i;
2945
2946        if (engine->id != RCS)
2947                return true;
2948
2949        i915_get_extra_instdone(engine->i915, instdone);
2950
2951        /* There might be unstable subunit states even when
2952         * actual head is not moving. Filter out the unstable ones by
2953         * accumulating the undone -> done transitions and only
2954         * consider those as progress.
2955         */
2956        stuck = true;
2957        for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2958                const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2959
2960                if (tmp != engine->hangcheck.instdone[i])
2961                        stuck = false;
2962
2963                engine->hangcheck.instdone[i] |= tmp;
2964        }
2965
2966        return stuck;
2967}
2968
2969static enum intel_engine_hangcheck_action
2970head_stuck(struct intel_engine_cs *engine, u64 acthd)
2971{
2972        if (acthd != engine->hangcheck.acthd) {
2973
2974                /* Clear subunit states on head movement */
2975                memset(engine->hangcheck.instdone, 0,
2976                       sizeof(engine->hangcheck.instdone));
2977
2978                return HANGCHECK_ACTIVE;
2979        }
2980
2981        if (!subunits_stuck(engine))
2982                return HANGCHECK_ACTIVE;
2983
2984        return HANGCHECK_HUNG;
2985}
2986
2987static enum intel_engine_hangcheck_action
2988engine_stuck(struct intel_engine_cs *engine, u64 acthd)
2989{
2990        struct drm_i915_private *dev_priv = engine->i915;
2991        enum intel_engine_hangcheck_action ha;
2992        u32 tmp;
2993
2994        ha = head_stuck(engine, acthd);
2995        if (ha != HANGCHECK_HUNG)
2996                return ha;
2997
2998        if (IS_GEN2(dev_priv))
2999                return HANGCHECK_HUNG;
3000
3001        /* Is the chip hanging on a WAIT_FOR_EVENT?
3002         * If so we can simply poke the RB_WAIT bit
3003         * and break the hang. This should work on
3004         * all but the second generation chipsets.
3005         */
3006        tmp = I915_READ_CTL(engine);
3007        if (tmp & RING_WAIT) {
3008                i915_handle_error(dev_priv, 0,
3009                                  "Kicking stuck wait on %s",
3010                                  engine->name);
3011                I915_WRITE_CTL(engine, tmp);
3012                return HANGCHECK_KICK;
3013        }
3014
3015        if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3016                switch (semaphore_passed(engine)) {
3017                default:
3018                        return HANGCHECK_HUNG;
3019                case 1:
3020                        i915_handle_error(dev_priv, 0,
3021                                          "Kicking stuck semaphore on %s",
3022                                          engine->name);
3023                        I915_WRITE_CTL(engine, tmp);
3024                        return HANGCHECK_KICK;
3025                case 0:
3026                        return HANGCHECK_WAIT;
3027                }
3028        }
3029
3030        return HANGCHECK_HUNG;
3031}
3032
3033/*
3034 * This is called when the chip hasn't reported back with completed
3035 * batchbuffers in a long time. We keep track per ring seqno progress and
3036 * if there are no progress, hangcheck score for that ring is increased.
3037 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3038 * we kick the ring. If we see no progress on three subsequent calls
3039 * we assume chip is wedged and try to fix it by resetting the chip.
3040 */
3041static void i915_hangcheck_elapsed(struct work_struct *work)
3042{
3043        struct drm_i915_private *dev_priv =
3044                container_of(work, typeof(*dev_priv),
3045                             gpu_error.hangcheck_work.work);
3046        struct intel_engine_cs *engine;
3047        unsigned int hung = 0, stuck = 0;
3048        int busy_count = 0;
3049#define BUSY 1
3050#define KICK 5
3051#define HUNG 20
3052#define ACTIVE_DECAY 15
3053
3054        if (!i915.enable_hangcheck)
3055                return;
3056
3057        if (!READ_ONCE(dev_priv->gt.awake))
3058                return;
3059
3060        /* As enabling the GPU requires fairly extensive mmio access,
3061         * periodically arm the mmio checker to see if we are triggering
3062         * any invalid access.
3063         */
3064        intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3065
3066        for_each_engine(engine, dev_priv) {
3067                bool busy = intel_engine_has_waiter(engine);
3068                u64 acthd;
3069                u32 seqno;
3070                u32 submit;
3071
3072                semaphore_clear_deadlocks(dev_priv);
3073
3074                /* We don't strictly need an irq-barrier here, as we are not
3075                 * serving an interrupt request, be paranoid in case the
3076                 * barrier has side-effects (such as preventing a broken
3077                 * cacheline snoop) and so be sure that we can see the seqno
3078                 * advance. If the seqno should stick, due to a stale
3079                 * cacheline, we would erroneously declare the GPU hung.
3080                 */
3081                if (engine->irq_seqno_barrier)
3082                        engine->irq_seqno_barrier(engine);
3083
3084                acthd = intel_engine_get_active_head(engine);
3085                seqno = intel_engine_get_seqno(engine);
3086                submit = READ_ONCE(engine->last_submitted_seqno);
3087
3088                if (engine->hangcheck.seqno == seqno) {
3089                        if (i915_seqno_passed(seqno, submit)) {
3090                                engine->hangcheck.action = HANGCHECK_IDLE;
3091                        } else {
3092                                /* We always increment the hangcheck score
3093                                 * if the engine is busy and still processing
3094                                 * the same request, so that no single request
3095                                 * can run indefinitely (such as a chain of
3096                                 * batches). The only time we do not increment
3097                                 * the hangcheck score on this ring, if this
3098                                 * engine is in a legitimate wait for another
3099                                 * engine. In that case the waiting engine is a
3100                                 * victim and we want to be sure we catch the
3101                                 * right culprit. Then every time we do kick
3102                                 * the ring, add a small increment to the
3103                                 * score so that we can catch a batch that is
3104                                 * being repeatedly kicked and so responsible
3105                                 * for stalling the machine.
3106                                 */
3107                                engine->hangcheck.action =
3108                                        engine_stuck(engine, acthd);
3109
3110                                switch (engine->hangcheck.action) {
3111                                case HANGCHECK_IDLE:
3112                                case HANGCHECK_WAIT:
3113                                        break;
3114                                case HANGCHECK_ACTIVE:
3115                                        engine->hangcheck.score += BUSY;
3116                                        break;
3117                                case HANGCHECK_KICK:
3118                                        engine->hangcheck.score += KICK;
3119                                        break;
3120                                case HANGCHECK_HUNG:
3121                                        engine->hangcheck.score += HUNG;
3122                                        break;
3123                                }
3124                        }
3125
3126                        if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3127                                hung |= intel_engine_flag(engine);
3128                                if (engine->hangcheck.action != HANGCHECK_HUNG)
3129                                        stuck |= intel_engine_flag(engine);
3130                        }
3131                } else {
3132                        engine->hangcheck.action = HANGCHECK_ACTIVE;
3133
3134                        /* Gradually reduce the count so that we catch DoS
3135                         * attempts across multiple batches.
3136                         */
3137                        if (engine->hangcheck.score > 0)
3138                                engine->hangcheck.score -= ACTIVE_DECAY;
3139                        if (engine->hangcheck.score < 0)
3140                                engine->hangcheck.score = 0;
3141
3142                        /* Clear head and subunit states on seqno movement */
3143                        acthd = 0;
3144
3145                        memset(engine->hangcheck.instdone, 0,
3146                               sizeof(engine->hangcheck.instdone));
3147                }
3148
3149                engine->hangcheck.seqno = seqno;
3150                engine->hangcheck.acthd = acthd;
3151                busy_count += busy;
3152        }
3153
3154        if (hung) {
3155                char msg[80];
3156                unsigned int tmp;
3157                int len;
3158
3159                /* If some rings hung but others were still busy, only
3160                 * blame the hanging rings in the synopsis.
3161                 */
3162                if (stuck != hung)
3163                        hung &= ~stuck;
3164                len = scnprintf(msg, sizeof(msg),
3165                                "%s on ", stuck == hung ? "No progress" : "Hang");
3166                for_each_engine_masked(engine, dev_priv, hung, tmp)
3167                        len += scnprintf(msg + len, sizeof(msg) - len,
3168                                         "%s, ", engine->name);
3169                msg[len-2] = '\0';
3170
3171                return i915_handle_error(dev_priv, hung, msg);
3172        }
3173
3174        /* Reset timer in case GPU hangs without another request being added */
3175        if (busy_count)
3176                i915_queue_hangcheck(dev_priv);
3177}
3178
3179static void ibx_irq_reset(struct drm_device *dev)
3180{
3181        struct drm_i915_private *dev_priv = to_i915(dev);
3182
3183        if (HAS_PCH_NOP(dev))
3184                return;
3185
3186        GEN5_IRQ_RESET(SDE);
3187
3188        if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3189                I915_WRITE(SERR_INT, 0xffffffff);
3190}
3191
3192/*
3193 * SDEIER is also touched by the interrupt handler to work around missed PCH
3194 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3195 * instead we unconditionally enable all PCH interrupt sources here, but then
3196 * only unmask them as needed with SDEIMR.
3197 *
3198 * This function needs to be called before interrupts are enabled.
3199 */
3200static void ibx_irq_pre_postinstall(struct drm_device *dev)
3201{
3202        struct drm_i915_private *dev_priv = to_i915(dev);
3203
3204        if (HAS_PCH_NOP(dev))
3205                return;
3206
3207        WARN_ON(I915_READ(SDEIER) != 0);
3208        I915_WRITE(SDEIER, 0xffffffff);
3209        POSTING_READ(SDEIER);
3210}
3211
3212static void gen5_gt_irq_reset(struct drm_device *dev)
3213{
3214        struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216        GEN5_IRQ_RESET(GT);
3217        if (INTEL_INFO(dev)->gen >= 6)
3218                GEN5_IRQ_RESET(GEN6_PM);
3219}
3220
3221static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3222{
3223        enum pipe pipe;
3224
3225        if (IS_CHERRYVIEW(dev_priv))
3226                I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3227        else
3228                I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3229
3230        i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3231        I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3232
3233        for_each_pipe(dev_priv, pipe) {
3234                I915_WRITE(PIPESTAT(pipe),
3235                           PIPE_FIFO_UNDERRUN_STATUS |
3236                           PIPESTAT_INT_STATUS_MASK);
3237                dev_priv->pipestat_irq_mask[pipe] = 0;
3238        }
3239
3240        GEN5_IRQ_RESET(VLV_);
3241        dev_priv->irq_mask = ~0;
3242}
3243
3244static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3245{
3246        u32 pipestat_mask;
3247        u32 enable_mask;
3248        enum pipe pipe;
3249
3250        pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3251                        PIPE_CRC_DONE_INTERRUPT_STATUS;
3252
3253        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3254        for_each_pipe(dev_priv, pipe)
3255                i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3256
3257        enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3258                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3259                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3260        if (IS_CHERRYVIEW(dev_priv))
3261                enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3262
3263        WARN_ON(dev_priv->irq_mask != ~0);
3264
3265        dev_priv->irq_mask = ~enable_mask;
3266
3267        GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3268}
3269
3270/* drm_dma.h hooks
3271*/
3272static void ironlake_irq_reset(struct drm_device *dev)
3273{
3274        struct drm_i915_private *dev_priv = to_i915(dev);
3275
3276        I915_WRITE(HWSTAM, 0xffffffff);
3277
3278        GEN5_IRQ_RESET(DE);
3279        if (IS_GEN7(dev))
3280                I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3281
3282        gen5_gt_irq_reset(dev);
3283
3284        ibx_irq_reset(dev);
3285}
3286
3287static void valleyview_irq_preinstall(struct drm_device *dev)
3288{
3289        struct drm_i915_private *dev_priv = to_i915(dev);
3290
3291        I915_WRITE(VLV_MASTER_IER, 0);
3292        POSTING_READ(VLV_MASTER_IER);
3293
3294        gen5_gt_irq_reset(dev);
3295
3296        spin_lock_irq(&dev_priv->irq_lock);
3297        if (dev_priv->display_irqs_enabled)
3298                vlv_display_irq_reset(dev_priv);
3299        spin_unlock_irq(&dev_priv->irq_lock);
3300}
3301
3302static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3303{
3304        GEN8_IRQ_RESET_NDX(GT, 0);
3305        GEN8_IRQ_RESET_NDX(GT, 1);
3306        GEN8_IRQ_RESET_NDX(GT, 2);
3307        GEN8_IRQ_RESET_NDX(GT, 3);
3308}
3309
3310static void gen8_irq_reset(struct drm_device *dev)
3311{
3312        struct drm_i915_private *dev_priv = to_i915(dev);
3313        int pipe;
3314
3315        I915_WRITE(GEN8_MASTER_IRQ, 0);
3316        POSTING_READ(GEN8_MASTER_IRQ);
3317
3318        gen8_gt_irq_reset(dev_priv);
3319
3320        for_each_pipe(dev_priv, pipe)
3321                if (intel_display_power_is_enabled(dev_priv,
3322                                                   POWER_DOMAIN_PIPE(pipe)))
3323                        GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3324
3325        GEN5_IRQ_RESET(GEN8_DE_PORT_);
3326        GEN5_IRQ_RESET(GEN8_DE_MISC_);
3327        GEN5_IRQ_RESET(GEN8_PCU_);
3328
3329        if (HAS_PCH_SPLIT(dev))
3330                ibx_irq_reset(dev);
3331}
3332
3333void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3334                                     unsigned int pipe_mask)
3335{
3336        uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3337        enum pipe pipe;
3338
3339        spin_lock_irq(&dev_priv->irq_lock);
3340        for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3341                GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3342                                  dev_priv->de_irq_mask[pipe],
3343                                  ~dev_priv->de_irq_mask[pipe] | extra_ier);
3344        spin_unlock_irq(&dev_priv->irq_lock);
3345}
3346
3347void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3348                                     unsigned int pipe_mask)
3349{
3350        enum pipe pipe;
3351
3352        spin_lock_irq(&dev_priv->irq_lock);
3353        for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3354                GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3355        spin_unlock_irq(&dev_priv->irq_lock);
3356
3357        /* make sure we're done processing display irqs */
3358        synchronize_irq(dev_priv->drm.irq);
3359}
3360
3361static void cherryview_irq_preinstall(struct drm_device *dev)
3362{
3363        struct drm_i915_private *dev_priv = to_i915(dev);
3364
3365        I915_WRITE(GEN8_MASTER_IRQ, 0);
3366        POSTING_READ(GEN8_MASTER_IRQ);
3367
3368        gen8_gt_irq_reset(dev_priv);
3369
3370        GEN5_IRQ_RESET(GEN8_PCU_);
3371
3372        spin_lock_irq(&dev_priv->irq_lock);
3373        if (dev_priv->display_irqs_enabled)
3374                vlv_display_irq_reset(dev_priv);
3375        spin_unlock_irq(&dev_priv->irq_lock);
3376}
3377
3378static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3379                                  const u32 hpd[HPD_NUM_PINS])
3380{
3381        struct intel_encoder *encoder;
3382        u32 enabled_irqs = 0;
3383
3384        for_each_intel_encoder(&dev_priv->drm, encoder)
3385                if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3386                        enabled_irqs |= hpd[encoder->hpd_pin];
3387
3388        return enabled_irqs;
3389}
3390
3391static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3392{
3393        u32 hotplug_irqs, hotplug, enabled_irqs;
3394
3395        if (HAS_PCH_IBX(dev_priv)) {
3396                hotplug_irqs = SDE_HOTPLUG_MASK;
3397                enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3398        } else {
3399                hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3400                enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3401        }
3402
3403        ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3404
3405        /*
3406         * Enable digital hotplug on the PCH, and configure the DP short pulse
3407         * duration to 2ms (which is the minimum in the Display Port spec).
3408         * The pulse duration bits are reserved on LPT+.
3409         */
3410        hotplug = I915_READ(PCH_PORT_HOTPLUG);
3411        hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3412        hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3413        hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3414        hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3415        /*
3416         * When CPU and PCH are on the same package, port A
3417         * HPD must be enabled in both north and south.
3418         */
3419        if (HAS_PCH_LPT_LP(dev_priv))
3420                hotplug |= PORTA_HOTPLUG_ENABLE;
3421        I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3422}
3423
3424static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3425{
3426        u32 hotplug_irqs, hotplug, enabled_irqs;
3427
3428        hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3429        enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3430
3431        ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3432
3433        /* Enable digital hotplug on the PCH */
3434        hotplug = I915_READ(PCH_PORT_HOTPLUG);
3435        hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3436                PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3437        I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3438
3439        hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3440        hotplug |= PORTE_HOTPLUG_ENABLE;
3441        I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3442}
3443
3444static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3445{
3446        u32 hotplug_irqs, hotplug, enabled_irqs;
3447
3448        if (INTEL_GEN(dev_priv) >= 8) {
3449                hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3450                enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3451
3452                bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3453        } else if (INTEL_GEN(dev_priv) >= 7) {
3454                hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3455                enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3456
3457                ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3458        } else {
3459                hotplug_irqs = DE_DP_A_HOTPLUG;
3460                enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3461
3462                ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3463        }
3464
3465        /*
3466         * Enable digital hotplug on the CPU, and configure the DP short pulse
3467         * duration to 2ms (which is the minimum in the Display Port spec)
3468         * The pulse duration bits are reserved on HSW+.
3469         */
3470        hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3471        hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3472        hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3473        I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3474
3475        ibx_hpd_irq_setup(dev_priv);
3476}
3477
3478static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3479{
3480        u32 hotplug_irqs, hotplug, enabled_irqs;
3481
3482        enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3483        hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3484
3485        bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3486
3487        hotplug = I915_READ(PCH_PORT_HOTPLUG);
3488        hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3489                PORTA_HOTPLUG_ENABLE;
3490
3491        DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3492                      hotplug, enabled_irqs);
3493        hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3494
3495        /*
3496         * For BXT invert bit has to be set based on AOB design
3497         * for HPD detection logic, update it based on VBT fields.
3498         */
3499
3500        if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3501            intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3502                hotplug |= BXT_DDIA_HPD_INVERT;
3503        if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3504            intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3505                hotplug |= BXT_DDIB_HPD_INVERT;
3506        if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3507            intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3508                hotplug |= BXT_DDIC_HPD_INVERT;
3509
3510        I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3511}
3512
3513static void ibx_irq_postinstall(struct drm_device *dev)
3514{
3515        struct drm_i915_private *dev_priv = to_i915(dev);
3516        u32 mask;
3517
3518        if (HAS_PCH_NOP(dev))
3519                return;
3520
3521        if (HAS_PCH_IBX(dev))
3522                mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3523        else
3524                mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3525
3526        gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3527        I915_WRITE(SDEIMR, ~mask);
3528}
3529
3530static void gen5_gt_irq_postinstall(struct drm_device *dev)
3531{
3532        struct drm_i915_private *dev_priv = to_i915(dev);
3533        u32 pm_irqs, gt_irqs;
3534
3535        pm_irqs = gt_irqs = 0;
3536
3537        dev_priv->gt_irq_mask = ~0;
3538        if (HAS_L3_DPF(dev)) {
3539                /* L3 parity interrupt is always unmasked. */
3540                dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3541                gt_irqs |= GT_PARITY_ERROR(dev);
3542        }
3543
3544        gt_irqs |= GT_RENDER_USER_INTERRUPT;
3545        if (IS_GEN5(dev)) {
3546                gt_irqs |= ILK_BSD_USER_INTERRUPT;
3547        } else {
3548                gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3549        }
3550
3551        GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3552
3553        if (INTEL_INFO(dev)->gen >= 6) {
3554                /*
3555                 * RPS interrupts will get enabled/disabled on demand when RPS
3556                 * itself is enabled/disabled.
3557                 */
3558                if (HAS_VEBOX(dev))
3559                        pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3560
3561                dev_priv->pm_irq_mask = 0xffffffff;
3562                GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3563        }
3564}
3565
3566static int ironlake_irq_postinstall(struct drm_device *dev)
3567{
3568        struct drm_i915_private *dev_priv = to_i915(dev);
3569        u32 display_mask, extra_mask;
3570
3571        if (INTEL_INFO(dev)->gen >= 7) {
3572                display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3573                                DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3574                                DE_PLANEB_FLIP_DONE_IVB |
3575                                DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3576                extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3577                              DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3578                              DE_DP_A_HOTPLUG_IVB);
3579        } else {
3580                display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3581                                DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3582                                DE_AUX_CHANNEL_A |
3583                                DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3584                                DE_POISON);
3585                extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3586                              DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3587                              DE_DP_A_HOTPLUG);
3588        }
3589
3590        dev_priv->irq_mask = ~display_mask;
3591
3592        I915_WRITE(HWSTAM, 0xeffe);
3593
3594        ibx_irq_pre_postinstall(dev);
3595
3596        GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3597
3598        gen5_gt_irq_postinstall(dev);
3599
3600        ibx_irq_postinstall(dev);
3601
3602        if (IS_IRONLAKE_M(dev)) {
3603                /* Enable PCU event interrupts
3604                 *
3605                 * spinlocking not required here for correctness since interrupt
3606                 * setup is guaranteed to run in single-threaded context. But we
3607                 * need it to make the assert_spin_locked happy. */
3608                spin_lock_irq(&dev_priv->irq_lock);
3609                ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3610                spin_unlock_irq(&dev_priv->irq_lock);
3611        }
3612
3613        return 0;
3614}
3615
3616void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3617{
3618        assert_spin_locked(&dev_priv->irq_lock);
3619
3620        if (dev_priv->display_irqs_enabled)
3621                return;
3622
3623        dev_priv->display_irqs_enabled = true;
3624
3625        if (intel_irqs_enabled(dev_priv)) {
3626                vlv_display_irq_reset(dev_priv);
3627                vlv_display_irq_postinstall(dev_priv);
3628        }
3629}
3630
3631void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3632{
3633        assert_spin_locked(&dev_priv->irq_lock);
3634
3635        if (!dev_priv->display_irqs_enabled)
3636                return;
3637
3638        dev_priv->display_irqs_enabled = false;
3639
3640        if (intel_irqs_enabled(dev_priv))
3641                vlv_display_irq_reset(dev_priv);
3642}
3643
3644
3645static int valleyview_irq_postinstall(struct drm_device *dev)
3646{
3647        struct drm_i915_private *dev_priv = to_i915(dev);
3648
3649        gen5_gt_irq_postinstall(dev);
3650
3651        spin_lock_irq(&dev_priv->irq_lock);
3652        if (dev_priv->display_irqs_enabled)
3653                vlv_display_irq_postinstall(dev_priv);
3654        spin_unlock_irq(&dev_priv->irq_lock);
3655
3656        I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3657        POSTING_READ(VLV_MASTER_IER);
3658
3659        return 0;
3660}
3661
3662static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3663{
3664        /* These are interrupts we'll toggle with the ring mask register */
3665        uint32_t gt_interrupts[] = {
3666                GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3667                        GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3668                        GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3669                        GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3670                GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3671                        GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3672                        GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3673                        GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3674                0,
3675                GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3676                        GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3677                };
3678
3679        if (HAS_L3_DPF(dev_priv))
3680                gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3681
3682        dev_priv->pm_irq_mask = 0xffffffff;
3683        GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3684        GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3685        /*
3686         * RPS interrupts will get enabled/disabled on demand when RPS itself
3687         * is enabled/disabled.
3688         */
3689        GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3690        GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3691}
3692
3693static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3694{
3695        uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3696        uint32_t de_pipe_enables;
3697        u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3698        u32 de_port_enables;
3699        u32 de_misc_masked = GEN8_DE_MISC_GSE;
3700        enum pipe pipe;
3701
3702        if (INTEL_INFO(dev_priv)->gen >= 9) {
3703                de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3704                                  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3705                de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3706                                  GEN9_AUX_CHANNEL_D;
3707                if (IS_BROXTON(dev_priv))
3708                        de_port_masked |= BXT_DE_PORT_GMBUS;
3709        } else {
3710                de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3711                                  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3712        }
3713
3714        de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3715                                           GEN8_PIPE_FIFO_UNDERRUN;
3716
3717        de_port_enables = de_port_masked;
3718        if (IS_BROXTON(dev_priv))
3719                de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3720        else if (IS_BROADWELL(dev_priv))
3721                de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3722
3723        dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3724        dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3725        dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3726
3727        for_each_pipe(dev_priv, pipe)
3728                if (intel_display_power_is_enabled(dev_priv,
3729                                POWER_DOMAIN_PIPE(pipe)))
3730                        GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3731                                          dev_priv->de_irq_mask[pipe],
3732                                          de_pipe_enables);
3733
3734        GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3735        GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3736}
3737
3738static int gen8_irq_postinstall(struct drm_device *dev)
3739{
3740        struct drm_i915_private *dev_priv = to_i915(dev);
3741
3742        if (HAS_PCH_SPLIT(dev))
3743                ibx_irq_pre_postinstall(dev);
3744
3745        gen8_gt_irq_postinstall(dev_priv);
3746        gen8_de_irq_postinstall(dev_priv);
3747
3748        if (HAS_PCH_SPLIT(dev))
3749                ibx_irq_postinstall(dev);
3750
3751        I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3752        POSTING_READ(GEN8_MASTER_IRQ);
3753
3754        return 0;
3755}
3756
3757static int cherryview_irq_postinstall(struct drm_device *dev)
3758{
3759        struct drm_i915_private *dev_priv = to_i915(dev);
3760
3761        gen8_gt_irq_postinstall(dev_priv);
3762
3763        spin_lock_irq(&dev_priv->irq_lock);
3764        if (dev_priv->display_irqs_enabled)
3765                vlv_display_irq_postinstall(dev_priv);
3766        spin_unlock_irq(&dev_priv->irq_lock);
3767
3768        I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3769        POSTING_READ(GEN8_MASTER_IRQ);
3770
3771        return 0;
3772}
3773
3774static void gen8_irq_uninstall(struct drm_device *dev)
3775{
3776        struct drm_i915_private *dev_priv = to_i915(dev);
3777
3778        if (!dev_priv)
3779                return;
3780
3781        gen8_irq_reset(dev);
3782}
3783
3784static void valleyview_irq_uninstall(struct drm_device *dev)
3785{
3786        struct drm_i915_private *dev_priv = to_i915(dev);
3787
3788        if (!dev_priv)
3789                return;
3790
3791        I915_WRITE(VLV_MASTER_IER, 0);
3792        POSTING_READ(VLV_MASTER_IER);
3793
3794        gen5_gt_irq_reset(dev);
3795
3796        I915_WRITE(HWSTAM, 0xffffffff);
3797
3798        spin_lock_irq(&dev_priv->irq_lock);
3799        if (dev_priv->display_irqs_enabled)
3800                vlv_display_irq_reset(dev_priv);
3801        spin_unlock_irq(&dev_priv->irq_lock);
3802}
3803
3804static void cherryview_irq_uninstall(struct drm_device *dev)
3805{
3806        struct drm_i915_private *dev_priv = to_i915(dev);
3807
3808        if (!dev_priv)
3809                return;
3810
3811        I915_WRITE(GEN8_MASTER_IRQ, 0);
3812        POSTING_READ(GEN8_MASTER_IRQ);
3813
3814        gen8_gt_irq_reset(dev_priv);
3815
3816        GEN5_IRQ_RESET(GEN8_PCU_);
3817
3818        spin_lock_irq(&dev_priv->irq_lock);
3819        if (dev_priv->display_irqs_enabled)
3820                vlv_display_irq_reset(dev_priv);
3821        spin_unlock_irq(&dev_priv->irq_lock);
3822}
3823
3824static void ironlake_irq_uninstall(struct drm_device *dev)
3825{
3826        struct drm_i915_private *dev_priv = to_i915(dev);
3827
3828        if (!dev_priv)
3829                return;
3830
3831        ironlake_irq_reset(dev);
3832}
3833
3834static void i8xx_irq_preinstall(struct drm_device * dev)
3835{
3836        struct drm_i915_private *dev_priv = to_i915(dev);
3837        int pipe;
3838
3839        for_each_pipe(dev_priv, pipe)
3840                I915_WRITE(PIPESTAT(pipe), 0);
3841        I915_WRITE16(IMR, 0xffff);
3842        I915_WRITE16(IER, 0x0);
3843        POSTING_READ16(IER);
3844}
3845
3846static int i8xx_irq_postinstall(struct drm_device *dev)
3847{
3848        struct drm_i915_private *dev_priv = to_i915(dev);
3849
3850        I915_WRITE16(EMR,
3851                     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3852
3853        /* Unmask the interrupts that we always want on. */
3854        dev_priv->irq_mask =
3855                ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3856                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3857                  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3858                  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3859        I915_WRITE16(IMR, dev_priv->irq_mask);
3860
3861        I915_WRITE16(IER,
3862                     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3863                     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3864                     I915_USER_INTERRUPT);
3865        POSTING_READ16(IER);
3866
3867        /* Interrupt setup is already guaranteed to be single-threaded, this is
3868         * just to make the assert_spin_locked check happy. */
3869        spin_lock_irq(&dev_priv->irq_lock);
3870        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3871        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3872        spin_unlock_irq(&dev_priv->irq_lock);
3873
3874        return 0;
3875}
3876
3877/*
3878 * Returns true when a page flip has completed.
3879 */
3880static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3881                               int plane, int pipe, u32 iir)
3882{
3883        u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3884
3885        if (!intel_pipe_handle_vblank(dev_priv, pipe))
3886                return false;
3887
3888        if ((iir & flip_pending) == 0)
3889                goto check_page_flip;
3890
3891        /* We detect FlipDone by looking for the change in PendingFlip from '1'
3892         * to '0' on the following vblank, i.e. IIR has the Pendingflip
3893         * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3894         * the flip is completed (no longer pending). Since this doesn't raise
3895         * an interrupt per se, we watch for the change at vblank.
3896         */
3897        if (I915_READ16(ISR) & flip_pending)
3898                goto check_page_flip;
3899
3900        intel_finish_page_flip_cs(dev_priv, pipe);
3901        return true;
3902
3903check_page_flip:
3904        intel_check_page_flip(dev_priv, pipe);
3905        return false;
3906}
3907
3908static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3909{
3910        struct drm_device *dev = arg;
3911        struct drm_i915_private *dev_priv = to_i915(dev);
3912        u16 iir, new_iir;
3913        u32 pipe_stats[2];
3914        int pipe;
3915        u16 flip_mask =
3916                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3917                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3918        irqreturn_t ret;
3919
3920        if (!intel_irqs_enabled(dev_priv))
3921                return IRQ_NONE;
3922
3923        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3924        disable_rpm_wakeref_asserts(dev_priv);
3925
3926        ret = IRQ_NONE;
3927        iir = I915_READ16(IIR);
3928        if (iir == 0)
3929                goto out;
3930
3931        while (iir & ~flip_mask) {
3932                /* Can't rely on pipestat interrupt bit in iir as it might
3933                 * have been cleared after the pipestat interrupt was received.
3934                 * It doesn't set the bit in iir again, but it still produces
3935                 * interrupts (for non-MSI).
3936                 */
3937                spin_lock(&dev_priv->irq_lock);
3938                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3939                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3940
3941                for_each_pipe(dev_priv, pipe) {
3942                        i915_reg_t reg = PIPESTAT(pipe);
3943                        pipe_stats[pipe] = I915_READ(reg);
3944
3945                        /*
3946                         * Clear the PIPE*STAT regs before the IIR
3947                         */
3948                        if (pipe_stats[pipe] & 0x8000ffff)
3949                                I915_WRITE(reg, pipe_stats[pipe]);
3950                }
3951                spin_unlock(&dev_priv->irq_lock);
3952
3953                I915_WRITE16(IIR, iir & ~flip_mask);
3954                new_iir = I915_READ16(IIR); /* Flush posted writes */
3955
3956                if (iir & I915_USER_INTERRUPT)
3957                        notify_ring(&dev_priv->engine[RCS]);
3958
3959                for_each_pipe(dev_priv, pipe) {
3960                        int plane = pipe;
3961                        if (HAS_FBC(dev_priv))
3962                                plane = !plane;
3963
3964                        if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3965                            i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3966                                flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3967
3968                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3969                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3970
3971                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3972                                intel_cpu_fifo_underrun_irq_handler(dev_priv,
3973                                                                    pipe);
3974                }
3975
3976                iir = new_iir;
3977        }
3978        ret = IRQ_HANDLED;
3979
3980out:
3981        enable_rpm_wakeref_asserts(dev_priv);
3982
3983        return ret;
3984}
3985
3986static void i8xx_irq_uninstall(struct drm_device * dev)
3987{
3988        struct drm_i915_private *dev_priv = to_i915(dev);
3989        int pipe;
3990
3991        for_each_pipe(dev_priv, pipe) {
3992                /* Clear enable bits; then clear status bits */
3993                I915_WRITE(PIPESTAT(pipe), 0);
3994                I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3995        }
3996        I915_WRITE16(IMR, 0xffff);
3997        I915_WRITE16(IER, 0x0);
3998        I915_WRITE16(IIR, I915_READ16(IIR));
3999}
4000
4001static void i915_irq_preinstall(struct drm_device * dev)
4002{
4003        struct drm_i915_private *dev_priv = to_i915(dev);
4004        int pipe;
4005
4006        if (I915_HAS_HOTPLUG(dev)) {
4007                i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4008                I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4009        }
4010
4011        I915_WRITE16(HWSTAM, 0xeffe);
4012        for_each_pipe(dev_priv, pipe)
4013                I915_WRITE(PIPESTAT(pipe), 0);
4014        I915_WRITE(IMR, 0xffffffff);
4015        I915_WRITE(IER, 0x0);
4016        POSTING_READ(IER);
4017}
4018
4019static int i915_irq_postinstall(struct drm_device *dev)
4020{
4021        struct drm_i915_private *dev_priv = to_i915(dev);
4022        u32 enable_mask;
4023
4024        I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4025
4026        /* Unmask the interrupts that we always want on. */
4027        dev_priv->irq_mask =
4028                ~(I915_ASLE_INTERRUPT |
4029                  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4030                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4031                  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4032                  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4033
4034        enable_mask =
4035                I915_ASLE_INTERRUPT |
4036                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4037                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4038                I915_USER_INTERRUPT;
4039
4040        if (I915_HAS_HOTPLUG(dev)) {
4041                i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4042                POSTING_READ(PORT_HOTPLUG_EN);
4043
4044                /* Enable in IER... */
4045                enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4046                /* and unmask in IMR */
4047                dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4048        }
4049
4050        I915_WRITE(IMR, dev_priv->irq_mask);
4051        I915_WRITE(IER, enable_mask);
4052        POSTING_READ(IER);
4053
4054        i915_enable_asle_pipestat(dev_priv);
4055
4056        /* Interrupt setup is already guaranteed to be single-threaded, this is
4057         * just to make the assert_spin_locked check happy. */
4058        spin_lock_irq(&dev_priv->irq_lock);
4059        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4060        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4061        spin_unlock_irq(&dev_priv->irq_lock);
4062
4063        return 0;
4064}
4065
4066/*
4067 * Returns true when a page flip has completed.
4068 */
4069static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4070                               int plane, int pipe, u32 iir)
4071{
4072        u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4073
4074        if (!intel_pipe_handle_vblank(dev_priv, pipe))
4075                return false;
4076
4077        if ((iir & flip_pending) == 0)
4078                goto check_page_flip;
4079
4080        /* We detect FlipDone by looking for the change in PendingFlip from '1'
4081         * to '0' on the following vblank, i.e. IIR has the Pendingflip
4082         * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4083         * the flip is completed (no longer pending). Since this doesn't raise
4084         * an interrupt per se, we watch for the change at vblank.
4085         */
4086        if (I915_READ(ISR) & flip_pending)
4087                goto check_page_flip;
4088
4089        intel_finish_page_flip_cs(dev_priv, pipe);
4090        return true;
4091
4092check_page_flip:
4093        intel_check_page_flip(dev_priv, pipe);
4094        return false;
4095}
4096
4097static irqreturn_t i915_irq_handler(int irq, void *arg)
4098{
4099        struct drm_device *dev = arg;
4100        struct drm_i915_private *dev_priv = to_i915(dev);
4101        u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4102        u32 flip_mask =
4103                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4104                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4105        int pipe, ret = IRQ_NONE;
4106
4107        if (!intel_irqs_enabled(dev_priv))
4108                return IRQ_NONE;
4109
4110        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4111        disable_rpm_wakeref_asserts(dev_priv);
4112
4113        iir = I915_READ(IIR);
4114        do {
4115                bool irq_received = (iir & ~flip_mask) != 0;
4116                bool blc_event = false;
4117
4118                /* Can't rely on pipestat interrupt bit in iir as it might
4119                 * have been cleared after the pipestat interrupt was received.
4120                 * It doesn't set the bit in iir again, but it still produces
4121                 * interrupts (for non-MSI).
4122                 */
4123                spin_lock(&dev_priv->irq_lock);
4124                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4125                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4126
4127                for_each_pipe(dev_priv, pipe) {
4128                        i915_reg_t reg = PIPESTAT(pipe);
4129                        pipe_stats[pipe] = I915_READ(reg);
4130
4131                        /* Clear the PIPE*STAT regs before the IIR */
4132                        if (pipe_stats[pipe] & 0x8000ffff) {
4133                                I915_WRITE(reg, pipe_stats[pipe]);
4134                                irq_received = true;
4135                        }
4136                }
4137                spin_unlock(&dev_priv->irq_lock);
4138
4139                if (!irq_received)
4140                        break;
4141
4142                /* Consume port.  Then clear IIR or we'll miss events */
4143                if (I915_HAS_HOTPLUG(dev_priv) &&
4144                    iir & I915_DISPLAY_PORT_INTERRUPT) {
4145                        u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4146                        if (hotplug_status)
4147                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4148                }
4149
4150                I915_WRITE(IIR, iir & ~flip_mask);
4151                new_iir = I915_READ(IIR); /* Flush posted writes */
4152
4153                if (iir & I915_USER_INTERRUPT)
4154                        notify_ring(&dev_priv->engine[RCS]);
4155
4156                for_each_pipe(dev_priv, pipe) {
4157                        int plane = pipe;
4158                        if (HAS_FBC(dev_priv))
4159                                plane = !plane;
4160
4161                        if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4162                            i915_handle_vblank(dev_priv, plane, pipe, iir))
4163                                flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4164
4165                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4166                                blc_event = true;
4167
4168                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4169                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4170
4171                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4172                                intel_cpu_fifo_underrun_irq_handler(dev_priv,
4173                                                                    pipe);
4174                }
4175
4176                if (blc_event || (iir & I915_ASLE_INTERRUPT))
4177                        intel_opregion_asle_intr(dev_priv);
4178
4179                /* With MSI, interrupts are only generated when iir
4180                 * transitions from zero to nonzero.  If another bit got
4181                 * set while we were handling the existing iir bits, then
4182                 * we would never get another interrupt.
4183                 *
4184                 * This is fine on non-MSI as well, as if we hit this path
4185                 * we avoid exiting the interrupt handler only to generate
4186                 * another one.
4187                 *
4188                 * Note that for MSI this could cause a stray interrupt report
4189                 * if an interrupt landed in the time between writing IIR and
4190                 * the posting read.  This should be rare enough to never
4191                 * trigger the 99% of 100,000 interrupts test for disabling
4192                 * stray interrupts.
4193                 */
4194                ret = IRQ_HANDLED;
4195                iir = new_iir;
4196        } while (iir & ~flip_mask);
4197
4198        enable_rpm_wakeref_asserts(dev_priv);
4199
4200        return ret;
4201}
4202
4203static void i915_irq_uninstall(struct drm_device * dev)
4204{
4205        struct drm_i915_private *dev_priv = to_i915(dev);
4206        int pipe;
4207
4208        if (I915_HAS_HOTPLUG(dev)) {
4209                i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4210                I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4211        }
4212
4213        I915_WRITE16(HWSTAM, 0xffff);
4214        for_each_pipe(dev_priv, pipe) {
4215                /* Clear enable bits; then clear status bits */
4216                I915_WRITE(PIPESTAT(pipe), 0);
4217                I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4218        }
4219        I915_WRITE(IMR, 0xffffffff);
4220        I915_WRITE(IER, 0x0);
4221
4222        I915_WRITE(IIR, I915_READ(IIR));
4223}
4224
4225static void i965_irq_preinstall(struct drm_device * dev)
4226{
4227        struct drm_i915_private *dev_priv = to_i915(dev);
4228        int pipe;
4229
4230        i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4231        I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4232
4233        I915_WRITE(HWSTAM, 0xeffe);
4234        for_each_pipe(dev_priv, pipe)
4235                I915_WRITE(PIPESTAT(pipe), 0);
4236        I915_WRITE(IMR, 0xffffffff);
4237        I915_WRITE(IER, 0x0);
4238        POSTING_READ(IER);
4239}
4240
4241static int i965_irq_postinstall(struct drm_device *dev)
4242{
4243        struct drm_i915_private *dev_priv = to_i915(dev);
4244        u32 enable_mask;
4245        u32 error_mask;
4246
4247        /* Unmask the interrupts that we always want on. */
4248        dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4249                               I915_DISPLAY_PORT_INTERRUPT |
4250                               I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4251                               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4252                               I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4253                               I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4254                               I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4255
4256        enable_mask = ~dev_priv->irq_mask;
4257        enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4258                         I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4259        enable_mask |= I915_USER_INTERRUPT;
4260
4261        if (IS_G4X(dev_priv))
4262                enable_mask |= I915_BSD_USER_INTERRUPT;
4263
4264        /* Interrupt setup is already guaranteed to be single-threaded, this is
4265         * just to make the assert_spin_locked check happy. */
4266        spin_lock_irq(&dev_priv->irq_lock);
4267        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4268        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4269        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4270        spin_unlock_irq(&dev_priv->irq_lock);
4271
4272        /*
4273         * Enable some error detection, note the instruction error mask
4274         * bit is reserved, so we leave it masked.
4275         */
4276        if (IS_G4X(dev_priv)) {
4277                error_mask = ~(GM45_ERROR_PAGE_TABLE |
4278                               GM45_ERROR_MEM_PRIV |
4279                               GM45_ERROR_CP_PRIV |
4280                               I915_ERROR_MEMORY_REFRESH);
4281        } else {
4282                error_mask = ~(I915_ERROR_PAGE_TABLE |
4283                               I915_ERROR_MEMORY_REFRESH);
4284        }
4285        I915_WRITE(EMR, error_mask);
4286
4287        I915_WRITE(IMR, dev_priv->irq_mask);
4288        I915_WRITE(IER, enable_mask);
4289        POSTING_READ(IER);
4290
4291        i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4292        POSTING_READ(PORT_HOTPLUG_EN);
4293
4294        i915_enable_asle_pipestat(dev_priv);
4295
4296        return 0;
4297}
4298
4299static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4300{
4301        u32 hotplug_en;
4302
4303        assert_spin_locked(&dev_priv->irq_lock);
4304
4305        /* Note HDMI and DP share hotplug bits */
4306        /* enable bits are the same for all generations */
4307        hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4308        /* Programming the CRT detection parameters tends
4309           to generate a spurious hotplug event about three
4310           seconds later.  So just do it once.
4311        */
4312        if (IS_G4X(dev_priv))
4313                hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4314        hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4315
4316        /* Ignore TV since it's buggy */
4317        i915_hotplug_interrupt_update_locked(dev_priv,
4318                                             HOTPLUG_INT_EN_MASK |
4319                                             CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4320                                             CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4321                                             hotplug_en);
4322}
4323
4324static irqreturn_t i965_irq_handler(int irq, void *arg)
4325{
4326        struct drm_device *dev = arg;
4327        struct drm_i915_private *dev_priv = to_i915(dev);
4328        u32 iir, new_iir;
4329        u32 pipe_stats[I915_MAX_PIPES];
4330        int ret = IRQ_NONE, pipe;
4331        u32 flip_mask =
4332                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4333                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4334
4335        if (!intel_irqs_enabled(dev_priv))
4336                return IRQ_NONE;
4337
4338        /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4339        disable_rpm_wakeref_asserts(dev_priv);
4340
4341        iir = I915_READ(IIR);
4342
4343        for (;;) {
4344                bool irq_received = (iir & ~flip_mask) != 0;
4345                bool blc_event = false;
4346
4347                /* Can't rely on pipestat interrupt bit in iir as it might
4348                 * have been cleared after the pipestat interrupt was received.
4349                 * It doesn't set the bit in iir again, but it still produces
4350                 * interrupts (for non-MSI).
4351                 */
4352                spin_lock(&dev_priv->irq_lock);
4353                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4354                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4355
4356                for_each_pipe(dev_priv, pipe) {
4357                        i915_reg_t reg = PIPESTAT(pipe);
4358                        pipe_stats[pipe] = I915_READ(reg);
4359
4360                        /*
4361                         * Clear the PIPE*STAT regs before the IIR
4362                         */
4363                        if (pipe_stats[pipe] & 0x8000ffff) {
4364                                I915_WRITE(reg, pipe_stats[pipe]);
4365                                irq_received = true;
4366                        }
4367                }
4368                spin_unlock(&dev_priv->irq_lock);
4369
4370                if (!irq_received)
4371                        break;
4372
4373                ret = IRQ_HANDLED;
4374
4375                /* Consume port.  Then clear IIR or we'll miss events */
4376                if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4377                        u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4378                        if (hotplug_status)
4379                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4380                }
4381
4382                I915_WRITE(IIR, iir & ~flip_mask);
4383                new_iir = I915_READ(IIR); /* Flush posted writes */
4384
4385                if (iir & I915_USER_INTERRUPT)
4386                        notify_ring(&dev_priv->engine[RCS]);
4387                if (iir & I915_BSD_USER_INTERRUPT)
4388                        notify_ring(&dev_priv->engine[VCS]);
4389
4390                for_each_pipe(dev_priv, pipe) {
4391                        if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4392                            i915_handle_vblank(dev_priv, pipe, pipe, iir))
4393                                flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4394
4395                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4396                                blc_event = true;
4397
4398                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4399                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4400
4401                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4402                                intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4403                }
4404
4405                if (blc_event || (iir & I915_ASLE_INTERRUPT))
4406                        intel_opregion_asle_intr(dev_priv);
4407
4408                if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4409                        gmbus_irq_handler(dev_priv);
4410
4411                /* With MSI, interrupts are only generated when iir
4412                 * transitions from zero to nonzero.  If another bit got
4413                 * set while we were handling the existing iir bits, then
4414                 * we would never get another interrupt.
4415                 *
4416                 * This is fine on non-MSI as well, as if we hit this path
4417                 * we avoid exiting the interrupt handler only to generate
4418                 * another one.
4419                 *
4420                 * Note that for MSI this could cause a stray interrupt report
4421                 * if an interrupt landed in the time between writing IIR and
4422                 * the posting read.  This should be rare enough to never
4423                 * trigger the 99% of 100,000 interrupts test for disabling
4424                 * stray interrupts.
4425                 */
4426                iir = new_iir;
4427        }
4428
4429        enable_rpm_wakeref_asserts(dev_priv);
4430
4431        return ret;
4432}
4433
4434static void i965_irq_uninstall(struct drm_device * dev)
4435{
4436        struct drm_i915_private *dev_priv = to_i915(dev);
4437        int pipe;
4438
4439        if (!dev_priv)
4440                return;
4441
4442        i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4443        I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4444
4445        I915_WRITE(HWSTAM, 0xffffffff);
4446        for_each_pipe(dev_priv, pipe)
4447                I915_WRITE(PIPESTAT(pipe), 0);
4448        I915_WRITE(IMR, 0xffffffff);
4449        I915_WRITE(IER, 0x0);
4450
4451        for_each_pipe(dev_priv, pipe)
4452                I915_WRITE(PIPESTAT(pipe),
4453                           I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4454        I915_WRITE(IIR, I915_READ(IIR));
4455}
4456
4457/**
4458 * intel_irq_init - initializes irq support
4459 * @dev_priv: i915 device instance
4460 *
4461 * This function initializes all the irq support including work items, timers
4462 * and all the vtables. It does not setup the interrupt itself though.
4463 */
4464void intel_irq_init(struct drm_i915_private *dev_priv)
4465{
4466        struct drm_device *dev = &dev_priv->drm;
4467
4468        intel_hpd_init_work(dev_priv);
4469
4470        INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4471        INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4472
4473        /* Let's track the enabled rps events */
4474        if (IS_VALLEYVIEW(dev_priv))
4475                /* WaGsvRC0ResidencyMethod:vlv */
4476                dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4477        else
4478                dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4479
4480        dev_priv->rps.pm_intr_keep = 0;
4481
4482        /*
4483         * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4484         * if GEN6_PM_UP_EI_EXPIRED is masked.
4485         *
4486         * TODO: verify if this can be reproduced on VLV,CHV.
4487         */
4488        if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4489                dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4490
4491        if (INTEL_INFO(dev_priv)->gen >= 8)
4492                dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4493
4494        INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4495                          i915_hangcheck_elapsed);
4496
4497        if (IS_GEN2(dev_priv)) {
4498                /* Gen2 doesn't have a hardware frame counter */
4499                dev->max_vblank_count = 0;
4500                dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4501        } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4502                dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4503                dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4504        } else {
4505                dev->driver->get_vblank_counter = i915_get_vblank_counter;
4506                dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4507        }
4508
4509        /*
4510         * Opt out of the vblank disable timer on everything except gen2.
4511         * Gen2 doesn't have a hardware frame counter and so depends on
4512         * vblank interrupts to produce sane vblank seuquence numbers.
4513         */
4514        if (!IS_GEN2(dev_priv))
4515                dev->vblank_disable_immediate = true;
4516
4517        /* Most platforms treat the display irq block as an always-on
4518         * power domain. vlv/chv can disable it at runtime and need
4519         * special care to avoid writing any of the display block registers
4520         * outside of the power domain. We defer setting up the display irqs
4521         * in this case to the runtime pm.
4522         */
4523        dev_priv->display_irqs_enabled = true;
4524        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4525                dev_priv->display_irqs_enabled = false;
4526
4527        dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4528        dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4529
4530        if (IS_CHERRYVIEW(dev_priv)) {
4531                dev->driver->irq_handler = cherryview_irq_handler;
4532                dev->driver->irq_preinstall = cherryview_irq_preinstall;
4533                dev->driver->irq_postinstall = cherryview_irq_postinstall;
4534                dev->driver->irq_uninstall = cherryview_irq_uninstall;
4535                dev->driver->enable_vblank = valleyview_enable_vblank;
4536                dev->driver->disable_vblank = valleyview_disable_vblank;
4537                dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4538        } else if (IS_VALLEYVIEW(dev_priv)) {
4539                dev->driver->irq_handler = valleyview_irq_handler;
4540                dev->driver->irq_preinstall = valleyview_irq_preinstall;
4541                dev->driver->irq_postinstall = valleyview_irq_postinstall;
4542                dev->driver->irq_uninstall = valleyview_irq_uninstall;
4543                dev->driver->enable_vblank = valleyview_enable_vblank;
4544                dev->driver->disable_vblank = valleyview_disable_vblank;
4545                dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4546        } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4547                dev->driver->irq_handler = gen8_irq_handler;
4548                dev->driver->irq_preinstall = gen8_irq_reset;
4549                dev->driver->irq_postinstall = gen8_irq_postinstall;
4550                dev->driver->irq_uninstall = gen8_irq_uninstall;
4551                dev->driver->enable_vblank = gen8_enable_vblank;
4552                dev->driver->disable_vblank = gen8_disable_vblank;
4553                if (IS_BROXTON(dev))
4554                        dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4555                else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4556                        dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4557                else
4558                        dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4559        } else if (HAS_PCH_SPLIT(dev)) {
4560                dev->driver->irq_handler = ironlake_irq_handler;
4561                dev->driver->irq_preinstall = ironlake_irq_reset;
4562                dev->driver->irq_postinstall = ironlake_irq_postinstall;
4563                dev->driver->irq_uninstall = ironlake_irq_uninstall;
4564                dev->driver->enable_vblank = ironlake_enable_vblank;
4565                dev->driver->disable_vblank = ironlake_disable_vblank;
4566                dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4567        } else {
4568                if (IS_GEN2(dev_priv)) {
4569                        dev->driver->irq_preinstall = i8xx_irq_preinstall;
4570                        dev->driver->irq_postinstall = i8xx_irq_postinstall;
4571                        dev->driver->irq_handler = i8xx_irq_handler;
4572                        dev->driver->irq_uninstall = i8xx_irq_uninstall;
4573                } else if (IS_GEN3(dev_priv)) {
4574                        dev->driver->irq_preinstall = i915_irq_preinstall;
4575                        dev->driver->irq_postinstall = i915_irq_postinstall;
4576                        dev->driver->irq_uninstall = i915_irq_uninstall;
4577                        dev->driver->irq_handler = i915_irq_handler;
4578                } else {
4579                        dev->driver->irq_preinstall = i965_irq_preinstall;
4580                        dev->driver->irq_postinstall = i965_irq_postinstall;
4581                        dev->driver->irq_uninstall = i965_irq_uninstall;
4582                        dev->driver->irq_handler = i965_irq_handler;
4583                }
4584                if (I915_HAS_HOTPLUG(dev_priv))
4585                        dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4586                dev->driver->enable_vblank = i915_enable_vblank;
4587                dev->driver->disable_vblank = i915_disable_vblank;
4588        }
4589}
4590
4591/**
4592 * intel_irq_install - enables the hardware interrupt
4593 * @dev_priv: i915 device instance
4594 *
4595 * This function enables the hardware interrupt handling, but leaves the hotplug
4596 * handling still disabled. It is called after intel_irq_init().
4597 *
4598 * In the driver load and resume code we need working interrupts in a few places
4599 * but don't want to deal with the hassle of concurrent probe and hotplug
4600 * workers. Hence the split into this two-stage approach.
4601 */
4602int intel_irq_install(struct drm_i915_private *dev_priv)
4603{
4604        /*
4605         * We enable some interrupt sources in our postinstall hooks, so mark
4606         * interrupts as enabled _before_ actually enabling them to avoid
4607         * special cases in our ordering checks.
4608         */
4609        dev_priv->pm.irqs_enabled = true;
4610
4611        return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4612}
4613
4614/**
4615 * intel_irq_uninstall - finilizes all irq handling
4616 * @dev_priv: i915 device instance
4617 *
4618 * This stops interrupt and hotplug handling and unregisters and frees all
4619 * resources acquired in the init functions.
4620 */
4621void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4622{
4623        drm_irq_uninstall(&dev_priv->drm);
4624        intel_hpd_cancel_work(dev_priv);
4625        dev_priv->pm.irqs_enabled = false;
4626}
4627
4628/**
4629 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4630 * @dev_priv: i915 device instance
4631 *
4632 * This function is used to disable interrupts at runtime, both in the runtime
4633 * pm and the system suspend/resume code.
4634 */
4635void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4636{
4637        dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4638        dev_priv->pm.irqs_enabled = false;
4639        synchronize_irq(dev_priv->drm.irq);
4640}
4641
4642/**
4643 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4644 * @dev_priv: i915 device instance
4645 *
4646 * This function is used to enable interrupts at runtime, both in the runtime
4647 * pm and the system suspend/resume code.
4648 */
4649void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4650{
4651        dev_priv->pm.irqs_enabled = true;
4652        dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4653        dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4654}
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