source: src/linux/universal/linux-4.9/drivers/gpu/drm/i915/i915_pci.c @ 31859

Last change on this file since 31859 was 31859, checked in by brainslayer, 3 months ago

kernel update

File size: 13.5 KB
Line 
1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/console.h>
26#include <linux/vgaarb.h>
27#include <linux/vga_switcheroo.h>
28
29#include "i915_drv.h"
30
31#define GEN_DEFAULT_PIPEOFFSETS \
32        .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
33                          PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
34        .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
35                           TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
36        .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
37
38#define GEN_CHV_PIPEOFFSETS \
39        .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
40                          CHV_PIPE_C_OFFSET }, \
41        .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
42                           CHV_TRANSCODER_C_OFFSET, }, \
43        .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
44                             CHV_PALETTE_C_OFFSET }
45
46#define CURSOR_OFFSETS \
47        .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
48
49#define IVB_CURSOR_OFFSETS \
50        .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
51
52#define BDW_COLORS \
53        .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
54#define CHV_COLORS \
55        .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
56
57#define GEN2_FEATURES \
58        .gen = 2, .num_pipes = 1, \
59        .has_overlay = 1, .overlay_needs_physical = 1, \
60        .has_gmch_display = 1, \
61        .hws_needs_physical = 1, \
62        .ring_mask = RENDER_RING, \
63        GEN_DEFAULT_PIPEOFFSETS, \
64        CURSOR_OFFSETS
65
66static const struct intel_device_info intel_i830_info = {
67        GEN2_FEATURES,
68        .is_mobile = 1, .cursor_needs_physical = 1,
69        .num_pipes = 2, /* legal, last one wins */
70};
71
72static const struct intel_device_info intel_845g_info = {
73        GEN2_FEATURES,
74};
75
76static const struct intel_device_info intel_i85x_info = {
77        GEN2_FEATURES,
78        .is_i85x = 1, .is_mobile = 1,
79        .num_pipes = 2, /* legal, last one wins */
80        .cursor_needs_physical = 1,
81        .has_fbc = 1,
82};
83
84static const struct intel_device_info intel_i865g_info = {
85        GEN2_FEATURES,
86};
87
88#define GEN3_FEATURES \
89        .gen = 3, .num_pipes = 2, \
90        .has_gmch_display = 1, \
91        .ring_mask = RENDER_RING, \
92        GEN_DEFAULT_PIPEOFFSETS, \
93        CURSOR_OFFSETS
94
95static const struct intel_device_info intel_i915g_info = {
96        GEN3_FEATURES,
97        .is_i915g = 1, .cursor_needs_physical = 1,
98        .has_overlay = 1, .overlay_needs_physical = 1,
99        .hws_needs_physical = 1,
100};
101static const struct intel_device_info intel_i915gm_info = {
102        GEN3_FEATURES,
103        .is_mobile = 1,
104        .cursor_needs_physical = 1,
105        .has_overlay = 1, .overlay_needs_physical = 1,
106        .supports_tv = 1,
107        .has_fbc = 1,
108        .hws_needs_physical = 1,
109};
110static const struct intel_device_info intel_i945g_info = {
111        GEN3_FEATURES,
112        .has_hotplug = 1, .cursor_needs_physical = 1,
113        .has_overlay = 1, .overlay_needs_physical = 1,
114        .hws_needs_physical = 1,
115};
116static const struct intel_device_info intel_i945gm_info = {
117        GEN3_FEATURES,
118        .is_i945gm = 1, .is_mobile = 1,
119        .has_hotplug = 1, .cursor_needs_physical = 1,
120        .has_overlay = 1, .overlay_needs_physical = 1,
121        .supports_tv = 1,
122        .has_fbc = 1,
123        .hws_needs_physical = 1,
124};
125
126#define GEN4_FEATURES \
127        .gen = 4, .num_pipes = 2, \
128        .has_hotplug = 1, \
129        .has_gmch_display = 1, \
130        .ring_mask = RENDER_RING, \
131        GEN_DEFAULT_PIPEOFFSETS, \
132        CURSOR_OFFSETS
133
134static const struct intel_device_info intel_i965g_info = {
135        GEN4_FEATURES,
136        .is_broadwater = 1,
137        .has_overlay = 1,
138        .hws_needs_physical = 1,
139};
140
141static const struct intel_device_info intel_i965gm_info = {
142        GEN4_FEATURES,
143        .is_crestline = 1,
144        .is_mobile = 1, .has_fbc = 1,
145        .has_overlay = 1,
146        .supports_tv = 1,
147        .hws_needs_physical = 1,
148};
149
150static const struct intel_device_info intel_g33_info = {
151        GEN3_FEATURES,
152        .is_g33 = 1,
153        .has_hotplug = 1,
154        .has_overlay = 1,
155};
156
157static const struct intel_device_info intel_g45_info = {
158        GEN4_FEATURES,
159        .is_g4x = 1,
160        .has_pipe_cxsr = 1,
161        .ring_mask = RENDER_RING | BSD_RING,
162};
163
164static const struct intel_device_info intel_gm45_info = {
165        GEN4_FEATURES,
166        .is_g4x = 1,
167        .is_mobile = 1, .has_fbc = 1,
168        .has_pipe_cxsr = 1,
169        .supports_tv = 1,
170        .ring_mask = RENDER_RING | BSD_RING,
171};
172
173static const struct intel_device_info intel_pineview_info = {
174        GEN3_FEATURES,
175        .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
176        .has_hotplug = 1,
177        .has_overlay = 1,
178};
179
180#define GEN5_FEATURES \
181        .gen = 5, .num_pipes = 2, \
182        .has_hotplug = 1, \
183        .has_gmbus_irq = 1, \
184        .ring_mask = RENDER_RING | BSD_RING, \
185        GEN_DEFAULT_PIPEOFFSETS, \
186        CURSOR_OFFSETS
187
188static const struct intel_device_info intel_ironlake_d_info = {
189        GEN5_FEATURES,
190};
191
192static const struct intel_device_info intel_ironlake_m_info = {
193        GEN5_FEATURES,
194        .is_mobile = 1,
195};
196
197#define GEN6_FEATURES \
198        .gen = 6, .num_pipes = 2, \
199        .has_hotplug = 1, \
200        .has_fbc = 1, \
201        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
202        .has_llc = 1, \
203        .has_rc6 = 1, \
204        .has_rc6p = 1, \
205        .has_gmbus_irq = 1, \
206        .has_hw_contexts = 1, \
207        GEN_DEFAULT_PIPEOFFSETS, \
208        CURSOR_OFFSETS
209
210static const struct intel_device_info intel_sandybridge_d_info = {
211        GEN6_FEATURES,
212};
213
214static const struct intel_device_info intel_sandybridge_m_info = {
215        GEN6_FEATURES,
216        .is_mobile = 1,
217};
218
219#define GEN7_FEATURES  \
220        .gen = 7, .num_pipes = 3, \
221        .has_hotplug = 1, \
222        .has_fbc = 1, \
223        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
224        .has_llc = 1, \
225        .has_rc6 = 1, \
226        .has_rc6p = 1, \
227        .has_gmbus_irq = 1, \
228        .has_hw_contexts = 1, \
229        GEN_DEFAULT_PIPEOFFSETS, \
230        IVB_CURSOR_OFFSETS
231
232static const struct intel_device_info intel_ivybridge_d_info = {
233        GEN7_FEATURES,
234        .is_ivybridge = 1,
235        .has_l3_dpf = 1,
236};
237
238static const struct intel_device_info intel_ivybridge_m_info = {
239        GEN7_FEATURES,
240        .is_ivybridge = 1,
241        .is_mobile = 1,
242        .has_l3_dpf = 1,
243};
244
245static const struct intel_device_info intel_ivybridge_q_info = {
246        GEN7_FEATURES,
247        .is_ivybridge = 1,
248        .num_pipes = 0, /* legal, last one wins */
249        .has_l3_dpf = 1,
250};
251
252#define VLV_FEATURES  \
253        .gen = 7, .num_pipes = 2, \
254        .has_psr = 1, \
255        .has_runtime_pm = 1, \
256        .has_rc6 = 1, \
257        .has_gmbus_irq = 1, \
258        .has_hw_contexts = 1, \
259        .has_gmch_display = 1, \
260        .has_hotplug = 1, \
261        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
262        .display_mmio_offset = VLV_DISPLAY_BASE, \
263        GEN_DEFAULT_PIPEOFFSETS, \
264        CURSOR_OFFSETS
265
266static const struct intel_device_info intel_valleyview_info = {
267        VLV_FEATURES,
268        .is_valleyview = 1,
269};
270
271#define HSW_FEATURES  \
272        GEN7_FEATURES, \
273        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
274        .has_ddi = 1, \
275        .has_fpga_dbg = 1, \
276        .has_psr = 1, \
277        .has_resource_streamer = 1, \
278        .has_dp_mst = 1, \
279        .has_rc6p = 0 /* RC6p removed-by HSW */, \
280        .has_runtime_pm = 1
281
282static const struct intel_device_info intel_haswell_info = {
283        HSW_FEATURES,
284        .is_haswell = 1,
285        .has_l3_dpf = 1,
286};
287
288#define BDW_FEATURES \
289        HSW_FEATURES, \
290        BDW_COLORS, \
291        .has_logical_ring_contexts = 1
292
293static const struct intel_device_info intel_broadwell_info = {
294        BDW_FEATURES,
295        .gen = 8,
296        .is_broadwell = 1,
297};
298
299static const struct intel_device_info intel_broadwell_gt3_info = {
300        BDW_FEATURES,
301        .gen = 8,
302        .is_broadwell = 1,
303        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
304};
305
306static const struct intel_device_info intel_cherryview_info = {
307        .gen = 8, .num_pipes = 3,
308        .has_hotplug = 1,
309        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
310        .is_cherryview = 1,
311        .has_psr = 1,
312        .has_runtime_pm = 1,
313        .has_resource_streamer = 1,
314        .has_rc6 = 1,
315        .has_gmbus_irq = 1,
316        .has_hw_contexts = 1,
317        .has_logical_ring_contexts = 1,
318        .has_gmch_display = 1,
319        .display_mmio_offset = VLV_DISPLAY_BASE,
320        GEN_CHV_PIPEOFFSETS,
321        CURSOR_OFFSETS,
322        CHV_COLORS,
323};
324
325static const struct intel_device_info intel_skylake_info = {
326        BDW_FEATURES,
327        .is_skylake = 1,
328        .gen = 9,
329        .has_csr = 1,
330        .has_guc = 1,
331        .ddb_size = 896,
332};
333
334static const struct intel_device_info intel_skylake_gt3_info = {
335        BDW_FEATURES,
336        .is_skylake = 1,
337        .gen = 9,
338        .has_csr = 1,
339        .has_guc = 1,
340        .ddb_size = 896,
341        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
342};
343
344static const struct intel_device_info intel_broxton_info = {
345        .is_broxton = 1,
346        .gen = 9,
347        .has_hotplug = 1,
348        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
349        .num_pipes = 3,
350        .has_ddi = 1,
351        .has_fpga_dbg = 1,
352        .has_fbc = 1,
353        .has_runtime_pm = 1,
354        .has_pooled_eu = 0,
355        .has_csr = 1,
356        .has_resource_streamer = 1,
357        .has_rc6 = 1,
358        .has_dp_mst = 1,
359        .has_gmbus_irq = 1,
360        .has_hw_contexts = 1,
361        .has_logical_ring_contexts = 1,
362        .has_guc = 1,
363        .ddb_size = 512,
364        GEN_DEFAULT_PIPEOFFSETS,
365        IVB_CURSOR_OFFSETS,
366        BDW_COLORS,
367};
368
369static const struct intel_device_info intel_kabylake_info = {
370        BDW_FEATURES,
371        .is_kabylake = 1,
372        .gen = 9,
373        .has_csr = 1,
374        .has_guc = 1,
375        .ddb_size = 896,
376};
377
378static const struct intel_device_info intel_kabylake_gt3_info = {
379        BDW_FEATURES,
380        .is_kabylake = 1,
381        .gen = 9,
382        .has_csr = 1,
383        .has_guc = 1,
384        .ddb_size = 896,
385        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
386};
387
388/*
389 * Make sure any device matches here are from most specific to most
390 * general.  For example, since the Quanta match is based on the subsystem
391 * and subvendor IDs, we need it to come before the more general IVB
392 * PCI ID matches, otherwise we'll use the wrong info struct above.
393 */
394static const struct pci_device_id pciidlist[] = {
395        INTEL_I830_IDS(&intel_i830_info),
396        INTEL_I845G_IDS(&intel_845g_info),
397        INTEL_I85X_IDS(&intel_i85x_info),
398        INTEL_I865G_IDS(&intel_i865g_info),
399        INTEL_I915G_IDS(&intel_i915g_info),
400        INTEL_I915GM_IDS(&intel_i915gm_info),
401        INTEL_I945G_IDS(&intel_i945g_info),
402        INTEL_I945GM_IDS(&intel_i945gm_info),
403        INTEL_I965G_IDS(&intel_i965g_info),
404        INTEL_G33_IDS(&intel_g33_info),
405        INTEL_I965GM_IDS(&intel_i965gm_info),
406        INTEL_GM45_IDS(&intel_gm45_info),
407        INTEL_G45_IDS(&intel_g45_info),
408        INTEL_PINEVIEW_IDS(&intel_pineview_info),
409        INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
410        INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
411        INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
412        INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
413        INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
414        INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
415        INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
416        INTEL_HSW_IDS(&intel_haswell_info),
417        INTEL_VLV_IDS(&intel_valleyview_info),
418        INTEL_BDW_GT12_IDS(&intel_broadwell_info),
419        INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
420        INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
421        INTEL_CHV_IDS(&intel_cherryview_info),
422        INTEL_SKL_GT1_IDS(&intel_skylake_info),
423        INTEL_SKL_GT2_IDS(&intel_skylake_info),
424        INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
425        INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
426        INTEL_BXT_IDS(&intel_broxton_info),
427        INTEL_KBL_GT1_IDS(&intel_kabylake_info),
428        INTEL_KBL_GT2_IDS(&intel_kabylake_info),
429        INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
430        INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
431        {0, 0, 0}
432};
433MODULE_DEVICE_TABLE(pci, pciidlist);
434
435static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
436{
437        struct intel_device_info *intel_info =
438                (struct intel_device_info *) ent->driver_data;
439
440        if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
441                DRM_INFO("This hardware requires preliminary hardware support.\n"
442                         "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
443                return -ENODEV;
444        }
445
446        /* Only bind to function 0 of the device. Early generations
447         * used function 1 as a placeholder for multi-head. This causes
448         * us confusion instead, especially on the systems where both
449         * functions have the same PCI-ID!
450         */
451        if (PCI_FUNC(pdev->devfn))
452                return -ENODEV;
453
454        /*
455         * apple-gmux is needed on dual GPU MacBook Pro
456         * to probe the panel if we're the inactive GPU.
457         */
458        if (vga_switcheroo_client_probe_defer(pdev))
459                return -EPROBE_DEFER;
460
461        return i915_driver_load(pdev, ent);
462}
463
464static void i915_pci_remove(struct pci_dev *pdev)
465{
466        struct drm_device *dev = pci_get_drvdata(pdev);
467
468        i915_driver_unload(dev);
469        drm_dev_unref(dev);
470}
471
472static struct pci_driver i915_pci_driver = {
473        .name = DRIVER_NAME,
474        .id_table = pciidlist,
475        .probe = i915_pci_probe,
476        .remove = i915_pci_remove,
477        .driver.pm = &i915_pm_ops,
478};
479
480static int __init i915_init(void)
481{
482        bool use_kms = true;
483
484        /*
485         * Enable KMS by default, unless explicitly overriden by
486         * either the i915.modeset prarameter or by the
487         * vga_text_mode_force boot option.
488         */
489
490        if (i915.modeset == 0)
491                use_kms = false;
492
493        if (vgacon_text_force() && i915.modeset == -1)
494                use_kms = false;
495
496        if (!use_kms) {
497                /* Silently fail loading to not upset userspace. */
498                DRM_DEBUG_DRIVER("KMS disabled.\n");
499                return 0;
500        }
501
502        return pci_register_driver(&i915_pci_driver);
503}
504
505static void __exit i915_exit(void)
506{
507        if (!i915_pci_driver.driver.owner)
508                return;
509
510        pci_unregister_driver(&i915_pci_driver);
511}
512
513module_init(i915_init);
514module_exit(i915_exit);
515
516MODULE_AUTHOR("Tungsten Graphics, Inc.");
517MODULE_AUTHOR("Intel Corporation");
518
519MODULE_DESCRIPTION(DRIVER_DESC);
520MODULE_LICENSE("GPL and additional rights");
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