source: src/linux/universal/linux-4.9/drivers/gpu/drm/i915/intel_pm.c @ 31884

Last change on this file since 31884 was 31884, checked in by brainslayer, 4 months ago

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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include <drm/drm_plane_helper.h>
30#include "i915_drv.h"
31#include "intel_drv.h"
32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
34
35/**
36 * DOC: RC6
37 *
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage.  This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE                        (1<<0)
55#define INTEL_RC6p_ENABLE                       (1<<1)
56#define INTEL_RC6pp_ENABLE                      (1<<2)
57
58static void gen9_init_clock_gating(struct drm_device *dev)
59{
60        struct drm_i915_private *dev_priv = dev->dev_private;
61
62        /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63        I915_WRITE(CHICKEN_PAR1_1,
64                   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
66        I915_WRITE(GEN8_CONFIG0,
67                   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
68
69        /* WaEnableChickenDCPR:skl,bxt,kbl */
70        I915_WRITE(GEN8_CHICKEN_DCPR_1,
71                   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
72
73        /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
74        /* WaFbcWakeMemOn:skl,bxt,kbl */
75        I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76                   DISP_FBC_WM_DIS |
77                   DISP_FBC_MEMORY_WAKE);
78
79        /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80        I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81                   ILK_DPFC_DISABLE_DUMMY0);
82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
86        struct drm_i915_private *dev_priv = to_i915(dev);
87
88        gen9_init_clock_gating(dev);
89
90        /* WaDisableSDEUnitClockGating:bxt */
91        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
94        /*
95         * FIXME:
96         * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
97         */
98        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
99                   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
100
101        /*
102         * Wa: Backlight PWM may stop in the asserted state, causing backlight
103         * to stay fully on.
104         */
105        if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106                I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107                           PWM1_GATING_DIS | PWM2_GATING_DIS);
108}
109
110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
112        struct drm_i915_private *dev_priv = to_i915(dev);
113        u32 tmp;
114
115        tmp = I915_READ(CLKCFG);
116
117        switch (tmp & CLKCFG_FSB_MASK) {
118        case CLKCFG_FSB_533:
119                dev_priv->fsb_freq = 533; /* 133*4 */
120                break;
121        case CLKCFG_FSB_800:
122                dev_priv->fsb_freq = 800; /* 200*4 */
123                break;
124        case CLKCFG_FSB_667:
125                dev_priv->fsb_freq =  667; /* 167*4 */
126                break;
127        case CLKCFG_FSB_400:
128                dev_priv->fsb_freq = 400; /* 100*4 */
129                break;
130        }
131
132        switch (tmp & CLKCFG_MEM_MASK) {
133        case CLKCFG_MEM_533:
134                dev_priv->mem_freq = 533;
135                break;
136        case CLKCFG_MEM_667:
137                dev_priv->mem_freq = 667;
138                break;
139        case CLKCFG_MEM_800:
140                dev_priv->mem_freq = 800;
141                break;
142        }
143
144        /* detect pineview DDR3 setting */
145        tmp = I915_READ(CSHRDDR3CTL);
146        dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
151        struct drm_i915_private *dev_priv = to_i915(dev);
152        u16 ddrpll, csipll;
153
154        ddrpll = I915_READ16(DDRMPLL1);
155        csipll = I915_READ16(CSIPLL0);
156
157        switch (ddrpll & 0xff) {
158        case 0xc:
159                dev_priv->mem_freq = 800;
160                break;
161        case 0x10:
162                dev_priv->mem_freq = 1066;
163                break;
164        case 0x14:
165                dev_priv->mem_freq = 1333;
166                break;
167        case 0x18:
168                dev_priv->mem_freq = 1600;
169                break;
170        default:
171                DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172                                 ddrpll & 0xff);
173                dev_priv->mem_freq = 0;
174                break;
175        }
176
177        dev_priv->ips.r_t = dev_priv->mem_freq;
178
179        switch (csipll & 0x3ff) {
180        case 0x00c:
181                dev_priv->fsb_freq = 3200;
182                break;
183        case 0x00e:
184                dev_priv->fsb_freq = 3733;
185                break;
186        case 0x010:
187                dev_priv->fsb_freq = 4266;
188                break;
189        case 0x012:
190                dev_priv->fsb_freq = 4800;
191                break;
192        case 0x014:
193                dev_priv->fsb_freq = 5333;
194                break;
195        case 0x016:
196                dev_priv->fsb_freq = 5866;
197                break;
198        case 0x018:
199                dev_priv->fsb_freq = 6400;
200                break;
201        default:
202                DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203                                 csipll & 0x3ff);
204                dev_priv->fsb_freq = 0;
205                break;
206        }
207
208        if (dev_priv->fsb_freq == 3200) {
209                dev_priv->ips.c_m = 0;
210        } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
211                dev_priv->ips.c_m = 1;
212        } else {
213                dev_priv->ips.c_m = 2;
214        }
215}
216
217static const struct cxsr_latency cxsr_latency_table[] = {
218        {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
219        {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
220        {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
221        {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
222        {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
223
224        {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
225        {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
226        {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
227        {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
228        {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
229
230        {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
231        {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
232        {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
233        {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
234        {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
235
236        {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
237        {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
238        {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
239        {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
240        {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
241
242        {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
243        {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
244        {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
245        {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
246        {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
247
248        {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
249        {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
250        {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
251        {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
252        {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
253};
254
255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
256                                                         int is_ddr3,
257                                                         int fsb,
258                                                         int mem)
259{
260        const struct cxsr_latency *latency;
261        int i;
262
263        if (fsb == 0 || mem == 0)
264                return NULL;
265
266        for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267                latency = &cxsr_latency_table[i];
268                if (is_desktop == latency->is_desktop &&
269                    is_ddr3 == latency->is_ddr3 &&
270                    fsb == latency->fsb_freq && mem == latency->mem_freq)
271                        return latency;
272        }
273
274        DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276        return NULL;
277}
278
279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281        u32 val;
282
283        mutex_lock(&dev_priv->rps.hw_lock);
284
285        val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286        if (enable)
287                val &= ~FORCE_DDR_HIGH_FREQ;
288        else
289                val |= FORCE_DDR_HIGH_FREQ;
290        val &= ~FORCE_DDR_LOW_FREQ;
291        val |= FORCE_DDR_FREQ_REQ_ACK;
292        vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294        if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295                      FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296                DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298        mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303        u32 val;
304
305        mutex_lock(&dev_priv->rps.hw_lock);
306
307        val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308        if (enable)
309                val |= DSP_MAXFIFO_PM5_ENABLE;
310        else
311                val &= ~DSP_MAXFIFO_PM5_ENABLE;
312        vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314        mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
317#define FW_WM(value, plane) \
318        (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
321{
322        struct drm_device *dev = &dev_priv->drm;
323        u32 val;
324
325        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
326                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
327                POSTING_READ(FW_BLC_SELF_VLV);
328                dev_priv->wm.vlv.cxsr = enable;
329        } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
331                POSTING_READ(FW_BLC_SELF);
332        } else if (IS_PINEVIEW(dev)) {
333                val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334                val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335                I915_WRITE(DSPFW3, val);
336                POSTING_READ(DSPFW3);
337        } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338                val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339                               _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340                I915_WRITE(FW_BLC_SELF, val);
341                POSTING_READ(FW_BLC_SELF);
342        } else if (IS_I915GM(dev)) {
343                /*
344                 * FIXME can't find a bit like this for 915G, and
345                 * and yet it does have the related watermark in
346                 * FW_BLC_SELF. What's going on?
347                 */
348                val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349                               _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350                I915_WRITE(INSTPM, val);
351                POSTING_READ(INSTPM);
352        } else {
353                return;
354        }
355
356        DRM_DEBUG_KMS("memory self-refresh is %s\n",
357                      enable ? "enabled" : "disabled");
358}
359
360
361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 *   - memory configuration (speed, channels)
364 *   - chipset
365 *   - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value.  It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
375static const int pessimal_latency_ns = 5000;
376
377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378        ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381                              enum pipe pipe, int plane)
382{
383        struct drm_i915_private *dev_priv = to_i915(dev);
384        int sprite0_start, sprite1_start, size;
385
386        switch (pipe) {
387                uint32_t dsparb, dsparb2, dsparb3;
388        case PIPE_A:
389                dsparb = I915_READ(DSPARB);
390                dsparb2 = I915_READ(DSPARB2);
391                sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392                sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393                break;
394        case PIPE_B:
395                dsparb = I915_READ(DSPARB);
396                dsparb2 = I915_READ(DSPARB2);
397                sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398                sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399                break;
400        case PIPE_C:
401                dsparb2 = I915_READ(DSPARB2);
402                dsparb3 = I915_READ(DSPARB3);
403                sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404                sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405                break;
406        default:
407                return 0;
408        }
409
410        switch (plane) {
411        case 0:
412                size = sprite0_start;
413                break;
414        case 1:
415                size = sprite1_start - sprite0_start;
416                break;
417        case 2:
418                size = 512 - 1 - sprite1_start;
419                break;
420        default:
421                return 0;
422        }
423
424        DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425                      pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426                      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427                      size);
428
429        return size;
430}
431
432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
433{
434        struct drm_i915_private *dev_priv = to_i915(dev);
435        uint32_t dsparb = I915_READ(DSPARB);
436        int size;
437
438        size = dsparb & 0x7f;
439        if (plane)
440                size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443                      plane ? "B" : "A", size);
444
445        return size;
446}
447
448static int i830_get_fifo_size(struct drm_device *dev, int plane)
449{
450        struct drm_i915_private *dev_priv = to_i915(dev);
451        uint32_t dsparb = I915_READ(DSPARB);
452        int size;
453
454        size = dsparb & 0x1ff;
455        if (plane)
456                size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457        size >>= 1; /* Convert to cachelines */
458
459        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460                      plane ? "B" : "A", size);
461
462        return size;
463}
464
465static int i845_get_fifo_size(struct drm_device *dev, int plane)
466{
467        struct drm_i915_private *dev_priv = to_i915(dev);
468        uint32_t dsparb = I915_READ(DSPARB);
469        int size;
470
471        size = dsparb & 0x7f;
472        size >>= 2; /* Convert to cachelines */
473
474        DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475                      plane ? "B" : "A",
476                      size);
477
478        return size;
479}
480
481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
483        .fifo_size = PINEVIEW_DISPLAY_FIFO,
484        .max_wm = PINEVIEW_MAX_WM,
485        .default_wm = PINEVIEW_DFT_WM,
486        .guard_size = PINEVIEW_GUARD_WM,
487        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
490        .fifo_size = PINEVIEW_DISPLAY_FIFO,
491        .max_wm = PINEVIEW_MAX_WM,
492        .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493        .guard_size = PINEVIEW_GUARD_WM,
494        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
495};
496static const struct intel_watermark_params pineview_cursor_wm = {
497        .fifo_size = PINEVIEW_CURSOR_FIFO,
498        .max_wm = PINEVIEW_CURSOR_MAX_WM,
499        .default_wm = PINEVIEW_CURSOR_DFT_WM,
500        .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
504        .fifo_size = PINEVIEW_CURSOR_FIFO,
505        .max_wm = PINEVIEW_CURSOR_MAX_WM,
506        .default_wm = PINEVIEW_CURSOR_DFT_WM,
507        .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508        .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
509};
510static const struct intel_watermark_params g4x_wm_info = {
511        .fifo_size = G4X_FIFO_SIZE,
512        .max_wm = G4X_MAX_WM,
513        .default_wm = G4X_MAX_WM,
514        .guard_size = 2,
515        .cacheline_size = G4X_FIFO_LINE_SIZE,
516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
518        .fifo_size = I965_CURSOR_FIFO,
519        .max_wm = I965_CURSOR_MAX_WM,
520        .default_wm = I965_CURSOR_DFT_WM,
521        .guard_size = 2,
522        .cacheline_size = G4X_FIFO_LINE_SIZE,
523};
524static const struct intel_watermark_params i965_cursor_wm_info = {
525        .fifo_size = I965_CURSOR_FIFO,
526        .max_wm = I965_CURSOR_MAX_WM,
527        .default_wm = I965_CURSOR_DFT_WM,
528        .guard_size = 2,
529        .cacheline_size = I915_FIFO_LINE_SIZE,
530};
531static const struct intel_watermark_params i945_wm_info = {
532        .fifo_size = I945_FIFO_SIZE,
533        .max_wm = I915_MAX_WM,
534        .default_wm = 1,
535        .guard_size = 2,
536        .cacheline_size = I915_FIFO_LINE_SIZE,
537};
538static const struct intel_watermark_params i915_wm_info = {
539        .fifo_size = I915_FIFO_SIZE,
540        .max_wm = I915_MAX_WM,
541        .default_wm = 1,
542        .guard_size = 2,
543        .cacheline_size = I915_FIFO_LINE_SIZE,
544};
545static const struct intel_watermark_params i830_a_wm_info = {
546        .fifo_size = I855GM_FIFO_SIZE,
547        .max_wm = I915_MAX_WM,
548        .default_wm = 1,
549        .guard_size = 2,
550        .cacheline_size = I830_FIFO_LINE_SIZE,
551};
552static const struct intel_watermark_params i830_bc_wm_info = {
553        .fifo_size = I855GM_FIFO_SIZE,
554        .max_wm = I915_MAX_WM/2,
555        .default_wm = 1,
556        .guard_size = 2,
557        .cacheline_size = I830_FIFO_LINE_SIZE,
558};
559static const struct intel_watermark_params i845_wm_info = {
560        .fifo_size = I830_FIFO_SIZE,
561        .max_wm = I915_MAX_WM,
562        .default_wm = 1,
563        .guard_size = 2,
564        .cacheline_size = I830_FIFO_LINE_SIZE,
565};
566
567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
571 * @cpp: bytes per pixel
572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again).  Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size.  When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586                                        const struct intel_watermark_params *wm,
587                                        int fifo_size, int cpp,
588                                        unsigned long latency_ns)
589{
590        long entries_required, wm_size;
591
592        /*
593         * Note: we need to make sure we don't overflow for various clock &
594         * latency values.
595         * clocks go from a few thousand to several hundred thousand.
596         * latency is usually a few thousand
597         */
598        entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
599                1000;
600        entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602        DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604        wm_size = fifo_size - (entries_required + wm->guard_size);
605
606        DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608        /* Don't promote wm_size to unsigned... */
609        if (wm_size > (long)wm->max_wm)
610                wm_size = wm->max_wm;
611        if (wm_size <= 0)
612                wm_size = wm->default_wm;
613
614        /*
615         * Bspec seems to indicate that the value shouldn't be lower than
616         * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617         * Lets go for 8 which is the burst size since certain platforms
618         * already use a hardcoded 8 (which is what the spec says should be
619         * done).
620         */
621        if (wm_size <= 8)
622                wm_size = 8;
623
624        return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629        struct drm_crtc *crtc, *enabled = NULL;
630
631        for_each_crtc(dev, crtc) {
632                if (intel_crtc_active(crtc)) {
633                        if (enabled)
634                                return NULL;
635                        enabled = crtc;
636                }
637        }
638
639        return enabled;
640}
641
642static void pineview_update_wm(struct drm_crtc *unused_crtc)
643{
644        struct drm_device *dev = unused_crtc->dev;
645        struct drm_i915_private *dev_priv = to_i915(dev);
646        struct drm_crtc *crtc;
647        const struct cxsr_latency *latency;
648        u32 reg;
649        unsigned long wm;
650
651        latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652                                         dev_priv->fsb_freq, dev_priv->mem_freq);
653        if (!latency) {
654                DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
655                intel_set_memory_cxsr(dev_priv, false);
656                return;
657        }
658
659        crtc = single_enabled_crtc(dev);
660        if (crtc) {
661                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
662                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
663                int clock = adjusted_mode->crtc_clock;
664
665                /* Display SR */
666                wm = intel_calculate_wm(clock, &pineview_display_wm,
667                                        pineview_display_wm.fifo_size,
668                                        cpp, latency->display_sr);
669                reg = I915_READ(DSPFW1);
670                reg &= ~DSPFW_SR_MASK;
671                reg |= FW_WM(wm, SR);
672                I915_WRITE(DSPFW1, reg);
673                DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675                /* cursor SR */
676                wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677                                        pineview_display_wm.fifo_size,
678                                        cpp, latency->cursor_sr);
679                reg = I915_READ(DSPFW3);
680                reg &= ~DSPFW_CURSOR_SR_MASK;
681                reg |= FW_WM(wm, CURSOR_SR);
682                I915_WRITE(DSPFW3, reg);
683
684                /* Display HPLL off SR */
685                wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686                                        pineview_display_hplloff_wm.fifo_size,
687                                        cpp, latency->display_hpll_disable);
688                reg = I915_READ(DSPFW3);
689                reg &= ~DSPFW_HPLL_SR_MASK;
690                reg |= FW_WM(wm, HPLL_SR);
691                I915_WRITE(DSPFW3, reg);
692
693                /* cursor HPLL off SR */
694                wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695                                        pineview_display_hplloff_wm.fifo_size,
696                                        cpp, latency->cursor_hpll_disable);
697                reg = I915_READ(DSPFW3);
698                reg &= ~DSPFW_HPLL_CURSOR_MASK;
699                reg |= FW_WM(wm, HPLL_CURSOR);
700                I915_WRITE(DSPFW3, reg);
701                DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
703                intel_set_memory_cxsr(dev_priv, true);
704        } else {
705                intel_set_memory_cxsr(dev_priv, false);
706        }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710                            int plane,
711                            const struct intel_watermark_params *display,
712                            int display_latency_ns,
713                            const struct intel_watermark_params *cursor,
714                            int cursor_latency_ns,
715                            int *plane_wm,
716                            int *cursor_wm)
717{
718        struct drm_crtc *crtc;
719        const struct drm_display_mode *adjusted_mode;
720        int htotal, hdisplay, clock, cpp;
721        int line_time_us, line_count;
722        int entries, tlb_miss;
723
724        crtc = intel_get_crtc_for_plane(dev, plane);
725        if (!intel_crtc_active(crtc)) {
726                *cursor_wm = cursor->guard_size;
727                *plane_wm = display->guard_size;
728                return false;
729        }
730
731        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
732        clock = adjusted_mode->crtc_clock;
733        htotal = adjusted_mode->crtc_htotal;
734        hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
735        cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
736
737        /* Use the small buffer method to calculate plane watermark */
738        entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
739        tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740        if (tlb_miss > 0)
741                entries += tlb_miss;
742        entries = DIV_ROUND_UP(entries, display->cacheline_size);
743        *plane_wm = entries + display->guard_size;
744        if (*plane_wm > (int)display->max_wm)
745                *plane_wm = display->max_wm;
746
747        /* Use the large buffer method to calculate cursor watermark */
748        line_time_us = max(htotal * 1000 / clock, 1);
749        line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
750        entries = line_count * crtc->cursor->state->crtc_w * cpp;
751        tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752        if (tlb_miss > 0)
753                entries += tlb_miss;
754        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755        *cursor_wm = entries + cursor->guard_size;
756        if (*cursor_wm > (int)cursor->max_wm)
757                *cursor_wm = (int)cursor->max_wm;
758
759        return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770                           int display_wm, int cursor_wm,
771                           const struct intel_watermark_params *display,
772                           const struct intel_watermark_params *cursor)
773{
774        DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775                      display_wm, cursor_wm);
776
777        if (display_wm > display->max_wm) {
778                DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779                              display_wm, display->max_wm);
780                return false;
781        }
782
783        if (cursor_wm > cursor->max_wm) {
784                DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785                              cursor_wm, cursor->max_wm);
786                return false;
787        }
788
789        if (!(display_wm || cursor_wm)) {
790                DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791                return false;
792        }
793
794        return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798                             int plane,
799                             int latency_ns,
800                             const struct intel_watermark_params *display,
801                             const struct intel_watermark_params *cursor,
802                             int *display_wm, int *cursor_wm)
803{
804        struct drm_crtc *crtc;
805        const struct drm_display_mode *adjusted_mode;
806        int hdisplay, htotal, cpp, clock;
807        unsigned long line_time_us;
808        int line_count, line_size;
809        int small, large;
810        int entries;
811
812        if (!latency_ns) {
813                *display_wm = *cursor_wm = 0;
814                return false;
815        }
816
817        crtc = intel_get_crtc_for_plane(dev, plane);
818        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
819        clock = adjusted_mode->crtc_clock;
820        htotal = adjusted_mode->crtc_htotal;
821        hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
822        cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
823
824        line_time_us = max(htotal * 1000 / clock, 1);
825        line_count = (latency_ns / line_time_us + 1000) / 1000;
826        line_size = hdisplay * cpp;
827
828        /* Use the minimum of the small and large buffer method for primary */
829        small = ((clock * cpp / 1000) * latency_ns) / 1000;
830        large = line_count * line_size;
831
832        entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833        *display_wm = entries + display->guard_size;
834
835        /* calculate the self-refresh watermark for display cursor */
836        entries = line_count * cpp * crtc->cursor->state->crtc_w;
837        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838        *cursor_wm = entries + cursor->guard_size;
839
840        return g4x_check_srwm(dev,
841                              *display_wm, *cursor_wm,
842                              display, cursor);
843}
844
845#define FW_WM_VLV(value, plane) \
846        (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
848static void vlv_write_wm_values(struct intel_crtc *crtc,
849                                const struct vlv_wm_values *wm)
850{
851        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852        enum pipe pipe = crtc->pipe;
853
854        I915_WRITE(VLV_DDL(pipe),
855                   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856                   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857                   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858                   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
860        I915_WRITE(DSPFW1,
861                   FW_WM(wm->sr.plane, SR) |
862                   FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863                   FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864                   FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
865        I915_WRITE(DSPFW2,
866                   FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867                   FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868                   FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
869        I915_WRITE(DSPFW3,
870                   FW_WM(wm->sr.cursor, CURSOR_SR));
871
872        if (IS_CHERRYVIEW(dev_priv)) {
873                I915_WRITE(DSPFW7_CHV,
874                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
876                I915_WRITE(DSPFW8_CHV,
877                           FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878                           FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
879                I915_WRITE(DSPFW9_CHV,
880                           FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881                           FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
882                I915_WRITE(DSPHOWM,
883                           FW_WM(wm->sr.plane >> 9, SR_HI) |
884                           FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885                           FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886                           FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887                           FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888                           FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889                           FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890                           FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891                           FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892                           FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
893        } else {
894                I915_WRITE(DSPFW7,
895                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896                           FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
897                I915_WRITE(DSPHOWM,
898                           FW_WM(wm->sr.plane >> 9, SR_HI) |
899                           FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900                           FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901                           FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902                           FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903                           FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904                           FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
905        }
906
907        /* zero (unused) WM1 watermarks */
908        I915_WRITE(DSPFW4, 0);
909        I915_WRITE(DSPFW5, 0);
910        I915_WRITE(DSPFW6, 0);
911        I915_WRITE(DSPHOWM1, 0);
912
913        POSTING_READ(DSPFW1);
914}
915
916#undef FW_WM_VLV
917
918enum vlv_wm_level {
919        VLV_WM_LEVEL_PM2,
920        VLV_WM_LEVEL_PM5,
921        VLV_WM_LEVEL_DDR_DVFS,
922};
923
924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926                                   unsigned int pipe_htotal,
927                                   unsigned int horiz_pixels,
928                                   unsigned int cpp,
929                                   unsigned int latency)
930{
931        unsigned int ret;
932
933        ret = (latency * pixel_rate) / (pipe_htotal * 10000);
934        ret = (ret + 1) * horiz_pixels * cpp;
935        ret = DIV_ROUND_UP(ret, 64);
936
937        return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
942        struct drm_i915_private *dev_priv = to_i915(dev);
943
944        /* all latencies in usec */
945        dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
947        dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
949        if (IS_CHERRYVIEW(dev_priv)) {
950                dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951                dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
952
953                dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
954        }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958                                     struct intel_crtc *crtc,
959                                     const struct intel_plane_state *state,
960                                     int level)
961{
962        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
963        int clock, htotal, cpp, width, wm;
964
965        if (dev_priv->wm.pri_latency[level] == 0)
966                return USHRT_MAX;
967
968        if (!state->base.visible)
969                return 0;
970
971        cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
972        clock = crtc->config->base.adjusted_mode.crtc_clock;
973        htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974        width = crtc->config->pipe_src_w;
975        if (WARN_ON(htotal == 0))
976                htotal = 1;
977
978        if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979                /*
980                 * FIXME the formula gives values that are
981                 * too big for the cursor FIFO, and hence we
982                 * would never be able to use cursors. For
983                 * now just hardcode the watermark.
984                 */
985                wm = 63;
986        } else {
987                wm = vlv_wm_method2(clock, htotal, width, cpp,
988                                    dev_priv->wm.pri_latency[level] * 10);
989        }
990
991        return min_t(int, wm, USHRT_MAX);
992}
993
994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996        struct drm_device *dev = crtc->base.dev;
997        struct vlv_wm_state *wm_state = &crtc->wm_state;
998        struct intel_plane *plane;
999        unsigned int total_rate = 0;
1000        const int fifo_size = 512 - 1;
1001        int fifo_extra, fifo_left = fifo_size;
1002
1003        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004                struct intel_plane_state *state =
1005                        to_intel_plane_state(plane->base.state);
1006
1007                if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008                        continue;
1009
1010                if (state->base.visible) {
1011                        wm_state->num_active_planes++;
1012                        total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                }
1014        }
1015
1016        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017                struct intel_plane_state *state =
1018                        to_intel_plane_state(plane->base.state);
1019                unsigned int rate;
1020
1021                if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022                        plane->wm.fifo_size = 63;
1023                        continue;
1024                }
1025
1026                if (!state->base.visible) {
1027                        plane->wm.fifo_size = 0;
1028                        continue;
1029                }
1030
1031                rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032                plane->wm.fifo_size = fifo_size * rate / total_rate;
1033                fifo_left -= plane->wm.fifo_size;
1034        }
1035
1036        fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038        /* spread the remainder evenly */
1039        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040                int plane_extra;
1041
1042                if (fifo_left == 0)
1043                        break;
1044
1045                if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046                        continue;
1047
1048                /* give it all to the first plane if none are active */
1049                if (plane->wm.fifo_size == 0 &&
1050                    wm_state->num_active_planes)
1051                        continue;
1052
1053                plane_extra = min(fifo_extra, fifo_left);
1054                plane->wm.fifo_size += plane_extra;
1055                fifo_left -= plane_extra;
1056        }
1057
1058        WARN_ON(fifo_left != 0);
1059}
1060
1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063        struct vlv_wm_state *wm_state = &crtc->wm_state;
1064        int level;
1065
1066        for (level = 0; level < wm_state->num_levels; level++) {
1067                struct drm_device *dev = crtc->base.dev;
1068                const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069                struct intel_plane *plane;
1070
1071                wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072                wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074                for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075                        switch (plane->base.type) {
1076                                int sprite;
1077                        case DRM_PLANE_TYPE_CURSOR:
1078                                wm_state->wm[level].cursor = plane->wm.fifo_size -
1079                                        wm_state->wm[level].cursor;
1080                                break;
1081                        case DRM_PLANE_TYPE_PRIMARY:
1082                                wm_state->wm[level].primary = plane->wm.fifo_size -
1083                                        wm_state->wm[level].primary;
1084                                break;
1085                        case DRM_PLANE_TYPE_OVERLAY:
1086                                sprite = plane->plane;
1087                                wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088                                        wm_state->wm[level].sprite[sprite];
1089                                break;
1090                        }
1091                }
1092        }
1093}
1094
1095static void vlv_compute_wm(struct intel_crtc *crtc)
1096{
1097        struct drm_device *dev = crtc->base.dev;
1098        struct vlv_wm_state *wm_state = &crtc->wm_state;
1099        struct intel_plane *plane;
1100        int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101        int level;
1102
1103        memset(wm_state, 0, sizeof(*wm_state));
1104
1105        wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1106        wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1107
1108        wm_state->num_active_planes = 0;
1109
1110        vlv_compute_fifo(crtc);
1111
1112        if (wm_state->num_active_planes != 1)
1113                wm_state->cxsr = false;
1114
1115        if (wm_state->cxsr) {
1116                for (level = 0; level < wm_state->num_levels; level++) {
1117                        wm_state->sr[level].plane = sr_fifo_size;
1118                        wm_state->sr[level].cursor = 63;
1119                }
1120        }
1121
1122        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123                struct intel_plane_state *state =
1124                        to_intel_plane_state(plane->base.state);
1125
1126                if (!state->base.visible)
1127                        continue;
1128
1129                /* normal watermarks */
1130                for (level = 0; level < wm_state->num_levels; level++) {
1131                        int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132                        int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134                        /* hack */
1135                        if (WARN_ON(level == 0 && wm > max_wm))
1136                                wm = max_wm;
1137
1138                        if (wm > plane->wm.fifo_size)
1139                                break;
1140
1141                        switch (plane->base.type) {
1142                                int sprite;
1143                        case DRM_PLANE_TYPE_CURSOR:
1144                                wm_state->wm[level].cursor = wm;
1145                                break;
1146                        case DRM_PLANE_TYPE_PRIMARY:
1147                                wm_state->wm[level].primary = wm;
1148                                break;
1149                        case DRM_PLANE_TYPE_OVERLAY:
1150                                sprite = plane->plane;
1151                                wm_state->wm[level].sprite[sprite] = wm;
1152                                break;
1153                        }
1154                }
1155
1156                wm_state->num_levels = level;
1157
1158                if (!wm_state->cxsr)
1159                        continue;
1160
1161                /* maxfifo watermarks */
1162                switch (plane->base.type) {
1163                        int sprite, level;
1164                case DRM_PLANE_TYPE_CURSOR:
1165                        for (level = 0; level < wm_state->num_levels; level++)
1166                                wm_state->sr[level].cursor =
1167                                        wm_state->wm[level].cursor;
1168                        break;
1169                case DRM_PLANE_TYPE_PRIMARY:
1170                        for (level = 0; level < wm_state->num_levels; level++)
1171                                wm_state->sr[level].plane =
1172                                        min(wm_state->sr[level].plane,
1173                                            wm_state->wm[level].primary);
1174                        break;
1175                case DRM_PLANE_TYPE_OVERLAY:
1176                        sprite = plane->plane;
1177                        for (level = 0; level < wm_state->num_levels; level++)
1178                                wm_state->sr[level].plane =
1179                                        min(wm_state->sr[level].plane,
1180                                            wm_state->wm[level].sprite[sprite]);
1181                        break;
1182                }
1183        }
1184
1185        /* clear any (partially) filled invalid levels */
1186        for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1187                memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188                memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189        }
1190
1191        vlv_invert_wms(crtc);
1192}
1193
1194#define VLV_FIFO(plane, value) \
1195        (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199        struct drm_device *dev = crtc->base.dev;
1200        struct drm_i915_private *dev_priv = to_i915(dev);
1201        struct intel_plane *plane;
1202        int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204        for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205                if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206                        WARN_ON(plane->wm.fifo_size != 63);
1207                        continue;
1208                }
1209
1210                if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211                        sprite0_start = plane->wm.fifo_size;
1212                else if (plane->plane == 0)
1213                        sprite1_start = sprite0_start + plane->wm.fifo_size;
1214                else
1215                        fifo_size = sprite1_start + plane->wm.fifo_size;
1216        }
1217
1218        WARN_ON(fifo_size != 512 - 1);
1219
1220        DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221                      pipe_name(crtc->pipe), sprite0_start,
1222                      sprite1_start, fifo_size);
1223
1224        switch (crtc->pipe) {
1225                uint32_t dsparb, dsparb2, dsparb3;
1226        case PIPE_A:
1227                dsparb = I915_READ(DSPARB);
1228                dsparb2 = I915_READ(DSPARB2);
1229
1230                dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231                            VLV_FIFO(SPRITEB, 0xff));
1232                dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233                           VLV_FIFO(SPRITEB, sprite1_start));
1234
1235                dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236                             VLV_FIFO(SPRITEB_HI, 0x1));
1237                dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238                           VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240                I915_WRITE(DSPARB, dsparb);
1241                I915_WRITE(DSPARB2, dsparb2);
1242                break;
1243        case PIPE_B:
1244                dsparb = I915_READ(DSPARB);
1245                dsparb2 = I915_READ(DSPARB2);
1246
1247                dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248                            VLV_FIFO(SPRITED, 0xff));
1249                dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250                           VLV_FIFO(SPRITED, sprite1_start));
1251
1252                dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253                             VLV_FIFO(SPRITED_HI, 0xff));
1254                dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255                           VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257                I915_WRITE(DSPARB, dsparb);
1258                I915_WRITE(DSPARB2, dsparb2);
1259                break;
1260        case PIPE_C:
1261                dsparb3 = I915_READ(DSPARB3);
1262                dsparb2 = I915_READ(DSPARB2);
1263
1264                dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265                             VLV_FIFO(SPRITEF, 0xff));
1266                dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267                            VLV_FIFO(SPRITEF, sprite1_start));
1268
1269                dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270                             VLV_FIFO(SPRITEF_HI, 0xff));
1271                dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272                           VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274                I915_WRITE(DSPARB3, dsparb3);
1275                I915_WRITE(DSPARB2, dsparb2);
1276                break;
1277        default:
1278                break;
1279        }
1280}
1281
1282#undef VLV_FIFO
1283
1284static void vlv_merge_wm(struct drm_device *dev,
1285                         struct vlv_wm_values *wm)
1286{
1287        struct intel_crtc *crtc;
1288        int num_active_crtcs = 0;
1289
1290        wm->level = to_i915(dev)->wm.max_level;
1291        wm->cxsr = true;
1292
1293        for_each_intel_crtc(dev, crtc) {
1294                const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296                if (!crtc->active)
1297                        continue;
1298
1299                if (!wm_state->cxsr)
1300                        wm->cxsr = false;
1301
1302                num_active_crtcs++;
1303                wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304        }
1305
1306        if (num_active_crtcs != 1)
1307                wm->cxsr = false;
1308
1309        if (num_active_crtcs > 1)
1310                wm->level = VLV_WM_LEVEL_PM2;
1311
1312        for_each_intel_crtc(dev, crtc) {
1313                struct vlv_wm_state *wm_state = &crtc->wm_state;
1314                enum pipe pipe = crtc->pipe;
1315
1316                if (!crtc->active)
1317                        continue;
1318
1319                wm->pipe[pipe] = wm_state->wm[wm->level];
1320                if (wm->cxsr)
1321                        wm->sr = wm_state->sr[wm->level];
1322
1323                wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324                wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325                wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326                wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327        }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332        struct drm_device *dev = crtc->dev;
1333        struct drm_i915_private *dev_priv = to_i915(dev);
1334        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335        enum pipe pipe = intel_crtc->pipe;
1336        struct vlv_wm_values wm = {};
1337
1338        vlv_compute_wm(intel_crtc);
1339        vlv_merge_wm(dev, &wm);
1340
1341        if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342                /* FIXME should be part of crtc atomic commit */
1343                vlv_pipe_set_fifo_size(intel_crtc);
1344                return;
1345        }
1346
1347        if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348            dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349                chv_set_memory_dvfs(dev_priv, false);
1350
1351        if (wm.level < VLV_WM_LEVEL_PM5 &&
1352            dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353                chv_set_memory_pm5(dev_priv, false);
1354
1355        if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1356                intel_set_memory_cxsr(dev_priv, false);
1357
1358        /* FIXME should be part of crtc atomic commit */
1359        vlv_pipe_set_fifo_size(intel_crtc);
1360
1361        vlv_write_wm_values(intel_crtc, &wm);
1362
1363        DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364                      "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365                      pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366                      wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367                      wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
1369        if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1370                intel_set_memory_cxsr(dev_priv, true);
1371
1372        if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373            dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374                chv_set_memory_pm5(dev_priv, true);
1375
1376        if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377            dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378                chv_set_memory_dvfs(dev_priv, true);
1379
1380        dev_priv->wm.vlv = wm;
1381}
1382
1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
1385static void g4x_update_wm(struct drm_crtc *crtc)
1386{
1387        struct drm_device *dev = crtc->dev;
1388        static const int sr_latency_ns = 12000;
1389        struct drm_i915_private *dev_priv = to_i915(dev);
1390        int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391        int plane_sr, cursor_sr;
1392        unsigned int enabled = 0;
1393        bool cxsr_enabled;
1394
1395        if (g4x_compute_wm0(dev, PIPE_A,
1396                            &g4x_wm_info, pessimal_latency_ns,
1397                            &g4x_cursor_wm_info, pessimal_latency_ns,
1398                            &planea_wm, &cursora_wm))
1399                enabled |= 1 << PIPE_A;
1400
1401        if (g4x_compute_wm0(dev, PIPE_B,
1402                            &g4x_wm_info, pessimal_latency_ns,
1403                            &g4x_cursor_wm_info, pessimal_latency_ns,
1404                            &planeb_wm, &cursorb_wm))
1405                enabled |= 1 << PIPE_B;
1406
1407        if (single_plane_enabled(enabled) &&
1408            g4x_compute_srwm(dev, ffs(enabled) - 1,
1409                             sr_latency_ns,
1410                             &g4x_wm_info,
1411                             &g4x_cursor_wm_info,
1412                             &plane_sr, &cursor_sr)) {
1413                cxsr_enabled = true;
1414        } else {
1415                cxsr_enabled = false;
1416                intel_set_memory_cxsr(dev_priv, false);
1417                plane_sr = cursor_sr = 0;
1418        }
1419
1420        DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421                      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422                      planea_wm, cursora_wm,
1423                      planeb_wm, cursorb_wm,
1424                      plane_sr, cursor_sr);
1425
1426        I915_WRITE(DSPFW1,
1427                   FW_WM(plane_sr, SR) |
1428                   FW_WM(cursorb_wm, CURSORB) |
1429                   FW_WM(planeb_wm, PLANEB) |
1430                   FW_WM(planea_wm, PLANEA));
1431        I915_WRITE(DSPFW2,
1432                   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433                   FW_WM(cursora_wm, CURSORA));
1434        /* HPLL off in SR has some issues on G4x... disable it */
1435        I915_WRITE(DSPFW3,
1436                   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1437                   FW_WM(cursor_sr, CURSOR_SR));
1438
1439        if (cxsr_enabled)
1440                intel_set_memory_cxsr(dev_priv, true);
1441}
1442
1443static void i965_update_wm(struct drm_crtc *unused_crtc)
1444{
1445        struct drm_device *dev = unused_crtc->dev;
1446        struct drm_i915_private *dev_priv = to_i915(dev);
1447        struct drm_crtc *crtc;
1448        int srwm = 1;
1449        int cursor_sr = 16;
1450        bool cxsr_enabled;
1451
1452        /* Calc sr entries for one plane configs */
1453        crtc = single_enabled_crtc(dev);
1454        if (crtc) {
1455                /* self-refresh has much higher latency */
1456                static const int sr_latency_ns = 12000;
1457                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1458                int clock = adjusted_mode->crtc_clock;
1459                int htotal = adjusted_mode->crtc_htotal;
1460                int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1461                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1462                unsigned long line_time_us;
1463                int entries;
1464
1465                line_time_us = max(htotal * 1000 / clock, 1);
1466
1467                /* Use ns/us then divide to preserve precision */
1468                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469                        cpp * hdisplay;
1470                entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471                srwm = I965_FIFO_SIZE - entries;
1472                if (srwm < 0)
1473                        srwm = 1;
1474                srwm &= 0x1ff;
1475                DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476                              entries, srwm);
1477
1478                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                        cpp * crtc->cursor->state->crtc_w;
1480                entries = DIV_ROUND_UP(entries,
1481                                          i965_cursor_wm_info.cacheline_size);
1482                cursor_sr = i965_cursor_wm_info.fifo_size -
1483                        (entries + i965_cursor_wm_info.guard_size);
1484
1485                if (cursor_sr > i965_cursor_wm_info.max_wm)
1486                        cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488                DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489                              "cursor %d\n", srwm, cursor_sr);
1490
1491                cxsr_enabled = true;
1492        } else {
1493                cxsr_enabled = false;
1494                /* Turn off self refresh if both pipes are enabled */
1495                intel_set_memory_cxsr(dev_priv, false);
1496        }
1497
1498        DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499                      srwm);
1500
1501        /* 965 has limitations... */
1502        I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503                   FW_WM(8, CURSORB) |
1504                   FW_WM(8, PLANEB) |
1505                   FW_WM(8, PLANEA));
1506        I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507                   FW_WM(8, PLANEC_OLD));
1508        /* update cursor SR watermark */
1509        I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1510
1511        if (cxsr_enabled)
1512                intel_set_memory_cxsr(dev_priv, true);
1513}
1514
1515#undef FW_WM
1516
1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1518{
1519        struct drm_device *dev = unused_crtc->dev;
1520        struct drm_i915_private *dev_priv = to_i915(dev);
1521        const struct intel_watermark_params *wm_info;
1522        uint32_t fwater_lo;
1523        uint32_t fwater_hi;
1524        int cwm, srwm = 1;
1525        int fifo_size;
1526        int planea_wm, planeb_wm;
1527        struct drm_crtc *crtc, *enabled = NULL;
1528
1529        if (IS_I945GM(dev))
1530                wm_info = &i945_wm_info;
1531        else if (!IS_GEN2(dev))
1532                wm_info = &i915_wm_info;
1533        else
1534                wm_info = &i830_a_wm_info;
1535
1536        fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537        crtc = intel_get_crtc_for_plane(dev, 0);
1538        if (intel_crtc_active(crtc)) {
1539                const struct drm_display_mode *adjusted_mode;
1540                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1541                if (IS_GEN2(dev))
1542                        cpp = 4;
1543
1544                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1545                planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546                                               wm_info, fifo_size, cpp,
1547                                               pessimal_latency_ns);
1548                enabled = crtc;
1549        } else {
1550                planea_wm = fifo_size - wm_info->guard_size;
1551                if (planea_wm > (long)wm_info->max_wm)
1552                        planea_wm = wm_info->max_wm;
1553        }
1554
1555        if (IS_GEN2(dev))
1556                wm_info = &i830_bc_wm_info;
1557
1558        fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559        crtc = intel_get_crtc_for_plane(dev, 1);
1560        if (intel_crtc_active(crtc)) {
1561                const struct drm_display_mode *adjusted_mode;
1562                int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1563                if (IS_GEN2(dev))
1564                        cpp = 4;
1565
1566                adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1567                planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568                                               wm_info, fifo_size, cpp,
1569                                               pessimal_latency_ns);
1570                if (enabled == NULL)
1571                        enabled = crtc;
1572                else
1573                        enabled = NULL;
1574        } else {
1575                planeb_wm = fifo_size - wm_info->guard_size;
1576                if (planeb_wm > (long)wm_info->max_wm)
1577                        planeb_wm = wm_info->max_wm;
1578        }
1579
1580        DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582        if (IS_I915GM(dev) && enabled) {
1583                struct drm_i915_gem_object *obj;
1584
1585                obj = intel_fb_obj(enabled->primary->state->fb);
1586
1587                /* self-refresh seems busted with untiled */
1588                if (!i915_gem_object_is_tiled(obj))
1589                        enabled = NULL;
1590        }
1591
1592        /*
1593         * Overlay gets an aggressive default since video jitter is bad.
1594         */
1595        cwm = 2;
1596
1597        /* Play safe and disable self-refresh before adjusting watermarks. */
1598        intel_set_memory_cxsr(dev_priv, false);
1599
1600        /* Calc sr entries for one plane configs */
1601        if (HAS_FW_BLC(dev) && enabled) {
1602                /* self-refresh has much higher latency */
1603                static const int sr_latency_ns = 6000;
1604                const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1605                int clock = adjusted_mode->crtc_clock;
1606                int htotal = adjusted_mode->crtc_htotal;
1607                int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1608                int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1609                unsigned long line_time_us;
1610                int entries;
1611
1612                if (IS_I915GM(dev) || IS_I945GM(dev))
1613                        cpp = 4;
1614
1615                line_time_us = max(htotal * 1000 / clock, 1);
1616
1617                /* Use ns/us then divide to preserve precision */
1618                entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619                        cpp * hdisplay;
1620                entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621                DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622                srwm = wm_info->fifo_size - entries;
1623                if (srwm < 0)
1624                        srwm = 1;
1625
1626                if (IS_I945G(dev) || IS_I945GM(dev))
1627                        I915_WRITE(FW_BLC_SELF,
1628                                   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1629                else
1630                        I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631        }
1632
1633        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634                      planea_wm, planeb_wm, cwm, srwm);
1635
1636        fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637        fwater_hi = (cwm & 0x1f);
1638
1639        /* Set request length to 8 cachelines per fetch */
1640        fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641        fwater_hi = fwater_hi | (1 << 8);
1642
1643        I915_WRITE(FW_BLC, fwater_lo);
1644        I915_WRITE(FW_BLC2, fwater_hi);
1645
1646        if (enabled)
1647                intel_set_memory_cxsr(dev_priv, true);
1648}
1649
1650static void i845_update_wm(struct drm_crtc *unused_crtc)
1651{
1652        struct drm_device *dev = unused_crtc->dev;
1653        struct drm_i915_private *dev_priv = to_i915(dev);
1654        struct drm_crtc *crtc;
1655        const struct drm_display_mode *adjusted_mode;
1656        uint32_t fwater_lo;
1657        int planea_wm;
1658
1659        crtc = single_enabled_crtc(dev);
1660        if (crtc == NULL)
1661                return;
1662
1663        adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1664        planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1665                                       &i845_wm_info,
1666                                       dev_priv->display.get_fifo_size(dev, 0),
1667                                       4, pessimal_latency_ns);
1668        fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669        fwater_lo |= (3<<8) | planea_wm;
1670
1671        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673        I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1677{
1678        uint32_t pixel_rate;
1679
1680        pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1681
1682        /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683         * adjust the pixel_rate here. */
1684
1685        if (pipe_config->pch_pfit.enabled) {
1686                uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1687                uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689                pipe_w = pipe_config->pipe_src_w;
1690                pipe_h = pipe_config->pipe_src_h;
1691
1692                pfit_w = (pfit_size >> 16) & 0xFFFF;
1693                pfit_h = pfit_size & 0xFFFF;
1694                if (pipe_w < pfit_w)
1695                        pipe_w = pfit_w;
1696                if (pipe_h < pfit_h)
1697                        pipe_h = pfit_h;
1698
1699                if (WARN_ON(!pfit_w || !pfit_h))
1700                        return pixel_rate;
1701
1702                pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703                                     pfit_w * pfit_h);
1704        }
1705
1706        return pixel_rate;
1707}
1708
1709/* latency must be in 0.1us units. */
1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1711{
1712        uint64_t ret;
1713
1714        if (WARN(latency == 0, "Latency value missing\n"))
1715                return UINT_MAX;
1716
1717        ret = (uint64_t) pixel_rate * cpp * latency;
1718        ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720        return ret;
1721}
1722
1723/* latency must be in 0.1us units. */
1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1725                               uint32_t horiz_pixels, uint8_t cpp,
1726                               uint32_t latency)
1727{
1728        uint32_t ret;
1729
1730        if (WARN(latency == 0, "Latency value missing\n"))
1731                return UINT_MAX;
1732        if (WARN_ON(!pipe_htotal))
1733                return UINT_MAX;
1734
1735        ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1736        ret = (ret + 1) * horiz_pixels * cpp;
1737        ret = DIV_ROUND_UP(ret, 64) + 2;
1738        return ret;
1739}
1740
1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1742                           uint8_t cpp)
1743{
1744        /*
1745         * Neither of these should be possible since this function shouldn't be
1746         * called if the CRTC is off or the plane is invisible.  But let's be
1747         * extra paranoid to avoid a potential divide-by-zero if we screw up
1748         * elsewhere in the driver.
1749         */
1750        if (WARN_ON(!cpp))
1751                return 0;
1752        if (WARN_ON(!horiz_pixels))
1753                return 0;
1754
1755        return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1756}
1757
1758struct ilk_wm_maximums {
1759        uint16_t pri;
1760        uint16_t spr;
1761        uint16_t cur;
1762        uint16_t fbc;
1763};
1764
1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1770                                   const struct intel_plane_state *pstate,
1771                                   uint32_t mem_value,
1772                                   bool is_lp)
1773{
1774        int cpp = pstate->base.fb ?
1775                drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1776        uint32_t method1, method2;
1777
1778        if (!cstate->base.active || !pstate->base.visible)
1779                return 0;
1780
1781        method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1782
1783        if (!is_lp)
1784                return method1;
1785
1786        method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787                                 cstate->base.adjusted_mode.crtc_htotal,
1788                                 drm_rect_width(&pstate->base.dst),
1789                                 cpp, mem_value);
1790
1791        return min(method1, method2);
1792}
1793
1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1799                                   const struct intel_plane_state *pstate,
1800                                   uint32_t mem_value)
1801{
1802        int cpp = pstate->base.fb ?
1803                drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804        uint32_t method1, method2;
1805
1806        if (!cstate->base.active || !pstate->base.visible)
1807                return 0;
1808
1809        method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810        method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811                                 cstate->base.adjusted_mode.crtc_htotal,
1812                                 drm_rect_width(&pstate->base.dst),
1813                                 cpp, mem_value);
1814        return min(method1, method2);
1815}
1816
1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1822                                   const struct intel_plane_state *pstate,
1823                                   uint32_t mem_value)
1824{
1825        /*
1826         * We treat the cursor plane as always-on for the purposes of watermark
1827         * calculation.  Until we have two-stage watermark programming merged,
1828         * this is necessary to avoid flickering.
1829         */
1830        int cpp = 4;
1831        int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1832
1833        if (!cstate->base.active)
1834                return 0;
1835
1836        return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837                              cstate->base.adjusted_mode.crtc_htotal,
1838                              width, cpp, mem_value);
1839}
1840
1841/* Only for WM_LP. */
1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1843                                   const struct intel_plane_state *pstate,
1844                                   uint32_t pri_val)
1845{
1846        int cpp = pstate->base.fb ?
1847                drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1848
1849        if (!cstate->base.active || !pstate->base.visible)
1850                return 0;
1851
1852        return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1853}
1854
1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
1857        if (INTEL_INFO(dev)->gen >= 8)
1858                return 3072;
1859        else if (INTEL_INFO(dev)->gen >= 7)
1860                return 768;
1861        else
1862                return 512;
1863}
1864
1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866                                         int level, bool is_sprite)
1867{
1868        if (INTEL_INFO(dev)->gen >= 8)
1869                /* BDW primary/sprite plane watermarks */
1870                return level == 0 ? 255 : 2047;
1871        else if (INTEL_INFO(dev)->gen >= 7)
1872                /* IVB/HSW primary/sprite plane watermarks */
1873                return level == 0 ? 127 : 1023;
1874        else if (!is_sprite)
1875                /* ILK/SNB primary plane watermarks */
1876                return level == 0 ? 127 : 511;
1877        else
1878                /* ILK/SNB sprite plane watermarks */
1879                return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883                                          int level)
1884{
1885        if (INTEL_INFO(dev)->gen >= 7)
1886                return level == 0 ? 63 : 255;
1887        else
1888                return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893        if (INTEL_INFO(dev)->gen >= 8)
1894                return 31;
1895        else
1896                return 15;
1897}
1898
1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901                                     int level,
1902                                     const struct intel_wm_config *config,
1903                                     enum intel_ddb_partitioning ddb_partitioning,
1904                                     bool is_sprite)
1905{
1906        unsigned int fifo_size = ilk_display_fifo_size(dev);
1907
1908        /* if sprites aren't enabled, sprites get nothing */
1909        if (is_sprite && !config->sprites_enabled)
1910                return 0;
1911
1912        /* HSW allows LP1+ watermarks even with multiple pipes */
1913        if (level == 0 || config->num_pipes_active > 1) {
1914                fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916                /*
1917                 * For some reason the non self refresh
1918                 * FIFO size is only half of the self
1919                 * refresh FIFO size on ILK/SNB.
1920                 */
1921                if (INTEL_INFO(dev)->gen <= 6)
1922                        fifo_size /= 2;
1923        }
1924
1925        if (config->sprites_enabled) {
1926                /* level 0 is always calculated with 1:1 split */
1927                if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928                        if (is_sprite)
1929                                fifo_size *= 5;
1930                        fifo_size /= 6;
1931                } else {
1932                        fifo_size /= 2;
1933                }
1934        }
1935
1936        /* clamp to max that the registers can hold */
1937        return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1942                                      int level,
1943                                      const struct intel_wm_config *config)
1944{
1945        /* HSW LP1+ watermarks w/ multiple pipes */
1946        if (level > 0 && config->num_pipes_active > 1)
1947                return 64;
1948
1949        /* otherwise just report max that registers can hold */
1950        return ilk_cursor_wm_reg_max(dev, level);
1951}
1952
1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
1954                                    int level,
1955                                    const struct intel_wm_config *config,
1956                                    enum intel_ddb_partitioning ddb_partitioning,
1957                                    struct ilk_wm_maximums *max)
1958{
1959        max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960        max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961        max->cur = ilk_cursor_wm_max(dev, level, config);
1962        max->fbc = ilk_fbc_wm_reg_max(dev);
1963}
1964
1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966                                        int level,
1967                                        struct ilk_wm_maximums *max)
1968{
1969        max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970        max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971        max->cur = ilk_cursor_wm_reg_max(dev, level);
1972        max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
1975static bool ilk_validate_wm_level(int level,
1976                                  const struct ilk_wm_maximums *max,
1977                                  struct intel_wm_level *result)
1978{
1979        bool ret;
1980
1981        /* already determined to be invalid? */
1982        if (!result->enable)
1983                return false;
1984
1985        result->enable = result->pri_val <= max->pri &&
1986                         result->spr_val <= max->spr &&
1987                         result->cur_val <= max->cur;
1988
1989        ret = result->enable;
1990
1991        /*
1992         * HACK until we can pre-compute everything,
1993         * and thus fail gracefully if LP0 watermarks
1994         * are exceeded...
1995         */
1996        if (level == 0 && !result->enable) {
1997                if (result->pri_val > max->pri)
1998                        DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999                                      level, result->pri_val, max->pri);
2000                if (result->spr_val > max->spr)
2001                        DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002                                      level, result->spr_val, max->spr);
2003                if (result->cur_val > max->cur)
2004                        DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005                                      level, result->cur_val, max->cur);
2006
2007                result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008                result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009                result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010                result->enable = true;
2011        }
2012
2013        return ret;
2014}
2015
2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2017                                 const struct intel_crtc *intel_crtc,
2018                                 int level,
2019                                 struct intel_crtc_state *cstate,
2020                                 struct intel_plane_state *pristate,
2021                                 struct intel_plane_state *sprstate,
2022                                 struct intel_plane_state *curstate,
2023                                 struct intel_wm_level *result)
2024{
2025        uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026        uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027        uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029        /* WM1+ latency values stored in 0.5us units */
2030        if (level > 0) {
2031                pri_latency *= 5;
2032                spr_latency *= 5;
2033                cur_latency *= 5;
2034        }
2035
2036        if (pristate) {
2037                result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038                                                     pri_latency, level);
2039                result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040        }
2041
2042        if (sprstate)
2043                result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045        if (curstate)
2046                result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
2048        result->enable = true;
2049}
2050
2051static uint32_t
2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2053{
2054        const struct intel_atomic_state *intel_state =
2055                to_intel_atomic_state(cstate->base.state);
2056        const struct drm_display_mode *adjusted_mode =
2057                &cstate->base.adjusted_mode;
2058        u32 linetime, ips_linetime;
2059
2060        if (!cstate->base.active)
2061                return 0;
2062        if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063                return 0;
2064        if (WARN_ON(intel_state->cdclk == 0))
2065                return 0;
2066
2067        /* The WM are computed with base on how long it takes to fill a single
2068         * row at the given clock rate, multiplied by 8.
2069         * */
2070        linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071                                     adjusted_mode->crtc_clock);
2072        ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                         intel_state->cdclk);
2074
2075        return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076               PIPE_WM_LINETIME_TIME(linetime);
2077}
2078
2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2080{
2081        struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083        if (IS_GEN9(dev)) {
2084                uint32_t val;
2085                int ret, i;
2086                int level, max_level = ilk_wm_max_level(dev);
2087
2088                /* read the first set of memory latencies[0:3] */
2089                val = 0; /* data0 to be programmed to 0 for first set */
2090                mutex_lock(&dev_priv->rps.hw_lock);
2091                ret = sandybridge_pcode_read(dev_priv,
2092                                             GEN9_PCODE_READ_MEM_LATENCY,
2093                                             &val);
2094                mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096                if (ret) {
2097                        DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098                        return;
2099                }
2100
2101                wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102                wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103                                GEN9_MEM_LATENCY_LEVEL_MASK;
2104                wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105                                GEN9_MEM_LATENCY_LEVEL_MASK;
2106                wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107                                GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109                /* read the second set of memory latencies[4:7] */
2110                val = 1; /* data0 to be programmed to 1 for second set */
2111                mutex_lock(&dev_priv->rps.hw_lock);
2112                ret = sandybridge_pcode_read(dev_priv,
2113                                             GEN9_PCODE_READ_MEM_LATENCY,
2114                                             &val);
2115                mutex_unlock(&dev_priv->rps.hw_lock);
2116                if (ret) {
2117                        DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118                        return;
2119                }
2120
2121                wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122                wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123                                GEN9_MEM_LATENCY_LEVEL_MASK;
2124                wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125                                GEN9_MEM_LATENCY_LEVEL_MASK;
2126                wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127                                GEN9_MEM_LATENCY_LEVEL_MASK;
2128
2129                /*
2130                 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131                 * need to be disabled. We make sure to sanitize the values out
2132                 * of the punit to satisfy this requirement.
2133                 */
2134                for (level = 1; level <= max_level; level++) {
2135                        if (wm[level] == 0) {
2136                                for (i = level + 1; i <= max_level; i++)
2137                                        wm[i] = 0;
2138                                break;
2139                        }
2140                }
2141
2142                /*
2143                 * WaWmMemoryReadLatency:skl
2144                 *
2145                 * punit doesn't take into account the read latency so we need
2146                 * to add 2us to the various latency levels we retrieve from the
2147                 * punit when level 0 response data us 0us.
2148                 */
2149                if (wm[0] == 0) {
2150                        wm[0] += 2;
2151                        for (level = 1; level <= max_level; level++) {
2152                                if (wm[level] == 0)
2153                                        break;
2154                                wm[level] += 2;
2155                        }
2156                }
2157
2158        } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2159                uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161                wm[0] = (sskpd >> 56) & 0xFF;
2162                if (wm[0] == 0)
2163                        wm[0] = sskpd & 0xF;
2164                wm[1] = (sskpd >> 4) & 0xFF;
2165                wm[2] = (sskpd >> 12) & 0xFF;
2166                wm[3] = (sskpd >> 20) & 0x1FF;
2167                wm[4] = (sskpd >> 32) & 0x1FF;
2168        } else if (INTEL_INFO(dev)->gen >= 6) {
2169                uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171                wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172                wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173                wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174                wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2175        } else if (INTEL_INFO(dev)->gen >= 5) {
2176                uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178                /* ILK primary LP0 latency is 700 ns */
2179                wm[0] = 7;
2180                wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181                wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2182        }
2183}
2184
2185static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186{
2187        /* ILK sprite LP0 latency is 1300 ns */
2188        if (IS_GEN5(dev))
2189                wm[0] = 13;
2190}
2191
2192static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194        /* ILK cursor LP0 latency is 1300 ns */
2195        if (IS_GEN5(dev))
2196                wm[0] = 13;
2197
2198        /* WaDoubleCursorLP3Latency:ivb */
2199        if (IS_IVYBRIDGE(dev))
2200                wm[3] *= 2;
2201}
2202
2203int ilk_wm_max_level(const struct drm_device *dev)
2204{
2205        /* how many WM levels are we expecting */
2206        if (INTEL_INFO(dev)->gen >= 9)
2207                return 7;
2208        else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2209                return 4;
2210        else if (INTEL_INFO(dev)->gen >= 6)
2211                return 3;
2212        else
2213                return 2;
2214}
2215
2216static void intel_print_wm_latency(struct drm_device *dev,
2217                                   const char *name,
2218                                   const uint16_t wm[8])
2219{
2220        int level, max_level = ilk_wm_max_level(dev);
2221
2222        for (level = 0; level <= max_level; level++) {
2223                unsigned int latency = wm[level];
2224
2225                if (latency == 0) {
2226                        DRM_ERROR("%s WM%d latency not provided\n",
2227                                  name, level);
2228                        continue;
2229                }
2230
2231                /*
2232                 * - latencies are in us on gen9.
2233                 * - before then, WM1+ latency values are in 0.5us units
2234                 */
2235                if (IS_GEN9(dev))
2236                        latency *= 10;
2237                else if (level > 0)
2238                        latency *= 5;
2239
2240                DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241                              name, level, wm[level],
2242                              latency / 10, latency % 10);
2243        }
2244}
2245
2246static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247                                    uint16_t wm[5], uint16_t min)
2248{
2249        int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2250
2251        if (wm[0] >= min)
2252                return false;
2253
2254        wm[0] = max(wm[0], min);
2255        for (level = 1; level <= max_level; level++)
2256                wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258        return true;
2259}
2260
2261static void snb_wm_latency_quirk(struct drm_device *dev)
2262{
2263        struct drm_i915_private *dev_priv = to_i915(dev);
2264        bool changed;
2265
2266        /*
2267         * The BIOS provided WM memory latency values are often
2268         * inadequate for high resolution displays. Adjust them.
2269         */
2270        changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271                ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272                ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274        if (!changed)
2275                return;
2276
2277        DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278        intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279        intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280        intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281}
2282
2283static void ilk_setup_wm_latency(struct drm_device *dev)
2284{
2285        struct drm_i915_private *dev_priv = to_i915(dev);
2286
2287        intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289        memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290               sizeof(dev_priv->wm.pri_latency));
2291        memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292               sizeof(dev_priv->wm.pri_latency));
2293
2294        intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295        intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2296
2297        intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298        intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299        intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2300
2301        if (IS_GEN6(dev))
2302                snb_wm_latency_quirk(dev);
2303}
2304
2305static void skl_setup_wm_latency(struct drm_device *dev)
2306{
2307        struct drm_i915_private *dev_priv = to_i915(dev);
2308
2309        intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310        intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311}
2312
2313static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314                                 struct intel_pipe_wm *pipe_wm)
2315{
2316        /* LP0 watermark maximums depend on this pipe alone */
2317        const struct intel_wm_config config = {
2318                .num_pipes_active = 1,
2319                .sprites_enabled = pipe_wm->sprites_enabled,
2320                .sprites_scaled = pipe_wm->sprites_scaled,
2321        };
2322        struct ilk_wm_maximums max;
2323
2324        /* LP0 watermarks always use 1/2 DDB partitioning */
2325        ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327        /* At least LP0 must be valid */
2328        if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329                DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330                return false;
2331        }
2332
2333        return true;
2334}
2335
2336/* Compute new watermarks for the pipe */
2337static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2338{
2339        struct drm_atomic_state *state = cstate->base.state;
2340        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2341        struct intel_pipe_wm *pipe_wm;
2342        struct drm_device *dev = state->dev;
2343        const struct drm_i915_private *dev_priv = to_i915(dev);
2344        struct intel_plane *intel_plane;
2345        struct intel_plane_state *pristate = NULL;
2346        struct intel_plane_state *sprstate = NULL;
2347        struct intel_plane_state *curstate = NULL;
2348        int level, max_level = ilk_wm_max_level(dev), usable_level;
2349        struct ilk_wm_maximums max;
2350
2351        pipe_wm = &cstate->wm.ilk.optimal;
2352
2353        for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2354                struct intel_plane_state *ps;
2355
2356                ps = intel_atomic_get_existing_plane_state(state,
2357                                                           intel_plane);
2358                if (!ps)
2359                        continue;
2360
2361                if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2362                        pristate = ps;
2363                else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2364                        sprstate = ps;
2365                else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2366                        curstate = ps;
2367        }
2368
2369        pipe_wm->pipe_enabled = cstate->base.active;
2370        if (sprstate) {
2371                pipe_wm->sprites_enabled = sprstate->base.visible;
2372                pipe_wm->sprites_scaled = sprstate->base.visible &&
2373                        (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374                         drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2375        }
2376
2377        usable_level = max_level;
2378
2379        /* ILK/SNB: LP2+ watermarks only w/o sprites */
2380        if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2381                usable_level = 1;
2382
2383        /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2384        if (pipe_wm->sprites_scaled)
2385                usable_level = 0;
2386
2387        ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2388                             pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390        memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391        pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2392
2393        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2394                pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2395
2396        if (!ilk_validate_pipe_wm(dev, pipe_wm))
2397                return -EINVAL;
2398
2399        ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401        for (level = 1; level <= max_level; level++) {
2402                struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2403
2404                ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2405                                     pristate, sprstate, curstate, wm);
2406
2407                /*
2408                 * Disable any watermark level that exceeds the
2409                 * register maximums since such watermarks are
2410                 * always invalid.
2411                 */
2412                if (level > usable_level)
2413                        continue;
2414
2415                if (ilk_validate_wm_level(level, &max, wm))
2416                        pipe_wm->wm[level] = *wm;
2417                else
2418                        usable_level = level;
2419        }
2420
2421        return 0;
2422}
2423
2424/*
2425 * Build a set of 'intermediate' watermark values that satisfy both the old
2426 * state and the new state.  These can be programmed to the hardware
2427 * immediately.
2428 */
2429static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430                                       struct intel_crtc *intel_crtc,
2431                                       struct intel_crtc_state *newstate)
2432{
2433        struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2434        struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435        int level, max_level = ilk_wm_max_level(dev);
2436
2437        /*
2438         * Start with the final, target watermarks, then combine with the
2439         * currently active watermarks to get values that are safe both before
2440         * and after the vblank.
2441         */
2442        *a = newstate->wm.ilk.optimal;
2443        a->pipe_enabled |= b->pipe_enabled;
2444        a->sprites_enabled |= b->sprites_enabled;
2445        a->sprites_scaled |= b->sprites_scaled;
2446
2447        for (level = 0; level <= max_level; level++) {
2448                struct intel_wm_level *a_wm = &a->wm[level];
2449                const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451                a_wm->enable &= b_wm->enable;
2452                a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453                a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454                a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455                a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456        }
2457
2458        /*
2459         * We need to make sure that these merged watermark values are
2460         * actually a valid configuration themselves.  If they're not,
2461         * there's no safe way to transition from the old state to
2462         * the new state, so we need to fail the atomic transaction.
2463         */
2464        if (!ilk_validate_pipe_wm(dev, a))
2465                return -EINVAL;
2466
2467        /*
2468         * If our intermediate WM are identical to the final WM, then we can
2469         * omit the post-vblank programming; only update if it's different.
2470         */
2471        if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2472                newstate->wm.need_postvbl_update = false;
2473
2474        return 0;
2475}
2476
2477/*
2478 * Merge the watermarks from all active pipes for a specific level.
2479 */
2480static void ilk_merge_wm_level(struct drm_device *dev,
2481                               int level,
2482                               struct intel_wm_level *ret_wm)
2483{
2484        const struct intel_crtc *intel_crtc;
2485
2486        ret_wm->enable = true;
2487
2488        for_each_intel_crtc(dev, intel_crtc) {
2489                const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2490                const struct intel_wm_level *wm = &active->wm[level];
2491
2492                if (!active->pipe_enabled)
2493                        continue;
2494
2495                /*
2496                 * The watermark values may have been used in the past,
2497                 * so we must maintain them in the registers for some
2498                 * time even if the level is now disabled.
2499                 */
2500                if (!wm->enable)
2501                        ret_wm->enable = false;
2502
2503                ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504                ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505                ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506                ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507        }
2508}
2509
2510/*
2511 * Merge all low power watermarks for all active pipes.
2512 */
2513static void ilk_wm_merge(struct drm_device *dev,
2514                         const struct intel_wm_config *config,
2515                         const struct ilk_wm_maximums *max,
2516                         struct intel_pipe_wm *merged)
2517{
2518        struct drm_i915_private *dev_priv = to_i915(dev);
2519        int level, max_level = ilk_wm_max_level(dev);
2520        int last_enabled_level = max_level;
2521
2522        /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523        if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524            config->num_pipes_active > 1)
2525                last_enabled_level = 0;
2526
2527        /* ILK: FBC WM must be disabled always */
2528        merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2529
2530        /* merge each WM1+ level */
2531        for (level = 1; level <= max_level; level++) {
2532                struct intel_wm_level *wm = &merged->wm[level];
2533
2534                ilk_merge_wm_level(dev, level, wm);
2535
2536                if (level > last_enabled_level)
2537                        wm->enable = false;
2538                else if (!ilk_validate_wm_level(level, max, wm))
2539                        /* make sure all following levels get disabled */
2540                        last_enabled_level = level - 1;
2541
2542                /*
2543                 * The spec says it is preferred to disable
2544                 * FBC WMs instead of disabling a WM level.
2545                 */
2546                if (wm->fbc_val > max->fbc) {
2547                        if (wm->enable)
2548                                merged->fbc_wm_enabled = false;
2549                        wm->fbc_val = 0;
2550                }
2551        }
2552
2553        /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554        /*
2555         * FIXME this is racy. FBC might get enabled later.
2556         * What we should check here is whether FBC can be
2557         * enabled sometime later.
2558         */
2559        if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2560            intel_fbc_is_active(dev_priv)) {
2561                for (level = 2; level <= max_level; level++) {
2562                        struct intel_wm_level *wm = &merged->wm[level];
2563
2564                        wm->enable = false;
2565                }
2566        }
2567}
2568
2569static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570{
2571        /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572        return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573}
2574
2575/* The value we need to program into the WM_LPx latency field */
2576static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577{
2578        struct drm_i915_private *dev_priv = to_i915(dev);
2579
2580        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2581                return 2 * level;
2582        else
2583                return dev_priv->wm.pri_latency[level];
2584}
2585
2586static void ilk_compute_wm_results(struct drm_device *dev,
2587                                   const struct intel_pipe_wm *merged,
2588                                   enum intel_ddb_partitioning partitioning,
2589                                   struct ilk_wm_values *results)
2590{
2591        struct intel_crtc *intel_crtc;
2592        int level, wm_lp;
2593
2594        results->enable_fbc_wm = merged->fbc_wm_enabled;
2595        results->partitioning = partitioning;
2596
2597        /* LP1+ register values */
2598        for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2599                const struct intel_wm_level *r;
2600
2601                level = ilk_wm_lp_to_level(wm_lp, merged);
2602
2603                r = &merged->wm[level];
2604
2605                /*
2606                 * Maintain the watermark values even if the level is
2607                 * disabled. Doing otherwise could cause underruns.
2608                 */
2609                results->wm_lp[wm_lp - 1] =
2610                        (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2611                        (r->pri_val << WM1_LP_SR_SHIFT) |
2612                        r->cur_val;
2613
2614                if (r->enable)
2615                        results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
2617                if (INTEL_INFO(dev)->gen >= 8)
2618                        results->wm_lp[wm_lp - 1] |=
2619                                r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620                else
2621                        results->wm_lp[wm_lp - 1] |=
2622                                r->fbc_val << WM1_LP_FBC_SHIFT;
2623
2624                /*
2625                 * Always set WM1S_LP_EN when spr_val != 0, even if the
2626                 * level is disabled. Doing otherwise could cause underruns.
2627                 */
2628                if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629                        WARN_ON(wm_lp != 1);
2630                        results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631                } else
2632                        results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2633        }
2634
2635        /* LP0 register values */
2636        for_each_intel_crtc(dev, intel_crtc) {
2637                enum pipe pipe = intel_crtc->pipe;
2638                const struct intel_wm_level *r =
2639                        &intel_crtc->wm.active.ilk.wm[0];
2640
2641                if (WARN_ON(!r->enable))
2642                        continue;
2643
2644                results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2645
2646                results->wm_pipe[pipe] =
2647                        (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648                        (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649                        r->cur_val;
2650        }
2651}
2652
2653/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654 * case both are at the same level. Prefer r1 in case they're the same. */
2655static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2656                                                  struct intel_pipe_wm *r1,
2657                                                  struct intel_pipe_wm *r2)
2658{
2659        int level, max_level = ilk_wm_max_level(dev);
2660        int level1 = 0, level2 = 0;
2661
2662        for (level = 1; level <= max_level; level++) {
2663                if (r1->wm[level].enable)
2664                        level1 = level;
2665                if (r2->wm[level].enable)
2666                        level2 = level;
2667        }
2668
2669        if (level1 == level2) {
2670                if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2671                        return r2;
2672                else
2673                        return r1;
2674        } else if (level1 > level2) {
2675                return r1;
2676        } else {
2677                return r2;
2678        }
2679}
2680
2681/* dirty bits used to track which watermarks need changes */
2682#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686#define WM_DIRTY_FBC (1 << 24)
2687#define WM_DIRTY_DDB (1 << 25)
2688
2689static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2690                                         const struct ilk_wm_values *old,
2691                                         const struct ilk_wm_values *new)
2692{
2693        unsigned int dirty = 0;
2694        enum pipe pipe;
2695        int wm_lp;
2696
2697        for_each_pipe(dev_priv, pipe) {
2698                if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699                        dirty |= WM_DIRTY_LINETIME(pipe);
2700                        /* Must disable LP1+ watermarks too */
2701                        dirty |= WM_DIRTY_LP_ALL;
2702                }
2703
2704                if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705                        dirty |= WM_DIRTY_PIPE(pipe);
2706                        /* Must disable LP1+ watermarks too */
2707                        dirty |= WM_DIRTY_LP_ALL;
2708                }
2709        }
2710
2711        if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712                dirty |= WM_DIRTY_FBC;
2713                /* Must disable LP1+ watermarks too */
2714                dirty |= WM_DIRTY_LP_ALL;
2715        }
2716
2717        if (old->partitioning != new->partitioning) {
2718                dirty |= WM_DIRTY_DDB;
2719                /* Must disable LP1+ watermarks too */
2720                dirty |= WM_DIRTY_LP_ALL;
2721        }
2722
2723        /* LP1+ watermarks already deemed dirty, no need to continue */
2724        if (dirty & WM_DIRTY_LP_ALL)
2725                return dirty;
2726
2727        /* Find the lowest numbered LP1+ watermark in need of an update... */
2728        for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729                if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730                    old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731                        break;
2732        }
2733
2734        /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735        for (; wm_lp <= 3; wm_lp++)
2736                dirty |= WM_DIRTY_LP(wm_lp);
2737
2738        return dirty;
2739}
2740
2741static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742                               unsigned int dirty)
2743{
2744        struct ilk_wm_values *previous = &dev_priv->wm.hw;
2745        bool changed = false;
2746
2747        if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748                previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749                I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2750                changed = true;
2751        }
2752        if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753                previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754                I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2755                changed = true;
2756        }
2757        if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758                previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759                I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2760                changed = true;
2761        }
2762
2763        /*
2764         * Don't touch WM1S_LP_EN here.
2765         * Doing so could cause underruns.
2766         */
2767
2768        return changed;
2769}
2770
2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
2775static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776                                struct ilk_wm_values *results)
2777{
2778        struct drm_device *dev = &dev_priv->drm;
2779        struct ilk_wm_values *previous = &dev_priv->wm.hw;
2780        unsigned int dirty;
2781        uint32_t val;
2782
2783        dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2784        if (!dirty)
2785                return;
2786
2787        _ilk_disable_lp_wm(dev_priv, dirty);
2788
2789        if (dirty & WM_DIRTY_PIPE(PIPE_A))
2790                I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2791        if (dirty & WM_DIRTY_PIPE(PIPE_B))
2792                I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2793        if (dirty & WM_DIRTY_PIPE(PIPE_C))
2794                I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
2796        if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2797                I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2798        if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2799                I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2800        if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2801                I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
2803        if (dirty & WM_DIRTY_DDB) {
2804                if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2805                        val = I915_READ(WM_MISC);
2806                        if (results->partitioning == INTEL_DDB_PART_1_2)
2807                                val &= ~WM_MISC_DATA_PARTITION_5_6;
2808                        else
2809                                val |= WM_MISC_DATA_PARTITION_5_6;
2810                        I915_WRITE(WM_MISC, val);
2811                } else {
2812                        val = I915_READ(DISP_ARB_CTL2);
2813                        if (results->partitioning == INTEL_DDB_PART_1_2)
2814                                val &= ~DISP_DATA_PARTITION_5_6;
2815                        else
2816                                val |= DISP_DATA_PARTITION_5_6;
2817                        I915_WRITE(DISP_ARB_CTL2, val);
2818                }
2819        }
2820
2821        if (dirty & WM_DIRTY_FBC) {
2822                val = I915_READ(DISP_ARB_CTL);
2823                if (results->enable_fbc_wm)
2824                        val &= ~DISP_FBC_WM_DIS;
2825                else
2826                        val |= DISP_FBC_WM_DIS;
2827                I915_WRITE(DISP_ARB_CTL, val);
2828        }
2829
2830        if (dirty & WM_DIRTY_LP(1) &&
2831            previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832                I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834        if (INTEL_INFO(dev)->gen >= 7) {
2835                if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836                        I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837                if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838                        I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839        }
2840
2841        if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2842                I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2843        if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2844                I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2845        if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2846                I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2847
2848        dev_priv->wm.hw = *results;
2849}
2850
2851bool ilk_disable_lp_wm(struct drm_device *dev)
2852{
2853        struct drm_i915_private *dev_priv = to_i915(dev);
2854
2855        return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856}
2857
2858#define SKL_SAGV_BLOCK_TIME     30 /* µs */
2859
2860/*
2861 * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2862 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863 * other universal planes are in indices 1..n.  Note that this may leave unused
2864 * indices between the top "sprite" plane and the cursor.
2865 */
2866static int
2867skl_wm_plane_id(const struct intel_plane *plane)
2868{
2869        switch (plane->base.type) {
2870        case DRM_PLANE_TYPE_PRIMARY:
2871                return 0;
2872        case DRM_PLANE_TYPE_CURSOR:
2873                return PLANE_CURSOR;
2874        case DRM_PLANE_TYPE_OVERLAY:
2875                return plane->plane + 1;
2876        default:
2877                MISSING_CASE(plane->base.type);
2878                return plane->plane;
2879        }
2880}
2881
2882/*
2883 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2884 * so assume we'll always need it in order to avoid underruns.
2885 */
2886static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2887{
2888        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2889
2890        if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2891            IS_KABYLAKE(dev_priv))
2892                return true;
2893
2894        return false;
2895}
2896
2897static bool
2898intel_has_sagv(struct drm_i915_private *dev_priv)
2899{
2900        if (IS_KABYLAKE(dev_priv))
2901                return true;
2902
2903        if (IS_SKYLAKE(dev_priv) &&
2904            dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2905                return true;
2906
2907        return false;
2908}
2909
2910/*
2911 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2912 * depending on power and performance requirements. The display engine access
2913 * to system memory is blocked during the adjustment time. Because of the
2914 * blocking time, having this enabled can cause full system hangs and/or pipe
2915 * underruns if we don't meet all of the following requirements:
2916 *
2917 *  - <= 1 pipe enabled
2918 *  - All planes can enable watermarks for latencies >= SAGV engine block time
2919 *  - We're not using an interlaced display configuration
2920 */
2921int
2922intel_enable_sagv(struct drm_i915_private *dev_priv)
2923{
2924        int ret;
2925
2926        if (!intel_has_sagv(dev_priv))
2927                return 0;
2928
2929        if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2930                return 0;
2931
2932        DRM_DEBUG_KMS("Enabling the SAGV\n");
2933        mutex_lock(&dev_priv->rps.hw_lock);
2934
2935        ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2936                                      GEN9_SAGV_ENABLE);
2937
2938        /* We don't need to wait for the SAGV when enabling */
2939        mutex_unlock(&dev_priv->rps.hw_lock);
2940
2941        /*
2942         * Some skl systems, pre-release machines in particular,
2943         * don't actually have an SAGV.
2944         */
2945        if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2946                DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2947                dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2948                return 0;
2949        } else if (ret < 0) {
2950                DRM_ERROR("Failed to enable the SAGV\n");
2951                return ret;
2952        }
2953
2954        dev_priv->sagv_status = I915_SAGV_ENABLED;
2955        return 0;
2956}
2957
2958int
2959intel_disable_sagv(struct drm_i915_private *dev_priv)
2960{
2961        int ret;
2962
2963        if (!intel_has_sagv(dev_priv))
2964                return 0;
2965
2966        if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2967                return 0;
2968
2969        DRM_DEBUG_KMS("Disabling the SAGV\n");
2970        mutex_lock(&dev_priv->rps.hw_lock);
2971
2972        /* bspec says to keep retrying for at least 1 ms */
2973        ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2974                                GEN9_SAGV_DISABLE,
2975                                GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2976                                1);
2977        mutex_unlock(&dev_priv->rps.hw_lock);
2978
2979        /*
2980         * Some skl systems, pre-release machines in particular,
2981         * don't actually have an SAGV.
2982         */
2983        if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2984                DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2985                dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2986                return 0;
2987        } else if (ret < 0) {
2988                DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2989                return ret;
2990        }
2991
2992        dev_priv->sagv_status = I915_SAGV_DISABLED;
2993        return 0;
2994}
2995
2996bool intel_can_enable_sagv(struct drm_atomic_state *state)
2997{
2998        struct drm_device *dev = state->dev;
2999        struct drm_i915_private *dev_priv = to_i915(dev);
3000        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3001        struct intel_crtc *crtc;
3002        struct intel_plane *plane;
3003        enum pipe pipe;
3004        int level, id, latency;
3005
3006        if (!intel_has_sagv(dev_priv))
3007                return false;
3008
3009        /*
3010         * SKL workaround: bspec recommends we disable the SAGV when we have
3011         * more then one pipe enabled
3012         *
3013         * If there are no active CRTCs, no additional checks need be performed
3014         */
3015        if (hweight32(intel_state->active_crtcs) == 0)
3016                return true;
3017        else if (hweight32(intel_state->active_crtcs) > 1)
3018                return false;
3019
3020        /* Since we're now guaranteed to only have one active CRTC... */
3021        pipe = ffs(intel_state->active_crtcs) - 1;
3022        crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3023
3024        if (crtc->base.state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025                return false;
3026
3027        for_each_intel_plane_on_crtc(dev, crtc, plane) {
3028                id = skl_wm_plane_id(plane);
3029
3030                /* Skip this plane if it's not enabled */
3031                if (intel_state->wm_results.plane[pipe][id][0] == 0)
3032                        continue;
3033
3034                /* Find the highest enabled wm level for this plane */
3035                for (level = ilk_wm_max_level(dev);
3036                     intel_state->wm_results.plane[pipe][id][level] == 0; --level)
3037                     { }
3038
3039                latency = dev_priv->wm.skl_latency[level];
3040
3041                if (skl_needs_memory_bw_wa(intel_state) &&
3042                    plane->base.state->fb->modifier[0] ==
3043                    I915_FORMAT_MOD_X_TILED)
3044                        latency += 15;
3045
3046                /*
3047                 * If any of the planes on this pipe don't enable wm levels
3048                 * that incur memory latencies higher then 30µs we can't enable
3049                 * the SAGV
3050                 */
3051                if (latency < SKL_SAGV_BLOCK_TIME)
3052                        return false;
3053        }
3054
3055        return true;
3056}
3057
3058static void
3059skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3060                                   const struct intel_crtc_state *cstate,
3061                                   struct skl_ddb_entry *alloc, /* out */
3062                                   int *num_active /* out */)
3063{
3064        struct drm_atomic_state *state = cstate->base.state;
3065        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3066        struct drm_i915_private *dev_priv = to_i915(dev);
3067        struct drm_crtc *for_crtc = cstate->base.crtc;
3068        unsigned int pipe_size, ddb_size;
3069        int nth_active_pipe;
3070        int pipe = to_intel_crtc(for_crtc)->pipe;
3071
3072        if (WARN_ON(!state) || !cstate->base.active) {
3073                alloc->start = 0;
3074                alloc->end = 0;
3075                *num_active = hweight32(dev_priv->active_crtcs);
3076                return;
3077        }
3078
3079        if (intel_state->active_pipe_changes)
3080                *num_active = hweight32(intel_state->active_crtcs);
3081        else
3082                *num_active = hweight32(dev_priv->active_crtcs);
3083
3084        ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3085        WARN_ON(ddb_size == 0);
3086
3087        ddb_size -= 4; /* 4 blocks for bypass path allocation */
3088
3089        /*
3090         * If the state doesn't change the active CRTC's, then there's
3091         * no need to recalculate; the existing pipe allocation limits
3092         * should remain unchanged.  Note that we're safe from racing
3093         * commits since any racing commit that changes the active CRTC
3094         * list would need to grab _all_ crtc locks, including the one
3095         * we currently hold.
3096         */
3097        if (!intel_state->active_pipe_changes) {
3098                *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3099                return;
3100        }
3101
3102        nth_active_pipe = hweight32(intel_state->active_crtcs &
3103                                    (drm_crtc_mask(for_crtc) - 1));
3104        pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3105        alloc->start = nth_active_pipe * ddb_size / *num_active;
3106        alloc->end = alloc->start + pipe_size;
3107}
3108
3109static unsigned int skl_cursor_allocation(int num_active)
3110{
3111        if (num_active == 1)
3112                return 32;
3113
3114        return 8;
3115}
3116
3117static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3118{
3119        entry->start = reg & 0x3ff;
3120        entry->end = (reg >> 16) & 0x3ff;
3121        if (entry->end)
3122                entry->end += 1;
3123}
3124
3125void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3126                          struct skl_ddb_allocation *ddb /* out */)
3127{
3128        enum pipe pipe;
3129        int plane;
3130        u32 val;
3131
3132        memset(ddb, 0, sizeof(*ddb));
3133
3134        for_each_pipe(dev_priv, pipe) {
3135                enum intel_display_power_domain power_domain;
3136
3137                power_domain = POWER_DOMAIN_PIPE(pipe);
3138                if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3139                        continue;
3140
3141                for_each_plane(dev_priv, pipe, plane) {
3142                        val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3143                        skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3144                                                   val);
3145                }
3146
3147                val = I915_READ(CUR_BUF_CFG(pipe));
3148                skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3149                                           val);
3150
3151                intel_display_power_put(dev_priv, power_domain);
3152        }
3153}
3154
3155/*
3156 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3157 * The bspec defines downscale amount as:
3158 *
3159 * """
3160 * Horizontal down scale amount = maximum[1, Horizontal source size /
3161 *                                           Horizontal destination size]
3162 * Vertical down scale amount = maximum[1, Vertical source size /
3163 *                                         Vertical destination size]
3164 * Total down scale amount = Horizontal down scale amount *
3165 *                           Vertical down scale amount
3166 * """
3167 *
3168 * Return value is provided in 16.16 fixed point form to retain fractional part.
3169 * Caller should take care of dividing & rounding off the value.
3170 */
3171static uint32_t
3172skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3173{
3174        uint32_t downscale_h, downscale_w;
3175        uint32_t src_w, src_h, dst_w, dst_h;
3176
3177        if (WARN_ON(!pstate->base.visible))
3178                return DRM_PLANE_HELPER_NO_SCALING;
3179
3180        /* n.b., src is 16.16 fixed point, dst is whole integer */
3181        src_w = drm_rect_width(&pstate->base.src);
3182        src_h = drm_rect_height(&pstate->base.src);
3183        dst_w = drm_rect_width(&pstate->base.dst);
3184        dst_h = drm_rect_height(&pstate->base.dst);
3185        if (intel_rotation_90_or_270(pstate->base.rotation))
3186                swap(dst_w, dst_h);
3187
3188        downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3189        downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3190
3191        /* Provide result in 16.16 fixed point */
3192        return (uint64_t)downscale_w * downscale_h >> 16;
3193}
3194
3195static unsigned int
3196skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3197                             const struct drm_plane_state *pstate,
3198                             int y)
3199{
3200        struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3201        struct drm_framebuffer *fb = pstate->fb;
3202        uint32_t down_scale_amount, data_rate;
3203        uint32_t width = 0, height = 0;
3204        unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3205
3206        if (!intel_pstate->base.visible)
3207                return 0;
3208        if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3209                return 0;
3210        if (y && format != DRM_FORMAT_NV12)
3211                return 0;
3212
3213        width = drm_rect_width(&intel_pstate->base.src) >> 16;
3214        height = drm_rect_height(&intel_pstate->base.src) >> 16;
3215
3216        if (intel_rotation_90_or_270(pstate->rotation))
3217                swap(width, height);
3218
3219        /* for planar format */
3220        if (format == DRM_FORMAT_NV12) {
3221                if (y)  /* y-plane data rate */
3222                        data_rate = width * height *
3223                                drm_format_plane_cpp(format, 0);
3224                else    /* uv-plane data rate */
3225                        data_rate = (width / 2) * (height / 2) *
3226                                drm_format_plane_cpp(format, 1);
3227        } else {
3228                /* for packed formats */
3229                data_rate = width * height * drm_format_plane_cpp(format, 0);
3230        }
3231
3232        down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3233
3234        return (uint64_t)data_rate * down_scale_amount >> 16;
3235}
3236
3237/*
3238 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3239 * a 8192x4096@32bpp framebuffer:
3240 *   3 * 4096 * 8192  * 4 < 2^32
3241 */
3242static unsigned int
3243skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3244{
3245        struct drm_crtc_state *cstate = &intel_cstate->base;
3246        struct drm_atomic_state *state = cstate->state;
3247        struct drm_crtc *crtc = cstate->crtc;
3248        struct drm_device *dev = crtc->dev;
3249        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250        const struct drm_plane *plane;
3251        const struct intel_plane *intel_plane;
3252        struct drm_plane_state *pstate;
3253        unsigned int rate, total_data_rate = 0;
3254        int id;
3255        int i;
3256
3257        if (WARN_ON(!state))
3258                return 0;
3259
3260        /* Calculate and cache data rate for each plane */
3261        for_each_plane_in_state(state, plane, pstate, i) {
3262                id = skl_wm_plane_id(to_intel_plane(plane));
3263                intel_plane = to_intel_plane(plane);
3264
3265                if (intel_plane->pipe != intel_crtc->pipe)
3266                        continue;
3267
3268                /* packed/uv */
3269                rate = skl_plane_relative_data_rate(intel_cstate,
3270                                                    pstate, 0);
3271                intel_cstate->wm.skl.plane_data_rate[id] = rate;
3272
3273                /* y-plane */
3274                rate = skl_plane_relative_data_rate(intel_cstate,
3275                                                    pstate, 1);
3276                intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3277        }
3278
3279        /* Calculate CRTC's total data rate from cached values */
3280        for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3281                int id = skl_wm_plane_id(intel_plane);
3282
3283                /* packed/uv */
3284                total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3285                total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3286        }
3287
3288        return total_data_rate;
3289}
3290
3291static uint16_t
3292skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3293                  const int y)
3294{
3295        struct drm_framebuffer *fb = pstate->fb;
3296        struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3297        uint32_t src_w, src_h;
3298        uint32_t min_scanlines = 8;
3299        uint8_t plane_bpp;
3300
3301        if (WARN_ON(!fb))
3302                return 0;
3303
3304        /* For packed formats, no y-plane, return 0 */
3305        if (y && fb->pixel_format != DRM_FORMAT_NV12)
3306                return 0;
3307
3308        /* For Non Y-tile return 8-blocks */
3309        if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3310            fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3311                return 8;
3312
3313        src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3314        src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3315
3316        if (intel_rotation_90_or_270(pstate->rotation))
3317                swap(src_w, src_h);
3318
3319        /* Halve UV plane width and height for NV12 */
3320        if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3321                src_w /= 2;
3322                src_h /= 2;
3323        }
3324
3325        if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3326                plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3327        else
3328                plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3329
3330        if (intel_rotation_90_or_270(pstate->rotation)) {
3331                switch (plane_bpp) {
3332                case 1:
3333                        min_scanlines = 32;
3334                        break;
3335                case 2:
3336                        min_scanlines = 16;
3337                        break;
3338                case 4:
3339                        min_scanlines = 8;
3340                        break;
3341                case 8:
3342                        min_scanlines = 4;
3343                        break;
3344                default:
3345                        WARN(1, "Unsupported pixel depth %u for rotation",
3346                             plane_bpp);
3347                        min_scanlines = 32;
3348                }
3349        }
3350
3351        return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3352}
3353
3354static int
3355skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3356                      struct skl_ddb_allocation *ddb /* out */)
3357{
3358        struct drm_atomic_state *state = cstate->base.state;
3359        struct drm_crtc *crtc = cstate->base.crtc;
3360        struct drm_device *dev = crtc->dev;
3361        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362        struct intel_plane *intel_plane;
3363        struct drm_plane *plane;
3364        struct drm_plane_state *pstate;
3365        enum pipe pipe = intel_crtc->pipe;
3366        struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3367        uint16_t alloc_size, start, cursor_blocks;
3368        uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3369        uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3370        unsigned int total_data_rate;
3371        int num_active;
3372        int id, i;
3373
3374        /* Clear the partitioning for disabled planes. */
3375        memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3376        memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3377
3378        if (WARN_ON(!state))
3379                return 0;
3380
3381        if (!cstate->base.active) {
3382                ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3383                return 0;
3384        }
3385
3386        skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3387        alloc_size = skl_ddb_entry_size(alloc);
3388        if (alloc_size == 0) {
3389                memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3390                return 0;
3391        }
3392
3393        cursor_blocks = skl_cursor_allocation(num_active);
3394        ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3395        ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3396
3397        alloc_size -= cursor_blocks;
3398
3399        /* 1. Allocate the mininum required blocks for each active plane */
3400        for_each_plane_in_state(state, plane, pstate, i) {
3401                intel_plane = to_intel_plane(plane);
3402                id = skl_wm_plane_id(intel_plane);
3403
3404                if (intel_plane->pipe != pipe)
3405                        continue;
3406
3407                if (!to_intel_plane_state(pstate)->base.visible) {
3408                        minimum[id] = 0;
3409                        y_minimum[id] = 0;
3410                        continue;
3411                }
3412                if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3413                        minimum[id] = 0;
3414                        y_minimum[id] = 0;
3415                        continue;
3416                }
3417
3418                minimum[id] = skl_ddb_min_alloc(pstate, 0);
3419                y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3420        }
3421
3422        for (i = 0; i < PLANE_CURSOR; i++) {
3423                alloc_size -= minimum[i];
3424                alloc_size -= y_minimum[i];
3425        }
3426
3427        /*
3428         * 2. Distribute the remaining space in proportion to the amount of
3429         * data each plane needs to fetch from memory.
3430         *
3431         * FIXME: we may not allocate every single block here.
3432         */
3433        total_data_rate = skl_get_total_relative_data_rate(cstate);
3434        if (total_data_rate == 0)
3435                return 0;
3436
3437        start = alloc->start;
3438        for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3439                unsigned int data_rate, y_data_rate;
3440                uint16_t plane_blocks, y_plane_blocks = 0;
3441                int id = skl_wm_plane_id(intel_plane);
3442
3443                data_rate = cstate->wm.skl.plane_data_rate[id];
3444
3445                /*
3446                 * allocation for (packed formats) or (uv-plane part of planar format):
3447                 * promote the expression to 64 bits to avoid overflowing, the
3448                 * result is < available as data_rate / total_data_rate < 1
3449                 */
3450                plane_blocks = minimum[id];
3451                plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3452                                        total_data_rate);
3453
3454                /* Leave disabled planes at (0,0) */
3455                if (data_rate) {
3456                        ddb->plane[pipe][id].start = start;
3457                        ddb->plane[pipe][id].end = start + plane_blocks;
3458                }
3459
3460                start += plane_blocks;
3461
3462                /*
3463                 * allocation for y_plane part of planar format:
3464                 */
3465                y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3466
3467                y_plane_blocks = y_minimum[id];
3468                y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3469                                        total_data_rate);
3470
3471                if (y_data_rate) {
3472                        ddb->y_plane[pipe][id].start = start;
3473                        ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3474                }
3475
3476                start += y_plane_blocks;
3477        }
3478
3479        return 0;
3480}
3481
3482/*
3483 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3484 * for the read latency) and cpp should always be <= 8, so that
3485 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3486 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3487*/
3488static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3489{
3490        uint32_t wm_intermediate_val, ret;
3491
3492        if (latency == 0)
3493                return UINT_MAX;
3494
3495        wm_intermediate_val = latency * pixel_rate * cpp / 512;
3496        ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3497
3498        return ret;
3499}
3500
3501static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3502                               uint32_t latency, uint32_t plane_blocks_per_line)
3503{
3504        uint32_t ret;
3505        uint32_t wm_intermediate_val;
3506
3507        if (latency == 0)
3508                return UINT_MAX;
3509
3510        wm_intermediate_val = latency * pixel_rate;
3511        ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3512                                plane_blocks_per_line;
3513
3514        return ret;
3515}
3516
3517static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3518                                              struct intel_plane_state *pstate)
3519{
3520        uint64_t adjusted_pixel_rate;
3521        uint64_t downscale_amount;
3522        uint64_t pixel_rate;
3523
3524        /* Shouldn't reach here on disabled planes... */
3525        if (WARN_ON(!pstate->base.visible))
3526                return 0;
3527
3528        /*
3529         * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3530         * with additional adjustments for plane-specific scaling.
3531         */
3532        adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3533        downscale_amount = skl_plane_downscale_amount(pstate);
3534
3535        pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3536        WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3537
3538        return pixel_rate;
3539}
3540
3541static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3542                                struct intel_crtc_state *cstate,
3543                                struct intel_plane_state *intel_pstate,
3544                                uint16_t ddb_allocation,
3545                                int level,
3546                                uint16_t *out_blocks, /* out */
3547                                uint8_t *out_lines, /* out */
3548                                bool *enabled /* out */)
3549{
3550        struct drm_plane_state *pstate = &intel_pstate->base;
3551        struct drm_framebuffer *fb = pstate->fb;
3552        uint32_t latency = dev_priv->wm.skl_latency[level];
3553        uint32_t method1, method2;
3554        uint32_t plane_bytes_per_line, plane_blocks_per_line;
3555        uint32_t res_blocks, res_lines;
3556        uint32_t selected_result;
3557        uint8_t cpp;
3558        uint32_t width = 0, height = 0;
3559        uint32_t plane_pixel_rate;
3560        uint32_t y_tile_minimum, y_min_scanlines;
3561        struct intel_atomic_state *state =
3562                to_intel_atomic_state(cstate->base.state);
3563        bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3564
3565        if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3566                *enabled = false;
3567                return 0;
3568        }
3569
3570        if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3571                latency += 15;
3572
3573        width = drm_rect_width(&intel_pstate->base.src) >> 16;
3574        height = drm_rect_height(&intel_pstate->base.src) >> 16;
3575
3576        if (intel_rotation_90_or_270(pstate->rotation))
3577                swap(width, height);
3578
3579        cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3580        plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3581
3582        if (intel_rotation_90_or_270(pstate->rotation)) {
3583                int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3584                        drm_format_plane_cpp(fb->pixel_format, 1) :
3585                        drm_format_plane_cpp(fb->pixel_format, 0);
3586
3587                switch (cpp) {
3588                case 1:
3589                        y_min_scanlines = 16;
3590                        break;
3591                case 2:
3592                        y_min_scanlines = 8;
3593                        break;
3594                default:
3595                        WARN(1, "Unsupported pixel depth for rotation");
3596                case 4:
3597                        y_min_scanlines = 4;
3598                        break;
3599                }
3600        } else {
3601                y_min_scanlines = 4;
3602        }
3603
3604        if (apply_memory_bw_wa)
3605                y_min_scanlines *= 2;
3606
3607        plane_bytes_per_line = width * cpp;
3608        if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3609            fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3610                plane_blocks_per_line =
3611                      DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3612                plane_blocks_per_line /= y_min_scanlines;
3613        } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3614                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3615                                        + 1;
3616        } else {
3617                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3618        }
3619
3620        method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3621        method2 = skl_wm_method2(plane_pixel_rate,
3622                                 cstate->base.adjusted_mode.crtc_htotal,
3623                                 latency,
3624                                 plane_blocks_per_line);
3625
3626        y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3627
3628        if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3629            fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3630                selected_result = max(method2, y_tile_minimum);
3631        } else {
3632                if ((ddb_allocation / plane_blocks_per_line) >= 1)
3633                        selected_result = min(method1, method2);
3634                else
3635                        selected_result = method1;
3636        }
3637
3638        res_blocks = selected_result + 1;
3639        res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3640
3641        if (level >= 1 && level <= 7) {
3642                if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3643                    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3644                        res_blocks += y_tile_minimum;
3645                        res_lines += y_min_scanlines;
3646                } else {
3647                        res_blocks++;
3648                }
3649        }
3650
3651        if (res_blocks >= ddb_allocation || res_lines > 31) {
3652                *enabled = false;
3653
3654                /*
3655                 * If there are no valid level 0 watermarks, then we can't
3656                 * support this display configuration.
3657                 */
3658                if (level) {
3659                        return 0;
3660                } else {
3661                        DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3662                        DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3663                                      to_intel_crtc(cstate->base.crtc)->pipe,
3664                                      skl_wm_plane_id(to_intel_plane(pstate->plane)),
3665                                      res_blocks, ddb_allocation, res_lines);
3666
3667                        return -EINVAL;
3668                }
3669        }
3670
3671        *out_blocks = res_blocks;
3672        *out_lines = res_lines;
3673        *enabled = true;
3674
3675        return 0;
3676}
3677
3678static int
3679skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3680                     struct skl_ddb_allocation *ddb,
3681                     struct intel_crtc_state *cstate,
3682                     int level,
3683                     struct skl_wm_level *result)
3684{
3685        struct drm_atomic_state *state = cstate->base.state;
3686        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3687        struct drm_plane *plane;
3688        struct intel_plane *intel_plane;
3689        struct intel_plane_state *intel_pstate;
3690        uint16_t ddb_blocks;
3691        enum pipe pipe = intel_crtc->pipe;
3692        int ret;
3693
3694        /*
3695         * We'll only calculate watermarks for planes that are actually
3696         * enabled, so make sure all other planes are set as disabled.
3697         */
3698        memset(result, 0, sizeof(*result));
3699
3700        for_each_intel_plane_mask(&dev_priv->drm,
3701                                  intel_plane,
3702                                  cstate->base.plane_mask) {
3703                int i = skl_wm_plane_id(intel_plane);
3704
3705                plane = &intel_plane->base;
3706                intel_pstate = NULL;
3707                if (state)
3708                        intel_pstate =
3709                                intel_atomic_get_existing_plane_state(state,
3710                                                                      intel_plane);
3711
3712                /*
3713                 * Note: If we start supporting multiple pending atomic commits
3714                 * against the same planes/CRTC's in the future, plane->state
3715                 * will no longer be the correct pre-state to use for the
3716                 * calculations here and we'll need to change where we get the
3717                 * 'unchanged' plane data from.
3718                 *
3719                 * For now this is fine because we only allow one queued commit
3720                 * against a CRTC.  Even if the plane isn't modified by this
3721                 * transaction and we don't have a plane lock, we still have
3722                 * the CRTC's lock, so we know that no other transactions are
3723                 * racing with us to update it.
3724                 */
3725                if (!intel_pstate)
3726                        intel_pstate = to_intel_plane_state(plane->state);
3727
3728                WARN_ON(!intel_pstate->base.fb);
3729
3730                ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3731
3732                ret = skl_compute_plane_wm(dev_priv,
3733                                           cstate,
3734                                           intel_pstate,
3735                                           ddb_blocks,
3736                                           level,
3737                                           &result->plane_res_b[i],
3738                                           &result->plane_res_l[i],
3739                                           &result->plane_en[i]);
3740                if (ret)
3741                        return ret;
3742        }
3743
3744        return 0;
3745}
3746
3747static uint32_t
3748skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3749{
3750        if (!cstate->base.active)
3751                return 0;
3752
3753        if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
3754                return 0;
3755
3756        return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3757                            ilk_pipe_pixel_rate(cstate));
3758}
3759
3760static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3761                                      struct skl_wm_level *trans_wm /* out */)
3762{
3763        struct drm_crtc *crtc = cstate->base.crtc;
3764        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765        struct intel_plane *intel_plane;
3766
3767        if (!cstate->base.active)
3768                return;
3769
3770        /* Until we know more, just disable transition WMs */
3771        for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3772                int i = skl_wm_plane_id(intel_plane);
3773
3774                trans_wm->plane_en[i] = false;
3775        }
3776}
3777
3778static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3779                             struct skl_ddb_allocation *ddb,
3780                             struct skl_pipe_wm *pipe_wm)
3781{
3782        struct drm_device *dev = cstate->base.crtc->dev;
3783        const struct drm_i915_private *dev_priv = to_i915(dev);
3784        int level, max_level = ilk_wm_max_level(dev);
3785        int ret;
3786
3787        for (level = 0; level <= max_level; level++) {
3788                ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3789                                           level, &pipe_wm->wm[level]);
3790                if (ret)
3791                        return ret;
3792        }
3793        pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3794
3795        skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3796
3797        return 0;
3798}
3799
3800static void skl_compute_wm_results(struct drm_device *dev,
3801                                   struct skl_pipe_wm *p_wm,
3802                                   struct skl_wm_values *r,
3803                                   struct intel_crtc *intel_crtc)
3804{
3805        int level, max_level = ilk_wm_max_level(dev);
3806        enum pipe pipe = intel_crtc->pipe;
3807        uint32_t temp;
3808        int i;
3809
3810        for (level = 0; level <= max_level; level++) {
3811                for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3812                        temp = 0;
3813
3814                        temp |= p_wm->wm[level].plane_res_l[i] <<
3815                                        PLANE_WM_LINES_SHIFT;
3816                        temp |= p_wm->wm[level].plane_res_b[i];
3817                        if (p_wm->wm[level].plane_en[i])
3818                                temp |= PLANE_WM_EN;
3819
3820                        r->plane[pipe][i][level] = temp;
3821                }
3822
3823                temp = 0;
3824
3825                temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3826                temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3827
3828                if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3829                        temp |= PLANE_WM_EN;
3830
3831                r->plane[pipe][PLANE_CURSOR][level] = temp;
3832
3833        }
3834
3835        /* transition WMs */
3836        for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3837                temp = 0;
3838                temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3839                temp |= p_wm->trans_wm.plane_res_b[i];
3840                if (p_wm->trans_wm.plane_en[i])
3841                        temp |= PLANE_WM_EN;
3842
3843                r->plane_trans[pipe][i] = temp;
3844        }
3845
3846        temp = 0;
3847        temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3848        temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3849        if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3850                temp |= PLANE_WM_EN;
3851
3852        r->plane_trans[pipe][PLANE_CURSOR] = temp;
3853
3854        r->wm_linetime[pipe] = p_wm->linetime;
3855}
3856
3857static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3858                                i915_reg_t reg,
3859                                const struct skl_ddb_entry *entry)
3860{
3861        if (entry->end)
3862                I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3863        else
3864                I915_WRITE(reg, 0);
3865}
3866
3867void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3868                        const struct skl_wm_values *wm,
3869                        int plane)
3870{
3871        struct drm_crtc *crtc = &intel_crtc->base;
3872        struct drm_device *dev = crtc->dev;
3873        struct drm_i915_private *dev_priv = to_i915(dev);
3874        int level, max_level = ilk_wm_max_level(dev);
3875        enum pipe pipe = intel_crtc->pipe;
3876
3877        for (level = 0; level <= max_level; level++) {
3878                I915_WRITE(PLANE_WM(pipe, plane, level),
3879                           wm->plane[pipe][plane][level]);
3880        }
3881        I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3882
3883        skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3884                            &wm->ddb.plane[pipe][plane]);
3885        skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3886                            &wm->ddb.y_plane[pipe][plane]);
3887}
3888
3889void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3890                         const struct skl_wm_values *wm)
3891{
3892        struct drm_crtc *crtc = &intel_crtc->base;
3893        struct drm_device *dev = crtc->dev;
3894        struct drm_i915_private *dev_priv = to_i915(dev);
3895        int level, max_level = ilk_wm_max_level(dev);
3896        enum pipe pipe = intel_crtc->pipe;
3897
3898        for (level = 0; level <= max_level; level++) {
3899                I915_WRITE(CUR_WM(pipe, level),
3900                           wm->plane[pipe][PLANE_CURSOR][level]);
3901        }
3902        I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3903
3904        skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3905                            &wm->ddb.plane[pipe][PLANE_CURSOR]);
3906}
3907
3908bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3909                               const struct skl_ddb_allocation *new,
3910                               enum pipe pipe)
3911{
3912        return new->pipe[pipe].start == old->pipe[pipe].start &&
3913               new->pipe[pipe].end == old->pipe[pipe].end;
3914}
3915
3916static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3917                                           const struct skl_ddb_entry *b)
3918{
3919        return a->start < b->end && b->start < a->end;
3920}
3921
3922bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3923                                 const struct skl_ddb_allocation *old,
3924                                 const struct skl_ddb_allocation *new,
3925                                 enum pipe pipe)
3926{
3927        struct drm_device *dev = state->dev;
3928        struct intel_crtc *intel_crtc;
3929        enum pipe otherp;
3930
3931        for_each_intel_crtc(dev, intel_crtc) {
3932                otherp = intel_crtc->pipe;
3933
3934                if (otherp == pipe)
3935                        continue;
3936
3937                if (skl_ddb_entries_overlap(&new->pipe[pipe],
3938                                            &old->pipe[otherp]))
3939                        return true;
3940        }
3941
3942        return false;
3943}
3944
3945static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3946                              struct skl_ddb_allocation *ddb, /* out */
3947                              struct skl_pipe_wm *pipe_wm, /* out */
3948                              bool *changed /* out */)
3949{
3950        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3951        struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3952        int ret;
3953
3954        ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3955        if (ret)
3956                return ret;
3957
3958        if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3959                *changed = false;
3960        else
3961                *changed = true;
3962
3963        return 0;
3964}
3965
3966static uint32_t
3967pipes_modified(struct drm_atomic_state *state)
3968{
3969        struct drm_crtc *crtc;
3970        struct drm_crtc_state *cstate;
3971        uint32_t i, ret = 0;
3972
3973        for_each_crtc_in_state(state, crtc, cstate, i)
3974                ret |= drm_crtc_mask(crtc);
3975
3976        return ret;
3977}
3978
3979int
3980skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3981{
3982        struct drm_atomic_state *state = cstate->base.state;
3983        struct drm_device *dev = state->dev;
3984        struct drm_crtc *crtc = cstate->base.crtc;
3985        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3986        struct drm_i915_private *dev_priv = to_i915(dev);
3987        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3988        struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3989        struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3990        struct drm_plane_state *plane_state;
3991        struct drm_plane *plane;
3992        enum pipe pipe = intel_crtc->pipe;
3993        int id;
3994
3995        WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3996
3997        drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3998                id = skl_wm_plane_id(to_intel_plane(plane));
3999
4000                if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
4001                                        &new_ddb->plane[pipe][id]) &&
4002                    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
4003                                        &new_ddb->y_plane[pipe][id]))
4004                        continue;
4005
4006                plane_state = drm_atomic_get_plane_state(state, plane);
4007                if (IS_ERR(plane_state))
4008                        return PTR_ERR(plane_state);
4009        }
4010
4011        return 0;
4012}
4013
4014static int
4015skl_compute_ddb(struct drm_atomic_state *state)
4016{
4017        struct drm_device *dev = state->dev;
4018        struct drm_i915_private *dev_priv = to_i915(dev);
4019        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4020        struct intel_crtc *intel_crtc;
4021        struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4022        uint32_t realloc_pipes = pipes_modified(state);
4023        int ret;
4024
4025        /*
4026         * If this is our first atomic update following hardware readout,
4027         * we can't trust the DDB that the BIOS programmed for us.  Let's
4028         * pretend that all pipes switched active status so that we'll
4029         * ensure a full DDB recompute.
4030         */
4031        if (dev_priv->wm.distrust_bios_wm) {
4032                ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4033                                       state->acquire_ctx);
4034                if (ret)
4035                        return ret;
4036
4037                intel_state->active_pipe_changes = ~0;
4038
4039                /*
4040                 * We usually only initialize intel_state->active_crtcs if we
4041                 * we're doing a modeset; make sure this field is always
4042                 * initialized during the sanitization process that happens
4043                 * on the first commit too.
4044                 */
4045                if (!intel_state->modeset)
4046                        intel_state->active_crtcs = dev_priv->active_crtcs;
4047        }
4048
4049        /*
4050         * If the modeset changes which CRTC's are active, we need to
4051         * recompute the DDB allocation for *all* active pipes, even
4052         * those that weren't otherwise being modified in any way by this
4053         * atomic commit.  Due to the shrinking of the per-pipe allocations
4054         * when new active CRTC's are added, it's possible for a pipe that
4055         * we were already using and aren't changing at all here to suddenly
4056         * become invalid if its DDB needs exceeds its new allocation.
4057         *
4058         * Note that if we wind up doing a full DDB recompute, we can't let
4059         * any other display updates race with this transaction, so we need
4060         * to grab the lock on *all* CRTC's.
4061         */
4062        if (intel_state->active_pipe_changes) {
4063                realloc_pipes = ~0;
4064                intel_state->wm_results.dirty_pipes = ~0;
4065        }
4066
4067        /*
4068         * We're not recomputing for the pipes not included in the commit, so
4069         * make sure we start with the current state.
4070         */
4071        memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4072
4073        for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4074                struct intel_crtc_state *cstate;
4075
4076                cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4077                if (IS_ERR(cstate))
4078                        return PTR_ERR(cstate);
4079
4080                ret = skl_allocate_pipe_ddb(cstate, ddb);
4081                if (ret)
4082                        return ret;
4083
4084                ret = skl_ddb_add_affected_planes(cstate);
4085                if (ret)
4086                        return ret;
4087        }
4088
4089        return 0;
4090}
4091
4092static void
4093skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4094                     struct skl_wm_values *src,
4095                     enum pipe pipe)
4096{
4097        dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4098        memcpy(dst->plane[pipe], src->plane[pipe],
4099               sizeof(dst->plane[pipe]));
4100        memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4101               sizeof(dst->plane_trans[pipe]));
4102
4103        dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4104        memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4105               sizeof(dst->ddb.y_plane[pipe]));
4106        memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4107               sizeof(dst->ddb.plane[pipe]));
4108}
4109
4110static int
4111skl_compute_wm(struct drm_atomic_state *state)
4112{
4113        struct drm_crtc *crtc;
4114        struct drm_crtc_state *cstate;
4115        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4116        struct skl_wm_values *results = &intel_state->wm_results;
4117        struct skl_pipe_wm *pipe_wm;
4118        bool changed = false;
4119        int ret, i;
4120
4121        /*
4122         * If this transaction isn't actually touching any CRTC's, don't
4123         * bother with watermark calculation.  Note that if we pass this
4124         * test, we're guaranteed to hold at least one CRTC state mutex,
4125         * which means we can safely use values like dev_priv->active_crtcs
4126         * since any racing commits that want to update them would need to
4127         * hold _all_ CRTC state mutexes.
4128         */
4129        for_each_crtc_in_state(state, crtc, cstate, i)
4130                changed = true;
4131        if (!changed)
4132                return 0;
4133
4134        /* Clear all dirty flags */
4135        results->dirty_pipes = 0;
4136
4137        ret = skl_compute_ddb(state);
4138        if (ret)
4139                return ret;
4140
4141        /*
4142         * Calculate WM's for all pipes that are part of this transaction.
4143         * Note that the DDB allocation above may have added more CRTC's that
4144         * weren't otherwise being modified (and set bits in dirty_pipes) if
4145         * pipe allocations had to change.
4146         *
4147         * FIXME:  Now that we're doing this in the atomic check phase, we
4148         * should allow skl_update_pipe_wm() to return failure in cases where
4149         * no suitable watermark values can be found.
4150         */
4151        for_each_crtc_in_state(state, crtc, cstate, i) {
4152                struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4153                struct intel_crtc_state *intel_cstate =
4154                        to_intel_crtc_state(cstate);
4155
4156                pipe_wm = &intel_cstate->wm.skl.optimal;
4157                ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4158                                         &changed);
4159                if (ret)
4160                        return ret;
4161
4162                if (changed)
4163                        results->dirty_pipes |= drm_crtc_mask(crtc);
4164
4165                if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4166                        /* This pipe's WM's did not change */
4167                        continue;
4168
4169                intel_cstate->update_wm_pre = true;
4170                skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4171        }
4172
4173        return 0;
4174}
4175
4176static void skl_update_wm(struct drm_crtc *crtc)
4177{
4178        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179        struct drm_device *dev = crtc->dev;
4180        struct drm_i915_private *dev_priv = to_i915(dev);
4181        struct skl_wm_values *results = &dev_priv->wm.skl_results;
4182        struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4183        struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4184        struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4185        enum pipe pipe = intel_crtc->pipe;
4186
4187        if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4188                return;
4189
4190        intel_crtc->wm.active.skl = *pipe_wm;
4191
4192        mutex_lock(&dev_priv->wm.wm_mutex);
4193
4194        /*
4195         * If this pipe isn't active already, we're going to be enabling it
4196         * very soon. Since it's safe to update a pipe's ddb allocation while
4197         * the pipe's shut off, just do so here. Already active pipes will have
4198         * their watermarks updated once we update their planes.
4199         */
4200        if (crtc->state->active_changed) {
4201                int plane;
4202
4203                for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4204                        skl_write_plane_wm(intel_crtc, results, plane);
4205
4206                skl_write_cursor_wm(intel_crtc, results);
4207        }
4208
4209        skl_copy_wm_for_pipe(hw_vals, results, pipe);
4210
4211        mutex_unlock(&dev_priv->wm.wm_mutex);
4212}
4213
4214static void ilk_compute_wm_config(struct drm_device *dev,
4215                                  struct intel_wm_config *config)
4216{
4217        struct intel_crtc *crtc;
4218
4219        /* Compute the currently _active_ config */
4220        for_each_intel_crtc(dev, crtc) {
4221                const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4222
4223                if (!wm->pipe_enabled)
4224                        continue;
4225
4226                config->sprites_enabled |= wm->sprites_enabled;
4227                config->sprites_scaled |= wm->sprites_scaled;
4228                config->num_pipes_active++;
4229        }
4230}
4231
4232static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4233{
4234        struct drm_device *dev = &dev_priv->drm;
4235        struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4236        struct ilk_wm_maximums max;
4237        struct intel_wm_config config = {};
4238        struct ilk_wm_values results = {};
4239        enum intel_ddb_partitioning partitioning;
4240
4241        ilk_compute_wm_config(dev, &config);
4242
4243        ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4244        ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4245
4246        /* 5/6 split only in single pipe config on IVB+ */
4247        if (INTEL_INFO(dev)->gen >= 7 &&
4248            config.num_pipes_active == 1 && config.sprites_enabled) {
4249                ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4250                ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4251
4252                best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4253        } else {
4254                best_lp_wm = &lp_wm_1_2;
4255        }
4256
4257        partitioning = (best_lp_wm == &lp_wm_1_2) ?
4258                       INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4259
4260        ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4261
4262        ilk_write_wm_values(dev_priv, &results);
4263}
4264
4265static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4266{
4267        struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4268        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4269
4270        mutex_lock(&dev_priv->wm.wm_mutex);
4271        intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4272        ilk_program_watermarks(dev_priv);
4273        mutex_unlock(&dev_priv->wm.wm_mutex);
4274}
4275
4276static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4277{
4278        struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4279        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4280
4281        mutex_lock(&dev_priv->wm.wm_mutex);
4282        if (cstate->wm.need_postvbl_update) {
4283                intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4284                ilk_program_watermarks(dev_priv);
4285        }
4286        mutex_unlock(&dev_priv->wm.wm_mutex);
4287}
4288
4289static void skl_pipe_wm_active_state(uint32_t val,
4290                                     struct skl_pipe_wm *active,
4291                                     bool is_transwm,
4292                                     bool is_cursor,
4293                                     int i,
4294                                     int level)
4295{
4296        bool is_enabled = (val & PLANE_WM_EN) != 0;
4297
4298        if (!is_transwm) {
4299                if (!is_cursor) {
4300                        active->wm[level].plane_en[i] = is_enabled;
4301                        active->wm[level].plane_res_b[i] =
4302                                        val & PLANE_WM_BLOCKS_MASK;
4303                        active->wm[level].plane_res_l[i] =
4304                                        (val >> PLANE_WM_LINES_SHIFT) &
4305                                                PLANE_WM_LINES_MASK;
4306                } else {
4307                        active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4308                        active->wm[level].plane_res_b[PLANE_CURSOR] =
4309                                        val & PLANE_WM_BLOCKS_MASK;
4310                        active->wm[level].plane_res_l[PLANE_CURSOR] =
4311                                        (val >> PLANE_WM_LINES_SHIFT) &
4312                                                PLANE_WM_LINES_MASK;
4313                }
4314        } else {
4315                if (!is_cursor) {
4316                        active->trans_wm.plane_en[i] = is_enabled;
4317                        active->trans_wm.plane_res_b[i] =
4318                                        val & PLANE_WM_BLOCKS_MASK;
4319                        active->trans_wm.plane_res_l[i] =
4320                                        (val >> PLANE_WM_LINES_SHIFT) &
4321                                                PLANE_WM_LINES_MASK;
4322                } else {
4323                        active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4324                        active->trans_wm.plane_res_b[PLANE_CURSOR] =
4325                                        val & PLANE_WM_BLOCKS_MASK;
4326                        active->trans_wm.plane_res_l[PLANE_CURSOR] =
4327                                        (val >> PLANE_WM_LINES_SHIFT) &
4328                                                PLANE_WM_LINES_MASK;
4329                }
4330        }
4331}
4332
4333static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4334{
4335        struct drm_device *dev = crtc->dev;
4336        struct drm_i915_private *dev_priv = to_i915(dev);
4337        struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4338        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4339        struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4340        struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4341        enum pipe pipe = intel_crtc->pipe;
4342        int level, i, max_level;
4343        uint32_t temp;
4344
4345        max_level = ilk_wm_max_level(dev);
4346
4347        hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4348
4349        for (level = 0; level <= max_level; level++) {
4350                for (i = 0; i < intel_num_planes(intel_crtc); i++)
4351                        hw->plane[pipe][i][level] =
4352                                        I915_READ(PLANE_WM(pipe, i, level));
4353                hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4354        }
4355
4356        for (i = 0; i < intel_num_planes(intel_crtc); i++)
4357                hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4358        hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4359
4360        if (!intel_crtc->active)
4361                return;
4362
4363        hw->dirty_pipes |= drm_crtc_mask(crtc);
4364
4365        active->linetime = hw->wm_linetime[pipe];
4366
4367        for (level = 0; level <= max_level; level++) {
4368                for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4369                        temp = hw->plane[pipe][i][level];
4370                        skl_pipe_wm_active_state(temp, active, false,
4371                                                false, i, level);
4372                }
4373                temp = hw->plane[pipe][PLANE_CURSOR][level];
4374                skl_pipe_wm_active_state(temp, active, false, true, i, level);
4375        }
4376
4377        for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4378                temp = hw->plane_trans[pipe][i];
4379                skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4380        }
4381
4382        temp = hw->plane_trans[pipe][PLANE_CURSOR];
4383        skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4384
4385        intel_crtc->wm.active.skl = *active;
4386}
4387
4388void skl_wm_get_hw_state(struct drm_device *dev)
4389{
4390        struct drm_i915_private *dev_priv = to_i915(dev);
4391        struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4392        struct drm_crtc *crtc;
4393
4394        skl_ddb_get_hw_state(dev_priv, ddb);
4395        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4396                skl_pipe_wm_get_hw_state(crtc);
4397
4398        if (dev_priv->active_crtcs) {
4399                /* Fully recompute DDB on first atomic commit */
4400                dev_priv->wm.distrust_bios_wm = true;
4401        } else {
4402                /* Easy/common case; just sanitize DDB now if everything off */
4403                memset(ddb, 0, sizeof(*ddb));
4404        }
4405}
4406
4407static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4408{
4409        struct drm_device *dev = crtc->dev;
4410        struct drm_i915_private *dev_priv = to_i915(dev);
4411        struct ilk_wm_values *hw = &dev_priv->wm.hw;
4412        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4413        struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4414        struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4415        enum pipe pipe = intel_crtc->pipe;
4416        static const i915_reg_t wm0_pipe_reg[] = {
4417                [PIPE_A] = WM0_PIPEA_ILK,
4418                [PIPE_B] = WM0_PIPEB_ILK,
4419                [PIPE_C] = WM0_PIPEC_IVB,
4420        };
4421
4422        hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4423        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4424                hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4425
4426        memset(active, 0, sizeof(*active));
4427
4428        active->pipe_enabled = intel_crtc->active;
4429
4430        if (active->pipe_enabled) {
4431                u32 tmp = hw->wm_pipe[pipe];
4432
4433                /*
4434                 * For active pipes LP0 watermark is marked as
4435                 * enabled, and LP1+ watermaks as disabled since
4436                 * we can't really reverse compute them in case
4437                 * multiple pipes are active.
4438                 */
4439                active->wm[0].enable = true;
4440                active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4441                active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4442                active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4443                active->linetime = hw->wm_linetime[pipe];
4444        } else {
4445                int level, max_level = ilk_wm_max_level(dev);
4446
4447                /*
4448                 * For inactive pipes, all watermark levels
4449                 * should be marked as enabled but zeroed,
4450                 * which is what we'd compute them to.
4451                 */
4452                for (level = 0; level <= max_level; level++)
4453                        active->wm[level].enable = true;
4454        }
4455
4456        intel_crtc->wm.active.ilk = *active;
4457}
4458
4459#define _FW_WM(value, plane) \
4460        (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4461#define _FW_WM_VLV(value, plane) \
4462        (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4463
4464static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4465                               struct vlv_wm_values *wm)
4466{
4467        enum pipe pipe;
4468        uint32_t tmp;
4469
4470        for_each_pipe(dev_priv, pipe) {
4471                tmp = I915_READ(VLV_DDL(pipe));
4472
4473                wm->ddl[pipe].primary =
4474                        (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4475                wm->ddl[pipe].cursor =
4476                        (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4477                wm->ddl[pipe].sprite[0] =
4478                        (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4479                wm->ddl[pipe].sprite[1] =
4480                        (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4481        }
4482
4483        tmp = I915_READ(DSPFW1);
4484        wm->sr.plane = _FW_WM(tmp, SR);
4485        wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4486        wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4487        wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4488
4489        tmp = I915_READ(DSPFW2);
4490        wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4491        wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4492        wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4493
4494        tmp = I915_READ(DSPFW3);
4495        wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4496
4497        if (IS_CHERRYVIEW(dev_priv)) {
4498                tmp = I915_READ(DSPFW7_CHV);
4499                wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4500                wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4501
4502                tmp = I915_READ(DSPFW8_CHV);
4503                wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4504                wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4505
4506                tmp = I915_READ(DSPFW9_CHV);
4507                wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4508                wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4509
4510                tmp = I915_READ(DSPHOWM);
4511                wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4512                wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4513                wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4514                wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4515                wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4516                wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4517                wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4518                wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4519                wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4520                wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4521        } else {
4522                tmp = I915_READ(DSPFW7);
4523                wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4524                wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4525
4526                tmp = I915_READ(DSPHOWM);
4527                wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4528                wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4529                wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4530                wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4531                wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4532                wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4533                wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4534        }
4535}
4536
4537#undef _FW_WM
4538#undef _FW_WM_VLV
4539
4540void vlv_wm_get_hw_state(struct drm_device *dev)
4541{
4542        struct drm_i915_private *dev_priv = to_i915(dev);
4543        struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4544        struct intel_plane *plane;
4545        enum pipe pipe;
4546        u32 val;
4547
4548        vlv_read_wm_values(dev_priv, wm);
4549
4550        for_each_intel_plane(dev, plane) {
4551                switch (plane->base.type) {
4552                        int sprite;
4553                case DRM_PLANE_TYPE_CURSOR:
4554                        plane->wm.fifo_size = 63;
4555                        break;
4556                case DRM_PLANE_TYPE_PRIMARY:
4557                        plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4558                        break;
4559                case DRM_PLANE_TYPE_OVERLAY:
4560                        sprite = plane->plane;
4561                        plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4562                        break;
4563                }
4564        }
4565
4566        wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4567        wm->level = VLV_WM_LEVEL_PM2;
4568
4569        if (IS_CHERRYVIEW(dev_priv)) {
4570                mutex_lock(&dev_priv->rps.hw_lock);
4571
4572                val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4573                if (val & DSP_MAXFIFO_PM5_ENABLE)
4574                        wm->level = VLV_WM_LEVEL_PM5;
4575
4576                /*
4577                 * If DDR DVFS is disabled in the BIOS, Punit
4578                 * will never ack the request. So if that happens
4579                 * assume we don't have to enable/disable DDR DVFS
4580                 * dynamically. To test that just set the REQ_ACK
4581                 * bit to poke the Punit, but don't change the
4582                 * HIGH/LOW bits so that we don't actually change
4583                 * the current state.
4584                 */
4585                val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4586                val |= FORCE_DDR_FREQ_REQ_ACK;
4587                vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4588
4589                if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4590                              FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4591                        DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4592                                      "assuming DDR DVFS is disabled\n");
4593                        dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4594                } else {
4595                        val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4596                        if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4597                                wm->level = VLV_WM_LEVEL_DDR_DVFS;
4598                }
4599
4600                mutex_unlock(&dev_priv->rps.hw_lock);
4601        }
4602
4603        for_each_pipe(dev_priv, pipe)
4604                DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4605                              pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4606                              wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4607
4608        DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4609                      wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4610}
4611
4612void ilk_wm_get_hw_state(struct drm_device *dev)
4613{
4614        struct drm_i915_private *dev_priv = to_i915(dev);
4615        struct ilk_wm_values *hw = &dev_priv->wm.hw;
4616        struct drm_crtc *crtc;
4617
4618        for_each_crtc(dev, crtc)
4619                ilk_pipe_wm_get_hw_state(crtc);
4620
4621        hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4622        hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4623        hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4624
4625        hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4626        if (INTEL_INFO(dev)->gen >= 7) {
4627                hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4628                hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4629        }
4630
4631        if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4632                hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4633                        INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4634        else if (IS_IVYBRIDGE(dev))
4635                hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4636                        INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4637
4638        hw->enable_fbc_wm =
4639                !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4640}
4641
4642/**
4643 * intel_update_watermarks - update FIFO watermark values based on current modes
4644 *
4645 * Calculate watermark values for the various WM regs based on current mode
4646 * and plane configuration.
4647 *
4648 * There are several cases to deal with here:
4649 *   - normal (i.e. non-self-refresh)
4650 *   - self-refresh (SR) mode
4651 *   - lines are large relative to FIFO size (buffer can hold up to 2)
4652 *   - lines are small relative to FIFO size (buffer can hold more than 2
4653 *     lines), so need to account for TLB latency
4654 *
4655 *   The normal calculation is:
4656 *     watermark = dotclock * bytes per pixel * latency
4657 *   where latency is platform & configuration dependent (we assume pessimal
4658 *   values here).
4659 *
4660 *   The SR calculation is:
4661 *     watermark = (trunc(latency/line time)+1) * surface width *
4662 *       bytes per pixel
4663 *   where
4664 *     line time = htotal / dotclock
4665 *     surface width = hdisplay for normal plane and 64 for cursor
4666 *   and latency is assumed to be high, as above.
4667 *
4668 * The final value programmed to the register should always be rounded up,
4669 * and include an extra 2 entries to account for clock crossings.
4670 *
4671 * We don't use the sprite, so we can ignore that.  And on Crestline we have
4672 * to set the non-SR watermarks to 8.
4673 */
4674void intel_update_watermarks(struct drm_crtc *crtc)
4675{
4676        struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4677
4678        if (dev_priv->display.update_wm)
4679                dev_priv->display.update_wm(crtc);
4680}
4681
4682/*
4683 * Lock protecting IPS related data structures
4684 */
4685DEFINE_SPINLOCK(mchdev_lock);
4686
4687/* Global for IPS driver to get at the current i915 device. Protected by
4688 * mchdev_lock. */
4689static struct drm_i915_private *i915_mch_dev;
4690
4691bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4692{
4693        u16 rgvswctl;
4694
4695        assert_spin_locked(&mchdev_lock);
4696
4697        rgvswctl = I915_READ16(MEMSWCTL);
4698        if (rgvswctl & MEMCTL_CMD_STS) {
4699                DRM_DEBUG("gpu busy, RCS change rejected\n");
4700                return false; /* still busy with another command */
4701        }
4702
4703        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4704                (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4705        I915_WRITE16(MEMSWCTL, rgvswctl);
4706        POSTING_READ16(MEMSWCTL);
4707
4708        rgvswctl |= MEMCTL_CMD_STS;
4709        I915_WRITE16(MEMSWCTL, rgvswctl);
4710
4711        return true;
4712}
4713
4714static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4715{
4716        u32 rgvmodectl;
4717        u8 fmax, fmin, fstart, vstart;
4718
4719        spin_lock_irq(&mchdev_lock);
4720
4721        rgvmodectl = I915_READ(MEMMODECTL);
4722
4723        /* Enable temp reporting */
4724        I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4725        I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4726
4727        /* 100ms RC evaluation intervals */
4728        I915_WRITE(RCUPEI, 100000);
4729        I915_WRITE(RCDNEI, 100000);
4730
4731        /* Set max/min thresholds to 90ms and 80ms respectively */
4732        I915_WRITE(RCBMAXAVG, 90000);
4733        I915_WRITE(RCBMINAVG, 80000);
4734
4735        I915_WRITE(MEMIHYST, 1);
4736
4737        /* Set up min, max, and cur for interrupt handling */
4738        fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4739        fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4740        fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4741                MEMMODE_FSTART_SHIFT;
4742
4743        vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4744                PXVFREQ_PX_SHIFT;
4745
4746        dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4747        dev_priv->ips.fstart = fstart;
4748
4749        dev_priv->ips.max_delay = fstart;
4750        dev_priv->ips.min_delay = fmin;
4751        dev_priv->ips.cur_delay = fstart;
4752
4753        DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4754                         fmax, fmin, fstart);
4755
4756        I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4757
4758        /*
4759         * Interrupts will be enabled in ironlake_irq_postinstall
4760         */
4761
4762        I915_WRITE(VIDSTART, vstart);
4763        POSTING_READ(VIDSTART);
4764
4765        rgvmodectl |= MEMMODE_SWMODE_EN;
4766        I915_WRITE(MEMMODECTL, rgvmodectl);
4767
4768        if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4769                DRM_ERROR("stuck trying to change perf mode\n");
4770        mdelay(1);
4771
4772        ironlake_set_drps(dev_priv, fstart);
4773
4774        dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4775                I915_READ(DDREC) + I915_READ(CSIEC);
4776        dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4777        dev_priv->ips.last_count2 = I915_READ(GFXEC);
4778        dev_priv->ips.last_time2 = ktime_get_raw_ns();
4779
4780        spin_unlock_irq(&mchdev_lock);
4781}
4782
4783static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4784{
4785        u16 rgvswctl;
4786
4787        spin_lock_irq(&mchdev_lock);
4788
4789        rgvswctl = I915_READ16(MEMSWCTL);
4790
4791        /* Ack interrupts, disable EFC interrupt */
4792        I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4793        I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4794        I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4795        I915_WRITE(DEIIR, DE_PCU_EVENT);
4796        I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4797
4798        /* Go back to the starting frequency */
4799        ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4800        mdelay(1);
4801        rgvswctl |= MEMCTL_CMD_STS;
4802        I915_WRITE(MEMSWCTL, rgvswctl);
4803        mdelay(1);
4804
4805        spin_unlock_irq(&mchdev_lock);
4806}
4807
4808/* There's a funny hw issue where the hw returns all 0 when reading from
4809 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4810 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4811 * all limits and the gpu stuck at whatever frequency it is at atm).
4812 */
4813static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4814{
4815        u32 limits;
4816
4817        /* Only set the down limit when we've reached the lowest level to avoid
4818         * getting more interrupts, otherwise leave this clear. This prevents a
4819         * race in the hw when coming out of rc6: There's a tiny window where
4820         * the hw runs at the minimal clock before selecting the desired
4821         * frequency, if the down threshold expires in that window we will not
4822         * receive a down interrupt. */
4823        if (IS_GEN9(dev_priv)) {
4824                limits = (dev_priv->rps.max_freq_softlimit) << 23;
4825                if (val <= dev_priv->rps.min_freq_softlimit)
4826                        limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4827        } else {
4828                limits = dev_priv->rps.max_freq_softlimit << 24;
4829                if (val <= dev_priv->rps.min_freq_softlimit)
4830                        limits |= dev_priv->rps.min_freq_softlimit << 16;
4831        }
4832
4833        return limits;
4834}
4835
4836static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4837{
4838        int new_power;
4839        u32 threshold_up = 0, threshold_down = 0; /* in % */
4840        u32 ei_up = 0, ei_down = 0;
4841
4842        new_power = dev_priv->rps.power;
4843        switch (dev_priv->rps.power) {
4844        case LOW_POWER:
4845                if (val > dev_priv->rps.efficient_freq + 1 &&
4846                    val > dev_priv->rps.cur_freq)
4847                        new_power = BETWEEN;
4848                break;
4849
4850        case BETWEEN:
4851                if (val <= dev_priv->rps.efficient_freq &&
4852                    val < dev_priv->rps.cur_freq)
4853                        new_power = LOW_POWER;
4854                else if (val >= dev_priv->rps.rp0_freq &&
4855                         val > dev_priv->rps.cur_freq)
4856                        new_power = HIGH_POWER;
4857                break;
4858
4859        case HIGH_POWER:
4860                if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4861                    val < dev_priv->rps.cur_freq)
4862                        new_power = BETWEEN;
4863                break;
4864        }
4865        /* Max/min bins are special */
4866        if (val <= dev_priv->rps.min_freq_softlimit)
4867                new_power = LOW_POWER;
4868        if (val >= dev_priv->rps.max_freq_softlimit)
4869                new_power = HIGH_POWER;
4870        if (new_power == dev_priv->rps.power)
4871                return;
4872
4873        /* Note the units here are not exactly 1us, but 1280ns. */
4874        switch (new_power) {
4875        case LOW_POWER:
4876                /* Upclock if more than 95% busy over 16ms */
4877                ei_up = 16000;
4878                threshold_up = 95;
4879
4880                /* Downclock if less than 85% busy over 32ms */
4881                ei_down = 32000;
4882                threshold_down = 85;
4883                break;
4884
4885        case BETWEEN:
4886                /* Upclock if more than 90% busy over 13ms */
4887                ei_up = 13000;
4888                threshold_up = 90;
4889
4890                /* Downclock if less than 75% busy over 32ms */
4891                ei_down = 32000;
4892                threshold_down = 75;
4893                break;
4894
4895        case HIGH_POWER:
4896                /* Upclock if more than 85% busy over 10ms */
4897                ei_up = 10000;
4898                threshold_up = 85;
4899
4900                /* Downclock if less than 60% busy over 32ms */
4901                ei_down = 32000;
4902                threshold_down = 60;
4903                break;
4904        }
4905
4906        /* When byt can survive without system hang with dynamic
4907         * sw freq adjustments, this restriction can be lifted.
4908         */
4909        if (IS_VALLEYVIEW(dev_priv))
4910                goto skip_hw_write;
4911
4912        I915_WRITE(GEN6_RP_UP_EI,
4913                   GT_INTERVAL_FROM_US(dev_priv, ei_up));
4914        I915_WRITE(GEN6_RP_UP_THRESHOLD,
4915                   GT_INTERVAL_FROM_US(dev_priv,
4916                                       ei_up * threshold_up / 100));
4917
4918        I915_WRITE(GEN6_RP_DOWN_EI,
4919                   GT_INTERVAL_FROM_US(dev_priv, ei_down));
4920        I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4921                   GT_INTERVAL_FROM_US(dev_priv,
4922                                       ei_down * threshold_down / 100));
4923
4924        I915_WRITE(GEN6_RP_CONTROL,
4925                   GEN6_RP_MEDIA_TURBO |
4926                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
4927                   GEN6_RP_MEDIA_IS_GFX |
4928                   GEN6_RP_ENABLE |
4929                   GEN6_RP_UP_BUSY_AVG |
4930                   GEN6_RP_DOWN_IDLE_AVG);
4931
4932skip_hw_write:
4933        dev_priv->rps.power = new_power;
4934        dev_priv->rps.up_threshold = threshold_up;
4935        dev_priv->rps.down_threshold = threshold_down;
4936        dev_priv->rps.last_adj = 0;
4937}
4938
4939static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4940{
4941        u32 mask = 0;
4942
4943        /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
4944        if (val > dev_priv->rps.min_freq_softlimit)
4945                mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4946        if (val < dev_priv->rps.max_freq_softlimit)
4947                mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4948
4949        mask &= dev_priv->pm_rps_events;
4950
4951        return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4952}
4953
4954/* gen6_set_rps is called to update the frequency request, but should also be
4955 * called when the range (min_delay and max_delay) is modified so that we can
4956 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4957static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4958{
4959        /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4960        if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4961                return;
4962
4963        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4964        WARN_ON(val > dev_priv->rps.max_freq);
4965        WARN_ON(val < dev_priv->rps.min_freq);
4966
4967        /* min/max delay may still have been modified so be sure to
4968         * write the limits value.
4969         */
4970        if (val != dev_priv->rps.cur_freq) {
4971                gen6_set_rps_thresholds(dev_priv, val);
4972
4973                if (IS_GEN9(dev_priv))
4974                        I915_WRITE(GEN6_RPNSWREQ,
4975                                   GEN9_FREQUENCY(val));
4976                else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4977                        I915_WRITE(GEN6_RPNSWREQ,
4978                                   HSW_FREQUENCY(val));
4979                else
4980                        I915_WRITE(GEN6_RPNSWREQ,
4981                                   GEN6_FREQUENCY(val) |
4982                                   GEN6_OFFSET(0) |
4983                                   GEN6_AGGRESSIVE_TURBO);
4984        }
4985
4986        /* Make sure we continue to get interrupts
4987         * until we hit the minimum or maximum frequencies.
4988         */
4989        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4990        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4991
4992        POSTING_READ(GEN6_RPNSWREQ);
4993
4994        dev_priv->rps.cur_freq = val;
4995        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4996}
4997
4998static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4999{
5000        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5001        WARN_ON(val > dev_priv->rps.max_freq);
5002        WARN_ON(val < dev_priv->rps.min_freq);
5003
5004        if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
5005                      "Odd GPU freq value\n"))
5006                val &= ~1;
5007
5008        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5009
5010        if (val != dev_priv->rps.cur_freq) {
5011                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
5012                if (!IS_CHERRYVIEW(dev_priv))
5013                        gen6_set_rps_thresholds(dev_priv, val);
5014        }
5015
5016        dev_priv->rps.cur_freq = val;
5017        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5018}
5019
5020/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5021 *
5022 * * If Gfx is Idle, then
5023 * 1. Forcewake Media well.
5024 * 2. Request idle freq.
5025 * 3. Release Forcewake of Media well.
5026*/
5027static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5028{
5029        u32 val = dev_priv->rps.idle_freq;
5030
5031        if (dev_priv->rps.cur_freq <= val)
5032                return;
5033
5034        /* Wake up the media well, as that takes a lot less
5035         * power than the Render well. */
5036        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5037        valleyview_set_rps(dev_priv, val);
5038        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5039}
5040
5041void gen6_rps_busy(struct drm_i915_private *dev_priv)
5042{
5043        mutex_lock(&dev_priv->rps.hw_lock);
5044        if (dev_priv->rps.enabled) {
5045                if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
5046                        gen6_rps_reset_ei(dev_priv);
5047                I915_WRITE(GEN6_PMINTRMSK,
5048                           gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5049
5050                gen6_enable_rps_interrupts(dev_priv);
5051
5052                /* Ensure we start at the user's desired frequency */
5053                intel_set_rps(dev_priv,
5054                              clamp(dev_priv->rps.cur_freq,
5055                                    dev_priv->rps.min_freq_softlimit,
5056                                    dev_priv->rps.max_freq_softlimit));
5057        }
5058        mutex_unlock(&dev_priv->rps.hw_lock);
5059}
5060
5061void gen6_rps_idle(struct drm_i915_private *dev_priv)
5062{
5063        /* Flush our bottom-half so that it does not race with us
5064         * setting the idle frequency and so that it is bounded by
5065         * our rpm wakeref. And then disable the interrupts to stop any
5066         * futher RPS reclocking whilst we are asleep.
5067         */
5068        gen6_disable_rps_interrupts(dev_priv);
5069
5070        mutex_lock(&dev_priv->rps.hw_lock);
5071        if (dev_priv->rps.enabled) {
5072                if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5073                        vlv_set_rps_idle(dev_priv);
5074                else
5075                        gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5076                dev_priv->rps.last_adj = 0;
5077                I915_WRITE(GEN6_PMINTRMSK,
5078                           gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5079        }
5080        mutex_unlock(&dev_priv->rps.hw_lock);
5081
5082        spin_lock(&dev_priv->rps.client_lock);
5083        while (!list_empty(&dev_priv->rps.clients))
5084                list_del_init(dev_priv->rps.clients.next);
5085        spin_unlock(&dev_priv->rps.client_lock);
5086}
5087
5088void gen6_rps_boost(struct drm_i915_private *dev_priv,
5089                    struct intel_rps_client *rps,
5090                    unsigned long submitted)
5091{
5092        /* This is intentionally racy! We peek at the state here, then
5093         * validate inside the RPS worker.
5094         */
5095        if (!(dev_priv->gt.awake &&
5096              dev_priv->rps.enabled &&
5097              dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5098                return;
5099
5100        /* Force a RPS boost (and don't count it against the client) if
5101         * the GPU is severely congested.
5102         */
5103        if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5104                rps = NULL;
5105
5106        spin_lock(&dev_priv->rps.client_lock);
5107        if (rps == NULL || list_empty(&rps->link)) {
5108                spin_lock_irq(&dev_priv->irq_lock);
5109                if (dev_priv->rps.interrupts_enabled) {
5110                        dev_priv->rps.client_boost = true;
5111                        schedule_work(&dev_priv->rps.work);
5112                }
5113                spin_unlock_irq(&dev_priv->irq_lock);
5114
5115                if (rps != NULL) {
5116                        list_add(&rps->link, &dev_priv->rps.clients);
5117                        rps->boosts++;
5118                } else
5119                        dev_priv->rps.boosts++;
5120        }
5121        spin_unlock(&dev_priv->rps.client_lock);
5122}
5123
5124void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5125{
5126        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5127                valleyview_set_rps(dev_priv, val);
5128        else
5129                gen6_set_rps(dev_priv, val);
5130}
5131
5132static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5133{
5134        I915_WRITE(GEN6_RC_CONTROL, 0);
5135        I915_WRITE(GEN9_PG_ENABLE, 0);
5136}
5137
5138static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5139{
5140        I915_WRITE(GEN6_RP_CONTROL, 0);
5141}
5142
5143static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5144{
5145        I915_WRITE(GEN6_RC_CONTROL, 0);
5146        I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5147        I915_WRITE(GEN6_RP_CONTROL, 0);
5148}
5149
5150static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5151{
5152        I915_WRITE(GEN6_RC_CONTROL, 0);
5153}
5154
5155static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5156{
5157        /* we're doing forcewake before Disabling RC6,
5158         * This what the BIOS expects when going into suspend */
5159        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5160
5161        I915_WRITE(GEN6_RC_CONTROL, 0);
5162
5163        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5164}
5165
5166static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5167{
5168        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5169                if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5170                        mode = GEN6_RC_CTL_RC6_ENABLE;
5171                else
5172                        mode = 0;
5173        }
5174        if (HAS_RC6p(dev_priv))
5175                DRM_DEBUG_DRIVER("Enabling RC6 states: "
5176                                 "RC6 %s RC6p %s RC6pp %s\n",
5177                                 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5178                                 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5179                                 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5180
5181        else
5182                DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5183                                 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5184}
5185
5186static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5187{
5188        struct i915_ggtt *ggtt = &dev_priv->ggtt;
5189        bool enable_rc6 = true;
5190        unsigned long rc6_ctx_base;
5191        u32 rc_ctl;
5192        int rc_sw_target;
5193
5194        rc_ctl = I915_READ(GEN6_RC_CONTROL);
5195        rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5196                       RC_SW_TARGET_STATE_SHIFT;
5197        DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5198                         "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5199                         onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5200                         onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5201                         rc_sw_target);
5202
5203        if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5204                DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5205                enable_rc6 = false;
5206        }
5207
5208        /*
5209         * The exact context size is not known for BXT, so assume a page size
5210         * for this check.
5211         */
5212        rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5213        if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5214              (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5215                                        ggtt->stolen_reserved_size))) {
5216                DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5217                enable_rc6 = false;
5218        }
5219
5220        if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5221              ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5222              ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5223              ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5224                DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5225                enable_rc6 = false;
5226        }
5227
5228        if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5229            !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5230            !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5231                DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5232                enable_rc6 = false;
5233        }
5234
5235        if (!I915_READ(GEN6_GFXPAUSE)) {
5236                DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5237                enable_rc6 = false;
5238        }
5239
5240        if (!I915_READ(GEN8_MISC_CTRL0)) {
5241                DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5242                enable_rc6 = false;
5243        }
5244
5245        return enable_rc6;
5246}
5247
5248int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5249{
5250        /* No RC6 before Ironlake and code is gone for ilk. */
5251        if (INTEL_INFO(dev_priv)->gen < 6)
5252                return 0;
5253
5254        if (!enable_rc6)
5255                return 0;
5256
5257        if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5258                DRM_INFO("RC6 disabled by BIOS\n");
5259                return 0;
5260        }
5261
5262        /* Respect the kernel parameter if it is set */
5263        if (enable_rc6 >= 0) {
5264                int mask;
5265
5266                if (HAS_RC6p(dev_priv))
5267                        mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5268                               INTEL_RC6pp_ENABLE;
5269                else
5270                        mask = INTEL_RC6_ENABLE;
5271
5272                if ((enable_rc6 & mask) != enable_rc6)
5273                        DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5274                                         "(requested %d, valid %d)\n",
5275                                         enable_rc6 & mask, enable_rc6, mask);
5276
5277                return enable_rc6 & mask;
5278        }
5279
5280        if (IS_IVYBRIDGE(dev_priv))
5281                return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5282
5283        return INTEL_RC6_ENABLE;
5284}
5285
5286static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5287{
5288        /* All of these values are in units of 50MHz */
5289
5290        /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5291        if (IS_BROXTON(dev_priv)) {
5292                u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5293                dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5294                dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5295                dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5296        } else {
5297                u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5298                dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5299                dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5300                dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5301        }
5302        /* hw_max = RP0 until we check for overclocking */
5303        dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5304
5305        dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5306        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5307            IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5308                u32 ddcc_status = 0;
5309
5310                if (sandybridge_pcode_read(dev_priv,
5311                                           HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5312                                           &ddcc_status) == 0)
5313                        dev_priv->rps.efficient_freq =
5314                                clamp_t(u8,
5315                                        ((ddcc_status >> 8) & 0xff),
5316                                        dev_priv->rps.min_freq,
5317                                        dev_priv->rps.max_freq);
5318        }
5319
5320        if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5321                /* Store the frequency values in 16.66 MHZ units, which is
5322                 * the natural hardware unit for SKL
5323                 */
5324                dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5325                dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5326                dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5327                dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5328                dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5329        }
5330}
5331
5332static void reset_rps(struct drm_i915_private *dev_priv,
5333                      void (*set)(struct drm_i915_private *, u8))
5334{
5335        u8 freq = dev_priv->rps.cur_freq;
5336
5337        /* force a reset */
5338        dev_priv->rps.power = -1;
5339        dev_priv->rps.cur_freq = -1;
5340
5341        set(dev_priv, freq);
5342}
5343
5344/* See the Gen9_GT_PM_Programming_Guide doc for the below */
5345static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5346{
5347        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5348
5349        /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5350        if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5351                /*
5352                 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5353                 * clear out the Control register just to avoid inconsitency
5354                 * with debugfs interface, which will show  Turbo as enabled
5355                 * only and that is not expected by the User after adding the
5356                 * WaGsvDisableTurbo. Apart from this there is no problem even
5357                 * if the Turbo is left enabled in the Control register, as the
5358                 * Up/Down interrupts would remain masked.
5359                 */
5360                gen9_disable_rps(dev_priv);
5361                intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5362                return;
5363        }
5364
5365        /* Program defaults and thresholds for RPS*/
5366        I915_WRITE(GEN6_RC_VIDEO_FREQ,
5367                GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5368
5369        /* 1 second timeout*/
5370        I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5371                GT_INTERVAL_FROM_US(dev_priv, 1000000));
5372
5373        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5374
5375        /* Leaning on the below call to gen6_set_rps to program/setup the
5376         * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5377         * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5378        reset_rps(dev_priv, gen6_set_rps);
5379
5380        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5381}
5382
5383static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5384{
5385        struct intel_engine_cs *engine;
5386        uint32_t rc6_mask = 0;
5387
5388        /* 1a: Software RC state - RC0 */
5389        I915_WRITE(GEN6_RC_STATE, 0);
5390
5391        /* 1b: Get forcewake during program sequence. Although the driver
5392         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5393        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5394
5395        /* 2a: Disable RC states. */
5396        I915_WRITE(GEN6_RC_CONTROL, 0);
5397
5398        /* 2b: Program RC6 thresholds.*/
5399
5400        /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5401        if (IS_SKYLAKE(dev_priv))
5402                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5403        else
5404                I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5405        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5406        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5407        for_each_engine(engine, dev_priv)
5408                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5409
5410        if (HAS_GUC(dev_priv))
5411                I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5412
5413        I915_WRITE(GEN6_RC_SLEEP, 0);
5414
5415        /* 2c: Program Coarse Power Gating Policies. */
5416        I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5417        I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5418
5419        /* 3a: Enable RC6 */
5420        if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5421                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5422        DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5423        /* WaRsUseTimeoutMode */
5424        if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5425            IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5426                I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5427                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5428                           GEN7_RC_CTL_TO_MODE |
5429                           rc6_mask);
5430        } else {
5431                I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5432                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5433                           GEN6_RC_CTL_EI_MODE(1) |
5434                           rc6_mask);
5435        }
5436
5437        /*
5438         * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5439         * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5440         */
5441        if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5442                I915_WRITE(GEN9_PG_ENABLE, 0);
5443        else
5444                I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5445                                (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5446
5447        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5448}
5449
5450static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5451{
5452        struct intel_engine_cs *engine;
5453        uint32_t rc6_mask = 0;
5454
5455        /* 1a: Software RC state - RC0 */
5456        I915_WRITE(GEN6_RC_STATE, 0);
5457
5458        /* 1c & 1d: Get forcewake during program sequence. Although the driver
5459         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5460        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5461
5462        /* 2a: Disable RC states. */
5463        I915_WRITE(GEN6_RC_CONTROL, 0);
5464
5465        /* 2b: Program RC6 thresholds.*/
5466        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5467        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5468        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5469        for_each_engine(engine, dev_priv)
5470                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5471        I915_WRITE(GEN6_RC_SLEEP, 0);
5472        if (IS_BROADWELL(dev_priv))
5473                I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5474        else
5475                I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5476
5477        /* 3: Enable RC6 */
5478        if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5479                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5480        intel_print_rc6_info(dev_priv, rc6_mask);
5481        if (IS_BROADWELL(dev_priv))
5482                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5483                                GEN7_RC_CTL_TO_MODE |
5484                                rc6_mask);
5485        else
5486                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5487                                GEN6_RC_CTL_EI_MODE(1) |
5488                                rc6_mask);
5489
5490        /* 4 Program defaults and thresholds for RPS*/
5491        I915_WRITE(GEN6_RPNSWREQ,
5492                   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5493        I915_WRITE(GEN6_RC_VIDEO_FREQ,
5494                   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5495        /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5496        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5497
5498        /* Docs recommend 900MHz, and 300 MHz respectively */
5499        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5500                   dev_priv->rps.max_freq_softlimit << 24 |
5501                   dev_priv->rps.min_freq_softlimit << 16);
5502
5503        I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5504        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5505        I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5506        I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5507
5508        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5509
5510        /* 5: Enable RPS */
5511        I915_WRITE(GEN6_RP_CONTROL,
5512                   GEN6_RP_MEDIA_TURBO |
5513                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
5514                   GEN6_RP_MEDIA_IS_GFX |
5515                   GEN6_RP_ENABLE |
5516                   GEN6_RP_UP_BUSY_AVG |
5517                   GEN6_RP_DOWN_IDLE_AVG);
5518
5519        /* 6: Ring frequency + overclocking (our driver does this later */
5520
5521        reset_rps(dev_priv, gen6_set_rps);
5522
5523        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5524}
5525
5526static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5527{
5528        struct intel_engine_cs *engine;
5529        u32 rc6vids, rc6_mask = 0;
5530        u32 gtfifodbg;
5531        int rc6_mode;
5532        int ret;
5533
5534        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5535
5536        /* Here begins a magic sequence of register writes to enable
5537         * auto-downclocking.
5538         *
5539         * Perhaps there might be some value in exposing these to
5540         * userspace...
5541         */
5542        I915_WRITE(GEN6_RC_STATE, 0);
5543
5544        /* Clear the DBG now so we don't confuse earlier errors */
5545        gtfifodbg = I915_READ(GTFIFODBG);
5546        if (gtfifodbg) {
5547                DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5548                I915_WRITE(GTFIFODBG, gtfifodbg);
5549        }
5550
5551        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5552
5553        /* disable the counters and set deterministic thresholds */
5554        I915_WRITE(GEN6_RC_CONTROL, 0);
5555
5556        I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5557        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5558        I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5559        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5560        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5561
5562        for_each_engine(engine, dev_priv)
5563                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5564
5565        I915_WRITE(GEN6_RC_SLEEP, 0);
5566        I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5567        if (IS_IVYBRIDGE(dev_priv))
5568                I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5569        else
5570                I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5571        I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5572        I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5573
5574        /* Check if we are enabling RC6 */
5575        rc6_mode = intel_enable_rc6();
5576        if (rc6_mode & INTEL_RC6_ENABLE)
5577                rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5578
5579        /* We don't use those on Haswell */
5580        if (!IS_HASWELL(dev_priv)) {
5581                if (rc6_mode & INTEL_RC6p_ENABLE)
5582                        rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5583
5584                if (rc6_mode & INTEL_RC6pp_ENABLE)
5585                        rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5586        }
5587
5588        intel_print_rc6_info(dev_priv, rc6_mask);
5589
5590        I915_WRITE(GEN6_RC_CONTROL,
5591                   rc6_mask |
5592                   GEN6_RC_CTL_EI_MODE(1) |
5593                   GEN6_RC_CTL_HW_ENABLE);
5594
5595        /* Power down if completely idle for over 50ms */
5596        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5597        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5598
5599        ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5600        if (ret)
5601                DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5602
5603        reset_rps(dev_priv, gen6_set_rps);
5604
5605        rc6vids = 0;
5606        ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5607        if (IS_GEN6(dev_priv) && ret) {
5608                DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5609        } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5610                DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5611                          GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5612                rc6vids &= 0xffff00;
5613                rc6vids |= GEN6_ENCODE_RC6_VID(450);
5614                ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5615                if (ret)
5616                        DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5617        }
5618
5619        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5620}
5621
5622static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5623{
5624        int min_freq = 15;
5625        unsigned int gpu_freq;
5626        unsigned int max_ia_freq, min_ring_freq;
5627        unsigned int max_gpu_freq, min_gpu_freq;
5628        int scaling_factor = 180;
5629        struct cpufreq_policy *policy;
5630
5631        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5632
5633        policy = cpufreq_cpu_get(0);
5634        if (policy) {
5635                max_ia_freq = policy->cpuinfo.max_freq;
5636                cpufreq_cpu_put(policy);
5637        } else {
5638                /*
5639                 * Default to measured freq if none found, PCU will ensure we
5640                 * don't go over
5641                 */
5642                max_ia_freq = tsc_khz;
5643        }
5644
5645        /* Convert from kHz to MHz */
5646        max_ia_freq /= 1000;
5647
5648        min_ring_freq = I915_READ(DCLK) & 0xf;
5649        /* convert DDR frequency from units of 266.6MHz to bandwidth */
5650        min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5651
5652        if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5653                /* Convert GT frequency to 50 HZ units */
5654                min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5655                max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5656        } else {
5657                min_gpu_freq = dev_priv->rps.min_freq;
5658                max_gpu_freq = dev_priv->rps.max_freq;
5659        }
5660
5661        /*
5662         * For each potential GPU frequency, load a ring frequency we'd like
5663         * to use for memory access.  We do this by specifying the IA frequency
5664         * the PCU should use as a reference to determine the ring frequency.
5665         */
5666        for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5667                int diff = max_gpu_freq - gpu_freq;
5668                unsigned int ia_freq = 0, ring_freq = 0;
5669
5670                if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5671                        /*
5672                         * ring_freq = 2 * GT. ring_freq is in 100MHz units
5673                         * No floor required for ring frequency on SKL.
5674                         */
5675                        ring_freq = gpu_freq;
5676                } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5677                        /* max(2 * GT, DDR). NB: GT is 50MHz units */
5678                        ring_freq = max(min_ring_freq, gpu_freq);
5679                } else if (IS_HASWELL(dev_priv)) {
5680                        ring_freq = mult_frac(gpu_freq, 5, 4);
5681                        ring_freq = max(min_ring_freq, ring_freq);
5682                        /* leave ia_freq as the default, chosen by cpufreq */
5683                } else {
5684                        /* On older processors, there is no separate ring
5685                         * clock domain, so in order to boost the bandwidth
5686                         * of the ring, we need to upclock the CPU (ia_freq).
5687                         *
5688                         * For GPU frequencies less than 750MHz,
5689                         * just use the lowest ring freq.
5690                         */
5691                        if (gpu_freq < min_freq)
5692                                ia_freq = 800;
5693                        else
5694                                ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5695                        ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5696                }
5697
5698                sandybridge_pcode_write(dev_priv,
5699                                        GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5700                                        ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5701                                        ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5702                                        gpu_freq);
5703        }
5704}
5705
5706static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5707{
5708        u32 val, rp0;
5709
5710        val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5711
5712        switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5713        case 8:
5714                /* (2 * 4) config */
5715                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5716                break;
5717        case 12:
5718                /* (2 * 6) config */
5719                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5720                break;
5721        case 16:
5722                /* (2 * 8) config */
5723        default:
5724                /* Setting (2 * 8) Min RP0 for any other combination */
5725                rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5726                break;
5727        }
5728
5729        rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5730
5731        return rp0;
5732}
5733
5734static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5735{
5736        u32 val, rpe;
5737
5738        val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5739        rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5740
5741        return rpe;
5742}
5743
5744static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5745{
5746        u32 val, rp1;
5747
5748        val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5749        rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5750
5751        return rp1;
5752}
5753
5754static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5755{
5756        u32 val, rp1;
5757
5758        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5759
5760        rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5761
5762        return rp1;
5763}
5764
5765static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5766{
5767        u32 val, rp0;
5768
5769        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5770
5771        rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5772        /* Clamp to max */
5773        rp0 = min_t(u32, rp0, 0xea);
5774
5775        return rp0;
5776}
5777
5778static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5779{
5780        u32 val, rpe;
5781
5782        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5783        rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5784        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5785        rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5786
5787        return rpe;
5788}
5789
5790static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5791{
5792        u32 val;
5793
5794        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5795        /*
5796         * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5797         * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5798         * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5799         * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5800         * to make sure it matches what Punit accepts.
5801         */
5802        return max_t(u32, val, 0xc0);
5803}
5804
5805/* Check that the pctx buffer wasn't move under us. */
5806static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5807{
5808        unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5809
5810        WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5811                             dev_priv->vlv_pctx->stolen->start);
5812}
5813
5814
5815/* Check that the pcbr address is not empty. */
5816static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5817{
5818        unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5819
5820        WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5821}
5822
5823static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5824{
5825        struct i915_ggtt *ggtt = &dev_priv->ggtt;
5826        unsigned long pctx_paddr, paddr;
5827        u32 pcbr;
5828        int pctx_size = 32*1024;
5829
5830        pcbr = I915_READ(VLV_PCBR);
5831        if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5832                DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5833                paddr = (dev_priv->mm.stolen_base +
5834                         (ggtt->stolen_size - pctx_size));
5835
5836                pctx_paddr = (paddr & (~4095));
5837                I915_WRITE(VLV_PCBR, pctx_paddr);
5838        }
5839
5840        DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5841}
5842
5843static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5844{
5845        struct drm_i915_gem_object *pctx;
5846        unsigned long pctx_paddr;
5847        u32 pcbr;
5848        int pctx_size = 24*1024;
5849
5850        pcbr = I915_READ(VLV_PCBR);
5851        if (pcbr) {
5852                /* BIOS set it up already, grab the pre-alloc'd space */
5853                int pcbr_offset;
5854
5855                pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5856                pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5857                                                                      pcbr_offset,
5858                                                                      I915_GTT_OFFSET_NONE,
5859                                                                      pctx_size);
5860                goto out;
5861        }
5862
5863        DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5864
5865        /*
5866         * From the Gunit register HAS:
5867         * The Gfx driver is expected to program this register and ensure
5868         * proper allocation within Gfx stolen memory.  For example, this
5869         * register should be programmed such than the PCBR range does not
5870         * overlap with other ranges, such as the frame buffer, protected
5871         * memory, or any other relevant ranges.
5872         */
5873        pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5874        if (!pctx) {
5875                DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5876                goto out;
5877        }
5878
5879        pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5880        I915_WRITE(VLV_PCBR, pctx_paddr);
5881
5882out:
5883        DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5884        dev_priv->vlv_pctx = pctx;
5885}
5886
5887static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5888{
5889        if (WARN_ON(!dev_priv->vlv_pctx))
5890                return;
5891
5892        i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5893        dev_priv->vlv_pctx = NULL;
5894}
5895
5896static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5897{
5898        dev_priv->rps.gpll_ref_freq =
5899                vlv_get_cck_clock(dev_priv, "GPLL ref",
5900                                  CCK_GPLL_CLOCK_CONTROL,
5901                                  dev_priv->czclk_freq);
5902
5903        DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5904                         dev_priv->rps.gpll_ref_freq);
5905}
5906
5907static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5908{
5909        u32 val;
5910
5911        valleyview_setup_pctx(dev_priv);
5912
5913        vlv_init_gpll_ref_freq(dev_priv);
5914
5915        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5916        switch ((val >> 6) & 3) {
5917        case 0:
5918        case 1:
5919                dev_priv->mem_freq = 800;
5920                break;
5921        case 2:
5922                dev_priv->mem_freq = 1066;
5923                break;
5924        case 3:
5925                dev_priv->mem_freq = 1333;
5926                break;
5927        }
5928        DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5929
5930        dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5931        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5932        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5933                         intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5934                         dev_priv->rps.max_freq);
5935
5936        dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5937        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5938                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5939                         dev_priv->rps.efficient_freq);
5940
5941        dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5942        DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5943                         intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5944                         dev_priv->rps.rp1_freq);
5945
5946        dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5947        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5948                         intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5949                         dev_priv->rps.min_freq);
5950}
5951
5952static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5953{
5954        u32 val;
5955
5956        cherryview_setup_pctx(dev_priv);
5957
5958        vlv_init_gpll_ref_freq(dev_priv);
5959
5960        mutex_lock(&dev_priv->sb_lock);
5961        val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5962        mutex_unlock(&dev_priv->sb_lock);
5963
5964        switch ((val >> 2) & 0x7) {
5965        case 3:
5966                dev_priv->mem_freq = 2000;
5967                break;
5968        default:
5969                dev_priv->mem_freq = 1600;
5970                break;
5971        }
5972        DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5973
5974        dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5975        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5976        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5977                         intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5978                         dev_priv->rps.max_freq);
5979
5980        dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5981        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5982                         intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5983                         dev_priv->rps.efficient_freq);
5984
5985        dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5986        DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5987                         intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5988                         dev_priv->rps.rp1_freq);
5989
5990        /* PUnit validated range is only [RPe, RP0] */
5991        dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5992        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5993                         intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5994                         dev_priv->rps.min_freq);
5995
5996        WARN_ONCE((dev_priv->rps.max_freq |
5997                   dev_priv->rps.efficient_freq |
5998                   dev_priv->rps.rp1_freq |
5999                   dev_priv->rps.min_freq) & 1,
6000                  "Odd GPU freq values\n");
6001}
6002
6003static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6004{
6005        valleyview_cleanup_pctx(dev_priv);
6006}
6007
6008static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
6009{
6010        struct intel_engine_cs *engine;
6011        u32 gtfifodbg, val, rc6_mode = 0, pcbr;
6012
6013        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6014
6015        gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6016                                             GT_FIFO_FREE_ENTRIES_CHV);
6017        if (gtfifodbg) {
6018                DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6019                                 gtfifodbg);
6020                I915_WRITE(GTFIFODBG, gtfifodbg);
6021        }
6022
6023        cherryview_check_pctx(dev_priv);
6024
6025        /* 1a & 1b: Get forcewake during program sequence. Although the driver
6026         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6027        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6028
6029        /*  Disable RC states. */
6030        I915_WRITE(GEN6_RC_CONTROL, 0);
6031
6032        /* 2a: Program RC6 thresholds.*/
6033        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6034        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6035        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6036
6037        for_each_engine(engine, dev_priv)
6038                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6039        I915_WRITE(GEN6_RC_SLEEP, 0);
6040
6041        /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6042        I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6043
6044        /* allows RC6 residency counter to work */
6045        I915_WRITE(VLV_COUNTER_CONTROL,
6046                   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6047                                      VLV_MEDIA_RC6_COUNT_EN |
6048                                      VLV_RENDER_RC6_COUNT_EN));
6049
6050        /* For now we assume BIOS is allocating and populating the PCBR  */
6051        pcbr = I915_READ(VLV_PCBR);
6052
6053        /* 3: Enable RC6 */
6054        if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6055            (pcbr >> VLV_PCBR_ADDR_SHIFT))
6056                rc6_mode = GEN7_RC_CTL_TO_MODE;
6057
6058        I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6059
6060        /* 4 Program defaults and thresholds for RPS*/
6061        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6062        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6063        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6064        I915_WRITE(GEN6_RP_UP_EI, 66000);
6065        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6066
6067        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6068
6069        /* 5: Enable RPS */
6070        I915_WRITE(GEN6_RP_CONTROL,
6071                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
6072                   GEN6_RP_MEDIA_IS_GFX |
6073                   GEN6_RP_ENABLE |
6074                   GEN6_RP_UP_BUSY_AVG |
6075                   GEN6_RP_DOWN_IDLE_AVG);
6076
6077        /* Setting Fixed Bias */
6078        val = VLV_OVERRIDE_EN |
6079                  VLV_SOC_TDP_EN |
6080                  CHV_BIAS_CPU_50_SOC_50;
6081        vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6082
6083        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6084
6085        /* RPS code assumes GPLL is used */
6086        WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6087
6088        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6089        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6090
6091        reset_rps(dev_priv, valleyview_set_rps);
6092
6093        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6094}
6095
6096static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6097{
6098        struct intel_engine_cs *engine;
6099        u32 gtfifodbg, val, rc6_mode = 0;
6100
6101        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6102
6103        valleyview_check_pctx(dev_priv);
6104
6105        gtfifodbg = I915_READ(GTFIFODBG);
6106        if (gtfifodbg) {
6107                DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6108                                 gtfifodbg);
6109                I915_WRITE(GTFIFODBG, gtfifodbg);
6110        }
6111
6112        /* If VLV, Forcewake all wells, else re-direct to regular path */
6113        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6114
6115        /*  Disable RC states. */
6116        I915_WRITE(GEN6_RC_CONTROL, 0);
6117
6118        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6119        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6120        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6121        I915_WRITE(GEN6_RP_UP_EI, 66000);
6122        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6123
6124        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6125
6126        I915_WRITE(GEN6_RP_CONTROL,
6127                   GEN6_RP_MEDIA_TURBO |
6128                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
6129                   GEN6_RP_MEDIA_IS_GFX |
6130                   GEN6_RP_ENABLE |
6131                   GEN6_RP_UP_BUSY_AVG |
6132                   GEN6_RP_DOWN_IDLE_CONT);
6133
6134        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6135        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6136        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6137
6138        for_each_engine(engine, dev_priv)
6139                I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6140
6141        I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6142
6143        /* allows RC6 residency counter to work */
6144        I915_WRITE(VLV_COUNTER_CONTROL,
6145                   _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6146                                      VLV_RENDER_RC0_COUNT_EN |
6147                                      VLV_MEDIA_RC6_COUNT_EN |
6148                                      VLV_RENDER_RC6_COUNT_EN));
6149
6150        if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6151                rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6152
6153        intel_print_rc6_info(dev_priv, rc6_mode);
6154
6155        I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6156
6157        /* Setting Fixed Bias */
6158        val = VLV_OVERRIDE_EN |
6159                  VLV_SOC_TDP_EN |
6160                  VLV_BIAS_CPU_125_SOC_875;
6161        vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6162
6163        val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6164
6165        /* RPS code assumes GPLL is used */
6166        WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6167
6168        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6169        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6170
6171        reset_rps(dev_priv, valleyview_set_rps);
6172
6173        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6174}
6175
6176static unsigned long intel_pxfreq(u32 vidfreq)
6177{
6178        unsigned long freq;
6179        int div = (vidfreq & 0x3f0000) >> 16;
6180        int post = (vidfreq & 0x3000) >> 12;
6181        int pre = (vidfreq & 0x7);
6182
6183        if (!pre)
6184                return 0;
6185
6186        freq = ((div * 133333) / ((1<<post) * pre));
6187
6188        return freq;
6189}
6190
6191static const struct cparams {
6192        u16 i;
6193        u16 t;
6194        u16 m;
6195        u16 c;
6196} cparams[] = {
6197        { 1, 1333, 301, 28664 },
6198        { 1, 1066, 294, 24460 },
6199        { 1, 800, 294, 25192 },
6200        { 0, 1333, 276, 27605 },
6201        { 0, 1066, 276, 27605 },
6202        { 0, 800, 231, 23784 },
6203};
6204
6205static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6206{
6207        u64 total_count, diff, ret;
6208        u32 count1, count2, count3, m = 0, c = 0;
6209        unsigned long now = jiffies_to_msecs(jiffies), diff1;
6210        int i;
6211
6212        assert_spin_locked(&mchdev_lock);
6213
6214        diff1 = now - dev_priv->ips.last_time1;
6215
6216        /* Prevent division-by-zero if we are asking too fast.
6217         * Also, we don't get interesting results if we are polling
6218         * faster than once in 10ms, so just return the saved value
6219         * in such cases.
6220         */
6221        if (diff1 <= 10)
6222                return dev_priv->ips.chipset_power;
6223
6224        count1 = I915_READ(DMIEC);
6225        count2 = I915_READ(DDREC);
6226        count3 = I915_READ(CSIEC);
6227
6228        total_count = count1 + count2 + count3;
6229
6230        /* FIXME: handle per-counter overflow */
6231        if (total_count < dev_priv->ips.last_count1) {
6232                diff = ~0UL - dev_priv->ips.last_count1;
6233                diff += total_count;
6234        } else {
6235                diff = total_count - dev_priv->ips.last_count1;
6236        }
6237
6238        for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6239                if (cparams[i].i == dev_priv->ips.c_m &&
6240                    cparams[i].t == dev_priv->ips.r_t) {
6241                        m = cparams[i].m;
6242                        c = cparams[i].c;
6243                        break;
6244                }
6245        }
6246
6247        diff = div_u64(diff, diff1);
6248        ret = ((m * diff) + c);
6249        ret = div_u64(ret, 10);
6250
6251        dev_priv->ips.last_count1 = total_count;
6252        dev_priv->ips.last_time1 = now;
6253
6254        dev_priv->ips.chipset_power = ret;
6255
6256        return ret;
6257}
6258
6259unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6260{
6261        unsigned long val;
6262
6263        if (INTEL_INFO(dev_priv)->gen != 5)
6264                return 0;
6265
6266        spin_lock_irq(&mchdev_lock);
6267
6268        val = __i915_chipset_val(dev_priv);
6269
6270        spin_unlock_irq(&mchdev_lock);
6271
6272        return val;
6273}
6274
6275unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6276{
6277        unsigned long m, x, b;
6278        u32 tsfs;
6279
6280        tsfs = I915_READ(TSFS);
6281
6282        m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6283        x = I915_READ8(TR1);
6284
6285        b = tsfs & TSFS_INTR_MASK;
6286
6287        return ((m * x) / 127) - b;
6288}
6289
6290static int _pxvid_to_vd(u8 pxvid)
6291{
6292        if (pxvid == 0)
6293                return 0;
6294
6295        if (pxvid >= 8 && pxvid < 31)
6296                pxvid = 31;
6297
6298        return (pxvid + 2) * 125;
6299}
6300
6301static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6302{
6303        const int vd = _pxvid_to_vd(pxvid);
6304        const int vm = vd - 1125;
6305
6306        if (INTEL_INFO(dev_priv)->is_mobile)
6307                return vm > 0 ? vm : 0;
6308
6309        return vd;
6310}
6311
6312static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6313{
6314        u64 now, diff, diffms;
6315        u32 count;
6316
6317        assert_spin_locked(&mchdev_lock);
6318
6319        now = ktime_get_raw_ns();
6320        diffms = now - dev_priv->ips.last_time2;
6321        do_div(diffms, NSEC_PER_MSEC);
6322
6323        /* Don't divide by 0 */
6324        if (!diffms)
6325                return;
6326
6327        count = I915_READ(GFXEC);
6328
6329        if (count < dev_priv->ips.last_count2) {
6330                diff = ~0UL - dev_priv->ips.last_count2;
6331                diff += count;
6332        } else {
6333                diff = count - dev_priv->ips.last_count2;
6334        }
6335
6336        dev_priv->ips.last_count2 = count;
6337        dev_priv->ips.last_time2 = now;
6338
6339        /* More magic constants... */
6340        diff = diff * 1181;
6341        diff = div_u64(diff, diffms * 10);
6342        dev_priv->ips.gfx_power = diff;
6343}
6344
6345void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6346{
6347        if (INTEL_INFO(dev_priv)->gen != 5)
6348                return;
6349
6350        spin_lock_irq(&mchdev_lock);
6351
6352        __i915_update_gfx_val(dev_priv);
6353
6354        spin_unlock_irq(&mchdev_lock);
6355}
6356
6357static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6358{
6359        unsigned long t, corr, state1, corr2, state2;
6360        u32 pxvid, ext_v;
6361
6362        assert_spin_locked(&mchdev_lock);
6363
6364        pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6365        pxvid = (pxvid >> 24) & 0x7f;
6366        ext_v = pvid_to_extvid(dev_priv, pxvid);
6367
6368        state1 = ext_v;
6369
6370        t = i915_mch_val(dev_priv);
6371
6372        /* Revel in the empirically derived constants */
6373
6374        /* Correction factor in 1/100000 units */
6375        if (t > 80)
6376                corr = ((t * 2349) + 135940);
6377        else if (t >= 50)
6378                corr = ((t * 964) + 29317);
6379        else /* < 50 */
6380                corr = ((t * 301) + 1004);
6381
6382        corr = corr * ((150142 * state1) / 10000 - 78642);
6383        corr /= 100000;
6384        corr2 = (corr * dev_priv->ips.corr);
6385
6386        state2 = (corr2 * state1) / 10000;
6387        state2 /= 100; /* convert to mW */
6388
6389        __i915_update_gfx_val(dev_priv);
6390
6391        return dev_priv->ips.gfx_power + state2;
6392}
6393
6394unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6395{
6396        unsigned long val;
6397
6398        if (INTEL_INFO(dev_priv)->gen != 5)
6399                return 0;
6400
6401        spin_lock_irq(&mchdev_lock);
6402
6403        val = __i915_gfx_val(dev_priv);
6404
6405        spin_unlock_irq(&mchdev_lock);
6406
6407        return val;
6408}
6409
6410/**
6411 * i915_read_mch_val - return value for IPS use
6412 *
6413 * Calculate and return a value for the IPS driver to use when deciding whether
6414 * we have thermal and power headroom to increase CPU or GPU power budget.
6415 */
6416unsigned long i915_read_mch_val(void)
6417{
6418        struct drm_i915_private *dev_priv;
6419        unsigned long chipset_val, graphics_val, ret = 0;
6420
6421        spin_lock_irq(&mchdev_lock);
6422        if (!i915_mch_dev)
6423                goto out_unlock;
6424        dev_priv = i915_mch_dev;
6425
6426        chipset_val = __i915_chipset_val(dev_priv);
6427        graphics_val = __i915_gfx_val(dev_priv);
6428
6429        ret = chipset_val + graphics_val;
6430
6431out_unlock:
6432        spin_unlock_irq(&mchdev_lock);
6433
6434        return ret;
6435}
6436EXPORT_SYMBOL_GPL(i915_read_mch_val);
6437
6438/**
6439 * i915_gpu_raise - raise GPU frequency limit
6440 *
6441 * Raise the limit; IPS indicates we have thermal headroom.
6442 */
6443bool i915_gpu_raise(void)
6444{
6445        struct drm_i915_private *dev_priv;
6446        bool ret = true;
6447
6448        spin_lock_irq(&mchdev_lock);
6449        if (!i915_mch_dev) {
6450                ret = false;
6451                goto out_unlock;
6452        }
6453        dev_priv = i915_mch_dev;
6454
6455        if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6456                dev_priv->ips.max_delay--;
6457
6458out_unlock:
6459        spin_unlock_irq(&mchdev_lock);
6460
6461        return ret;
6462}
6463EXPORT_SYMBOL_GPL(i915_gpu_raise);
6464
6465/**
6466 * i915_gpu_lower - lower GPU frequency limit
6467 *
6468 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6469 * frequency maximum.
6470 */
6471bool i915_gpu_lower(void)
6472{
6473        struct drm_i915_private *dev_priv;
6474        bool ret = true;
6475
6476        spin_lock_irq(&mchdev_lock);
6477        if (!i915_mch_dev) {
6478                ret = false;
6479                goto out_unlock;
6480        }
6481        dev_priv = i915_mch_dev;
6482
6483        if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6484                dev_priv->ips.max_delay++;
6485
6486out_unlock:
6487        spin_unlock_irq(&mchdev_lock);
6488
6489        return ret;
6490}
6491EXPORT_SYMBOL_GPL(i915_gpu_lower);
6492
6493/**
6494 * i915_gpu_busy - indicate GPU business to IPS
6495 *
6496 * Tell the IPS driver whether or not the GPU is busy.
6497 */
6498bool i915_gpu_busy(void)
6499{
6500        bool ret = false;
6501
6502        spin_lock_irq(&mchdev_lock);
6503        if (i915_mch_dev)
6504                ret = i915_mch_dev->gt.awake;
6505        spin_unlock_irq(&mchdev_lock);
6506
6507        return ret;
6508}
6509EXPORT_SYMBOL_GPL(i915_gpu_busy);
6510
6511/**
6512 * i915_gpu_turbo_disable - disable graphics turbo
6513 *
6514 * Disable graphics turbo by resetting the max frequency and setting the
6515 * current frequency to the default.
6516 */
6517bool i915_gpu_turbo_disable(void)
6518{
6519        struct drm_i915_private *dev_priv;
6520        bool ret = true;
6521
6522        spin_lock_irq(&mchdev_lock);
6523        if (!i915_mch_dev) {
6524                ret = false;
6525                goto out_unlock;
6526        }
6527        dev_priv = i915_mch_dev;
6528
6529        dev_priv->ips.max_delay = dev_priv->ips.fstart;
6530
6531        if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6532                ret = false;
6533
6534out_unlock:
6535        spin_unlock_irq(&mchdev_lock);
6536
6537        return ret;
6538}
6539EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6540
6541/**
6542 * Tells the intel_ips driver that the i915 driver is now loaded, if
6543 * IPS got loaded first.
6544 *
6545 * This awkward dance is so that neither module has to depend on the
6546 * other in order for IPS to do the appropriate communication of
6547 * GPU turbo limits to i915.
6548 */
6549static void
6550ips_ping_for_i915_load(void)
6551{
6552        void (*link)(void);
6553
6554        link = symbol_get(ips_link_to_i915_driver);
6555        if (link) {
6556                link();
6557                symbol_put(ips_link_to_i915_driver);
6558        }
6559}
6560
6561void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6562{
6563        /* We only register the i915 ips part with intel-ips once everything is
6564         * set up, to avoid intel-ips sneaking in and reading bogus values. */
6565        spin_lock_irq(&mchdev_lock);
6566        i915_mch_dev = dev_priv;
6567        spin_unlock_irq(&mchdev_lock);
6568
6569        ips_ping_for_i915_load();
6570}
6571
6572void intel_gpu_ips_teardown(void)
6573{
6574        spin_lock_irq(&mchdev_lock);
6575        i915_mch_dev = NULL;
6576        spin_unlock_irq(&mchdev_lock);
6577}
6578
6579static void intel_init_emon(struct drm_i915_private *dev_priv)
6580{
6581        u32 lcfuse;
6582        u8 pxw[16];
6583        int i;
6584
6585        /* Disable to program */
6586        I915_WRITE(ECR, 0);
6587        POSTING_READ(ECR);
6588
6589        /* Program energy weights for various events */
6590        I915_WRITE(SDEW, 0x15040d00);
6591        I915_WRITE(CSIEW0, 0x007f0000);
6592        I915_WRITE(CSIEW1, 0x1e220004);
6593        I915_WRITE(CSIEW2, 0x04000004);
6594
6595        for (i = 0; i < 5; i++)
6596                I915_WRITE(PEW(i), 0);
6597        for (i = 0; i < 3; i++)
6598                I915_WRITE(DEW(i), 0);
6599
6600        /* Program P-state weights to account for frequency power adjustment */
6601        for (i = 0; i < 16; i++) {
6602                u32 pxvidfreq = I915_READ(PXVFREQ(i));
6603                unsigned long freq = intel_pxfreq(pxvidfreq);
6604                unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6605                        PXVFREQ_PX_SHIFT;
6606                unsigned long val;
6607
6608                val = vid * vid;
6609                val *= (freq / 1000);
6610                val *= 255;
6611                val /= (127*127*900);
6612                if (val > 0xff)
6613                        DRM_ERROR("bad pxval: %ld\n", val);
6614                pxw[i] = val;
6615        }
6616        /* Render standby states get 0 weight */
6617        pxw[14] = 0;
6618        pxw[15] = 0;
6619
6620        for (i = 0; i < 4; i++) {
6621                u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6622                        (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6623                I915_WRITE(PXW(i), val);
6624        }
6625
6626        /* Adjust magic regs to magic values (more experimental results) */
6627        I915_WRITE(OGW0, 0);
6628        I915_WRITE(OGW1, 0);
6629        I915_WRITE(EG0, 0x00007f00);
6630        I915_WRITE(EG1, 0x0000000e);
6631        I915_WRITE(EG2, 0x000e0000);
6632        I915_WRITE(EG3, 0x68000300);
6633        I915_WRITE(EG4, 0x42000000);
6634        I915_WRITE(EG5, 0x00140031);
6635        I915_WRITE(EG6, 0);
6636        I915_WRITE(EG7, 0);
6637
6638        for (i = 0; i < 8; i++)
6639                I915_WRITE(PXWL(i), 0);
6640
6641        /* Enable PMON + select events */
6642        I915_WRITE(ECR, 0x80000019);
6643
6644        lcfuse = I915_READ(LCFUSE02);
6645
6646        dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6647}
6648
6649void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6650{
6651        /*
6652         * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6653         * requirement.
6654         */
6655        if (!i915.enable_rc6) {
6656                DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6657                intel_runtime_pm_get(dev_priv);
6658        }
6659
6660        mutex_lock(&dev_priv->drm.struct_mutex);
6661        mutex_lock(&dev_priv->rps.hw_lock);
6662
6663        /* Initialize RPS limits (for userspace) */
6664        if (IS_CHERRYVIEW(dev_priv))
6665                cherryview_init_gt_powersave(dev_priv);
6666        else if (IS_VALLEYVIEW(dev_priv))
6667                valleyview_init_gt_powersave(dev_priv);
6668        else if (INTEL_GEN(dev_priv) >= 6)
6669                gen6_init_rps_frequencies(dev_priv);
6670
6671        /* Derive initial user preferences/limits from the hardware limits */
6672        dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6673        dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6674
6675        dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6676        dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6677
6678        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6679                dev_priv->rps.min_freq_softlimit =
6680                        max_t(int,
6681                              dev_priv->rps.efficient_freq,
6682                              intel_freq_opcode(dev_priv, 450));
6683
6684        /* After setting max-softlimit, find the overclock max freq */
6685        if (IS_GEN6(dev_priv) ||
6686            IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6687                u32 params = 0;
6688
6689                sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6690                if (params & BIT(31)) { /* OC supported */
6691                        DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6692                                         (dev_priv->rps.max_freq & 0xff) * 50,
6693                                         (params & 0xff) * 50);
6694                        dev_priv->rps.max_freq = params & 0xff;
6695                }
6696        }
6697
6698        /* Finally allow us to boost to max by default */
6699        dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6700
6701        mutex_unlock(&dev_priv->rps.hw_lock);
6702        mutex_unlock(&dev_priv->drm.struct_mutex);
6703
6704        intel_autoenable_gt_powersave(dev_priv);
6705}
6706
6707void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6708{
6709        if (IS_VALLEYVIEW(dev_priv))
6710                valleyview_cleanup_gt_powersave(dev_priv);
6711
6712        if (!i915.enable_rc6)
6713                intel_runtime_pm_put(dev_priv);
6714}
6715
6716/**
6717 * intel_suspend_gt_powersave - suspend PM work and helper threads
6718 * @dev_priv: i915 device
6719 *
6720 * We don't want to disable RC6 or other features here, we just want
6721 * to make sure any work we've queued has finished and won't bother
6722 * us while we're suspended.
6723 */
6724void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6725{
6726        if (INTEL_GEN(dev_priv) < 6)
6727                return;
6728
6729        if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6730                intel_runtime_pm_put(dev_priv);
6731
6732        /* gen6_rps_idle() will be called later to disable interrupts */
6733}
6734
6735void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6736{
6737        dev_priv->rps.enabled = true; /* force disabling */
6738        intel_disable_gt_powersave(dev_priv);
6739
6740        gen6_reset_rps_interrupts(dev_priv);
6741}
6742
6743void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6744{
6745        if (!READ_ONCE(dev_priv->rps.enabled))
6746                return;
6747
6748        mutex_lock(&dev_priv->rps.hw_lock);
6749
6750        if (INTEL_GEN(dev_priv) >= 9) {
6751                gen9_disable_rc6(dev_priv);
6752                gen9_disable_rps(dev_priv);
6753        } else if (IS_CHERRYVIEW(dev_priv)) {
6754                cherryview_disable_rps(dev_priv);
6755        } else if (IS_VALLEYVIEW(dev_priv)) {
6756                valleyview_disable_rps(dev_priv);
6757        } else if (INTEL_GEN(dev_priv) >= 6) {
6758                gen6_disable_rps(dev_priv);
6759        }  else if (IS_IRONLAKE_M(dev_priv)) {
6760                ironlake_disable_drps(dev_priv);
6761        }
6762
6763        dev_priv->rps.enabled = false;
6764        mutex_unlock(&dev_priv->rps.hw_lock);
6765}
6766
6767void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6768{
6769        /* We shouldn't be disabling as we submit, so this should be less
6770         * racy than it appears!
6771         */
6772        if (READ_ONCE(dev_priv->rps.enabled))
6773                return;
6774
6775        /* Powersaving is controlled by the host when inside a VM */
6776        if (intel_vgpu_active(dev_priv))
6777                return;
6778
6779        mutex_lock(&dev_priv->rps.hw_lock);
6780
6781        if (IS_CHERRYVIEW(dev_priv)) {
6782                cherryview_enable_rps(dev_priv);
6783        } else if (IS_VALLEYVIEW(dev_priv)) {
6784                valleyview_enable_rps(dev_priv);
6785        } else if (INTEL_GEN(dev_priv) >= 9) {
6786                gen9_enable_rc6(dev_priv);
6787                gen9_enable_rps(dev_priv);
6788                if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6789                        gen6_update_ring_freq(dev_priv);
6790        } else if (IS_BROADWELL(dev_priv)) {
6791                gen8_enable_rps(dev_priv);
6792                gen6_update_ring_freq(dev_priv);
6793        } else if (INTEL_GEN(dev_priv) >= 6) {
6794                gen6_enable_rps(dev_priv);
6795                gen6_update_ring_freq(dev_priv);
6796        } else if (IS_IRONLAKE_M(dev_priv)) {
6797                ironlake_enable_drps(dev_priv);
6798                intel_init_emon(dev_priv);
6799        }
6800
6801        WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6802        WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6803
6804        WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6805        WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6806
6807        dev_priv->rps.enabled = true;
6808        mutex_unlock(&dev_priv->rps.hw_lock);
6809}
6810
6811static void __intel_autoenable_gt_powersave(struct work_struct *work)
6812{
6813        struct drm_i915_private *dev_priv =
6814                container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6815        struct intel_engine_cs *rcs;
6816        struct drm_i915_gem_request *req;
6817
6818        if (READ_ONCE(dev_priv->rps.enabled))
6819                goto out;
6820
6821        rcs = &dev_priv->engine[RCS];
6822        if (rcs->last_context)
6823                goto out;
6824
6825        if (!rcs->init_context)
6826                goto out;
6827
6828        mutex_lock(&dev_priv->drm.struct_mutex);
6829
6830        req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6831        if (IS_ERR(req))
6832                goto unlock;
6833
6834        if (!i915.enable_execlists && i915_switch_context(req) == 0)
6835                rcs->init_context(req);
6836
6837        /* Mark the device busy, calling intel_enable_gt_powersave() */
6838        i915_add_request_no_flush(req);
6839
6840unlock:
6841        mutex_unlock(&dev_priv->drm.struct_mutex);
6842out:
6843        intel_runtime_pm_put(dev_priv);
6844}
6845
6846void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6847{
6848        if (READ_ONCE(dev_priv->rps.enabled))
6849                return;
6850
6851        if (IS_IRONLAKE_M(dev_priv)) {
6852                ironlake_enable_drps(dev_priv);
6853                intel_init_emon(dev_priv);
6854        } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6855                /*
6856                 * PCU communication is slow and this doesn't need to be
6857                 * done at any specific time, so do this out of our fast path
6858                 * to make resume and init faster.
6859                 *
6860                 * We depend on the HW RC6 power context save/restore
6861                 * mechanism when entering D3 through runtime PM suspend. So
6862                 * disable RPM until RPS/RC6 is properly setup. We can only
6863                 * get here via the driver load/system resume/runtime resume
6864                 * paths, so the _noresume version is enough (and in case of
6865                 * runtime resume it's necessary).
6866                 */
6867                if (queue_delayed_work(dev_priv->wq,
6868                                       &dev_priv->rps.autoenable_work,
6869                                       round_jiffies_up_relative(HZ)))
6870                        intel_runtime_pm_get_noresume(dev_priv);
6871        }
6872}
6873
6874static void ibx_init_clock_gating(struct drm_device *dev)
6875{
6876        struct drm_i915_private *dev_priv = to_i915(dev);
6877
6878        /*
6879         * On Ibex Peak and Cougar Point, we need to disable clock
6880         * gating for the panel power sequencer or it will fail to
6881         * start up when no ports are active.
6882         */
6883        I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6884}
6885
6886static void g4x_disable_trickle_feed(struct drm_device *dev)
6887{
6888        struct drm_i915_private *dev_priv = to_i915(dev);
6889        enum pipe pipe;
6890
6891        for_each_pipe(dev_priv, pipe) {
6892                I915_WRITE(DSPCNTR(pipe),
6893                           I915_READ(DSPCNTR(pipe)) |
6894                           DISPPLANE_TRICKLE_FEED_DISABLE);
6895
6896                I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6897                POSTING_READ(DSPSURF(pipe));
6898        }
6899}
6900
6901static void ilk_init_lp_watermarks(struct drm_device *dev)
6902{
6903        struct drm_i915_private *dev_priv = to_i915(dev);
6904
6905        I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6906        I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6907        I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6908
6909        /*
6910         * Don't touch WM1S_LP_EN here.
6911         * Doing so could cause underruns.
6912         */
6913}
6914
6915static void ironlake_init_clock_gating(struct drm_device *dev)
6916{
6917        struct drm_i915_private *dev_priv = to_i915(dev);
6918        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6919
6920        /*
6921         * Required for FBC
6922         * WaFbcDisableDpfcClockGating:ilk
6923         */
6924        dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6925                   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6926                   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6927
6928        I915_WRITE(PCH_3DCGDIS0,
6929                   MARIUNIT_CLOCK_GATE_DISABLE |
6930                   SVSMUNIT_CLOCK_GATE_DISABLE);
6931        I915_WRITE(PCH_3DCGDIS1,
6932                   VFMUNIT_CLOCK_GATE_DISABLE);
6933
6934        /*
6935         * According to the spec the following bits should be set in
6936         * order to enable memory self-refresh
6937         * The bit 22/21 of 0x42004
6938         * The bit 5 of 0x42020
6939         * The bit 15 of 0x45000
6940         */
6941        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6942                   (I915_READ(ILK_DISPLAY_CHICKEN2) |
6943                    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6944        dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6945        I915_WRITE(DISP_ARB_CTL,
6946                   (I915_READ(DISP_ARB_CTL) |
6947                    DISP_FBC_WM_DIS));
6948
6949        ilk_init_lp_watermarks(dev);
6950
6951        /*
6952         * Based on the document from hardware guys the following bits
6953         * should be set unconditionally in order to enable FBC.
6954         * The bit 22 of 0x42000
6955         * The bit 22 of 0x42004
6956         * The bit 7,8,9 of 0x42020.
6957         */
6958        if (IS_IRONLAKE_M(dev)) {
6959                /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6960                I915_WRITE(ILK_DISPLAY_CHICKEN1,
6961                           I915_READ(ILK_DISPLAY_CHICKEN1) |
6962                           ILK_FBCQ_DIS);
6963                I915_WRITE(ILK_DISPLAY_CHICKEN2,
6964                           I915_READ(ILK_DISPLAY_CHICKEN2) |
6965                           ILK_DPARB_GATE);
6966        }
6967
6968        I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6969
6970        I915_WRITE(ILK_DISPLAY_CHICKEN2,
6971                   I915_READ(ILK_DISPLAY_CHICKEN2) |
6972                   ILK_ELPIN_409_SELECT);
6973        I915_WRITE(_3D_CHICKEN2,
6974                   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6975                   _3D_CHICKEN2_WM_READ_PIPELINED);
6976
6977        /* WaDisableRenderCachePipelinedFlush:ilk */
6978        I915_WRITE(CACHE_MODE_0,
6979                   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6980
6981        /* WaDisable_RenderCache_OperationalFlush:ilk */
6982        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6983
6984        g4x_disable_trickle_feed(dev);
6985
6986        ibx_init_clock_gating(dev);
6987}
6988
6989static void cpt_init_clock_gating(struct drm_device *dev)
6990{
6991        struct drm_i915_private *dev_priv = to_i915(dev);
6992        int pipe;
6993        uint32_t val;
6994
6995        /*
6996         * On Ibex Peak and Cougar Point, we need to disable clock
6997         * gating for the panel power sequencer or it will fail to
6998         * start up when no ports are active.
6999         */
7000        I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
7001                   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
7002                   PCH_CPUNIT_CLOCK_GATE_DISABLE);
7003        I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7004                   DPLS_EDP_PPS_FIX_DIS);
7005        /* The below fixes the weird display corruption, a few pixels shifted
7006         * downward, on (only) LVDS of some HP laptops with IVY.
7007         */
7008        for_each_pipe(dev_priv, pipe) {
7009                val = I915_READ(TRANS_CHICKEN2(pipe));
7010                val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7011                val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7012                if (dev_priv->vbt.fdi_rx_polarity_inverted)
7013                        val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7014                val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7015                val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7016                val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7017                I915_WRITE(TRANS_CHICKEN2(pipe), val);
7018        }
7019        /* WADP0ClockGatingDisable */
7020        for_each_pipe(dev_priv, pipe) {
7021                I915_WRITE(TRANS_CHICKEN1(pipe),
7022                           TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7023        }
7024}
7025
7026static void gen6_check_mch_setup(struct drm_device *dev)
7027{
7028        struct drm_i915_private *dev_priv = to_i915(dev);
7029        uint32_t tmp;
7030
7031        tmp = I915_READ(MCH_SSKPD);
7032        if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7033                DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7034                              tmp);
7035}
7036
7037static void gen6_init_clock_gating(struct drm_device *dev)
7038{
7039        struct drm_i915_private *dev_priv = to_i915(dev);
7040        uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7041
7042        I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7043
7044        I915_WRITE(ILK_DISPLAY_CHICKEN2,
7045                   I915_READ(ILK_DISPLAY_CHICKEN2) |
7046                   ILK_ELPIN_409_SELECT);
7047
7048        /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7049        I915_WRITE(_3D_CHICKEN,
7050                   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7051
7052        /* WaDisable_RenderCache_OperationalFlush:snb */
7053        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7054
7055        /*
7056         * BSpec recoomends 8x4 when MSAA is used,
7057         * however in practice 16x4 seems fastest.
7058         *
7059         * Note that PS/WM thread counts depend on the WIZ hashing
7060         * disable bit, which we don't touch here, but it's good
7061         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7062         */
7063        I915_WRITE(GEN6_GT_MODE,
7064                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7065
7066        ilk_init_lp_watermarks(dev);
7067
7068        I915_WRITE(CACHE_MODE_0,
7069                   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7070
7071        I915_WRITE(GEN6_UCGCTL1,
7072                   I915_READ(GEN6_UCGCTL1) |
7073                   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7074                   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7075
7076        /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7077         * gating disable must be set.  Failure to set it results in
7078         * flickering pixels due to Z write ordering failures after
7079         * some amount of runtime in the Mesa "fire" demo, and Unigine
7080         * Sanctuary and Tropics, and apparently anything else with
7081         * alpha test or pixel discard.
7082         *
7083         * According to the spec, bit 11 (RCCUNIT) must also be set,
7084         * but we didn't debug actual testcases to find it out.
7085         *
7086         * WaDisableRCCUnitClockGating:snb
7087         * WaDisableRCPBUnitClockGating:snb
7088         */
7089        I915_WRITE(GEN6_UCGCTL2,
7090                   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7091                   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7092
7093        /* WaStripsFansDisableFastClipPerformanceFix:snb */
7094        I915_WRITE(_3D_CHICKEN3,
7095                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7096
7097        /*
7098         * Bspec says:
7099         * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7100         * 3DSTATE_SF number of SF output attributes is more than 16."
7101         */
7102        I915_WRITE(_3D_CHICKEN3,
7103                   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7104
7105        /*
7106         * According to the spec the following bits should be
7107         * set in order to enable memory self-refresh and fbc:
7108         * The bit21 and bit22 of 0x42000
7109         * The bit21 and bit22 of 0x42004
7110         * The bit5 and bit7 of 0x42020
7111         * The bit14 of 0x70180
7112         * The bit14 of 0x71180
7113         *
7114         * WaFbcAsynchFlipDisableFbcQueue:snb
7115         */
7116        I915_WRITE(ILK_DISPLAY_CHICKEN1,
7117                   I915_READ(ILK_DISPLAY_CHICKEN1) |
7118                   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7119        I915_WRITE(ILK_DISPLAY_CHICKEN2,
7120                   I915_READ(ILK_DISPLAY_CHICKEN2) |
7121                   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7122        I915_WRITE(ILK_DSPCLK_GATE_D,
7123                   I915_READ(ILK_DSPCLK_GATE_D) |
7124                   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7125                   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7126
7127        g4x_disable_trickle_feed(dev);
7128
7129        cpt_init_clock_gating(dev);
7130
7131        gen6_check_mch_setup(dev);
7132}
7133
7134static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7135{
7136        uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7137
7138        /*
7139         * WaVSThreadDispatchOverride:ivb,vlv
7140         *
7141         * This actually overrides the dispatch
7142         * mode for all thread types.
7143         */
7144        reg &= ~GEN7_FF_SCHED_MASK;
7145        reg |= GEN7_FF_TS_SCHED_HW;
7146        reg |= GEN7_FF_VS_SCHED_HW;
7147        reg |= GEN7_FF_DS_SCHED_HW;
7148
7149        I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7150}
7151
7152static void lpt_init_clock_gating(struct drm_device *dev)
7153{
7154        struct drm_i915_private *dev_priv = to_i915(dev);
7155
7156        /*
7157         * TODO: this bit should only be enabled when really needed, then
7158         * disabled when not needed anymore in order to save power.
7159         */
7160        if (HAS_PCH_LPT_LP(dev))
7161                I915_WRITE(SOUTH_DSPCLK_GATE_D,
7162                           I915_READ(SOUTH_DSPCLK_GATE_D) |
7163                           PCH_LP_PARTITION_LEVEL_DISABLE);
7164
7165        /* WADPOClockGatingDisable:hsw */
7166        I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7167                   I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7168                   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7169}
7170
7171static void lpt_suspend_hw(struct drm_device *dev)
7172{
7173        struct drm_i915_private *dev_priv = to_i915(dev);
7174
7175        if (HAS_PCH_LPT_LP(dev)) {
7176                uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7177
7178                val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7179                I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7180        }
7181}
7182
7183static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7184                                   int general_prio_credits,
7185                                   int high_prio_credits)
7186{
7187        u32 misccpctl;
7188
7189        /* WaTempDisableDOPClkGating:bdw */
7190        misccpctl = I915_READ(GEN7_MISCCPCTL);
7191        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7192
7193        I915_WRITE(GEN8_L3SQCREG1,
7194                   L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7195                   L3_HIGH_PRIO_CREDITS(high_prio_credits));
7196
7197        /*
7198         * Wait at least 100 clocks before re-enabling clock gating.
7199         * See the definition of L3SQCREG1 in BSpec.
7200         */
7201        POSTING_READ(GEN8_L3SQCREG1);
7202        udelay(1);
7203        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7204}
7205
7206static void kabylake_init_clock_gating(struct drm_device *dev)
7207{
7208        struct drm_i915_private *dev_priv = dev->dev_private;
7209
7210        gen9_init_clock_gating(dev);
7211
7212        /* WaDisableSDEUnitClockGating:kbl */
7213        if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7214                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7215                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7216
7217        /* WaDisableGamClockGating:kbl */
7218        if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7219                I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7220                           GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7221
7222        /* WaFbcNukeOnHostModify:kbl */
7223        I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7224                   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7225}
7226
7227static void skylake_init_clock_gating(struct drm_device *dev)
7228{
7229        struct drm_i915_private *dev_priv = dev->dev_private;
7230
7231        gen9_init_clock_gating(dev);
7232
7233        /* WAC6entrylatency:skl */
7234        I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7235                   FBC_LLC_FULLY_OPEN);
7236
7237        /* WaFbcNukeOnHostModify:skl */
7238        I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7239                   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7240}
7241
7242static void broadwell_init_clock_gating(struct drm_device *dev)
7243{
7244        struct drm_i915_private *dev_priv = to_i915(dev);
7245        enum pipe pipe;
7246
7247        ilk_init_lp_watermarks(dev);
7248
7249        /* WaSwitchSolVfFArbitrationPriority:bdw */
7250        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7251
7252        /* WaPsrDPAMaskVBlankInSRD:bdw */
7253        I915_WRITE(CHICKEN_PAR1_1,
7254                   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7255
7256        /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7257        for_each_pipe(dev_priv, pipe) {
7258                I915_WRITE(CHICKEN_PIPESL_1(pipe),
7259                           I915_READ(CHICKEN_PIPESL_1(pipe)) |
7260                           BDW_DPRS_MASK_VBLANK_SRD);
7261        }
7262
7263        /* WaVSRefCountFullforceMissDisable:bdw */
7264        /* WaDSRefCountFullforceMissDisable:bdw */
7265        I915_WRITE(GEN7_FF_THREAD_MODE,
7266                   I915_READ(GEN7_FF_THREAD_MODE) &
7267                   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7268
7269        I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7270                   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7271
7272        /* WaDisableSDEUnitClockGating:bdw */
7273        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7274                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7275
7276        /* WaProgramL3SqcReg1Default:bdw */
7277        gen8_set_l3sqc_credits(dev_priv, 30, 2);
7278
7279        /*
7280         * WaGttCachingOffByDefault:bdw
7281         * GTT cache may not work with big pages, so if those
7282         * are ever enabled GTT cache may need to be disabled.
7283         */
7284        I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7285
7286        /* WaKVMNotificationOnConfigChange:bdw */
7287        I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7288                   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7289
7290        lpt_init_clock_gating(dev);
7291}
7292
7293static void haswell_init_clock_gating(struct drm_device *dev)
7294{
7295        struct drm_i915_private *dev_priv = to_i915(dev);
7296
7297        ilk_init_lp_watermarks(dev);
7298
7299        /* L3 caching of data atomics doesn't work -- disable it. */
7300        I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7301        I915_WRITE(HSW_ROW_CHICKEN3,
7302                   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7303
7304        /* This is required by WaCatErrorRejectionIssue:hsw */
7305        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7306                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7307                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7308
7309        /* WaVSRefCountFullforceMissDisable:hsw */
7310        I915_WRITE(GEN7_FF_THREAD_MODE,
7311                   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7312
7313        /* WaDisable_RenderCache_OperationalFlush:hsw */
7314        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7315
7316        /* enable HiZ Raw Stall Optimization */
7317        I915_WRITE(CACHE_MODE_0_GEN7,
7318                   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7319
7320        /* WaDisable4x2SubspanOptimization:hsw */
7321        I915_WRITE(CACHE_MODE_1,
7322                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7323
7324        /*
7325         * BSpec recommends 8x4 when MSAA is used,
7326         * however in practice 16x4 seems fastest.
7327         *
7328         * Note that PS/WM thread counts depend on the WIZ hashing
7329         * disable bit, which we don't touch here, but it's good
7330         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7331         */
7332        I915_WRITE(GEN7_GT_MODE,
7333                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7334
7335        /* WaSampleCChickenBitEnable:hsw */
7336        I915_WRITE(HALF_SLICE_CHICKEN3,
7337                   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7338
7339        /* WaSwitchSolVfFArbitrationPriority:hsw */
7340        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7341
7342        /* WaRsPkgCStateDisplayPMReq:hsw */
7343        I915_WRITE(CHICKEN_PAR1_1,
7344                   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7345
7346        lpt_init_clock_gating(dev);
7347}
7348
7349static void ivybridge_init_clock_gating(struct drm_device *dev)
7350{
7351        struct drm_i915_private *dev_priv = to_i915(dev);
7352        uint32_t snpcr;
7353
7354        ilk_init_lp_watermarks(dev);
7355
7356        I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7357
7358        /* WaDisableEarlyCull:ivb */
7359        I915_WRITE(_3D_CHICKEN3,
7360                   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7361
7362        /* WaDisableBackToBackFlipFix:ivb */
7363        I915_WRITE(IVB_CHICKEN3,
7364                   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7365                   CHICKEN3_DGMG_DONE_FIX_DISABLE);
7366
7367        /* WaDisablePSDDualDispatchEnable:ivb */
7368        if (IS_IVB_GT1(dev))
7369                I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7370                           _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7371
7372        /* WaDisable_RenderCache_OperationalFlush:ivb */
7373        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7374
7375        /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7376        I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7377                   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7378
7379        /* WaApplyL3ControlAndL3ChickenMode:ivb */
7380        I915_WRITE(GEN7_L3CNTLREG1,
7381                        GEN7_WA_FOR_GEN7_L3_CONTROL);
7382        I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7383                   GEN7_WA_L3_CHICKEN_MODE);
7384        if (IS_IVB_GT1(dev))
7385                I915_WRITE(GEN7_ROW_CHICKEN2,
7386                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7387        else {
7388                /* must write both registers */
7389                I915_WRITE(GEN7_ROW_CHICKEN2,
7390                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7391                I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7392                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7393        }
7394
7395        /* WaForceL3Serialization:ivb */
7396        I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7397                   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7398
7399        /*
7400         * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7401         * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7402         */
7403        I915_WRITE(GEN6_UCGCTL2,
7404                   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7405
7406        /* This is required by WaCatErrorRejectionIssue:ivb */
7407        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7408                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7409                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7410
7411        g4x_disable_trickle_feed(dev);
7412
7413        gen7_setup_fixed_func_scheduler(dev_priv);
7414
7415        if (0) { /* causes HiZ corruption on ivb:gt1 */
7416                /* enable HiZ Raw Stall Optimization */
7417                I915_WRITE(CACHE_MODE_0_GEN7,
7418                           _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7419        }
7420
7421        /* WaDisable4x2SubspanOptimization:ivb */
7422        I915_WRITE(CACHE_MODE_1,
7423                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7424
7425        /*
7426         * BSpec recommends 8x4 when MSAA is used,
7427         * however in practice 16x4 seems fastest.
7428         *
7429         * Note that PS/WM thread counts depend on the WIZ hashing
7430         * disable bit, which we don't touch here, but it's good
7431         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7432         */
7433        I915_WRITE(GEN7_GT_MODE,
7434                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7435
7436        snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7437        snpcr &= ~GEN6_MBC_SNPCR_MASK;
7438        snpcr |= GEN6_MBC_SNPCR_MED;
7439        I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7440
7441        if (!HAS_PCH_NOP(dev))
7442                cpt_init_clock_gating(dev);
7443
7444        gen6_check_mch_setup(dev);
7445}
7446
7447static void valleyview_init_clock_gating(struct drm_device *dev)
7448{
7449        struct drm_i915_private *dev_priv = to_i915(dev);
7450
7451        /* WaDisableEarlyCull:vlv */
7452        I915_WRITE(_3D_CHICKEN3,
7453                   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7454
7455        /* WaDisableBackToBackFlipFix:vlv */
7456        I915_WRITE(IVB_CHICKEN3,
7457                   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7458                   CHICKEN3_DGMG_DONE_FIX_DISABLE);
7459
7460        /* WaPsdDispatchEnable:vlv */
7461        /* WaDisablePSDDualDispatchEnable:vlv */
7462        I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7463                   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7464                                      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7465
7466        /* WaDisable_RenderCache_OperationalFlush:vlv */
7467        I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7468
7469        /* WaForceL3Serialization:vlv */
7470        I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7471                   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7472
7473        /* WaDisableDopClockGating:vlv */
7474        I915_WRITE(GEN7_ROW_CHICKEN2,
7475                   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7476
7477        /* This is required by WaCatErrorRejectionIssue:vlv */
7478        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7479                   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7480                   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7481
7482        gen7_setup_fixed_func_scheduler(dev_priv);
7483
7484        /*
7485         * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7486         * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7487         */
7488        I915_WRITE(GEN6_UCGCTL2,
7489                   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7490
7491        /* WaDisableL3Bank2xClockGate:vlv
7492         * Disabling L3 clock gating- MMIO 940c[25] = 1
7493         * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7494        I915_WRITE(GEN7_UCGCTL4,
7495                   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7496
7497        /*
7498         * BSpec says this must be set, even though
7499         * WaDisable4x2SubspanOptimization isn't listed for VLV.
7500         */
7501        I915_WRITE(CACHE_MODE_1,
7502                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7503
7504        /*
7505         * BSpec recommends 8x4 when MSAA is used,
7506         * however in practice 16x4 seems fastest.
7507         *
7508         * Note that PS/WM thread counts depend on the WIZ hashing
7509         * disable bit, which we don't touch here, but it's good
7510         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7511         */
7512        I915_WRITE(GEN7_GT_MODE,
7513                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7514
7515        /*
7516         * WaIncreaseL3CreditsForVLVB0:vlv
7517         * This is the hardware default actually.
7518         */
7519        I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7520
7521        /*
7522         * WaDisableVLVClockGating_VBIIssue:vlv
7523         * Disable clock gating on th GCFG unit to prevent a delay
7524         * in the reporting of vblank events.
7525         */
7526        I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7527}
7528
7529static void cherryview_init_clock_gating(struct drm_device *dev)
7530{
7531        struct drm_i915_private *dev_priv = to_i915(dev);
7532
7533        /* WaVSRefCountFullforceMissDisable:chv */
7534        /* WaDSRefCountFullforceMissDisable:chv */
7535        I915_WRITE(GEN7_FF_THREAD_MODE,
7536                   I915_READ(GEN7_FF_THREAD_MODE) &
7537                   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7538
7539        /* WaDisableSemaphoreAndSyncFlipWait:chv */
7540        I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7541                   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7542
7543        /* WaDisableCSUnitClockGating:chv */
7544        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7545                   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7546
7547        /* WaDisableSDEUnitClockGating:chv */
7548        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7549                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7550
7551        /*
7552         * WaProgramL3SqcReg1Default:chv
7553         * See gfxspecs/Related Documents/Performance Guide/
7554         * LSQC Setting Recommendations.
7555         */
7556        gen8_set_l3sqc_credits(dev_priv, 38, 2);
7557
7558        /*
7559         * GTT cache may not work with big pages, so if those
7560         * are ever enabled GTT cache may need to be disabled.
7561         */
7562        I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7563}
7564
7565static void g4x_init_clock_gating(struct drm_device *dev)
7566{
7567        struct drm_i915_private *dev_priv = to_i915(dev);
7568        uint32_t dspclk_gate;
7569
7570        I915_WRITE(RENCLK_GATE_D1, 0);
7571        I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7572                   GS_UNIT_CLOCK_GATE_DISABLE |
7573                   CL_UNIT_CLOCK_GATE_DISABLE);
7574        I915_WRITE(RAMCLK_GATE_D, 0);
7575        dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7576                OVRUNIT_CLOCK_GATE_DISABLE |
7577                OVCUNIT_CLOCK_GATE_DISABLE;
7578        if (IS_GM45(dev))
7579                dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7580        I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7581
7582        /* WaDisableRenderCachePipelinedFlush */
7583        I915_WRITE(CACHE_MODE_0,
7584                   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7585
7586        /* WaDisable_RenderCache_OperationalFlush:g4x */
7587        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7588
7589        g4x_disable_trickle_feed(dev);
7590}
7591
7592static void crestline_init_clock_gating(struct drm_device *dev)
7593{
7594        struct drm_i915_private *dev_priv = to_i915(dev);
7595
7596        I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7597        I915_WRITE(RENCLK_GATE_D2, 0);
7598        I915_WRITE(DSPCLK_GATE_D, 0);
7599        I915_WRITE(RAMCLK_GATE_D, 0);
7600        I915_WRITE16(DEUC, 0);
7601        I915_WRITE(MI_ARB_STATE,
7602                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7603
7604        /* WaDisable_RenderCache_OperationalFlush:gen4 */
7605        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7606}
7607
7608static void broadwater_init_clock_gating(struct drm_device *dev)
7609{
7610        struct drm_i915_private *dev_priv = to_i915(dev);
7611
7612        I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7613                   I965_RCC_CLOCK_GATE_DISABLE |
7614                   I965_RCPB_CLOCK_GATE_DISABLE |
7615                   I965_ISC_CLOCK_GATE_DISABLE |
7616                   I965_FBC_CLOCK_GATE_DISABLE);
7617        I915_WRITE(RENCLK_GATE_D2, 0);
7618        I915_WRITE(MI_ARB_STATE,
7619                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7620
7621        /* WaDisable_RenderCache_OperationalFlush:gen4 */
7622        I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7623}
7624
7625static void gen3_init_clock_gating(struct drm_device *dev)
7626{
7627        struct drm_i915_private *dev_priv = to_i915(dev);
7628        u32 dstate = I915_READ(D_STATE);
7629
7630        dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7631                DSTATE_DOT_CLOCK_GATING;
7632        I915_WRITE(D_STATE, dstate);
7633
7634        if (IS_PINEVIEW(dev))
7635                I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7636
7637        /* IIR "flip pending" means done if this bit is set */
7638        I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7639
7640        /* interrupts should cause a wake up from C3 */
7641        I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7642
7643        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7644        I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7645
7646        I915_WRITE(MI_ARB_STATE,
7647                   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7648}
7649
7650static void i85x_init_clock_gating(struct drm_device *dev)
7651{
7652        struct drm_i915_private *dev_priv = to_i915(dev);
7653
7654        I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7655
7656        /* interrupts should cause a wake up from C3 */
7657        I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7658                   _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7659
7660        I915_WRITE(MEM_MODE,
7661                   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7662}
7663
7664static void i830_init_clock_gating(struct drm_device *dev)
7665{
7666        struct drm_i915_private *dev_priv = to_i915(dev);
7667
7668        I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7669
7670        I915_WRITE(MEM_MODE,
7671                   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7672                   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7673}
7674
7675void intel_init_clock_gating(struct drm_device *dev)
7676{
7677        struct drm_i915_private *dev_priv = to_i915(dev);
7678
7679        dev_priv->display.init_clock_gating(dev);
7680}
7681
7682void intel_suspend_hw(struct drm_device *dev)
7683{
7684        if (HAS_PCH_LPT(dev))
7685                lpt_suspend_hw(dev);
7686}
7687
7688static void nop_init_clock_gating(struct drm_device *dev)
7689{
7690        DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7691}
7692
7693/**
7694 * intel_init_clock_gating_hooks - setup the clock gating hooks
7695 * @dev_priv: device private
7696 *
7697 * Setup the hooks that configure which clocks of a given platform can be
7698 * gated and also apply various GT and display specific workarounds for these
7699 * platforms. Note that some GT specific workarounds are applied separately
7700 * when GPU contexts or batchbuffers start their execution.
7701 */
7702void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7703{
7704        if (IS_SKYLAKE(dev_priv))
7705                dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7706        else if (IS_KABYLAKE(dev_priv))
7707                dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7708        else if (IS_BROXTON(dev_priv))
7709                dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7710        else if (IS_BROADWELL(dev_priv))
7711                dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7712        else if (IS_CHERRYVIEW(dev_priv))
7713                dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7714        else if (IS_HASWELL(dev_priv))
7715                dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7716        else if (IS_IVYBRIDGE(dev_priv))
7717                dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7718        else if (IS_VALLEYVIEW(dev_priv))
7719                dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7720        else if (IS_GEN6(dev_priv))
7721                dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7722        else if (IS_GEN5(dev_priv))
7723                dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7724        else if (IS_G4X(dev_priv))
7725                dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7726        else if (IS_CRESTLINE(dev_priv))
7727                dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7728        else if (IS_BROADWATER(dev_priv))
7729                dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7730        else if (IS_GEN3(dev_priv))
7731                dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7732        else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7733                dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7734        else if (IS_GEN2(dev_priv))
7735                dev_priv->display.init_clock_gating = i830_init_clock_gating;
7736        else {
7737                MISSING_CASE(INTEL_DEVID(dev_priv));
7738                dev_priv->display.init_clock_gating = nop_init_clock_gating;
7739        }
7740}
7741
7742/* Set up chip specific power management-related functions */
7743void intel_init_pm(struct drm_device *dev)
7744{
7745        struct drm_i915_private *dev_priv = to_i915(dev);
7746
7747        intel_fbc_init(dev_priv);
7748
7749        /* For cxsr */
7750        if (IS_PINEVIEW(dev))
7751                i915_pineview_get_mem_freq(dev);
7752        else if (IS_GEN5(dev))
7753                i915_ironlake_get_mem_freq(dev);
7754
7755        /* For FIFO watermark updates */
7756        if (INTEL_INFO(dev)->gen >= 9) {
7757                skl_setup_wm_latency(dev);
7758                dev_priv->display.update_wm = skl_update_wm;
7759                dev_priv->display.compute_global_watermarks = skl_compute_wm;
7760        } else if (HAS_PCH_SPLIT(dev)) {
7761                ilk_setup_wm_latency(dev);
7762
7763                if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7764                     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7765                    (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7766                     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7767                        dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7768                        dev_priv->display.compute_intermediate_wm =
7769                                ilk_compute_intermediate_wm;
7770                        dev_priv->display.initial_watermarks =
7771                                ilk_initial_watermarks;
7772                        dev_priv->display.optimize_watermarks =
7773                                ilk_optimize_watermarks;
7774                } else {
7775                        DRM_DEBUG_KMS("Failed to read display plane latency. "
7776                                      "Disable CxSR\n");
7777                }
7778        } else if (IS_CHERRYVIEW(dev)) {
7779                vlv_setup_wm_latency(dev);
7780                dev_priv->display.update_wm = vlv_update_wm;
7781        } else if (IS_VALLEYVIEW(dev)) {
7782                vlv_setup_wm_latency(dev);
7783                dev_priv->display.update_wm = vlv_update_wm;
7784        } else if (IS_PINEVIEW(dev)) {
7785                if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7786                                            dev_priv->is_ddr3,
7787                                            dev_priv->fsb_freq,
7788                                            dev_priv->mem_freq)) {
7789                        DRM_INFO("failed to find known CxSR latency "
7790                                 "(found ddr%s fsb freq %d, mem freq %d), "
7791                                 "disabling CxSR\n",
7792                                 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7793                                 dev_priv->fsb_freq, dev_priv->mem_freq);
7794                        /* Disable CxSR and never update its watermark again */
7795                        intel_set_memory_cxsr(dev_priv, false);
7796                        dev_priv->display.update_wm = NULL;
7797                } else
7798                        dev_priv->display.update_wm = pineview_update_wm;
7799        } else if (IS_G4X(dev)) {
7800                dev_priv->display.update_wm = g4x_update_wm;
7801        } else if (IS_GEN4(dev)) {
7802                dev_priv->display.update_wm = i965_update_wm;
7803        } else if (IS_GEN3(dev)) {
7804                dev_priv->display.update_wm = i9xx_update_wm;
7805                dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7806        } else if (IS_GEN2(dev)) {
7807                if (INTEL_INFO(dev)->num_pipes == 1) {
7808                        dev_priv->display.update_wm = i845_update_wm;
7809                        dev_priv->display.get_fifo_size = i845_get_fifo_size;
7810                } else {
7811                        dev_priv->display.update_wm = i9xx_update_wm;
7812                        dev_priv->display.get_fifo_size = i830_get_fifo_size;
7813                }
7814        } else {
7815                DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7816        }
7817}
7818
7819static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7820{
7821        uint32_t flags =
7822                I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7823
7824        switch (flags) {
7825        case GEN6_PCODE_SUCCESS:
7826                return 0;
7827        case GEN6_PCODE_UNIMPLEMENTED_CMD:
7828        case GEN6_PCODE_ILLEGAL_CMD:
7829                return -ENXIO;
7830        case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7831        case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7832                return -EOVERFLOW;
7833        case GEN6_PCODE_TIMEOUT:
7834                return -ETIMEDOUT;
7835        default:
7836                MISSING_CASE(flags)
7837                return 0;
7838        }
7839}
7840
7841static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7842{
7843        uint32_t flags =
7844                I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7845
7846        switch (flags) {
7847        case GEN6_PCODE_SUCCESS:
7848                return 0;
7849        case GEN6_PCODE_ILLEGAL_CMD:
7850                return -ENXIO;
7851        case GEN7_PCODE_TIMEOUT:
7852                return -ETIMEDOUT;
7853        case GEN7_PCODE_ILLEGAL_DATA:
7854                return -EINVAL;
7855        case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7856                return -EOVERFLOW;
7857        default:
7858                MISSING_CASE(flags);
7859                return 0;
7860        }
7861}
7862
7863int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7864{
7865        int status;
7866
7867        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7868
7869        /* GEN6_PCODE_* are outside of the forcewake domain, we can
7870         * use te fw I915_READ variants to reduce the amount of work
7871         * required when reading/writing.
7872         */
7873
7874        if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7875                DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7876                return -EAGAIN;
7877        }
7878
7879        I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7880        I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7881        I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7882
7883        if (intel_wait_for_register_fw(dev_priv,
7884                                       GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7885                                       500)) {
7886                DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7887                return -ETIMEDOUT;
7888        }
7889
7890        *val = I915_READ_FW(GEN6_PCODE_DATA);
7891        I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7892
7893        if (INTEL_GEN(dev_priv) > 6)
7894                status = gen7_check_mailbox_status(dev_priv);
7895        else
7896                status = gen6_check_mailbox_status(dev_priv);
7897
7898        if (status) {
7899                DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7900                                 status);
7901                return status;
7902        }
7903
7904        return 0;
7905}
7906
7907int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7908                            u32 mbox, u32 val)
7909{
7910        int status;
7911
7912        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7913
7914        /* GEN6_PCODE_* are outside of the forcewake domain, we can
7915         * use te fw I915_READ variants to reduce the amount of work
7916         * required when reading/writing.
7917         */
7918
7919        if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7920                DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7921                return -EAGAIN;
7922        }
7923
7924        I915_WRITE_FW(GEN6_PCODE_DATA, val);
7925        I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7926
7927        if (intel_wait_for_register_fw(dev_priv,
7928                                       GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7929                                       500)) {
7930                DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7931                return -ETIMEDOUT;
7932        }
7933
7934        I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7935
7936        if (INTEL_GEN(dev_priv) > 6)
7937                status = gen7_check_mailbox_status(dev_priv);
7938        else
7939                status = gen6_check_mailbox_status(dev_priv);
7940
7941        if (status) {
7942                DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7943                                 status);
7944                return status;
7945        }
7946
7947        return 0;
7948}
7949
7950static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7951                                  u32 request, u32 reply_mask, u32 reply,
7952                                  u32 *status)
7953{
7954        u32 val = request;
7955
7956        *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7957
7958        return *status || ((val & reply_mask) == reply);
7959}
7960
7961/**
7962 * skl_pcode_request - send PCODE request until acknowledgment
7963 * @dev_priv: device private
7964 * @mbox: PCODE mailbox ID the request is targeted for
7965 * @request: request ID
7966 * @reply_mask: mask used to check for request acknowledgment
7967 * @reply: value used to check for request acknowledgment
7968 * @timeout_base_ms: timeout for polling with preemption enabled
7969 *
7970 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7971 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7972 * The request is acknowledged once the PCODE reply dword equals @reply after
7973 * applying @reply_mask. Polling is first attempted with preemption enabled
7974 * for @timeout_base_ms and if this times out for another 50 ms with
7975 * preemption disabled.
7976 *
7977 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7978 * other error as reported by PCODE.
7979 */
7980int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7981                      u32 reply_mask, u32 reply, int timeout_base_ms)
7982{
7983        u32 status;
7984        int ret;
7985
7986        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7987
7988#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7989                                   &status)
7990
7991        /*
7992         * Prime the PCODE by doing a request first. Normally it guarantees
7993         * that a subsequent request, at most @timeout_base_ms later, succeeds.
7994         * _wait_for() doesn't guarantee when its passed condition is evaluated
7995         * first, so send the first request explicitly.
7996         */
7997        if (COND) {
7998                ret = 0;
7999                goto out;
8000        }
8001        ret = _wait_for(COND, timeout_base_ms * 1000, 10);
8002        if (!ret)
8003                goto out;
8004
8005        /*
8006         * The above can time out if the number of requests was low (2 in the
8007         * worst case) _and_ PCODE was busy for some reason even after a
8008         * (queued) request and @timeout_base_ms delay. As a workaround retry
8009         * the poll with preemption disabled to maximize the number of
8010         * requests. Increase the timeout from @timeout_base_ms to 50ms to
8011         * account for interrupts that could reduce the number of these
8012         * requests, and for any quirks of the PCODE firmware that delays
8013         * the request completion.
8014         */
8015        DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
8016        WARN_ON_ONCE(timeout_base_ms > 3);
8017        preempt_disable();
8018        ret = wait_for_atomic(COND, 50);
8019        preempt_enable();
8020
8021out:
8022        return ret ? ret : status;
8023#undef COND
8024}
8025
8026static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
8027{
8028        /*
8029         * N = val - 0xb7
8030         * Slow = Fast = GPLL ref * N
8031         */
8032        return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
8033}
8034
8035static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
8036{
8037        return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
8038}
8039
8040static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
8041{
8042        /*
8043         * N = val / 2
8044         * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
8045         */
8046        return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
8047}
8048
8049static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
8050{
8051        /* CHV needs even values */
8052        return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
8053}
8054
8055int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
8056{
8057        if (IS_GEN9(dev_priv))
8058                return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8059                                         GEN9_FREQ_SCALER);
8060        else if (IS_CHERRYVIEW(dev_priv))
8061                return chv_gpu_freq(dev_priv, val);
8062        else if (IS_VALLEYVIEW(dev_priv))
8063                return byt_gpu_freq(dev_priv, val);
8064        else
8065                return val * GT_FREQUENCY_MULTIPLIER;
8066}
8067
8068int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8069{
8070        if (IS_GEN9(dev_priv))
8071                return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8072                                         GT_FREQUENCY_MULTIPLIER);
8073        else if (IS_CHERRYVIEW(dev_priv))
8074                return chv_freq_opcode(dev_priv, val);
8075        else if (IS_VALLEYVIEW(dev_priv))
8076                return byt_freq_opcode(dev_priv, val);
8077        else
8078                return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8079}
8080
8081struct request_boost {
8082        struct work_struct work;
8083        struct drm_i915_gem_request *req;
8084};
8085
8086static void __intel_rps_boost_work(struct work_struct *work)
8087{
8088        struct request_boost *boost = container_of(work, struct request_boost, work);
8089        struct drm_i915_gem_request *req = boost->req;
8090
8091        if (!i915_gem_request_completed(req))
8092                gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8093
8094        i915_gem_request_put(req);
8095        kfree(boost);
8096}
8097
8098void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8099{
8100        struct request_boost *boost;
8101
8102        if (req == NULL || INTEL_GEN(req->i915) < 6)
8103                return;
8104
8105        if (i915_gem_request_completed(req))
8106                return;
8107
8108        boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8109        if (boost == NULL)
8110                return;
8111
8112        boost->req = i915_gem_request_get(req);
8113
8114        INIT_WORK(&boost->work, __intel_rps_boost_work);
8115        queue_work(req->i915->wq, &boost->work);
8116}
8117
8118void intel_pm_setup(struct drm_device *dev)
8119{
8120        struct drm_i915_private *dev_priv = to_i915(dev);
8121
8122        mutex_init(&dev_priv->rps.hw_lock);
8123        spin_lock_init(&dev_priv->rps.client_lock);
8124
8125        INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8126                          __intel_autoenable_gt_powersave);
8127        INIT_LIST_HEAD(&dev_priv->rps.clients);
8128
8129        dev_priv->pm.suspended = false;
8130        atomic_set(&dev_priv->pm.wakeref_count, 0);
8131        atomic_set(&dev_priv->pm.atomic_seq, 0);
8132}
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