source: src/linux/universal/linux-4.9/drivers/misc/cxl/pci.c @ 31662

Last change on this file since 31662 was 31662, checked in by brainslayer, 4 months ago

use new squashfs in all kernels

File size: 56.0 KB
Line 
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci_regs.h>
11#include <linux/pci_ids.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
22#include <asm/pnv-pci.h>
23#include <asm/io.h>
24#include <asm/reg.h>
25
26#include "cxl.h"
27#include <misc/cxl.h>
28
29
30#define CXL_PCI_VSEC_ID 0x1280
31#define CXL_VSEC_MIN_SIZE 0x80
32
33#define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
34        {                                                       \
35                pci_read_config_word(dev, vsec + 0x6, dest);    \
36                *dest >>= 4;                                    \
37        }
38#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39        pci_read_config_byte(dev, vsec + 0x8, dest)
40
41#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42        pci_read_config_byte(dev, vsec + 0x9, dest)
43#define CXL_STATUS_SECOND_PORT  0x80
44#define CXL_STATUS_MSI_X_FULL   0x40
45#define CXL_STATUS_MSI_X_SINGLE 0x20
46#define CXL_STATUS_FLASH_RW     0x08
47#define CXL_STATUS_FLASH_RO     0x04
48#define CXL_STATUS_LOADABLE_AFU 0x02
49#define CXL_STATUS_LOADABLE_PSL 0x01
50/* If we see these features we won't try to use the card */
51#define CXL_UNSUPPORTED_FEATURES \
52        (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55        pci_read_config_byte(dev, vsec + 0xa, dest)
56#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57        pci_write_config_byte(dev, vsec + 0xa, val)
58#define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59        pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60#define CXL_VSEC_PROTOCOL_MASK   0xe0
61#define CXL_VSEC_PROTOCOL_1024TB 0x80
62#define CXL_VSEC_PROTOCOL_512TB  0x40
63#define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8 uses this */
64#define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67        pci_read_config_word(dev, vsec + 0xc, dest)
68#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69        pci_read_config_byte(dev, vsec + 0xe, dest)
70#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71        pci_read_config_byte(dev, vsec + 0xf, dest)
72#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73        pci_read_config_word(dev, vsec + 0x10, dest)
74
75#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76        pci_read_config_byte(dev, vsec + 0x13, dest)
77#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78        pci_write_config_byte(dev, vsec + 0x13, val)
79#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84        pci_read_config_dword(dev, vsec + 0x20, dest)
85#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86        pci_read_config_dword(dev, vsec + 0x24, dest)
87#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88        pci_read_config_dword(dev, vsec + 0x28, dest)
89#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90        pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93/* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95#define AFUD_READ(afu, off)             in_be64(afu->native->afu_desc_mmio + off)
96#define AFUD_READ_LE(afu, off)          in_le64(afu->native->afu_desc_mmio + off)
97#define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
98#define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100#define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
101#define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
102#define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
103#define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
104#define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
105#define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106#define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
107#define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
108#define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
109#define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
110#define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
111#define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
112#define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
113#define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
114#define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
115#define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
116#define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
117#define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
118#define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
119#define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
120
121static const struct pci_device_id cxl_pci_tbl[] = {
122        { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123        { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124        { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125        { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126        { PCI_DEVICE_CLASS(0x120000, ~0), },
127
128        { }
129};
130MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
131
132
133/*
134 * Mostly using these wrappers to avoid confusion:
135 * priv 1 is BAR2, while priv 2 is BAR0
136 */
137static inline resource_size_t p1_base(struct pci_dev *dev)
138{
139        return pci_resource_start(dev, 2);
140}
141
142static inline resource_size_t p1_size(struct pci_dev *dev)
143{
144        return pci_resource_len(dev, 2);
145}
146
147static inline resource_size_t p2_base(struct pci_dev *dev)
148{
149        return pci_resource_start(dev, 0);
150}
151
152static inline resource_size_t p2_size(struct pci_dev *dev)
153{
154        return pci_resource_len(dev, 0);
155}
156
157static int find_cxl_vsec(struct pci_dev *dev)
158{
159        int vsec = 0;
160        u16 val;
161
162        while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
163                pci_read_config_word(dev, vsec + 0x4, &val);
164                if (val == CXL_PCI_VSEC_ID)
165                        return vsec;
166        }
167        return 0;
168
169}
170
171static void dump_cxl_config_space(struct pci_dev *dev)
172{
173        int vsec;
174        u32 val;
175
176        dev_info(&dev->dev, "dump_cxl_config_space\n");
177
178        pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
179        dev_info(&dev->dev, "BAR0: %#.8x\n", val);
180        pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
181        dev_info(&dev->dev, "BAR1: %#.8x\n", val);
182        pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
183        dev_info(&dev->dev, "BAR2: %#.8x\n", val);
184        pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
185        dev_info(&dev->dev, "BAR3: %#.8x\n", val);
186        pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
187        dev_info(&dev->dev, "BAR4: %#.8x\n", val);
188        pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
189        dev_info(&dev->dev, "BAR5: %#.8x\n", val);
190
191        dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
192                p1_base(dev), p1_size(dev));
193        dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
194                p2_base(dev), p2_size(dev));
195        dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
196                pci_resource_start(dev, 4), pci_resource_len(dev, 4));
197
198        if (!(vsec = find_cxl_vsec(dev)))
199                return;
200
201#define show_reg(name, what) \
202        dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
203
204        pci_read_config_dword(dev, vsec + 0x0, &val);
205        show_reg("Cap ID", (val >> 0) & 0xffff);
206        show_reg("Cap Ver", (val >> 16) & 0xf);
207        show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
208        pci_read_config_dword(dev, vsec + 0x4, &val);
209        show_reg("VSEC ID", (val >> 0) & 0xffff);
210        show_reg("VSEC Rev", (val >> 16) & 0xf);
211        show_reg("VSEC Length", (val >> 20) & 0xfff);
212        pci_read_config_dword(dev, vsec + 0x8, &val);
213        show_reg("Num AFUs", (val >> 0) & 0xff);
214        show_reg("Status", (val >> 8) & 0xff);
215        show_reg("Mode Control", (val >> 16) & 0xff);
216        show_reg("Reserved", (val >> 24) & 0xff);
217        pci_read_config_dword(dev, vsec + 0xc, &val);
218        show_reg("PSL Rev", (val >> 0) & 0xffff);
219        show_reg("CAIA Ver", (val >> 16) & 0xffff);
220        pci_read_config_dword(dev, vsec + 0x10, &val);
221        show_reg("Base Image Rev", (val >> 0) & 0xffff);
222        show_reg("Reserved", (val >> 16) & 0x0fff);
223        show_reg("Image Control", (val >> 28) & 0x3);
224        show_reg("Reserved", (val >> 30) & 0x1);
225        show_reg("Image Loaded", (val >> 31) & 0x1);
226
227        pci_read_config_dword(dev, vsec + 0x14, &val);
228        show_reg("Reserved", val);
229        pci_read_config_dword(dev, vsec + 0x18, &val);
230        show_reg("Reserved", val);
231        pci_read_config_dword(dev, vsec + 0x1c, &val);
232        show_reg("Reserved", val);
233
234        pci_read_config_dword(dev, vsec + 0x20, &val);
235        show_reg("AFU Descriptor Offset", val);
236        pci_read_config_dword(dev, vsec + 0x24, &val);
237        show_reg("AFU Descriptor Size", val);
238        pci_read_config_dword(dev, vsec + 0x28, &val);
239        show_reg("Problem State Offset", val);
240        pci_read_config_dword(dev, vsec + 0x2c, &val);
241        show_reg("Problem State Size", val);
242
243        pci_read_config_dword(dev, vsec + 0x30, &val);
244        show_reg("Reserved", val);
245        pci_read_config_dword(dev, vsec + 0x34, &val);
246        show_reg("Reserved", val);
247        pci_read_config_dword(dev, vsec + 0x38, &val);
248        show_reg("Reserved", val);
249        pci_read_config_dword(dev, vsec + 0x3c, &val);
250        show_reg("Reserved", val);
251
252        pci_read_config_dword(dev, vsec + 0x40, &val);
253        show_reg("PSL Programming Port", val);
254        pci_read_config_dword(dev, vsec + 0x44, &val);
255        show_reg("PSL Programming Control", val);
256
257        pci_read_config_dword(dev, vsec + 0x48, &val);
258        show_reg("Reserved", val);
259        pci_read_config_dword(dev, vsec + 0x4c, &val);
260        show_reg("Reserved", val);
261
262        pci_read_config_dword(dev, vsec + 0x50, &val);
263        show_reg("Flash Address Register", val);
264        pci_read_config_dword(dev, vsec + 0x54, &val);
265        show_reg("Flash Size Register", val);
266        pci_read_config_dword(dev, vsec + 0x58, &val);
267        show_reg("Flash Status/Control Register", val);
268        pci_read_config_dword(dev, vsec + 0x58, &val);
269        show_reg("Flash Data Port", val);
270
271#undef show_reg
272}
273
274static void dump_afu_descriptor(struct cxl_afu *afu)
275{
276        u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
277        int i;
278
279#define show_reg(name, what) \
280        dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
281
282        val = AFUD_READ_INFO(afu);
283        show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
284        show_reg("num_of_processes", AFUD_NUM_PROCS(val));
285        show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
286        show_reg("req_prog_mode", val & 0xffffULL);
287        afu_cr_num = AFUD_NUM_CRS(val);
288
289        val = AFUD_READ(afu, 0x8);
290        show_reg("Reserved", val);
291        val = AFUD_READ(afu, 0x10);
292        show_reg("Reserved", val);
293        val = AFUD_READ(afu, 0x18);
294        show_reg("Reserved", val);
295
296        val = AFUD_READ_CR(afu);
297        show_reg("Reserved", (val >> (63-7)) & 0xff);
298        show_reg("AFU_CR_len", AFUD_CR_LEN(val));
299        afu_cr_len = AFUD_CR_LEN(val) * 256;
300
301        val = AFUD_READ_CR_OFF(afu);
302        afu_cr_off = val;
303        show_reg("AFU_CR_offset", val);
304
305        val = AFUD_READ_PPPSA(afu);
306        show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
307        show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
308
309        val = AFUD_READ_PPPSA_OFF(afu);
310        show_reg("PerProcessPSA_offset", val);
311
312        val = AFUD_READ_EB(afu);
313        show_reg("Reserved", (val >> (63-7)) & 0xff);
314        show_reg("AFU_EB_len", AFUD_EB_LEN(val));
315
316        val = AFUD_READ_EB_OFF(afu);
317        show_reg("AFU_EB_offset", val);
318
319        for (i = 0; i < afu_cr_num; i++) {
320                val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
321                show_reg("CR Vendor", val & 0xffff);
322                show_reg("CR Device", (val >> 16) & 0xffff);
323        }
324#undef show_reg
325}
326
327#define CAPP_UNIT0_ID 0xBA
328#define CAPP_UNIT1_ID 0XBE
329
330static u64 get_capp_unit_id(struct device_node *np)
331{
332        u32 phb_index;
333
334        /*
335         * For chips other than POWER8NVL, we only have CAPP 0,
336         * irrespective of which PHB is used.
337         */
338        if (!pvr_version_is(PVR_POWER8NVL))
339                return CAPP_UNIT0_ID;
340
341        /*
342         * For POWER8NVL, assume CAPP 0 is attached to PHB0 and
343         * CAPP 1 is attached to PHB1.
344         */
345        if (of_property_read_u32(np, "ibm,phb-index", &phb_index))
346                return 0;
347
348        if (phb_index == 0)
349                return CAPP_UNIT0_ID;
350
351        if (phb_index == 1)
352                return CAPP_UNIT1_ID;
353
354        return 0;
355}
356
357static int calc_capp_routing(struct pci_dev *dev, u64 *chipid, u64 *capp_unit_id)
358{
359        struct device_node *np;
360        const __be32 *prop;
361
362        if (!(np = pnv_pci_get_phb_node(dev)))
363                return -ENODEV;
364
365        while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
366                np = of_get_next_parent(np);
367        if (!np)
368                return -ENODEV;
369        *chipid = be32_to_cpup(prop);
370        *capp_unit_id = get_capp_unit_id(np);
371        of_node_put(np);
372        if (!*capp_unit_id) {
373                pr_err("cxl: invalid capp unit id\n");
374                return -ENODEV;
375        }
376
377        return 0;
378}
379
380static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_dev *dev)
381{
382        u64 psl_dsnctl, psl_fircntl;
383        u64 chipid;
384        u64 capp_unit_id;
385        int rc;
386
387        rc = calc_capp_routing(dev, &chipid, &capp_unit_id);
388        if (rc)
389                return rc;
390
391        psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
392        psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
393        /* Tell PSL where to route data to */
394        psl_dsnctl |= (chipid << (63-5));
395        psl_dsnctl |= (capp_unit_id << (63-13));
396
397        cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
398        cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
399        /* snoop write mask */
400        cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
401        /* set fir_cntl to recommended value for production env */
402        psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
403        psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
404        psl_fircntl |= 0x1ULL; /* ce_thresh */
405        cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
406        /* for debugging with trace arrays */
407        cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
408
409        return 0;
410}
411
412static int init_implementation_adapter_xsl_regs(struct cxl *adapter, struct pci_dev *dev)
413{
414        u64 xsl_dsnctl;
415        u64 chipid;
416        u64 capp_unit_id;
417        int rc;
418
419        rc = calc_capp_routing(dev, &chipid, &capp_unit_id);
420        if (rc)
421                return rc;
422
423        /* Tell XSL where to route data to */
424        xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
425        xsl_dsnctl |= (capp_unit_id << (63-13));
426        cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
427
428        return 0;
429}
430
431/* PSL & XSL */
432#define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
433#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
434/* For the PSL this is a multiple for 0 < n <= 7: */
435#define PSL_2048_250MHZ_CYCLES 1
436
437static void write_timebase_ctrl_psl(struct cxl *adapter)
438{
439        cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
440                     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
441}
442
443/* XSL */
444#define TBSYNC_ENA (1ULL << 63)
445/* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
446#define XSL_2000_CLOCKS 1
447#define XSL_4000_CLOCKS 2
448#define XSL_8000_CLOCKS 3
449
450static void write_timebase_ctrl_xsl(struct cxl *adapter)
451{
452        cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
453                     TBSYNC_ENA |
454                     TBSYNC_CAL(3) |
455                     TBSYNC_CNT(XSL_4000_CLOCKS));
456}
457
458static u64 timebase_read_psl(struct cxl *adapter)
459{
460        return cxl_p1_read(adapter, CXL_PSL_Timebase);
461}
462
463static u64 timebase_read_xsl(struct cxl *adapter)
464{
465        return cxl_p1_read(adapter, CXL_XSL_Timebase);
466}
467
468static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
469{
470        u64 psl_tb;
471        int delta;
472        unsigned int retry = 0;
473        struct device_node *np;
474
475        adapter->psl_timebase_synced = false;
476
477        if (!(np = pnv_pci_get_phb_node(dev)))
478                return;
479
480        /* Do not fail when CAPP timebase sync is not supported by OPAL */
481        of_node_get(np);
482        if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
483                of_node_put(np);
484                dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
485                return;
486        }
487        of_node_put(np);
488
489        /*
490         * Setup PSL Timebase Control and Status register
491         * with the recommended Timebase Sync Count value
492         */
493        adapter->native->sl_ops->write_timebase_ctrl(adapter);
494
495        /* Enable PSL Timebase */
496        cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
497        cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
498
499        /* Wait until CORE TB and PSL TB difference <= 16usecs */
500        do {
501                msleep(1);
502                if (retry++ > 5) {
503                        dev_info(&dev->dev, "PSL timebase can't synchronize\n");
504                        return;
505                }
506                psl_tb = adapter->native->sl_ops->timebase_read(adapter);
507                delta = mftb() - psl_tb;
508                if (delta < 0)
509                        delta = -delta;
510        } while (tb_to_ns(delta) > 16000);
511
512        adapter->psl_timebase_synced = true;
513        return;
514}
515
516static int init_implementation_afu_psl_regs(struct cxl_afu *afu)
517{
518        /* read/write masks for this slice */
519        cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
520        /* APC read/write masks for this slice */
521        cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
522        /* for debugging with trace arrays */
523        cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
524        cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
525
526        return 0;
527}
528
529int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
530                unsigned int virq)
531{
532        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
533
534        return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
535}
536
537int cxl_update_image_control(struct cxl *adapter)
538{
539        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
540        int rc;
541        int vsec;
542        u8 image_state;
543
544        if (!(vsec = find_cxl_vsec(dev))) {
545                dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
546                return -ENODEV;
547        }
548
549        if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
550                dev_err(&dev->dev, "failed to read image state: %i\n", rc);
551                return rc;
552        }
553
554        if (adapter->perst_loads_image)
555                image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
556        else
557                image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
558
559        if (adapter->perst_select_user)
560                image_state |= CXL_VSEC_PERST_SELECT_USER;
561        else
562                image_state &= ~CXL_VSEC_PERST_SELECT_USER;
563
564        if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
565                dev_err(&dev->dev, "failed to update image control: %i\n", rc);
566                return rc;
567        }
568
569        return 0;
570}
571
572int cxl_pci_alloc_one_irq(struct cxl *adapter)
573{
574        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
575
576        return pnv_cxl_alloc_hwirqs(dev, 1);
577}
578
579void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
580{
581        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
582
583        return pnv_cxl_release_hwirqs(dev, hwirq, 1);
584}
585
586int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
587                        struct cxl *adapter, unsigned int num)
588{
589        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
590
591        return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
592}
593
594void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
595                                struct cxl *adapter)
596{
597        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
598
599        pnv_cxl_release_hwirq_ranges(irqs, dev);
600}
601
602static int setup_cxl_bars(struct pci_dev *dev)
603{
604        /* Safety check in case we get backported to < 3.17 without M64 */
605        if ((p1_base(dev) < 0x100000000ULL) ||
606            (p2_base(dev) < 0x100000000ULL)) {
607                dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
608                return -ENODEV;
609        }
610
611        /*
612         * BAR 4/5 has a special meaning for CXL and must be programmed with a
613         * special value corresponding to the CXL protocol address range.
614         * For POWER 8 that means bits 48:49 must be set to 10
615         */
616        pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
617        pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
618
619        return 0;
620}
621
622#ifdef CONFIG_CXL_BIMODAL
623
624struct cxl_switch_work {
625        struct pci_dev *dev;
626        struct work_struct work;
627        int vsec;
628        int mode;
629};
630
631static void switch_card_to_cxl(struct work_struct *work)
632{
633        struct cxl_switch_work *switch_work =
634                container_of(work, struct cxl_switch_work, work);
635        struct pci_dev *dev = switch_work->dev;
636        struct pci_bus *bus = dev->bus;
637        struct pci_controller *hose = pci_bus_to_host(bus);
638        struct pci_dev *bridge;
639        struct pnv_php_slot *php_slot;
640        unsigned int devfn;
641        u8 val;
642        int rc;
643
644        dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
645        bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
646                                          bus_list);
647        if (!bridge) {
648                dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
649                goto err_dev_put;
650        }
651
652        php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
653        if (!php_slot) {
654                dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
655                                   "information. You may need to upgrade "
656                                   "skiboot. Aborting.\n");
657                goto err_dev_put;
658        }
659
660        rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
661        if (rc) {
662                dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
663                goto err_dev_put;
664        }
665        devfn = dev->devfn;
666
667        /* Release the reference obtained in cxl_check_and_switch_mode() */
668        pci_dev_put(dev);
669
670        dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
671        pci_lock_rescan_remove();
672        pci_hp_remove_devices(bridge->subordinate);
673        pci_unlock_rescan_remove();
674
675        /* Switch the CXL protocol on the card */
676        if (switch_work->mode == CXL_BIMODE_CXL) {
677                dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
678                val &= ~CXL_VSEC_PROTOCOL_MASK;
679                val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
680                rc = pnv_cxl_enable_phb_kernel_api(hose, true);
681                if (rc) {
682                        dev_err(&bus->dev, "cxl: Failed to enable kernel API"
683                                           " on real PHB, aborting\n");
684                        goto err_free_work;
685                }
686        } else {
687                dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
688                goto err_free_work;
689        }
690
691        rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
692        if (rc) {
693                dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
694                goto err_free_work;
695        }
696
697        /*
698         * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
699         * we must wait 100ms after this mode switch before touching PCIe config
700         * space.
701         */
702        msleep(100);
703
704        /*
705         * Hot reset to cause the card to come back in cxl mode. A
706         * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
707         * in skiboot, so we use a hot reset instead.
708         *
709         * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
710         * guaranteed to sit directly under the root port, and setting the reset
711         * state on a device directly under the root port is equivalent to doing
712         * it on the root port iself.
713         */
714        dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
715        pci_set_pcie_reset_state(bridge, pcie_hot_reset);
716        pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
717
718        dev_dbg(&bus->dev, "cxl: Offlining slot\n");
719        rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
720        if (rc) {
721                dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
722                goto err_free_work;
723        }
724
725        dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
726        rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
727        if (rc) {
728                dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
729                goto err_free_work;
730        }
731
732        pci_lock_rescan_remove();
733        pci_hp_add_devices(bridge->subordinate);
734        pci_unlock_rescan_remove();
735
736        dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
737        kfree(switch_work);
738        return;
739
740err_dev_put:
741        /* Release the reference obtained in cxl_check_and_switch_mode() */
742        pci_dev_put(dev);
743err_free_work:
744        kfree(switch_work);
745}
746
747int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
748{
749        struct cxl_switch_work *work;
750        u8 val;
751        int rc;
752
753        if (!cpu_has_feature(CPU_FTR_HVMODE))
754                return -ENODEV;
755
756        if (!vsec) {
757                vsec = find_cxl_vsec(dev);
758                if (!vsec) {
759                        dev_info(&dev->dev, "CXL VSEC not found\n");
760                        return -ENODEV;
761                }
762        }
763
764        rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
765        if (rc) {
766                dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
767                return rc;
768        }
769
770        if (mode == CXL_BIMODE_PCI) {
771                if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
772                        dev_info(&dev->dev, "Card is already in PCI mode\n");
773                        return 0;
774                }
775                /*
776                 * TODO: Before it's safe to switch the card back to PCI mode
777                 * we need to disable the CAPP and make sure any cachelines the
778                 * card holds have been flushed out. Needs skiboot support.
779                 */
780                dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
781                return -EIO;
782        }
783
784        if (val & CXL_VSEC_PROTOCOL_ENABLE) {
785                dev_info(&dev->dev, "Card is already in CXL mode\n");
786                return 0;
787        }
788
789        dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
790                            "to switch to CXL mode\n");
791
792        work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
793        if (!work)
794                return -ENOMEM;
795
796        pci_dev_get(dev);
797        work->dev = dev;
798        work->vsec = vsec;
799        work->mode = mode;
800        INIT_WORK(&work->work, switch_card_to_cxl);
801
802        schedule_work(&work->work);
803
804        /*
805         * We return a failure now to abort the driver init. Once the
806         * link has been cycled and the card is in cxl mode we will
807         * come back (possibly using the generic cxl driver), but
808         * return success as the card should then be in cxl mode.
809         *
810         * TODO: What if the card comes back in PCI mode even after
811         *       the switch?  Don't want to spin endlessly.
812         */
813        return -EBUSY;
814}
815EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
816
817#endif /* CONFIG_CXL_BIMODAL */
818
819static int setup_cxl_protocol_area(struct pci_dev *dev)
820{
821        u8 val;
822        int rc;
823        int vsec = find_cxl_vsec(dev);
824
825        if (!vsec) {
826                dev_info(&dev->dev, "CXL VSEC not found\n");
827                return -ENODEV;
828        }
829
830        rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
831        if (rc) {
832                dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
833                return rc;
834        }
835
836        if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
837                dev_err(&dev->dev, "Card not in CAPI mode!\n");
838                return -EIO;
839        }
840
841        if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
842                val &= ~CXL_VSEC_PROTOCOL_MASK;
843                val |= CXL_VSEC_PROTOCOL_256TB;
844                rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
845                if (rc) {
846                        dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
847                        return rc;
848                }
849        }
850
851        return 0;
852}
853
854static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
855{
856        u64 p1n_base, p2n_base, afu_desc;
857        const u64 p1n_size = 0x100;
858        const u64 p2n_size = 0x1000;
859
860        p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
861        p2n_base = p2_base(dev) + (afu->slice * p2n_size);
862        afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
863        afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
864
865        if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
866                goto err;
867        if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
868                goto err1;
869        if (afu_desc) {
870                if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
871                        goto err2;
872        }
873
874        return 0;
875err2:
876        iounmap(afu->p2n_mmio);
877err1:
878        iounmap(afu->native->p1n_mmio);
879err:
880        dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
881        return -ENOMEM;
882}
883
884static void pci_unmap_slice_regs(struct cxl_afu *afu)
885{
886        if (afu->p2n_mmio) {
887                iounmap(afu->p2n_mmio);
888                afu->p2n_mmio = NULL;
889        }
890        if (afu->native->p1n_mmio) {
891                iounmap(afu->native->p1n_mmio);
892                afu->native->p1n_mmio = NULL;
893        }
894        if (afu->native->afu_desc_mmio) {
895                iounmap(afu->native->afu_desc_mmio);
896                afu->native->afu_desc_mmio = NULL;
897        }
898}
899
900void cxl_pci_release_afu(struct device *dev)
901{
902        struct cxl_afu *afu = to_cxl_afu(dev);
903
904        pr_devel("%s\n", __func__);
905
906        idr_destroy(&afu->contexts_idr);
907        cxl_release_spa(afu);
908
909        kfree(afu->native);
910        kfree(afu);
911}
912
913/* Expects AFU struct to have recently been zeroed out */
914static int cxl_read_afu_descriptor(struct cxl_afu *afu)
915{
916        u64 val;
917
918        val = AFUD_READ_INFO(afu);
919        afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
920        afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
921        afu->crs_num = AFUD_NUM_CRS(val);
922
923        if (AFUD_AFU_DIRECTED(val))
924                afu->modes_supported |= CXL_MODE_DIRECTED;
925        if (AFUD_DEDICATED_PROCESS(val))
926                afu->modes_supported |= CXL_MODE_DEDICATED;
927        if (AFUD_TIME_SLICED(val))
928                afu->modes_supported |= CXL_MODE_TIME_SLICED;
929
930        val = AFUD_READ_PPPSA(afu);
931        afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
932        afu->psa = AFUD_PPPSA_PSA(val);
933        if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
934                afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
935
936        val = AFUD_READ_CR(afu);
937        afu->crs_len = AFUD_CR_LEN(val) * 256;
938        afu->crs_offset = AFUD_READ_CR_OFF(afu);
939
940
941        /* eb_len is in multiple of 4K */
942        afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
943        afu->eb_offset = AFUD_READ_EB_OFF(afu);
944
945        /* eb_off is 4K aligned so lower 12 bits are always zero */
946        if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
947                dev_warn(&afu->dev,
948                         "Invalid AFU error buffer offset %Lx\n",
949                         afu->eb_offset);
950                dev_info(&afu->dev,
951                         "Ignoring AFU error buffer in the descriptor\n");
952                /* indicate that no afu buffer exists */
953                afu->eb_len = 0;
954        }
955
956        return 0;
957}
958
959static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
960{
961        int i, rc;
962        u32 val;
963
964        if (afu->psa && afu->adapter->ps_size <
965                        (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
966                dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
967                return -ENODEV;
968        }
969
970        if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
971                dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
972
973        for (i = 0; i < afu->crs_num; i++) {
974                rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
975                if (rc || val == 0) {
976                        dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
977                        return -EINVAL;
978                }
979        }
980
981        if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
982                /*
983                 * We could also check this for the dedicated process model
984                 * since the architecture indicates it should be set to 1, but
985                 * in that case we ignore the value and I'd rather not risk
986                 * breaking any existing dedicated process AFUs that left it as
987                 * 0 (not that I'm aware of any). It is clearly an error for an
988                 * AFU directed AFU to set this to 0, and would have previously
989                 * triggered a bug resulting in the maximum not being enforced
990                 * at all since idr_alloc treats 0 as no maximum.
991                 */
992                dev_err(&afu->dev, "AFU does not support any processes\n");
993                return -EINVAL;
994        }
995
996        return 0;
997}
998
999static int sanitise_afu_regs(struct cxl_afu *afu)
1000{
1001        u64 reg;
1002
1003        /*
1004         * Clear out any regs that contain either an IVTE or address or may be
1005         * waiting on an acknowledgement to try to be a bit safer as we bring
1006         * it online
1007         */
1008        reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1009        if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1010                dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1011                if (cxl_ops->afu_reset(afu))
1012                        return -EIO;
1013                if (cxl_afu_disable(afu))
1014                        return -EIO;
1015                if (cxl_psl_purge(afu))
1016                        return -EIO;
1017        }
1018        cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1019        cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1020        cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1021        cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1022        cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1023        cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1024        cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1025        cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1026        cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1027        cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1028        cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1029        reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1030        if (reg) {
1031                dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1032                if (reg & CXL_PSL_DSISR_TRANS)
1033                        cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1034                else
1035                        cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1036        }
1037        if (afu->adapter->native->sl_ops->register_serr_irq) {
1038                reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1039                if (reg) {
1040                        if (reg & ~0xffff)
1041                                dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1042                        cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1043                }
1044        }
1045        reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1046        if (reg) {
1047                dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1048                cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1049        }
1050
1051        return 0;
1052}
1053
1054#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1055/*
1056 * afu_eb_read:
1057 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1058 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1059 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1060 */
1061ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1062                                loff_t off, size_t count)
1063{
1064        loff_t aligned_start, aligned_end;
1065        size_t aligned_length;
1066        void *tbuf;
1067        const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1068
1069        if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1070                return 0;
1071
1072        /* calculate aligned read window */
1073        count = min((size_t)(afu->eb_len - off), count);
1074        aligned_start = round_down(off, 8);
1075        aligned_end = round_up(off + count, 8);
1076        aligned_length = aligned_end - aligned_start;
1077
1078        /* max we can copy in one read is PAGE_SIZE */
1079        if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1080                aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1081                count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1082        }
1083
1084        /* use bounce buffer for copy */
1085        tbuf = (void *)__get_free_page(GFP_TEMPORARY);
1086        if (!tbuf)
1087                return -ENOMEM;
1088
1089        /* perform aligned read from the mmio region */
1090        memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1091        memcpy(buf, tbuf + (off & 0x7), count);
1092
1093        free_page((unsigned long)tbuf);
1094
1095        return count;
1096}
1097
1098static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1099{
1100        int rc;
1101
1102        if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1103                return rc;
1104
1105        if ((rc = sanitise_afu_regs(afu)))
1106                goto err1;
1107
1108        /* We need to reset the AFU before we can read the AFU descriptor */
1109        if ((rc = cxl_ops->afu_reset(afu)))
1110                goto err1;
1111
1112        if (cxl_verbose)
1113                dump_afu_descriptor(afu);
1114
1115        if ((rc = cxl_read_afu_descriptor(afu)))
1116                goto err1;
1117
1118        if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1119                goto err1;
1120
1121        if (adapter->native->sl_ops->afu_regs_init)
1122                if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1123                        goto err1;
1124
1125        if (adapter->native->sl_ops->register_serr_irq)
1126                if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1127                        goto err1;
1128
1129        if ((rc = cxl_native_register_psl_irq(afu)))
1130                goto err2;
1131
1132        atomic_set(&afu->configured_state, 0);
1133        return 0;
1134
1135err2:
1136        if (adapter->native->sl_ops->release_serr_irq)
1137                adapter->native->sl_ops->release_serr_irq(afu);
1138err1:
1139        pci_unmap_slice_regs(afu);
1140        return rc;
1141}
1142
1143static void pci_deconfigure_afu(struct cxl_afu *afu)
1144{
1145        /*
1146         * It's okay to deconfigure when AFU is already locked, otherwise wait
1147         * until there are no readers
1148         */
1149        if (atomic_read(&afu->configured_state) != -1) {
1150                while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1151                        schedule();
1152        }
1153        cxl_native_release_psl_irq(afu);
1154        if (afu->adapter->native->sl_ops->release_serr_irq)
1155                afu->adapter->native->sl_ops->release_serr_irq(afu);
1156        pci_unmap_slice_regs(afu);
1157}
1158
1159static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1160{
1161        struct cxl_afu *afu;
1162        int rc = -ENOMEM;
1163
1164        afu = cxl_alloc_afu(adapter, slice);
1165        if (!afu)
1166                return -ENOMEM;
1167
1168        afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1169        if (!afu->native)
1170                goto err_free_afu;
1171
1172        mutex_init(&afu->native->spa_mutex);
1173
1174        rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1175        if (rc)
1176                goto err_free_native;
1177
1178        rc = pci_configure_afu(afu, adapter, dev);
1179        if (rc)
1180                goto err_free_native;
1181
1182        /* Don't care if this fails */
1183        cxl_debugfs_afu_add(afu);
1184
1185        /*
1186         * After we call this function we must not free the afu directly, even
1187         * if it returns an error!
1188         */
1189        if ((rc = cxl_register_afu(afu)))
1190                goto err_put1;
1191
1192        if ((rc = cxl_sysfs_afu_add(afu)))
1193                goto err_put1;
1194
1195        adapter->afu[afu->slice] = afu;
1196
1197        if ((rc = cxl_pci_vphb_add(afu)))
1198                dev_info(&afu->dev, "Can't register vPHB\n");
1199
1200        return 0;
1201
1202err_put1:
1203        pci_deconfigure_afu(afu);
1204        cxl_debugfs_afu_remove(afu);
1205        device_unregister(&afu->dev);
1206        return rc;
1207
1208err_free_native:
1209        kfree(afu->native);
1210err_free_afu:
1211        kfree(afu);
1212        return rc;
1213
1214}
1215
1216static void cxl_pci_remove_afu(struct cxl_afu *afu)
1217{
1218        pr_devel("%s\n", __func__);
1219
1220        if (!afu)
1221                return;
1222
1223        cxl_pci_vphb_remove(afu);
1224        cxl_sysfs_afu_remove(afu);
1225        cxl_debugfs_afu_remove(afu);
1226
1227        spin_lock(&afu->adapter->afu_list_lock);
1228        afu->adapter->afu[afu->slice] = NULL;
1229        spin_unlock(&afu->adapter->afu_list_lock);
1230
1231        cxl_context_detach_all(afu);
1232        cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1233
1234        pci_deconfigure_afu(afu);
1235        device_unregister(&afu->dev);
1236}
1237
1238int cxl_pci_reset(struct cxl *adapter)
1239{
1240        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1241        int rc;
1242
1243        if (adapter->perst_same_image) {
1244                dev_warn(&dev->dev,
1245                         "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1246                return -EINVAL;
1247        }
1248
1249        dev_info(&dev->dev, "CXL reset\n");
1250
1251        /* the adapter is about to be reset, so ignore errors */
1252        cxl_data_cache_flush(adapter);
1253
1254        /* pcie_warm_reset requests a fundamental pci reset which includes a
1255         * PERST assert/deassert.  PERST triggers a loading of the image
1256         * if "user" or "factory" is selected in sysfs */
1257        if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1258                dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1259                return rc;
1260        }
1261
1262        return rc;
1263}
1264
1265static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1266{
1267        if (pci_request_region(dev, 2, "priv 2 regs"))
1268                goto err1;
1269        if (pci_request_region(dev, 0, "priv 1 regs"))
1270                goto err2;
1271
1272        pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1273                        p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1274
1275        if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1276                goto err3;
1277
1278        if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1279                goto err4;
1280
1281        return 0;
1282
1283err4:
1284        iounmap(adapter->native->p1_mmio);
1285        adapter->native->p1_mmio = NULL;
1286err3:
1287        pci_release_region(dev, 0);
1288err2:
1289        pci_release_region(dev, 2);
1290err1:
1291        return -ENOMEM;
1292}
1293
1294static void cxl_unmap_adapter_regs(struct cxl *adapter)
1295{
1296        if (adapter->native->p1_mmio) {
1297                iounmap(adapter->native->p1_mmio);
1298                adapter->native->p1_mmio = NULL;
1299                pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1300        }
1301        if (adapter->native->p2_mmio) {
1302                iounmap(adapter->native->p2_mmio);
1303                adapter->native->p2_mmio = NULL;
1304                pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1305        }
1306}
1307
1308static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1309{
1310        int vsec;
1311        u32 afu_desc_off, afu_desc_size;
1312        u32 ps_off, ps_size;
1313        u16 vseclen;
1314        u8 image_state;
1315
1316        if (!(vsec = find_cxl_vsec(dev))) {
1317                dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1318                return -ENODEV;
1319        }
1320
1321        CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1322        if (vseclen < CXL_VSEC_MIN_SIZE) {
1323                dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1324                return -EINVAL;
1325        }
1326
1327        CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1328        CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1329        CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1330        CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1331        CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1332        CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1333        adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1334        adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1335
1336        CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1337        CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1338        CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1339        CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1340        CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1341
1342        /* Convert everything to bytes, because there is NO WAY I'd look at the
1343         * code a month later and forget what units these are in ;-) */
1344        adapter->native->ps_off = ps_off * 64 * 1024;
1345        adapter->ps_size = ps_size * 64 * 1024;
1346        adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1347        adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1348
1349        /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1350        adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1351
1352        return 0;
1353}
1354
1355/*
1356 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1357 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1358 * reported. Mask this error in the Uncorrectable Error Mask Register.
1359 *
1360 * The upper nibble of the PSL revision is used to distinguish between
1361 * different cards. The affected ones have it set to 0.
1362 */
1363static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1364{
1365        int aer;
1366        u32 data;
1367
1368        if (adapter->psl_rev & 0xf000)
1369                return;
1370        if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1371                return;
1372        pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1373        if (data & PCI_ERR_UNC_MALF_TLP)
1374                if (data & PCI_ERR_UNC_INTN)
1375                        return;
1376        data |= PCI_ERR_UNC_MALF_TLP;
1377        data |= PCI_ERR_UNC_INTN;
1378        pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1379}
1380
1381static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1382{
1383        if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1384                return -EBUSY;
1385
1386        if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1387                dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1388                return -EINVAL;
1389        }
1390
1391        if (!adapter->slices) {
1392                /* Once we support dynamic reprogramming we can use the card if
1393                 * it supports loadable AFUs */
1394                dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1395                return -EINVAL;
1396        }
1397
1398        if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1399                dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1400                return -EINVAL;
1401        }
1402
1403        if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1404                dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1405                                   "available in BAR2: 0x%llx > 0x%llx\n",
1406                         adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1407                return -EINVAL;
1408        }
1409
1410        return 0;
1411}
1412
1413ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1414{
1415        return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1416}
1417
1418static void cxl_release_adapter(struct device *dev)
1419{
1420        struct cxl *adapter = to_cxl_adapter(dev);
1421
1422        pr_devel("cxl_release_adapter\n");
1423
1424        cxl_remove_adapter_nr(adapter);
1425
1426        kfree(adapter->native);
1427        kfree(adapter);
1428}
1429
1430#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1431
1432static int sanitise_adapter_regs(struct cxl *adapter)
1433{
1434        /* Clear PSL tberror bit by writing 1 to it */
1435        cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1436        return cxl_tlb_slb_invalidate(adapter);
1437}
1438
1439/* This should contain *only* operations that can safely be done in
1440 * both creation and recovery.
1441 */
1442static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1443{
1444        int rc;
1445
1446        adapter->dev.parent = &dev->dev;
1447        adapter->dev.release = cxl_release_adapter;
1448        pci_set_drvdata(dev, adapter);
1449
1450        rc = pci_enable_device(dev);
1451        if (rc) {
1452                dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1453                return rc;
1454        }
1455
1456        if ((rc = cxl_read_vsec(adapter, dev)))
1457                return rc;
1458
1459        if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1460                return rc;
1461
1462        cxl_fixup_malformed_tlp(adapter, dev);
1463
1464        if ((rc = setup_cxl_bars(dev)))
1465                return rc;
1466
1467        if ((rc = setup_cxl_protocol_area(dev)))
1468                return rc;
1469
1470        if ((rc = cxl_update_image_control(adapter)))
1471                return rc;
1472
1473        if ((rc = cxl_map_adapter_regs(adapter, dev)))
1474                return rc;
1475
1476        if ((rc = sanitise_adapter_regs(adapter)))
1477                goto err;
1478
1479        if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1480                goto err;
1481
1482        /* Required for devices using CAPP DMA mode, harmless for others */
1483        pci_set_master(dev);
1484
1485        if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1486                goto err;
1487
1488        /* If recovery happened, the last step is to turn on snooping.
1489         * In the non-recovery case this has no effect */
1490        if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1491                goto err;
1492
1493        /* Ignore error, adapter init is not dependant on timebase sync */
1494        cxl_setup_psl_timebase(adapter, dev);
1495
1496        if ((rc = cxl_native_register_psl_err_irq(adapter)))
1497                goto err;
1498
1499        /* Release the context lock as adapter is configured */
1500        cxl_adapter_context_unlock(adapter);
1501        return 0;
1502
1503err:
1504        cxl_unmap_adapter_regs(adapter);
1505        return rc;
1506
1507}
1508
1509static void cxl_deconfigure_adapter(struct cxl *adapter)
1510{
1511        struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1512
1513        cxl_native_release_psl_err_irq(adapter);
1514        cxl_unmap_adapter_regs(adapter);
1515
1516        pci_disable_device(pdev);
1517}
1518
1519static const struct cxl_service_layer_ops psl_ops = {
1520        .adapter_regs_init = init_implementation_adapter_psl_regs,
1521        .afu_regs_init = init_implementation_afu_psl_regs,
1522        .register_serr_irq = cxl_native_register_serr_irq,
1523        .release_serr_irq = cxl_native_release_serr_irq,
1524        .debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_psl_regs,
1525        .debugfs_add_afu_sl_regs = cxl_debugfs_add_afu_psl_regs,
1526        .psl_irq_dump_registers = cxl_native_psl_irq_dump_regs,
1527        .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1528        .debugfs_stop_trace = cxl_stop_trace,
1529        .write_timebase_ctrl = write_timebase_ctrl_psl,
1530        .timebase_read = timebase_read_psl,
1531        .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1532        .needs_reset_before_disable = true,
1533};
1534
1535static const struct cxl_service_layer_ops xsl_ops = {
1536        .adapter_regs_init = init_implementation_adapter_xsl_regs,
1537        .debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_xsl_regs,
1538        .write_timebase_ctrl = write_timebase_ctrl_xsl,
1539        .timebase_read = timebase_read_xsl,
1540        .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1541};
1542
1543static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1544{
1545        if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1546                /* Mellanox CX-4 */
1547                dev_info(&dev->dev, "Device uses an XSL\n");
1548                adapter->native->sl_ops = &xsl_ops;
1549                adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1550        } else {
1551                dev_info(&dev->dev, "Device uses a PSL\n");
1552                adapter->native->sl_ops = &psl_ops;
1553        }
1554}
1555
1556
1557static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1558{
1559        struct cxl *adapter;
1560        int rc;
1561
1562        adapter = cxl_alloc_adapter();
1563        if (!adapter)
1564                return ERR_PTR(-ENOMEM);
1565
1566        adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1567        if (!adapter->native) {
1568                rc = -ENOMEM;
1569                goto err_release;
1570        }
1571
1572        set_sl_ops(adapter, dev);
1573
1574        /* Set defaults for parameters which need to persist over
1575         * configure/reconfigure
1576         */
1577        adapter->perst_loads_image = true;
1578        adapter->perst_same_image = false;
1579
1580        rc = cxl_configure_adapter(adapter, dev);
1581        if (rc) {
1582                pci_disable_device(dev);
1583                goto err_release;
1584        }
1585
1586        /* Don't care if this one fails: */
1587        cxl_debugfs_adapter_add(adapter);
1588
1589        /*
1590         * After we call this function we must not free the adapter directly,
1591         * even if it returns an error!
1592         */
1593        if ((rc = cxl_register_adapter(adapter)))
1594                goto err_put1;
1595
1596        if ((rc = cxl_sysfs_adapter_add(adapter)))
1597                goto err_put1;
1598
1599        return adapter;
1600
1601err_put1:
1602        /* This should mirror cxl_remove_adapter, except without the
1603         * sysfs parts
1604         */
1605        cxl_debugfs_adapter_remove(adapter);
1606        cxl_deconfigure_adapter(adapter);
1607        device_unregister(&adapter->dev);
1608        return ERR_PTR(rc);
1609
1610err_release:
1611        cxl_release_adapter(&adapter->dev);
1612        return ERR_PTR(rc);
1613}
1614
1615static void cxl_pci_remove_adapter(struct cxl *adapter)
1616{
1617        pr_devel("cxl_remove_adapter\n");
1618
1619        cxl_sysfs_adapter_remove(adapter);
1620        cxl_debugfs_adapter_remove(adapter);
1621
1622        cxl_deconfigure_adapter(adapter);
1623
1624        device_unregister(&adapter->dev);
1625}
1626
1627#define CXL_MAX_PCIEX_PARENT 2
1628
1629static int cxl_slot_is_switched(struct pci_dev *dev)
1630{
1631        struct device_node *np;
1632        int depth = 0;
1633        const __be32 *prop;
1634
1635        if (!(np = pci_device_to_OF_node(dev))) {
1636                pr_err("cxl: np = NULL\n");
1637                return -ENODEV;
1638        }
1639        of_node_get(np);
1640        while (np) {
1641                np = of_get_next_parent(np);
1642                prop = of_get_property(np, "device_type", NULL);
1643                if (!prop || strcmp((char *)prop, "pciex"))
1644                        break;
1645                depth++;
1646        }
1647        of_node_put(np);
1648        return (depth > CXL_MAX_PCIEX_PARENT);
1649}
1650
1651bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1652{
1653        if (!cpu_has_feature(CPU_FTR_HVMODE))
1654                return false;
1655
1656        if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1657                /*
1658                 * CAPP DMA mode is technically supported on regular P8, but
1659                 * will EEH if the card attempts to access memory < 4GB, which
1660                 * we cannot realistically avoid. We might be able to work
1661                 * around the issue, but until then return unsupported:
1662                 */
1663                return false;
1664        }
1665
1666        if (cxl_slot_is_switched(dev))
1667                return false;
1668
1669        /*
1670         * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1671         * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1672         * served basis, which is racy to check from here. If we need to
1673         * support this in future we might need to consider having this
1674         * function effectively reserve it ahead of time.
1675         *
1676         * Currently, the only user of this API is the Mellanox CX4, which is
1677         * only supported on P8NVL due to the above mentioned limitation of
1678         * CAPP DMA mode and therefore does not need to worry about this. If the
1679         * issue with CAPP DMA mode is later worked around on P8 we might need
1680         * to revisit this.
1681         */
1682
1683        return true;
1684}
1685EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1686
1687
1688static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1689{
1690        struct cxl *adapter;
1691        int slice;
1692        int rc;
1693
1694        if (cxl_pci_is_vphb_device(dev)) {
1695                dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1696                return -ENODEV;
1697        }
1698
1699        if (cxl_slot_is_switched(dev)) {
1700                dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1701                return -ENODEV;
1702        }
1703
1704        if (cxl_verbose)
1705                dump_cxl_config_space(dev);
1706
1707        adapter = cxl_pci_init_adapter(dev);
1708        if (IS_ERR(adapter)) {
1709                dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1710                return PTR_ERR(adapter);
1711        }
1712
1713        for (slice = 0; slice < adapter->slices; slice++) {
1714                if ((rc = pci_init_afu(adapter, slice, dev))) {
1715                        dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1716                        continue;
1717                }
1718
1719                rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1720                if (rc)
1721                        dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1722        }
1723
1724        if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
1725                pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
1726
1727        return 0;
1728}
1729
1730static void cxl_remove(struct pci_dev *dev)
1731{
1732        struct cxl *adapter = pci_get_drvdata(dev);
1733        struct cxl_afu *afu;
1734        int i;
1735
1736        /*
1737         * Lock to prevent someone grabbing a ref through the adapter list as
1738         * we are removing it
1739         */
1740        for (i = 0; i < adapter->slices; i++) {
1741                afu = adapter->afu[i];
1742                cxl_pci_remove_afu(afu);
1743        }
1744        cxl_pci_remove_adapter(adapter);
1745}
1746
1747static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1748                                                pci_channel_state_t state)
1749{
1750        struct pci_dev *afu_dev;
1751        pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1752        pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1753
1754        /* There should only be one entry, but go through the list
1755         * anyway
1756         */
1757        list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1758                if (!afu_dev->driver)
1759                        continue;
1760
1761                afu_dev->error_state = state;
1762
1763                if (afu_dev->driver->err_handler)
1764                        afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
1765                                                                                  state);
1766                /* Disconnect trumps all, NONE trumps NEED_RESET */
1767                if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1768                        result = PCI_ERS_RESULT_DISCONNECT;
1769                else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1770                         (result == PCI_ERS_RESULT_NEED_RESET))
1771                        result = PCI_ERS_RESULT_NONE;
1772        }
1773        return result;
1774}
1775
1776static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1777                                               pci_channel_state_t state)
1778{
1779        struct cxl *adapter = pci_get_drvdata(pdev);
1780        struct cxl_afu *afu;
1781        pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1782        int i;
1783
1784        /* At this point, we could still have an interrupt pending.
1785         * Let's try to get them out of the way before they do
1786         * anything we don't like.
1787         */
1788        schedule();
1789
1790        /* If we're permanently dead, give up. */
1791        if (state == pci_channel_io_perm_failure) {
1792                /* Tell the AFU drivers; but we don't care what they
1793                 * say, we're going away.
1794                 */
1795                for (i = 0; i < adapter->slices; i++) {
1796                        afu = adapter->afu[i];
1797                        /* Only participate in EEH if we are on a virtual PHB */
1798                        if (afu->phb == NULL)
1799                                return PCI_ERS_RESULT_NONE;
1800                        cxl_vphb_error_detected(afu, state);
1801                }
1802                return PCI_ERS_RESULT_DISCONNECT;
1803        }
1804
1805        /* Are we reflashing?
1806         *
1807         * If we reflash, we could come back as something entirely
1808         * different, including a non-CAPI card. As such, by default
1809         * we don't participate in the process. We'll be unbound and
1810         * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1811         * us!)
1812         *
1813         * However, this isn't the entire story: for reliablity
1814         * reasons, we usually want to reflash the FPGA on PERST in
1815         * order to get back to a more reliable known-good state.
1816         *
1817         * This causes us a bit of a problem: if we reflash we can't
1818         * trust that we'll come back the same - we could have a new
1819         * image and been PERSTed in order to load that
1820         * image. However, most of the time we actually *will* come
1821         * back the same - for example a regular EEH event.
1822         *
1823         * Therefore, we allow the user to assert that the image is
1824         * indeed the same and that we should continue on into EEH
1825         * anyway.
1826         */
1827        if (adapter->perst_loads_image && !adapter->perst_same_image) {
1828                /* TODO take the PHB out of CXL mode */
1829                dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1830                return PCI_ERS_RESULT_NONE;
1831        }
1832
1833        /*
1834         * At this point, we want to try to recover.  We'll always
1835         * need a complete slot reset: we don't trust any other reset.
1836         *
1837         * Now, we go through each AFU:
1838         *  - We send the driver, if bound, an error_detected callback.
1839         *    We expect it to clean up, but it can also tell us to give
1840         *    up and permanently detach the card. To simplify things, if
1841         *    any bound AFU driver doesn't support EEH, we give up on EEH.
1842         *
1843         *  - We detach all contexts associated with the AFU. This
1844         *    does not free them, but puts them into a CLOSED state
1845         *    which causes any the associated files to return useful
1846         *    errors to userland. It also unmaps, but does not free,
1847         *    any IRQs.
1848         *
1849         *  - We clean up our side: releasing and unmapping resources we hold
1850         *    so we can wire them up again when the hardware comes back up.
1851         *
1852         * Driver authors should note:
1853         *
1854         *  - Any contexts you create in your kernel driver (except
1855         *    those associated with anonymous file descriptors) are
1856         *    your responsibility to free and recreate. Likewise with
1857         *    any attached resources.
1858         *
1859         *  - We will take responsibility for re-initialising the
1860         *    device context (the one set up for you in
1861         *    cxl_pci_enable_device_hook and accessed through
1862         *    cxl_get_context). If you've attached IRQs or other
1863         *    resources to it, they remains yours to free.
1864         *
1865         * You can call the same functions to release resources as you
1866         * normally would: we make sure that these functions continue
1867         * to work when the hardware is down.
1868         *
1869         * Two examples:
1870         *
1871         * 1) If you normally free all your resources at the end of
1872         *    each request, or if you use anonymous FDs, your
1873         *    error_detected callback can simply set a flag to tell
1874         *    your driver not to start any new calls. You can then
1875         *    clear the flag in the resume callback.
1876         *
1877         * 2) If you normally allocate your resources on startup:
1878         *     * Set a flag in error_detected as above.
1879         *     * Let CXL detach your contexts.
1880         *     * In slot_reset, free the old resources and allocate new ones.
1881         *     * In resume, clear the flag to allow things to start.
1882         */
1883        for (i = 0; i < adapter->slices; i++) {
1884                afu = adapter->afu[i];
1885
1886                result = cxl_vphb_error_detected(afu, state);
1887
1888                /* Only continue if everyone agrees on NEED_RESET */
1889                if (result != PCI_ERS_RESULT_NEED_RESET)
1890                        return result;
1891
1892                cxl_context_detach_all(afu);
1893                cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1894                pci_deconfigure_afu(afu);
1895        }
1896        cxl_deconfigure_adapter(adapter);
1897
1898        return result;
1899}
1900
1901static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1902{
1903        struct cxl *adapter = pci_get_drvdata(pdev);
1904        struct cxl_afu *afu;
1905        struct cxl_context *ctx;
1906        struct pci_dev *afu_dev;
1907        pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1908        pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1909        int i;
1910
1911        if (cxl_configure_adapter(adapter, pdev))
1912                goto err;
1913
1914        for (i = 0; i < adapter->slices; i++) {
1915                afu = adapter->afu[i];
1916
1917                if (pci_configure_afu(afu, adapter, pdev))
1918                        goto err;
1919
1920                if (cxl_afu_select_best_mode(afu))
1921                        goto err;
1922
1923                list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1924                        /* Reset the device context.
1925                         * TODO: make this less disruptive
1926                         */
1927                        ctx = cxl_get_context(afu_dev);
1928
1929                        if (ctx && cxl_release_context(ctx))
1930                                goto err;
1931
1932                        ctx = cxl_dev_context_init(afu_dev);
1933                        if (!ctx)
1934                                goto err;
1935
1936                        afu_dev->dev.archdata.cxl_ctx = ctx;
1937
1938                        if (cxl_ops->afu_check_and_enable(afu))
1939                                goto err;
1940
1941                        afu_dev->error_state = pci_channel_io_normal;
1942
1943                        /* If there's a driver attached, allow it to
1944                         * chime in on recovery. Drivers should check
1945                         * if everything has come back OK, but
1946                         * shouldn't start new work until we call
1947                         * their resume function.
1948                         */
1949                        if (!afu_dev->driver)
1950                                continue;
1951
1952                        if (afu_dev->driver->err_handler &&
1953                            afu_dev->driver->err_handler->slot_reset)
1954                                afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
1955
1956                        if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1957                                result = PCI_ERS_RESULT_DISCONNECT;
1958                }
1959        }
1960        return result;
1961
1962err:
1963        /* All the bits that happen in both error_detected and cxl_remove
1964         * should be idempotent, so we don't need to worry about leaving a mix
1965         * of unconfigured and reconfigured resources.
1966         */
1967        dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
1968        return PCI_ERS_RESULT_DISCONNECT;
1969}
1970
1971static void cxl_pci_resume(struct pci_dev *pdev)
1972{
1973        struct cxl *adapter = pci_get_drvdata(pdev);
1974        struct cxl_afu *afu;
1975        struct pci_dev *afu_dev;
1976        int i;
1977
1978        /* Everything is back now. Drivers should restart work now.
1979         * This is not the place to be checking if everything came back up
1980         * properly, because there's no return value: do that in slot_reset.
1981         */
1982        for (i = 0; i < adapter->slices; i++) {
1983                afu = adapter->afu[i];
1984
1985                list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1986                        if (afu_dev->driver && afu_dev->driver->err_handler &&
1987                            afu_dev->driver->err_handler->resume)
1988                                afu_dev->driver->err_handler->resume(afu_dev);
1989                }
1990        }
1991}
1992
1993static const struct pci_error_handlers cxl_err_handler = {
1994        .error_detected = cxl_pci_error_detected,
1995        .slot_reset = cxl_pci_slot_reset,
1996        .resume = cxl_pci_resume,
1997};
1998
1999struct pci_driver cxl_pci_driver = {
2000        .name = "cxl-pci",
2001        .id_table = cxl_pci_tbl,
2002        .probe = cxl_probe,
2003        .remove = cxl_remove,
2004        .shutdown = cxl_remove,
2005        .err_handler = &cxl_err_handler,
2006};
Note: See TracBrowser for help on using the repository browser.