source: src/linux/universal/linux-4.9/drivers/mtd/bcm947xx/nand/brcmnand.c @ 31574

Last change on this file since 31574 was 31574, checked in by brainslayer, 3 weeks ago

kernel 4.9 update

File size: 30.8 KB
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1/*
2 * Nortstar NAND controller driver
3 * for Linux NAND library and MTD interface
4 *
5 *  Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
6 * 
7 *  Permission to use, copy, modify, and/or distribute this software for any
8 *  purpose with or without fee is hereby granted, provided that the above
9 *  copyright notice and this permission notice appear in all copies.
10 * 
11 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
14 *  SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
16 *  OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 *  CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * This module interfaces the NAND controller and hardware ECC capabilities
20 * tp the generic NAND chip support in the NAND library.
21 *
22 * Notes:
23 *      This driver depends on generic NAND driver, but works at the
24 *      page level for operations.
25 *
26 *      When a page is written, the ECC calculated also protects the OOB
27 *      bytes not taken by ECC, and so the OOB must be combined with any
28 *      OOB data that preceded the page-write operation in order for the
29 *      ECC to be calculated correctly.
30 *      Also, when the page is erased, but OOB data is not, HW ECC will
31 *      indicate an error, because it checks OOB too, which calls for some
32 *      help from the software in this driver.
33 *
34 * TBD:
35 *      Block locking/unlocking support, OTP support
36 *
37 * $Id: $
38 */
39
40#include <linux/io.h>
41#include <linux/ioport.h>
42#include <linux/delay.h>
43#include <linux/bug.h>
44#include <linux/err.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#ifdef  CONFIG_MTD
49#include <linux/mtd/partitions.h>
50#endif
51#include "../../mtdcore.h"
52
53#include <typedefs.h>
54#include <osl.h>
55#include <hndsoc.h>
56#include <siutils.h>
57#include <hndnand.h>
58#include <nand_core.h>
59#include <bcmnvram.h>
60#include <bcmutils.h>
61
62/*
63 * Because the bcm_nflash doesn't consider second chip case,
64 * So in this brcmnand driver we just define NANDC_MAX_CHIPS to 1
65 * And in the brcmnand_select_chip the argument chip_num == -1 means
66 * de-select the device. Since the bcm_nflash doesn't do select_chip,
67 * we must be careful to select other chip in the brcmnand driver.
68 *
69*/
70#define NANDC_MAX_CHIPS         1
71
72#define DRV_NAME                "brcmnand"
73#define DRV_VERSION             "0.1"
74#define DRV_DESC                "Northstar brcmnand NAND Flash Controller driver"
75
76/* Mutexing is version-dependent */
77extern struct nand_hw_control *nand_hwcontrol_lock_init(void);
78
79/*
80 * Driver private control structure
81 */
82struct brcmnand_mtd {
83        si_t                    *sih;
84        struct mtd_info         mtd;
85        struct nand_chip        chip;
86#ifdef  CONFIG_MTD
87        struct mtd_partition    *parts;
88#endif
89        hndnand_t               *nfl;
90
91        struct nand_ecclayout   ecclayout;
92        int                     cmd_ret;        /* saved error code */
93        int                     page_addr;      /* saved page address from SEQIN */
94        unsigned char           oob_index;
95        unsigned char           id_byte_index;
96        unsigned char           last_cmd;
97        unsigned char           ecc_level;
98        unsigned char           sector_size_shift;
99        unsigned char           sec_per_page_shift;
100};
101
102/* Single device present */
103static struct brcmnand_mtd brcmnand;
104
105/*
106 * NAND Controller hardware ECC data size
107 *
108 * The following table contains the number of bytes needed for
109 * each of the ECC levels, per "sector", which is either 512 or 1024 bytes.
110 * The actual layout is as follows:
111 * The entire spare area is equally divided into as many sections as there
112 * are sectors per page, and the ECC data is located at the end of each
113 * of these sections.
114 * For example, given a 2K per page and 64 bytes spare device, configured for
115 * sector size 1k and ECC level of 4, the spare area will be divided into 2
116 * sections 32 bytes each, and the last 14 bytes of 32 in each section will
117 * be filled with ECC data.
118 * Note: the name of the algorythm and the number of error bits it can correct
119 * is of no consequence to this driver, therefore omitted.
120 */
121static const struct brcmnand_ecc_size_s {
122        unsigned char sector_size_shift;
123        unsigned char ecc_level;
124        unsigned char ecc_bytes_per_sec;
125        unsigned char reserved;
126} brcmnand_ecc_sizes [] = {
127        {9,     0,      0},
128        {10,    0,      0},
129        {9,     1,      2},
130        {10,    1,      4},
131        {9,     2,      4},
132        {10,    2,      7},
133        {9,     3,      6},
134        {10,    3,      11},
135        {9,     4,      7},
136        {10,    4,      14},
137        {9,     5,      9},
138        {10,    5,      18},
139        {9,     6,      11},
140        {10,    6,      21},
141        {9,     7,      13},
142        {10,    7,      25},
143        {9,     8,      14},
144        {10,    8,      28},
145
146        {9,     9,      16},
147        {9,     10,     18},
148        {9,     11,     20},
149        {9,     12,     21},
150
151        {10,    9,      32},
152        {10,    10,     35},
153        {10,    11,     39},
154        {10,    12,     42},
155};
156
157/*
158 * INTERNAL - Populate the various fields that depend on how
159 * the hardware ECC data is located in the spare area
160 *
161 * For this controiller, it is easier to fill-in these
162 * structures at run time.
163 *
164 * The bad-block marker is assumed to occupy one byte
165 * at chip->badblockpos, which must be in the first
166 * sector of the spare area, namely it is either
167 * at offset 0 or 5.
168 * Some chips use both for manufacturer's bad block
169 * markers, but we ingore that issue here, and assume only
170 * one byte is used as bad-block marker always.
171 */
172static int
173brcmnand_hw_ecc_layout(struct brcmnand_mtd *brcmnand)
174{
175        struct nand_ecclayout *layout;
176        unsigned i, j, k;
177        unsigned ecc_per_sec, oob_per_sec;
178        unsigned bbm_pos = brcmnand->chip.badblockpos;
179
180        pr_debug("%s: ecc_level %d\n",
181                __func__, brcmnand->ecc_level);
182
183        /* Caclculate spare area per sector size */
184        oob_per_sec = brcmnand->mtd.oobsize >> brcmnand->sec_per_page_shift;
185
186        /* Try to calculate the amount of ECC bytes per sector with a formula */
187        if (brcmnand->sector_size_shift == 9)
188                ecc_per_sec = ((brcmnand->ecc_level * 14) + 7) >> 3;
189        else if (brcmnand->sector_size_shift == 10)
190                ecc_per_sec = ((brcmnand->ecc_level * 14) + 3) >> 2;
191        else
192                ecc_per_sec = oob_per_sec + 1;  /* cause an error if not in table */
193
194        pr_debug("%s: calc eccbytes %d\n", __func__, ecc_per_sec);
195
196        /* Now find out the answer according to the table */
197        for (i = 0; i < ARRAY_SIZE(brcmnand_ecc_sizes); i++) {
198                if (brcmnand_ecc_sizes[i].ecc_level == brcmnand->ecc_level &&
199                    brcmnand_ecc_sizes[i].sector_size_shift == brcmnand->sector_size_shift) {
200                        pr_debug("%s: table eccbytes %d\n", __func__,
201                                brcmnand_ecc_sizes[i].ecc_bytes_per_sec);
202                        break;
203                }
204        }
205
206        /* Table match overrides formula */
207        if (brcmnand_ecc_sizes[i].ecc_level == brcmnand->ecc_level &&
208            brcmnand_ecc_sizes[i].sector_size_shift == brcmnand->sector_size_shift)
209                ecc_per_sec = brcmnand_ecc_sizes[i].ecc_bytes_per_sec;
210
211        /* Return an error if calculated ECC leaves no room for OOB */
212        if ((brcmnand->sec_per_page_shift != 0 && ecc_per_sec >= oob_per_sec) ||
213            (brcmnand->sec_per_page_shift == 0 && ecc_per_sec >= (oob_per_sec-1))) {
214                printk(KERN_WARNING "%s: ERROR: ECC level %d too high, "
215                        "leaves no room for OOB data\n", __func__, brcmnand->ecc_level);
216                return -EINVAL;
217        }
218
219        /* Fill in the needed fields */
220        brcmnand->chip.ecc.size = brcmnand->mtd.writesize >> brcmnand->sec_per_page_shift;
221        brcmnand->chip.ecc.bytes = ecc_per_sec;
222        brcmnand->chip.ecc.steps = 1 << brcmnand->sec_per_page_shift;
223        brcmnand->chip.ecc.total = ecc_per_sec << brcmnand->sec_per_page_shift;
224
225        /* Build an ecc layout data structure */
226        layout = &brcmnand->ecclayout;
227        memset(layout, 0, sizeof(*layout));
228
229        /* Total number of bytes used by HW ECC */
230        layout->eccbytes = ecc_per_sec << brcmnand->sec_per_page_shift;
231
232        /* Location for each of the HW ECC bytes */
233        for (i = j = 0, k = 1;
234                i < ARRAY_SIZE(layout->eccpos) && i < layout->eccbytes;
235                i++, j++) {
236                /* switch sector # */
237                if (j == ecc_per_sec) {
238                        j = 0;
239                        k ++;
240                }
241                /* save position of each HW-generated ECC byte */
242                layout->eccpos[i] = (oob_per_sec * k) - ecc_per_sec + j;
243
244                /* Check that HW ECC does not overlap bad-block marker */
245                if (bbm_pos == layout->eccpos[i]) {
246                        printk(KERN_WARNING "%s: ERROR: ECC level %d too high, "
247                        "HW ECC collides with bad-block marker position\n",
248                        __func__, brcmnand->ecc_level);
249
250                        return -EINVAL;
251                }
252        }
253
254        /* Location of all user-available OOB byte-ranges */
255        for (i = 0; i < ARRAY_SIZE(layout->oobfree); i++) {
256                if (i >= (1 << brcmnand->sec_per_page_shift))
257                        break;
258                layout->oobfree[i].offset = oob_per_sec * i;
259                layout->oobfree[i].length = oob_per_sec - ecc_per_sec;
260
261
262                /* Bad-block marker must be in the first sector spare area */
263                BUG_ON(bbm_pos >= (layout->oobfree[i].offset+layout->oobfree[i].length));
264                if (i != 0)
265                        continue;
266
267                /* Remove bad-block marker from available byte range */
268                if (bbm_pos == layout->oobfree[i].offset) {
269                        layout->oobfree[i].offset += 1;
270                        layout->oobfree[i].length -= 1;
271                }
272                else if (bbm_pos ==
273                  (layout->oobfree[i].offset+layout->oobfree[i].length-1)) {
274                        layout->oobfree[i].length -= 1;
275                }
276                else {
277                        layout->oobfree[i+1].offset = bbm_pos + 1;
278                        layout->oobfree[i+1].length =
279                                layout->oobfree[i].length - bbm_pos - 1;
280                        layout->oobfree[i].length = bbm_pos;
281                        i ++;
282                }
283        }
284
285        layout->oobavail = ((oob_per_sec - ecc_per_sec) << brcmnand->sec_per_page_shift) - 1;
286
287        brcmnand->mtd.oobavail = layout->oobavail;
288//      brcmnand->chip.ecclayout = layout;
289        brcmnand->chip.ecc.layout = layout;
290
291        /* Output layout for debugging */
292        printk("Spare area=%d eccbytes %d, ecc bytes located at:\n",
293                brcmnand->mtd.oobsize, layout->eccbytes);
294        for (i = j = 0; i < ARRAY_SIZE(layout->eccpos) && i < layout->eccbytes; i++) {
295                printk(" %d", layout->eccpos[i]);
296        }
297        printk("\nAvailable %d bytes at (off,len):\n", layout->oobavail);
298        for (i = 0; i < ARRAY_SIZE(layout->oobfree); i++) {
299                printk("(%d,%d) ",
300                        layout->oobfree[i].offset,
301                        layout->oobfree[i].length);
302        }
303        printk("\n");
304
305        return 0;
306}
307
308/*
309 * INTERNAL - print NAND chip options
310 *
311 * Useful for debugging
312 */
313static void
314brcmnand_options_print(unsigned opts)
315{
316        unsigned bit;
317        const char * n;
318
319        printk("Options: ");
320        for (bit = 0; bit < 32; bit ++) {
321                if (0 == (opts & (1<<bit)))
322                        continue;
323                switch (1 << bit) {
324                        default:
325                                printk("OPT_%x", 1 << bit);
326                                n = NULL;
327                                break;
328//                      case NAND_NO_AUTOINCR:
329//                              n = "NO_AUTOINCR"; break;
330                        case NAND_BUSWIDTH_16:
331                                n = "BUSWIDTH_16"; break;
332//                      case NAND_NO_PADDING:
333//                              n = "NO_PADDING"; break;
334                        case NAND_CACHEPRG:
335                                n = "CACHEPRG"; break;
336//                      case NAND_COPYBACK:
337//                              n = "COPYBACK"; break;
338//                      case NAND_IS_AND:
339//                              n = "IS_AND"; break;
340//                      case NAND_4PAGE_ARRAY:
341//                              n = "4PAGE_ARRAY"; break;
342//                      case BBT_AUTO_REFRESH:
343//                              n = "AUTO_REFRESH"; break;
344//                      case NAND_NO_READRDY:
345//                              n = "NO_READRDY"; break;
346                        case NAND_NO_SUBPAGE_WRITE:
347                                n = "NO_SUBPAGE_WRITE"; break;
348                        case NAND_BROKEN_XD:
349                                n = "BROKEN_XD"; break;
350                        case NAND_ROM:
351                                n = "ROM"; break;
352//                      case NAND_BBT_USE_FLASH:
353//                              n = "USE_FLASH_BBT"; break;
354                        case NAND_SKIP_BBTSCAN:
355                                n = "SKIP_BBTSCAN"; break;
356                        case NAND_OWN_BUFFERS:
357                                n = "OWN_BUFFERS"; break;
358                        case NAND_SCAN_SILENT_NODEV:
359                                n = "SCAN_SILENT_NODEV"; break;
360                        case NAND_CONTROLLER_ALLOC:
361                                n = "SCAN_SILENT_NODEV"; break;
362                        case NAND_BBT_SCAN2NDPAGE:
363                                n = "BBT_SCAN2NDPAGE"; break;
364//                      case NAND_BBT_SCANBYTE1AND6:
365//                              n = "BBT_SCANBYTE1AND6"; break;
366//                      case NAND_BBT_SCANLASTPAGE:
367//                              n = "BBT_SCANLASTPAGE"; break;
368                }
369                printk("%s,", n);
370        }
371        printk("\n");
372}
373
374/*
375 * NAND Interface - dev_ready
376 *
377 * Return 1 if device is ready, 0 otherwise
378 */
379static int
380brcmnand_dev_ready(struct mtd_info *mtd)
381{
382        struct nand_chip *chip = (struct nand_chip *)mtd->priv;
383        struct brcmnand_mtd *brcmnand = (struct brcmnand_mtd *)chip->priv;
384
385        return (hndnand_dev_ready(brcmnand->nfl));
386}
387
388/*
389 * NAND Interface - waitfunc
390 */
391static int
392brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
393{
394        int ret, status;
395        struct brcmnand_mtd *brcmnand = chip->priv;
396
397        /* deliver deferred error code if any */
398        if ((ret = brcmnand->cmd_ret) < 0)
399                brcmnand->cmd_ret = 0;
400        else {
401                if ((ret = hndnand_waitfunc(brcmnand->nfl, &status)) == 0)
402                        ret = status;
403        }
404
405        /* Timeout */
406        if (ret < 0) {
407                pr_debug("%s: timeout\n", __func__);
408                return NAND_STATUS_FAIL;
409        }
410
411        pr_debug("%s: status=%#x\n", __func__, ret);
412
413        return ret;
414}
415
416/*
417 * NAND Interface - read_oob
418 */
419static int
420brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
421{
422        struct brcmnand_mtd *brcmnand = chip->priv;
423        uint64 nand_addr;
424
425        nand_addr = ((uint64)page << chip->page_shift);
426        return hndnand_read_oob(brcmnand->nfl, nand_addr, chip->oob_poi);
427}
428
429/*
430 * NAND Interface - write_oob
431 */
432static int
433brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
434{
435        struct brcmnand_mtd *brcmnand = chip->priv;
436        uint64 nand_addr;
437        int status = 0;
438
439        nand_addr = ((uint64)page << chip->page_shift);
440        hndnand_write_oob(brcmnand->nfl, nand_addr, chip->oob_poi);
441
442        status = brcmnand_waitfunc(mtd, chip);
443
444        return status & NAND_STATUS_FAIL ? -EIO : 0;
445}
446
447/*
448 * INTERNAL - read a page, with or without ECC checking
449 */
450static int
451_brcmnand_read_page_do(struct mtd_info *mtd, struct nand_chip *chip,
452        uint8_t *buf, int page, bool ecc)
453{
454        struct brcmnand_mtd *brcmnand = chip->priv;
455        uint64 nand_addr;
456        uint32 herr = 0, serr = 0;
457        int ret;
458
459        nand_addr = ((uint64)page << chip->page_shift);
460        ret = hndnand_read_page(brcmnand->nfl, nand_addr, buf, chip->oob_poi, ecc, &herr, &serr);
461
462        if (ecc && ret == 0) {
463                /* Report hard ECC errors */
464                mtd->ecc_stats.failed += herr;
465
466                /* Get ECC soft error stats */
467                mtd->ecc_stats.corrected += serr;
468
469                pr_debug("%s: page=%#x err hard %d soft %d\n", __func__, page,
470                        mtd->ecc_stats.failed, mtd->ecc_stats.corrected);
471        }
472
473        return ret;
474}
475
476/*
477 * NAND Interface - read_page_ecc
478 */
479static int
480brcmnand_read_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
481                uint8_t *buf, int oob_required, int page)
482{
483        return _brcmnand_read_page_do(mtd, chip, buf, page, TRUE);
484}
485
486/*
487 * NAND Interface - read_page_raw
488 */
489static int
490brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
491                uint8_t *buf, int oob_required, int page)
492{
493        return _brcmnand_read_page_do(mtd, chip, buf, page, TRUE);
494}
495#define NAND_MAX_OOBSIZE        640
496#define NAND_MAX_PAGESIZE       8192
497
498/*
499 * INTERNAL - do page write, with or without ECC generation enabled
500 */
501static void
502_brcmnand_write_page_do(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, bool ecc)
503{
504        struct brcmnand_mtd *brcmnand = chip->priv;
505        uint8_t tmp_poi[NAND_MAX_OOBSIZE];
506        uint64 nand_addr;
507        int i;
508
509        BUG_ON(brcmnand->page_addr == 0);
510        BUG_ON(mtd->oobsize > sizeof(tmp_poi));
511
512        /* Retreive pre-existing OOB values */
513        memcpy(tmp_poi, chip->oob_poi, mtd->oobsize);
514        brcmnand->cmd_ret = brcmnand_read_oob(mtd, chip, brcmnand->page_addr);
515        if (brcmnand->cmd_ret < 0)
516                return;
517
518        /* Apply new OOB data bytes just like they would end up on the chip */
519        for (i = 0; i < mtd->oobsize; i ++)
520                chip->oob_poi[i] &= tmp_poi[i];
521
522        nand_addr = ((uint64)brcmnand->page_addr << chip->page_shift);
523        brcmnand->cmd_ret = hndnand_write_page(brcmnand->nfl, nand_addr, buf,
524                chip->oob_poi, ecc);
525
526        return;
527}
528
529/*
530 * NAND Interface = write_page_ecc
531 */
532static int
533brcmnand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
534                const uint8_t *buf, int oob_required)
535{
536        _brcmnand_write_page_do(mtd, chip, buf, TRUE);
537        return 0;
538}
539
540/*
541 * NAND Interface = write_page_raw
542 */
543static int
544brcmnand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
545                const uint8_t *buf, int oob_required)
546{
547        printk(KERN_INFO "%s: Enter!\n", __FUNCTION__);
548
549        _brcmnand_write_page_do(mtd, chip, buf, FALSE);
550        return 0;
551}
552
553/*
554 * MTD Interface - read_byte
555 *
556 * This function emulates simple controllers behavior
557 * for just a few relevant commands
558 */
559static uint8_t
560brcmnand_read_byte(struct mtd_info *mtd)
561{
562        struct nand_chip *chip = mtd->priv;
563        struct brcmnand_mtd *brcmnand = chip->priv;
564        uint32 reg;
565        uint8_t b = ~0;
566
567        switch (brcmnand->last_cmd) {
568                case NAND_CMD_READID:
569                        if (brcmnand->id_byte_index < 8) {
570                                reg = hndnand_cmd_read_byte(brcmnand->nfl, CMDFUNC_READID,
571                                        (brcmnand->id_byte_index & 0x4));
572                                reg >>= 24 - ((brcmnand->id_byte_index & 3) << 3);
573                                b = (uint8_t) (reg & ((1 << 8) - 1));
574
575                                brcmnand->id_byte_index ++;
576                        }
577                        break;
578                case NAND_CMD_READOOB:
579                        if (brcmnand->oob_index < mtd->oobsize) {
580                                b = chip->oob_poi[brcmnand->oob_index++];
581                        }
582                        break;
583                case NAND_CMD_STATUS:
584                        b = (uint8_t)hndnand_cmd_read_byte(brcmnand->nfl, CMDFUNC_STATUS, 0);
585                        break;
586                default:
587                        BUG_ON(1);
588        }
589
590        pr_debug( "%s: %#x\n", __func__, b);
591
592        return b;
593}
594
595/*
596 * MTD Interface - read_word
597 *
598 * Can not be tested without x16 chip, but the SoC does not support x16 i/f.
599 */
600static u16
601brcmnand_read_word(struct mtd_info *mtd)
602{
603        u16 w = ~0;
604
605        w = brcmnand_read_byte(mtd);
606        barrier();
607        w |= brcmnand_read_byte(mtd) << 8;
608
609        pr_debug( "%s: %#x\n", __func__, w);
610
611        return w;
612}
613
614/*
615 * MTD Interface - select a chip from an array
616 */
617static void
618brcmnand_select_chip(struct mtd_info *mtd, int chip_num)
619{
620        struct nand_chip *chip = mtd->priv;
621        struct brcmnand_mtd *brcmnand = chip->priv;
622        /* chip_num == -1 means de-select the device */
623        hndnand_select_chip(brcmnand->nfl, 0);
624}
625
626/*
627 * NAND Interface - emulate low-level NAND commands
628 *
629 * Only a few low-level commands are really needed by generic NAND,
630 * and they do not call for CMD_LL operations the controller can support.
631 */
632static void
633brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr)
634{
635        struct nand_chip *chip = mtd->priv;
636        struct brcmnand_mtd *brcmnand = chip->priv;
637        uint64 nand_addr;
638
639        pr_debug("%s: cmd=%#x col=%#x pg=%#x\n", __func__,
640                command, column, page_addr);
641
642        brcmnand->last_cmd = command;
643
644        switch (command) {
645                case NAND_CMD_ERASE1:
646                        column = 0;
647                        BUG_ON(column >= mtd->writesize);
648                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
649                        hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_ERASE1);
650                        break;
651
652                case NAND_CMD_ERASE2:
653                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_ERASE2);
654                        break;
655
656                case NAND_CMD_SEQIN:
657                        BUG_ON(column >= mtd->writesize);
658                        brcmnand->page_addr = page_addr;
659                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
660                        hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_SEQIN);
661                        break;
662
663                case NAND_CMD_READ0:
664                case NAND_CMD_READ1:
665                        BUG_ON(column >= mtd->writesize);
666                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
667                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_READ);
668                        break;
669
670                case NAND_CMD_RESET:
671                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_RESET);
672                        break;
673
674                case NAND_CMD_READID:
675                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_READID);
676                        brcmnand->id_byte_index = 0;
677                        break;
678
679                case NAND_CMD_STATUS:
680                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_STATUS);
681                        break;
682
683                case NAND_CMD_PAGEPROG:
684                        /* Cmd already set from write_page */
685                        break;
686
687                case NAND_CMD_READOOB:
688                        /* Emulate simple interface */
689                        brcmnand_read_oob(mtd, chip, page_addr);
690                        brcmnand->oob_index = 0;
691                        break;
692
693                default:
694                        BUG_ON(1);
695        }
696}
697
698static int
699brcmnand_scan(struct mtd_info *mtd)
700{
701        struct nand_chip *chip = mtd->priv;
702        struct brcmnand_mtd *brcmnand = chip->priv;
703        hndnand_t *nfl = brcmnand->nfl;
704        int ret;
705
706        /*
707         * The spin_lock of chip->controller->lock is enough here,
708         * because we don't start any transation yet.
709         */
710        spin_lock(&chip->controller->lock);
711        ret = nand_scan_ident(mtd, NANDC_MAX_CHIPS, NULL);
712        spin_unlock(&chip->controller->lock);
713        if (ret)
714                return ret;
715
716        pr_debug( "%s: scan_ident ret=%d num_chips=%d\n", __func__,
717                ret, chip->numchips);
718
719        /* Get configuration from first chip */
720        mtd->writesize_shift = chip->page_shift;
721        brcmnand->ecc_level = nfl->ecclevel;
722        brcmnand->sector_size_shift = ffs(nfl->sectorsize) - 1;
723        brcmnand->sec_per_page_shift = mtd->writesize_shift - brcmnand->sector_size_shift;
724
725        /* Generate ecc layout,  will return -EINVAL if OOB space exhausted */
726        if ((ret = brcmnand_hw_ecc_layout(brcmnand)) != 0)
727                return ret;
728
729        pr_debug( "%s: layout.oobavail=%d\n", __func__,
730                chip->ecc.layout->oobavail);
731
732        ret = nand_scan_tail(mtd);
733
734        pr_debug( "%s: scan_tail ret=%d\n", __func__, ret);
735
736        if (chip->badblockbits == 0)
737                chip->badblockbits = 8;
738        BUG_ON((1<<chip->page_shift) != mtd->writesize);
739
740        /* Spit out some key chip parameters as detected by nand_base */
741        pr_debug( "%s: erasesize=%d writesize=%d oobsize=%d "
742                " page_shift=%d badblockpos=%d badblockbits=%d\n", __func__,
743                mtd->erasesize, mtd->writesize, mtd->oobsize,
744                chip->page_shift, chip->badblockpos, chip->badblockbits);
745
746        brcmnand_options_print(chip->options);
747
748        return ret;
749}
750
751/*
752 * Dummy function to make sure generic NAND does not call anything unexpected.
753 */
754static int
755brcmnand_dummy_func(struct mtd_info * mtd)
756{
757        BUG_ON(1);
758}
759
760# define NAND_ALE_COL   0x08
761# define NAND_ALE_ROW   0x10
762
763#ifdef CONFIG_MIPS_BRCM
764
765/**
766 * brcmnand_command_lp - [DEFAULT] Send command to NAND large page device
767 * @mtd:        MTD device structure
768 * @command:    the command to be sent
769 * @column:     the column address for this command, -1 if none
770 * @page_addr:  the page address for this command, -1 if none
771 *
772 * Send command to NAND device. This is the version for the new large page
773 * devices We dont have the separate regions as we have in the small page
774 * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
775 */
776static void
777brcmnand_command_lp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
778{
779        register struct nand_chip *chip = mtd->priv;
780
781        /* Emulate NAND_CMD_READOOB */
782        if (command == NAND_CMD_READOOB) {
783                column += mtd->writesize;
784                command = NAND_CMD_READ0;
785        }
786
787        /* Command latch cycle */
788        chip->cmd_ctrl(mtd, command & 0xff, NAND_NCE | NAND_CLE);
789
790        if (column != -1 || page_addr != -1) {
791                int ctrl = NAND_NCE | NAND_ALE;
792
793                /* Serially input address */
794                if (column != -1) {
795                        ctrl |= NAND_ALE_COL;
796
797                        /* Adjust columns for 16 bit buswidth */
798                        if (chip->options & NAND_BUSWIDTH_16)
799                                column >>= 1;
800
801                        chip->cmd_ctrl(mtd, column, ctrl);
802                }
803
804                if (page_addr != -1) {
805                        ctrl &= ~NAND_ALE_COL;
806                        ctrl |= NAND_ALE_ROW;
807
808                        chip->cmd_ctrl(mtd, page_addr, ctrl);
809                }
810        }
811
812        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
813
814        /*
815         * program and erase have their own busy handlers
816         * status, sequential in, and deplete1 need no delay
817         */
818        switch (command) {
819
820        case NAND_CMD_CACHEDPROG:
821        case NAND_CMD_PAGEPROG:
822        case NAND_CMD_ERASE1:
823        case NAND_CMD_ERASE2:
824        case NAND_CMD_SEQIN:
825        case NAND_CMD_RNDIN:
826        case NAND_CMD_STATUS:
827        case NAND_CMD_DEPLETE1:
828                return;
829
830        /*
831         * read error status commands require only a short delay
832         */
833        case NAND_CMD_STATUS_ERROR:
834        case NAND_CMD_STATUS_ERROR0:
835        case NAND_CMD_STATUS_ERROR1:
836        case NAND_CMD_STATUS_ERROR2:
837        case NAND_CMD_STATUS_ERROR3:
838                udelay(chip->chip_delay);
839                return;
840
841        case NAND_CMD_RESET:
842                if (chip->dev_ready)
843                        break;
844
845                udelay(chip->chip_delay);
846
847                chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE);
848                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
849
850                while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
851                return;
852
853        case NAND_CMD_RNDOUT:
854                /* No ready / busy check necessary */
855                chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_NCE | NAND_CLE);
856                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
857                return;
858
859        case NAND_CMD_READ0:
860                chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE);
861                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
862
863        /* This applies to read commands */
864        default:
865                /*
866                 * If we don't have access to the busy pin, we apply the given
867                 * command delay
868                 */
869                if (!chip->dev_ready) {
870                        udelay(chip->chip_delay);
871                        return;
872                }
873        }
874
875        /* Apply this short delay always to ensure that we do wait tWB in
876         * any case on any machine.
877         */
878        ndelay(100);
879
880        nand_wait_ready(mtd);
881}
882
883/**
884 * brcmnand_command - [DEFAULT] Send command to NAND device
885 * @mtd:        MTD device structure
886 * @command:    the command to be sent
887 * @column:     the column address for this command, -1 if none
888 * @page_addr:  the page address for this command, -1 if none
889 *
890 * Send command to NAND device. This function is used for small page
891 * devices (256/512 Bytes per page)
892 */
893static void
894brcmnand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
895{
896        register struct nand_chip *chip = mtd->priv;
897        int ctrl = NAND_CTRL_CLE;
898
899        /* Invoke large page command function */
900        if (mtd->writesize > 512) {
901                brcmnand_command_lp(mtd, command, column, page_addr);
902                return;
903        }
904
905        /*
906         * Write out the command to the device.
907         */
908        if (command == NAND_CMD_SEQIN) {
909                int readcmd;
910
911                if (column >= mtd->writesize) {
912                        /* OOB area */
913                        column -= mtd->writesize;
914                        readcmd = NAND_CMD_READOOB;
915                } else if (column < 256) {
916                        /* First 256 bytes --> READ0 */
917                        readcmd = NAND_CMD_READ0;
918                } else {
919                        column -= 256;
920                        readcmd = NAND_CMD_READ1;
921                }
922
923                chip->cmd_ctrl(mtd, readcmd, ctrl);
924        }
925
926        chip->cmd_ctrl(mtd, command, ctrl);
927
928        /*
929         * Address cycle, when necessary
930         */
931        ctrl = NAND_CTRL_ALE;
932
933        /* Serially input address */
934        if (column != -1) {
935                ctrl |= NAND_ALE_COL;
936
937                /* Adjust columns for 16 bit buswidth */
938                if (chip->options & NAND_BUSWIDTH_16)
939                        column >>= 1;
940
941                chip->cmd_ctrl(mtd, column, ctrl);
942        }
943
944        if (page_addr != -1) {
945                ctrl &= ~NAND_ALE_COL;
946                ctrl |= NAND_ALE_ROW;
947
948                chip->cmd_ctrl(mtd, page_addr, ctrl);
949        }
950
951        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
952
953        /*
954         * program and erase have their own busy handlers
955         * status and sequential in needs no delay
956         */
957        switch (command) {
958
959        case NAND_CMD_PAGEPROG:
960        case NAND_CMD_ERASE1:
961        case NAND_CMD_ERASE2:
962        case NAND_CMD_SEQIN:
963        case NAND_CMD_STATUS:
964                return;
965
966        case NAND_CMD_RESET:
967                if (chip->dev_ready)
968                        break;
969
970                udelay(chip->chip_delay);
971
972                chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_CTRL_CLE);
973
974                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
975
976                while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
977
978                return;
979
980                /* This applies to read commands */
981        default:
982                /*
983                 * If we don't have access to the busy pin, we apply the given
984                 * command delay
985                 */
986                if (!chip->dev_ready) {
987                        udelay(chip->chip_delay);
988                        return;
989                }
990        }
991
992        /* Apply this short delay always to ensure that we do wait tWB in
993         * any case on any machine.
994         */
995        ndelay(100);
996
997        nand_wait_ready(mtd);
998}
999
1000#endif
1001
1002
1003#ifdef CONFIG_MTD
1004struct mtd_partition brcmnand_parts[] = {
1005        {
1006                .name = "ddwrt",
1007                .size = 0,
1008                .offset = 0
1009        },
1010        {
1011                .name = 0,
1012                .size = 0,
1013                .offset = 0
1014        }
1015};
1016
1017struct mtd_partition *
1018init_brcmnand_mtd_partitions(struct mtd_info *mtd, size_t size)
1019{
1020        int knldev;
1021        int offset = 0;
1022        struct nand_chip *chip = mtd->priv;
1023        struct brcmnand_mtd *brcmnand = chip->priv;
1024        int isbufdual=0;
1025        uint boardnum = bcm_strtoul(nvram_safe_get("boardnum"), NULL, 0);
1026
1027        knldev = soc_knl_dev((void *)brcmnand->sih);
1028        if (knldev == SOC_KNLDEV_NANDFLASH)
1029                offset = NFL_BOOT_OS_SIZE;
1030
1031        if ((!strncmp(nvram_safe_get("boardnum"),"2013",4) || !strncmp(nvram_safe_get("boardnum"),"2014",4)) && nvram_match("boardtype", "0x0646")
1032            && nvram_match("boardrev", "0x1110")) {
1033                printk(KERN_EMERG "Buffalo WZR-900DHP dualboot\n");
1034                isbufdual = 1;
1035        }
1036
1037        if (boardnum == 1 && nvram_match("boardtype","0xD646") && nvram_match("boardrev","0x1100")) {
1038                offset = 0x4000000;
1039               
1040        }
1041
1042        if (((boardnum == 1) || (nvram_get("boardnum") == NULL)) && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1100") && !strncmp(nvram_safe_get("modelNumber"),"EA6400",6)) {
1043                offset = 0x4000000;
1044        }
1045
1046        if (((boardnum == 1) || (nvram_get("boardnum") == NULL)) && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1100") && !strncmp(nvram_safe_get("modelNumber"),"EA6300",6)) {
1047                offset = 0x4000000;
1048        }
1049
1050        if (nvram_match("model","RT-AC87U")) {
1051                printk(KERN_EMERG "Asus AC87U\n");
1052                offset = 0x4000000;
1053        }
1054
1055        if (boardnum == 1 && nvram_match("boardtype","0xF646") && nvram_match("boardrev","0x1100")) {
1056                offset = 0x4000000;
1057               
1058        }
1059
1060        if (nvram_get("bootpartition") && isbufdual) {
1061                offset = 0x4800000;
1062                size -= 0x100000;
1063        }
1064       
1065        if (boardnum == 32 && nvram_match("boardtype", "0x0665") && nvram_match("boardrev", "0x1301")) {
1066                offset = 0x2240000;
1067        }
1068       
1069        if (boardnum == 32 && nvram_match("boardtype", "0x0665") && nvram_match("boardrev", "0x1101")) {
1070                offset = 0x2680000;
1071        }
1072        ASSERT(size > offset);
1073
1074        if (boardnum == 00 && nvram_match("boardtype", "0x0665")
1075            && nvram_match("boardrev", "0x1103")
1076            && nvram_match("melco_id", "RD_BB13049")) {
1077                printk(KERN_EMERG "Buffalo WXR-1900DHP dualboot part\n");
1078                isbufdual = 1;
1079                offset = 0x6000000;
1080                size -= 0x100000;
1081        }
1082       
1083        if (boardnum == 32 && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1601")) {
1084                size   -= 0x1000000;
1085        }
1086       
1087        if (boardnum == 32 && nvram_match("boardtype", "0x072F") && nvram_match("boardrev", "0x1101")) {
1088                size   -= 0x1000000;
1089        }
1090
1091        brcmnand_parts[0].offset = offset;
1092        brcmnand_parts[0].size = size - offset;
1093
1094        return brcmnand_parts;
1095}
1096#endif /* CONFIG_MTD_PARTITIONS */
1097
1098static int __init
1099brcmnand_mtd_init(void)
1100{
1101        int ret = 0;
1102        unsigned chip_num;
1103        hndnand_t *nfl;
1104        struct nand_chip *chip;
1105        struct mtd_info *mtd;
1106#ifdef CONFIG_MTD
1107        struct mtd_partition *parts;
1108        int i;
1109#endif
1110        uint32 *offset;
1111        uint32 reg, size, block, page, ecc_level;
1112
1113        printk(KERN_INFO "%s, Version %s (c) Broadcom Inc. 2012\n",
1114                DRV_DESC, DRV_VERSION);
1115
1116        memset(&brcmnand, 0, sizeof(struct brcmnand_mtd));
1117
1118        /* attach to the backplane */
1119        if (!(brcmnand.sih = si_kattach(SI_OSH))) {
1120                printk(KERN_ERR "brcmnand: error attaching to backplane\n");
1121                ret = -EIO;
1122                goto fail;
1123        }
1124
1125        /* Initialize serial flash access */
1126        if (!(nfl = hndnand_init(brcmnand.sih))) {
1127                printk(KERN_ERR "brcmnand: found no supported devices\n");
1128                ret = -ENODEV;
1129                goto fail;
1130        }
1131
1132        brcmnand.nfl = nfl;
1133
1134        /* Software variables init */
1135        mtd = &brcmnand.mtd;
1136        chip = &brcmnand.chip;
1137
1138        mtd->priv = chip;
1139        mtd->owner = THIS_MODULE;
1140        mtd->name = DRV_NAME;
1141
1142        chip->priv = &brcmnand;
1143        chip->controller = nand_hwcontrol_lock_init();
1144        if (!chip->controller) {
1145                ret = -ENOMEM;
1146                goto fail;
1147        }
1148
1149        chip->chip_delay = 5;   /* not used */
1150        chip->IO_ADDR_R = chip->IO_ADDR_W = (void *)~0L;
1151
1152        /* CS0 device width */
1153        if (nfl->width)
1154                chip->options |= NAND_BUSWIDTH_16;
1155
1156        chip->options |= NAND_NO_SUBPAGE_WRITE; /* Subpages unsupported */
1157
1158        chip->ecc.mode = NAND_ECC_HW;
1159
1160        chip->dev_ready = brcmnand_dev_ready;
1161        chip->read_byte = brcmnand_read_byte;
1162        chip->read_word = brcmnand_read_word;
1163        chip->ecc.read_page_raw = brcmnand_read_page_raw;
1164        chip->ecc.write_page_raw = brcmnand_write_page_raw;
1165        chip->ecc.read_page = brcmnand_read_page_ecc;
1166        chip->ecc.write_page = brcmnand_write_page_ecc;
1167        chip->ecc.read_oob = brcmnand_read_oob;
1168        chip->ecc.write_oob = brcmnand_write_oob;
1169        chip->ecc.strength = 1;
1170        chip->select_chip = brcmnand_select_chip;
1171#ifdef CONFIG_MIPS_BRCM
1172        chip->cmdfunc = brcmnand_command;
1173#else
1174        chip->cmdfunc = brcmnand_cmdfunc;
1175#endif
1176        chip->waitfunc = brcmnand_waitfunc;
1177        chip->read_buf = (void *)brcmnand_dummy_func;
1178        chip->write_buf = (void *)brcmnand_dummy_func;
1179
1180        if (brcmnand_scan(mtd)) {
1181                ret = -ENXIO;
1182                goto fail;
1183        }
1184
1185#ifdef CONFIG_MTD
1186        parts = init_brcmnand_mtd_partitions(&brcmnand.mtd, brcmnand.mtd.size);
1187        if (!parts)
1188                goto fail;
1189
1190        for (i = 0; parts[i].name; i++);
1191
1192        ret = add_mtd_partitions(&brcmnand.mtd, parts, i);
1193        if (ret < 0) {
1194                pr_debug( "%s: failed to add mtd partitions\n", __func__);
1195                goto fail;
1196        }
1197
1198        brcmnand.parts = parts;
1199#endif /* CONFIG_MTD_PARTITIONS */
1200
1201        return 0;
1202
1203fail:
1204        return ret;
1205}
1206
1207static void __exit
1208brcmnand_mtd_exit(void)
1209{
1210#ifdef CONFIG_MTD
1211        del_mtd_partitions(&brcmnand.mtd);
1212#else
1213        del_mtd_device(&brcmnand.mtd);
1214#endif
1215}
1216
1217late_initcall(brcmnand_mtd_init);
1218module_exit(brcmnand_mtd_exit);
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