source: src/linux/universal/linux-4.9/drivers/mtd/bcm947xx/nand/brcmnand.c @ 31707

Last change on this file since 31707 was 31707, checked in by brainslayer, 5 days ago

compiles on northstar, but nand driver will likelly not work yet. still something todo

File size: 30.9 KB
Line 
1/*
2 * Nortstar NAND controller driver
3 * for Linux NAND library and MTD interface
4 *
5 *  Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
6 * 
7 *  Permission to use, copy, modify, and/or distribute this software for any
8 *  purpose with or without fee is hereby granted, provided that the above
9 *  copyright notice and this permission notice appear in all copies.
10 * 
11 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
14 *  SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
16 *  OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 *  CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * This module interfaces the NAND controller and hardware ECC capabilities
20 * tp the generic NAND chip support in the NAND library.
21 *
22 * Notes:
23 *      This driver depends on generic NAND driver, but works at the
24 *      page level for operations.
25 *
26 *      When a page is written, the ECC calculated also protects the OOB
27 *      bytes not taken by ECC, and so the OOB must be combined with any
28 *      OOB data that preceded the page-write operation in order for the
29 *      ECC to be calculated correctly.
30 *      Also, when the page is erased, but OOB data is not, HW ECC will
31 *      indicate an error, because it checks OOB too, which calls for some
32 *      help from the software in this driver.
33 *
34 * TBD:
35 *      Block locking/unlocking support, OTP support
36 *
37 * $Id: $
38 */
39
40#include <linux/io.h>
41#include <linux/ioport.h>
42#include <linux/delay.h>
43#include <linux/bug.h>
44#include <linux/err.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#ifdef  CONFIG_MTD
49#include <linux/mtd/partitions.h>
50#endif
51#include "../../mtdcore.h"
52
53#include <typedefs.h>
54#include <osl.h>
55#include <hndsoc.h>
56#include <siutils.h>
57#include <hndnand.h>
58#include <nand_core.h>
59#include <bcmnvram.h>
60#include <bcmutils.h>
61
62
63struct nand_ecclayout {
64        __u32 eccbytes;
65        __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES];
66        __u32 oobavail;
67        struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
68};
69/*
70 * Because the bcm_nflash doesn't consider second chip case,
71 * So in this brcmnand driver we just define NANDC_MAX_CHIPS to 1
72 * And in the brcmnand_select_chip the argument chip_num == -1 means
73 * de-select the device. Since the bcm_nflash doesn't do select_chip,
74 * we must be careful to select other chip in the brcmnand driver.
75 *
76*/
77#define NANDC_MAX_CHIPS         1
78
79#define DRV_NAME                "brcmnand"
80#define DRV_VERSION             "0.1"
81#define DRV_DESC                "Northstar brcmnand NAND Flash Controller driver"
82
83/* Mutexing is version-dependent */
84extern struct nand_hw_control *nand_hwcontrol_lock_init(void);
85
86/*
87 * Driver private control structure
88 */
89struct brcmnand_mtd {
90        si_t                    *sih;
91        struct mtd_info         mtd;
92        struct nand_chip        chip;
93#ifdef  CONFIG_MTD
94        struct mtd_partition    *parts;
95#endif
96        hndnand_t               *nfl;
97
98        struct nand_ecclayout   ecclayout;
99        int                     cmd_ret;        /* saved error code */
100        unsigned char           oob_index;
101        unsigned char           id_byte_index;
102        unsigned char           last_cmd;
103        unsigned char           ecc_level;
104        unsigned char           sector_size_shift;
105        unsigned char           sec_per_page_shift;
106};
107
108/* Single device present */
109static struct brcmnand_mtd brcmnand;
110
111/*
112 * NAND Controller hardware ECC data size
113 *
114 * The following table contains the number of bytes needed for
115 * each of the ECC levels, per "sector", which is either 512 or 1024 bytes.
116 * The actual layout is as follows:
117 * The entire spare area is equally divided into as many sections as there
118 * are sectors per page, and the ECC data is located at the end of each
119 * of these sections.
120 * For example, given a 2K per page and 64 bytes spare device, configured for
121 * sector size 1k and ECC level of 4, the spare area will be divided into 2
122 * sections 32 bytes each, and the last 14 bytes of 32 in each section will
123 * be filled with ECC data.
124 * Note: the name of the algorythm and the number of error bits it can correct
125 * is of no consequence to this driver, therefore omitted.
126 */
127static const struct brcmnand_ecc_size_s {
128        unsigned char sector_size_shift;
129        unsigned char ecc_level;
130        unsigned char ecc_bytes_per_sec;
131        unsigned char reserved;
132} brcmnand_ecc_sizes [] = {
133        {9,     0,      0},
134        {10,    0,      0},
135        {9,     1,      2},
136        {10,    1,      4},
137        {9,     2,      4},
138        {10,    2,      7},
139        {9,     3,      6},
140        {10,    3,      11},
141        {9,     4,      7},
142        {10,    4,      14},
143        {9,     5,      9},
144        {10,    5,      18},
145        {9,     6,      11},
146        {10,    6,      21},
147        {9,     7,      13},
148        {10,    7,      25},
149        {9,     8,      14},
150        {10,    8,      28},
151
152        {9,     9,      16},
153        {9,     10,     18},
154        {9,     11,     20},
155        {9,     12,     21},
156
157        {10,    9,      32},
158        {10,    10,     35},
159        {10,    11,     39},
160        {10,    12,     42},
161};
162
163/*
164 * INTERNAL - Populate the various fields that depend on how
165 * the hardware ECC data is located in the spare area
166 *
167 * For this controiller, it is easier to fill-in these
168 * structures at run time.
169 *
170 * The bad-block marker is assumed to occupy one byte
171 * at chip->badblockpos, which must be in the first
172 * sector of the spare area, namely it is either
173 * at offset 0 or 5.
174 * Some chips use both for manufacturer's bad block
175 * markers, but we ingore that issue here, and assume only
176 * one byte is used as bad-block marker always.
177 */
178static int
179brcmnand_hw_ecc_layout(struct brcmnand_mtd *brcmnand)
180{
181        struct nand_ecclayout *layout;
182        unsigned i, j, k;
183        unsigned ecc_per_sec, oob_per_sec;
184        unsigned bbm_pos = brcmnand->chip.badblockpos;
185
186        pr_debug("%s: ecc_level %d\n",
187                __func__, brcmnand->ecc_level);
188
189        /* Caclculate spare area per sector size */
190        oob_per_sec = brcmnand->mtd.oobsize >> brcmnand->sec_per_page_shift;
191
192        /* Try to calculate the amount of ECC bytes per sector with a formula */
193        if (brcmnand->sector_size_shift == 9)
194                ecc_per_sec = ((brcmnand->ecc_level * 14) + 7) >> 3;
195        else if (brcmnand->sector_size_shift == 10)
196                ecc_per_sec = ((brcmnand->ecc_level * 14) + 3) >> 2;
197        else
198                ecc_per_sec = oob_per_sec + 1;  /* cause an error if not in table */
199
200        pr_debug("%s: calc eccbytes %d\n", __func__, ecc_per_sec);
201
202        /* Now find out the answer according to the table */
203        for (i = 0; i < ARRAY_SIZE(brcmnand_ecc_sizes); i++) {
204                if (brcmnand_ecc_sizes[i].ecc_level == brcmnand->ecc_level &&
205                    brcmnand_ecc_sizes[i].sector_size_shift == brcmnand->sector_size_shift) {
206                        pr_debug("%s: table eccbytes %d\n", __func__,
207                                brcmnand_ecc_sizes[i].ecc_bytes_per_sec);
208                        break;
209                }
210        }
211
212        /* Table match overrides formula */
213        if (brcmnand_ecc_sizes[i].ecc_level == brcmnand->ecc_level &&
214            brcmnand_ecc_sizes[i].sector_size_shift == brcmnand->sector_size_shift)
215                ecc_per_sec = brcmnand_ecc_sizes[i].ecc_bytes_per_sec;
216
217        /* Return an error if calculated ECC leaves no room for OOB */
218        if ((brcmnand->sec_per_page_shift != 0 && ecc_per_sec >= oob_per_sec) ||
219            (brcmnand->sec_per_page_shift == 0 && ecc_per_sec >= (oob_per_sec-1))) {
220                printk(KERN_WARNING "%s: ERROR: ECC level %d too high, "
221                        "leaves no room for OOB data\n", __func__, brcmnand->ecc_level);
222                return -EINVAL;
223        }
224
225        /* Fill in the needed fields */
226        brcmnand->chip.ecc.size = brcmnand->mtd.writesize >> brcmnand->sec_per_page_shift;
227        brcmnand->chip.ecc.bytes = ecc_per_sec;
228        brcmnand->chip.ecc.steps = 1 << brcmnand->sec_per_page_shift;
229        brcmnand->chip.ecc.total = ecc_per_sec << brcmnand->sec_per_page_shift;
230
231        /* Build an ecc layout data structure */
232        layout = &brcmnand->ecclayout;
233        memset(layout, 0, sizeof(*layout));
234
235        /* Total number of bytes used by HW ECC */
236        layout->eccbytes = ecc_per_sec << brcmnand->sec_per_page_shift;
237
238        /* Location for each of the HW ECC bytes */
239        for (i = j = 0, k = 1;
240                i < ARRAY_SIZE(layout->eccpos) && i < layout->eccbytes;
241                i++, j++) {
242                /* switch sector # */
243                if (j == ecc_per_sec) {
244                        j = 0;
245                        k ++;
246                }
247                /* save position of each HW-generated ECC byte */
248                layout->eccpos[i] = (oob_per_sec * k) - ecc_per_sec + j;
249
250                /* Check that HW ECC does not overlap bad-block marker */
251                if (bbm_pos == layout->eccpos[i]) {
252                        printk(KERN_WARNING "%s: ERROR: ECC level %d too high, "
253                        "HW ECC collides with bad-block marker position\n",
254                        __func__, brcmnand->ecc_level);
255
256                        return -EINVAL;
257                }
258        }
259
260        /* Location of all user-available OOB byte-ranges */
261        for (i = 0; i < ARRAY_SIZE(layout->oobfree); i++) {
262                if (i >= (1 << brcmnand->sec_per_page_shift))
263                        break;
264                layout->oobfree[i].offset = oob_per_sec * i;
265                layout->oobfree[i].length = oob_per_sec - ecc_per_sec;
266
267
268                /* Bad-block marker must be in the first sector spare area */
269                BUG_ON(bbm_pos >= (layout->oobfree[i].offset+layout->oobfree[i].length));
270                if (i != 0)
271                        continue;
272
273                /* Remove bad-block marker from available byte range */
274                if (bbm_pos == layout->oobfree[i].offset) {
275                        layout->oobfree[i].offset += 1;
276                        layout->oobfree[i].length -= 1;
277                }
278                else if (bbm_pos ==
279                  (layout->oobfree[i].offset+layout->oobfree[i].length-1)) {
280                        layout->oobfree[i].length -= 1;
281                }
282                else {
283                        layout->oobfree[i+1].offset = bbm_pos + 1;
284                        layout->oobfree[i+1].length =
285                                layout->oobfree[i].length - bbm_pos - 1;
286                        layout->oobfree[i].length = bbm_pos;
287                        i ++;
288                }
289        }
290
291        layout->oobavail = ((oob_per_sec - ecc_per_sec) << brcmnand->sec_per_page_shift) - 1;
292
293//      brcmnand->mtd.oobavail = layout->oobavail;
294//      brcmnand->chip.ecclayout = layout;
295//      brcmnand->chip.ecc.layout = layout;
296        mtd_set_ooblayout(&brcmnand->mtd, &nand_ooblayout_lp_ops);
297        /* Output layout for debugging */
298        printk("Spare area=%d eccbytes %d, ecc bytes located at:\n",
299                brcmnand->mtd.oobsize, layout->eccbytes);
300        for (i = j = 0; i < ARRAY_SIZE(layout->eccpos) && i < layout->eccbytes; i++) {
301                printk(" %d", layout->eccpos[i]);
302        }
303        printk("\nAvailable %d bytes at (off,len):\n", layout->oobavail);
304        for (i = 0; i < ARRAY_SIZE(layout->oobfree); i++) {
305                printk("(%d,%d) ",
306                        layout->oobfree[i].offset,
307                        layout->oobfree[i].length);
308        }
309        printk("\n");
310
311        return 0;
312}
313
314/*
315 * INTERNAL - print NAND chip options
316 *
317 * Useful for debugging
318 */
319static void
320brcmnand_options_print(unsigned opts)
321{
322        unsigned bit;
323        const char * n;
324
325        printk("Options: ");
326        for (bit = 0; bit < 32; bit ++) {
327                if (0 == (opts & (1<<bit)))
328                        continue;
329                switch (1 << bit) {
330                        default:
331                                printk("OPT_%x", 1 << bit);
332                                n = NULL;
333                                break;
334//                      case NAND_NO_AUTOINCR:
335//                              n = "NO_AUTOINCR"; break;
336                        case NAND_BUSWIDTH_16:
337                                n = "BUSWIDTH_16"; break;
338//                      case NAND_NO_PADDING:
339//                              n = "NO_PADDING"; break;
340                        case NAND_CACHEPRG:
341                                n = "CACHEPRG"; break;
342//                      case NAND_COPYBACK:
343//                              n = "COPYBACK"; break;
344//                      case NAND_IS_AND:
345//                              n = "IS_AND"; break;
346//                      case NAND_4PAGE_ARRAY:
347//                              n = "4PAGE_ARRAY"; break;
348//                      case BBT_AUTO_REFRESH:
349//                              n = "AUTO_REFRESH"; break;
350//                      case NAND_NO_READRDY:
351//                              n = "NO_READRDY"; break;
352                        case NAND_NO_SUBPAGE_WRITE:
353                                n = "NO_SUBPAGE_WRITE"; break;
354                        case NAND_BROKEN_XD:
355                                n = "BROKEN_XD"; break;
356                        case NAND_ROM:
357                                n = "ROM"; break;
358//                      case NAND_BBT_USE_FLASH:
359//                              n = "USE_FLASH_BBT"; break;
360                        case NAND_SKIP_BBTSCAN:
361                                n = "SKIP_BBTSCAN"; break;
362                        case NAND_OWN_BUFFERS:
363                                n = "OWN_BUFFERS"; break;
364                        case NAND_SCAN_SILENT_NODEV:
365                                n = "SCAN_SILENT_NODEV"; break;
366                        case NAND_CONTROLLER_ALLOC:
367                                n = "SCAN_SILENT_NODEV"; break;
368                        case NAND_BBT_SCAN2NDPAGE:
369                                n = "BBT_SCAN2NDPAGE"; break;
370//                      case NAND_BBT_SCANBYTE1AND6:
371//                              n = "BBT_SCANBYTE1AND6"; break;
372//                      case NAND_BBT_SCANLASTPAGE:
373//                              n = "BBT_SCANLASTPAGE"; break;
374                }
375                printk("%s,", n);
376        }
377        printk("\n");
378}
379
380/*
381 * NAND Interface - dev_ready
382 *
383 * Return 1 if device is ready, 0 otherwise
384 */
385static int
386brcmnand_dev_ready(struct mtd_info *mtd)
387{
388        struct nand_chip *chip = mtd_to_nand(mtd);;
389        struct brcmnand_mtd *brcmnand = (struct brcmnand_mtd *)chip->priv;
390
391        return (hndnand_dev_ready(brcmnand->nfl));
392}
393
394/*
395 * NAND Interface - waitfunc
396 */
397static int
398brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
399{
400        int ret, status;
401        struct brcmnand_mtd *brcmnand = chip->priv;
402
403        /* deliver deferred error code if any */
404        if ((ret = brcmnand->cmd_ret) < 0)
405                brcmnand->cmd_ret = 0;
406        else {
407                if ((ret = hndnand_waitfunc(brcmnand->nfl, &status)) == 0)
408                        ret = status;
409        }
410
411        /* Timeout */
412        if (ret < 0) {
413                pr_debug("%s: timeout\n", __func__);
414                return NAND_STATUS_FAIL;
415        }
416
417        pr_debug("%s: status=%#x\n", __func__, ret);
418
419        return ret;
420}
421
422/*
423 * NAND Interface - read_oob
424 */
425static int
426brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
427{
428        struct brcmnand_mtd *brcmnand = chip->priv;
429        uint64 nand_addr;
430
431        nand_addr = ((uint64)page << chip->page_shift);
432        return hndnand_read_oob(brcmnand->nfl, nand_addr, chip->oob_poi);
433}
434
435/*
436 * NAND Interface - write_oob
437 */
438static int
439brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
440{
441        struct brcmnand_mtd *brcmnand = chip->priv;
442        uint64 nand_addr;
443        int status = 0;
444
445        nand_addr = ((uint64)page << chip->page_shift);
446        hndnand_write_oob(brcmnand->nfl, nand_addr, chip->oob_poi);
447
448        status = brcmnand_waitfunc(mtd, chip);
449
450        return status & NAND_STATUS_FAIL ? -EIO : 0;
451}
452
453/*
454 * INTERNAL - read a page, with or without ECC checking
455 */
456static int
457_brcmnand_read_page_do(struct mtd_info *mtd, struct nand_chip *chip,
458        uint8_t *buf, int page, bool ecc)
459{
460        struct brcmnand_mtd *brcmnand = chip->priv;
461        uint64 nand_addr;
462        uint32 herr = 0, serr = 0;
463        int ret;
464
465        nand_addr = ((uint64)page << chip->page_shift);
466        ret = hndnand_read_page(brcmnand->nfl, nand_addr, buf, chip->oob_poi, ecc, &herr, &serr);
467
468        if (ecc && ret == 0) {
469                /* Report hard ECC errors */
470                mtd->ecc_stats.failed += herr;
471
472                /* Get ECC soft error stats */
473                mtd->ecc_stats.corrected += serr;
474
475                pr_debug("%s: page=%#x err hard %d soft %d\n", __func__, page,
476                        mtd->ecc_stats.failed, mtd->ecc_stats.corrected);
477        }
478
479        return ret;
480}
481
482/*
483 * NAND Interface - read_page_ecc
484 */
485static int
486brcmnand_read_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
487                uint8_t *buf, int oob_required, int page)
488{
489        return _brcmnand_read_page_do(mtd, chip, buf, page, TRUE);
490}
491
492/*
493 * NAND Interface - read_page_raw
494 */
495static int
496brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
497                uint8_t *buf, int oob_required, int page)
498{
499        return _brcmnand_read_page_do(mtd, chip, buf, page, TRUE);
500}
501#define NAND_MAX_OOBSIZE        640
502#define NAND_MAX_PAGESIZE       8192
503
504/*
505 * INTERNAL - do page write, with or without ECC generation enabled
506 */
507 
508 
509static void
510_brcmnand_write_page_do(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf, int page, bool ecc)
511{
512        struct brcmnand_mtd *brcmnand = chip->priv;
513        uint8_t tmp_poi[NAND_MAX_OOBSIZE];
514        uint64 nand_addr;
515        int i;
516
517        BUG_ON(mtd->oobsize > sizeof(tmp_poi));
518
519        /* Retreive pre-existing OOB values */
520        memcpy(tmp_poi, chip->oob_poi, mtd->oobsize);
521        brcmnand->cmd_ret = brcmnand_read_oob(mtd, chip, page);
522        if (brcmnand->cmd_ret < 0)
523                return;
524
525        /* Apply new OOB data bytes just like they would end up on the chip */
526        for (i = 0; i < mtd->oobsize; i ++)
527                chip->oob_poi[i] &= tmp_poi[i];
528
529                       
530        nand_addr = ((uint64)page << chip->page_shift);
531        brcmnand->cmd_ret = hndnand_write_page(brcmnand->nfl, nand_addr, buf,
532                chip->oob_poi, ecc);
533
534        return;
535}
536
537/*
538 * NAND Interface = write_page_ecc
539 */
540static int
541brcmnand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
542                const uint8_t *buf, int oob_required, int page)
543{
544        _brcmnand_write_page_do(mtd, chip, buf, page, TRUE);
545        return 0;
546}
547
548/*
549 * NAND Interface = write_page_raw
550 */
551static int
552brcmnand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
553                const uint8_t *buf, int oob_required, int page)
554{
555        printk(KERN_INFO "%s: Enter!\n", __FUNCTION__);
556
557        _brcmnand_write_page_do(mtd, chip, buf, page, FALSE);
558        return 0;
559}
560
561/*
562 * MTD Interface - read_byte
563 *
564 * This function emulates simple controllers behavior
565 * for just a few relevant commands
566 */
567static uint8_t
568brcmnand_read_byte(struct mtd_info *mtd)
569{
570        struct nand_chip *chip = mtd_to_nand(mtd);
571        struct brcmnand_mtd *brcmnand = chip->priv;
572        uint32 reg;
573        uint8_t b = ~0;
574
575        switch (brcmnand->last_cmd) {
576                case NAND_CMD_READID:
577                        if (brcmnand->id_byte_index < 8) {
578                                reg = hndnand_cmd_read_byte(brcmnand->nfl, CMDFUNC_READID,
579                                        (brcmnand->id_byte_index & 0x4));
580                                reg >>= 24 - ((brcmnand->id_byte_index & 3) << 3);
581                                b = (uint8_t) (reg & ((1 << 8) - 1));
582
583                                brcmnand->id_byte_index ++;
584                        }
585                        break;
586                case NAND_CMD_READOOB:
587                        if (brcmnand->oob_index < mtd->oobsize) {
588                                b = chip->oob_poi[brcmnand->oob_index++];
589                        }
590                        break;
591                case NAND_CMD_STATUS:
592                        b = (uint8_t)hndnand_cmd_read_byte(brcmnand->nfl, CMDFUNC_STATUS, 0);
593                        break;
594                default:
595                        BUG_ON(1);
596        }
597
598        pr_debug( "%s: %#x\n", __func__, b);
599
600        return b;
601}
602
603/*
604 * MTD Interface - read_word
605 *
606 * Can not be tested without x16 chip, but the SoC does not support x16 i/f.
607 */
608static u16
609brcmnand_read_word(struct mtd_info *mtd)
610{
611        u16 w = ~0;
612
613        w = brcmnand_read_byte(mtd);
614        barrier();
615        w |= brcmnand_read_byte(mtd) << 8;
616
617        pr_debug( "%s: %#x\n", __func__, w);
618
619        return w;
620}
621
622/*
623 * MTD Interface - select a chip from an array
624 */
625static void
626brcmnand_select_chip(struct mtd_info *mtd, int chip_num)
627{
628        struct nand_chip *chip = mtd_to_nand(mtd);
629        struct brcmnand_mtd *brcmnand = chip->priv;
630        /* chip_num == -1 means de-select the device */
631        hndnand_select_chip(brcmnand->nfl, 0);
632}
633
634/*
635 * NAND Interface - emulate low-level NAND commands
636 *
637 * Only a few low-level commands are really needed by generic NAND,
638 * and they do not call for CMD_LL operations the controller can support.
639 */
640static void
641brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr)
642{
643        struct nand_chip *chip = mtd_to_nand(mtd);
644        struct brcmnand_mtd *brcmnand = chip->priv;
645        uint64 nand_addr;
646
647        pr_debug("%s: cmd=%#x col=%#x pg=%#x\n", __func__,
648                command, column, page_addr);
649
650        brcmnand->last_cmd = command;
651
652        switch (command) {
653                case NAND_CMD_ERASE1:
654                        column = 0;
655                        BUG_ON(column >= mtd->writesize);
656                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
657                        hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_ERASE1);
658                        break;
659
660                case NAND_CMD_ERASE2:
661                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_ERASE2);
662                        break;
663
664                case NAND_CMD_SEQIN:
665                        BUG_ON(column >= mtd->writesize);
666                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
667                        hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_SEQIN);
668                        break;
669
670                case NAND_CMD_READ0:
671                case NAND_CMD_READ1:
672                        BUG_ON(column >= mtd->writesize);
673                        nand_addr = (uint64) column | ((uint64)page_addr << chip->page_shift);
674                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, nand_addr, CMDFUNC_READ);
675                        break;
676
677                case NAND_CMD_RESET:
678                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_RESET);
679                        break;
680
681                case NAND_CMD_READID:
682                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_READID);
683                        brcmnand->id_byte_index = 0;
684                        break;
685
686                case NAND_CMD_STATUS:
687                        brcmnand->cmd_ret = hndnand_cmdfunc(brcmnand->nfl, 0, CMDFUNC_STATUS);
688                        break;
689
690                case NAND_CMD_PAGEPROG:
691                        /* Cmd already set from write_page */
692                        break;
693
694                case NAND_CMD_READOOB:
695                        /* Emulate simple interface */
696                        brcmnand_read_oob(mtd, chip, page_addr);
697                        brcmnand->oob_index = 0;
698                        break;
699
700                default:
701                        BUG_ON(1);
702        }
703}
704
705static int
706brcmnand_scan(struct mtd_info *mtd)
707{
708        struct nand_chip *chip = mtd_to_nand(mtd);
709        struct brcmnand_mtd *brcmnand = chip->priv;
710        hndnand_t *nfl = brcmnand->nfl;
711        int ret;
712
713        /*
714         * The spin_lock of chip->controller->lock is enough here,
715         * because we don't start any transation yet.
716         */
717        spin_lock(&chip->controller->lock);
718        ret = nand_scan_ident(mtd, NANDC_MAX_CHIPS, NULL);
719        spin_unlock(&chip->controller->lock);
720        if (ret)
721                return ret;
722
723        pr_debug( "%s: scan_ident ret=%d num_chips=%d\n", __func__,
724                ret, chip->numchips);
725
726        /* Get configuration from first chip */
727        mtd->writesize_shift = chip->page_shift;
728        brcmnand->ecc_level = nfl->ecclevel;
729        brcmnand->sector_size_shift = ffs(nfl->sectorsize) - 1;
730        brcmnand->sec_per_page_shift = mtd->writesize_shift - brcmnand->sector_size_shift;
731
732        /* Generate ecc layout,  will return -EINVAL if OOB space exhausted */
733        if ((ret = brcmnand_hw_ecc_layout(brcmnand)) != 0)
734                return ret;
735
736//      pr_debug( "%s: layout.oobavail=%d\n", __func__,
737//              chip->ecc.layout->oobavail);
738
739        ret = nand_scan_tail(mtd);
740
741        pr_debug( "%s: scan_tail ret=%d\n", __func__, ret);
742
743        if (chip->badblockbits == 0)
744                chip->badblockbits = 8;
745        BUG_ON((1<<chip->page_shift) != mtd->writesize);
746
747        /* Spit out some key chip parameters as detected by nand_base */
748        pr_debug( "%s: erasesize=%d writesize=%d oobsize=%d "
749                " page_shift=%d badblockpos=%d badblockbits=%d\n", __func__,
750                mtd->erasesize, mtd->writesize, mtd->oobsize,
751                chip->page_shift, chip->badblockpos, chip->badblockbits);
752
753        brcmnand_options_print(chip->options);
754
755        return ret;
756}
757
758/*
759 * Dummy function to make sure generic NAND does not call anything unexpected.
760 */
761static int
762brcmnand_dummy_func(struct mtd_info * mtd)
763{
764        BUG_ON(1);
765}
766
767# define NAND_ALE_COL   0x08
768# define NAND_ALE_ROW   0x10
769
770#ifdef CONFIG_MIPS_BRCM
771
772/**
773 * brcmnand_command_lp - [DEFAULT] Send command to NAND large page device
774 * @mtd:        MTD device structure
775 * @command:    the command to be sent
776 * @column:     the column address for this command, -1 if none
777 * @page_addr:  the page address for this command, -1 if none
778 *
779 * Send command to NAND device. This is the version for the new large page
780 * devices We dont have the separate regions as we have in the small page
781 * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
782 */
783static void
784brcmnand_command_lp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
785{
786        register struct nand_chip *chip = mtd_to_nand(mtd);
787
788        /* Emulate NAND_CMD_READOOB */
789        if (command == NAND_CMD_READOOB) {
790                column += mtd->writesize;
791                command = NAND_CMD_READ0;
792        }
793
794        /* Command latch cycle */
795        chip->cmd_ctrl(mtd, command & 0xff, NAND_NCE | NAND_CLE);
796
797        if (column != -1 || page_addr != -1) {
798                int ctrl = NAND_NCE | NAND_ALE;
799
800                /* Serially input address */
801                if (column != -1) {
802                        ctrl |= NAND_ALE_COL;
803
804                        /* Adjust columns for 16 bit buswidth */
805                        if (chip->options & NAND_BUSWIDTH_16)
806                                column >>= 1;
807
808                        chip->cmd_ctrl(mtd, column, ctrl);
809                }
810
811                if (page_addr != -1) {
812                        ctrl &= ~NAND_ALE_COL;
813                        ctrl |= NAND_ALE_ROW;
814
815                        chip->cmd_ctrl(mtd, page_addr, ctrl);
816                }
817        }
818
819        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
820
821        /*
822         * program and erase have their own busy handlers
823         * status, sequential in, and deplete1 need no delay
824         */
825        switch (command) {
826
827        case NAND_CMD_CACHEDPROG:
828        case NAND_CMD_PAGEPROG:
829        case NAND_CMD_ERASE1:
830        case NAND_CMD_ERASE2:
831        case NAND_CMD_SEQIN:
832        case NAND_CMD_RNDIN:
833        case NAND_CMD_STATUS:
834        case NAND_CMD_DEPLETE1:
835                return;
836
837        /*
838         * read error status commands require only a short delay
839         */
840        case NAND_CMD_STATUS_ERROR:
841        case NAND_CMD_STATUS_ERROR0:
842        case NAND_CMD_STATUS_ERROR1:
843        case NAND_CMD_STATUS_ERROR2:
844        case NAND_CMD_STATUS_ERROR3:
845                udelay(chip->chip_delay);
846                return;
847
848        case NAND_CMD_RESET:
849                if (chip->dev_ready)
850                        break;
851
852                udelay(chip->chip_delay);
853
854                chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_NCE | NAND_CLE);
855                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
856
857                while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
858                return;
859
860        case NAND_CMD_RNDOUT:
861                /* No ready / busy check necessary */
862                chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_NCE | NAND_CLE);
863                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
864                return;
865
866        case NAND_CMD_READ0:
867                chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_NCE | NAND_CLE);
868                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
869
870        /* This applies to read commands */
871        default:
872                /*
873                 * If we don't have access to the busy pin, we apply the given
874                 * command delay
875                 */
876                if (!chip->dev_ready) {
877                        udelay(chip->chip_delay);
878                        return;
879                }
880        }
881
882        /* Apply this short delay always to ensure that we do wait tWB in
883         * any case on any machine.
884         */
885        ndelay(100);
886
887        nand_wait_ready(mtd);
888}
889
890/**
891 * brcmnand_command - [DEFAULT] Send command to NAND device
892 * @mtd:        MTD device structure
893 * @command:    the command to be sent
894 * @column:     the column address for this command, -1 if none
895 * @page_addr:  the page address for this command, -1 if none
896 *
897 * Send command to NAND device. This function is used for small page
898 * devices (256/512 Bytes per page)
899 */
900static void
901brcmnand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
902{
903        register struct nand_chip *chip = mtd_to_nand(mtd);
904        int ctrl = NAND_CTRL_CLE;
905
906        /* Invoke large page command function */
907        if (mtd->writesize > 512) {
908                brcmnand_command_lp(mtd, command, column, page_addr);
909                return;
910        }
911
912        /*
913         * Write out the command to the device.
914         */
915        if (command == NAND_CMD_SEQIN) {
916                int readcmd;
917
918                if (column >= mtd->writesize) {
919                        /* OOB area */
920                        column -= mtd->writesize;
921                        readcmd = NAND_CMD_READOOB;
922                } else if (column < 256) {
923                        /* First 256 bytes --> READ0 */
924                        readcmd = NAND_CMD_READ0;
925                } else {
926                        column -= 256;
927                        readcmd = NAND_CMD_READ1;
928                }
929
930                chip->cmd_ctrl(mtd, readcmd, ctrl);
931        }
932
933        chip->cmd_ctrl(mtd, command, ctrl);
934
935        /*
936         * Address cycle, when necessary
937         */
938        ctrl = NAND_CTRL_ALE;
939
940        /* Serially input address */
941        if (column != -1) {
942                ctrl |= NAND_ALE_COL;
943
944                /* Adjust columns for 16 bit buswidth */
945                if (chip->options & NAND_BUSWIDTH_16)
946                        column >>= 1;
947
948                chip->cmd_ctrl(mtd, column, ctrl);
949        }
950
951        if (page_addr != -1) {
952                ctrl &= ~NAND_ALE_COL;
953                ctrl |= NAND_ALE_ROW;
954
955                chip->cmd_ctrl(mtd, page_addr, ctrl);
956        }
957
958        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
959
960        /*
961         * program and erase have their own busy handlers
962         * status and sequential in needs no delay
963         */
964        switch (command) {
965
966        case NAND_CMD_PAGEPROG:
967        case NAND_CMD_ERASE1:
968        case NAND_CMD_ERASE2:
969        case NAND_CMD_SEQIN:
970        case NAND_CMD_STATUS:
971                return;
972
973        case NAND_CMD_RESET:
974                if (chip->dev_ready)
975                        break;
976
977                udelay(chip->chip_delay);
978
979                chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_CTRL_CLE);
980
981                chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
982
983                while (!(chip->read_byte(mtd) & NAND_STATUS_READY));
984
985                return;
986
987                /* This applies to read commands */
988        default:
989                /*
990                 * If we don't have access to the busy pin, we apply the given
991                 * command delay
992                 */
993                if (!chip->dev_ready) {
994                        udelay(chip->chip_delay);
995                        return;
996                }
997        }
998
999        /* Apply this short delay always to ensure that we do wait tWB in
1000         * any case on any machine.
1001         */
1002        ndelay(100);
1003
1004        nand_wait_ready(mtd);
1005}
1006
1007#endif
1008
1009
1010#ifdef CONFIG_MTD
1011struct mtd_partition brcmnand_parts[] = {
1012        {
1013                .name = "ddwrt",
1014                .size = 0,
1015                .offset = 0
1016        },
1017        {
1018                .name = 0,
1019                .size = 0,
1020                .offset = 0
1021        }
1022};
1023
1024struct mtd_partition *
1025init_brcmnand_mtd_partitions(struct mtd_info *mtd, size_t size)
1026{
1027        int knldev;
1028        int offset = 0;
1029        struct nand_chip *chip = mtd_to_nand(mtd);
1030        struct brcmnand_mtd *brcmnand = chip->priv;
1031        int isbufdual=0;
1032        uint boardnum = bcm_strtoul(nvram_safe_get("boardnum"), NULL, 0);
1033
1034        knldev = soc_knl_dev((void *)brcmnand->sih);
1035        if (knldev == SOC_KNLDEV_NANDFLASH)
1036                offset = NFL_BOOT_OS_SIZE;
1037
1038        if ((!strncmp(nvram_safe_get("boardnum"),"2013",4) || !strncmp(nvram_safe_get("boardnum"),"2014",4)) && nvram_match("boardtype", "0x0646")
1039            && nvram_match("boardrev", "0x1110")) {
1040                printk(KERN_EMERG "Buffalo WZR-900DHP dualboot\n");
1041                isbufdual = 1;
1042        }
1043
1044        if (boardnum == 1 && nvram_match("boardtype","0xD646") && nvram_match("boardrev","0x1100")) {
1045                offset = 0x4000000;
1046               
1047        }
1048
1049        if (((boardnum == 1) || (nvram_get("boardnum") == NULL)) && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1100") && !strncmp(nvram_safe_get("modelNumber"),"EA6400",6)) {
1050                offset = 0x4000000;
1051        }
1052
1053        if (((boardnum == 1) || (nvram_get("boardnum") == NULL)) && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1100") && !strncmp(nvram_safe_get("modelNumber"),"EA6300",6)) {
1054                offset = 0x4000000;
1055        }
1056
1057        if (nvram_match("model","RT-AC87U")) {
1058                printk(KERN_EMERG "Asus AC87U\n");
1059                offset = 0x4000000;
1060        }
1061
1062        if (boardnum == 1 && nvram_match("boardtype","0xF646") && nvram_match("boardrev","0x1100")) {
1063                offset = 0x4000000;
1064               
1065        }
1066
1067        if (nvram_get("bootpartition") && isbufdual) {
1068                offset = 0x4800000;
1069                size -= 0x100000;
1070        }
1071       
1072        if (boardnum == 32 && nvram_match("boardtype", "0x0665") && nvram_match("boardrev", "0x1301")) {
1073                offset = 0x2240000;
1074        }
1075       
1076        if (boardnum == 32 && nvram_match("boardtype", "0x0665") && nvram_match("boardrev", "0x1101")) {
1077                offset = 0x2680000;
1078        }
1079        ASSERT(size > offset);
1080
1081        if (boardnum == 00 && nvram_match("boardtype", "0x0665")
1082            && nvram_match("boardrev", "0x1103")
1083            && nvram_match("melco_id", "RD_BB13049")) {
1084                printk(KERN_EMERG "Buffalo WXR-1900DHP dualboot part\n");
1085                isbufdual = 1;
1086                offset = 0x6000000;
1087                size -= 0x100000;
1088        }
1089       
1090        if (boardnum == 32 && nvram_match("boardtype", "0x0646") && nvram_match("boardrev", "0x1601")) {
1091                size   -= 0x1000000;
1092        }
1093       
1094        if (boardnum == 32 && nvram_match("boardtype", "0x072F") && nvram_match("boardrev", "0x1101")) {
1095                size   -= 0x1000000;
1096        }
1097
1098        brcmnand_parts[0].offset = offset;
1099        brcmnand_parts[0].size = size - offset;
1100
1101        return brcmnand_parts;
1102}
1103#endif /* CONFIG_MTD_PARTITIONS */
1104
1105static int __init
1106brcmnand_mtd_init(void)
1107{
1108        int ret = 0;
1109        unsigned chip_num;
1110        hndnand_t *nfl;
1111        struct nand_chip *chip;
1112        struct mtd_info *mtd;
1113#ifdef CONFIG_MTD
1114        struct mtd_partition *parts;
1115        int i;
1116#endif
1117        uint32 *offset;
1118        uint32 reg, size, block, page, ecc_level;
1119
1120        printk(KERN_INFO "%s, Version %s (c) Broadcom Inc. 2012\n",
1121                DRV_DESC, DRV_VERSION);
1122
1123        memset(&brcmnand, 0, sizeof(struct brcmnand_mtd));
1124
1125        /* attach to the backplane */
1126        if (!(brcmnand.sih = si_kattach(SI_OSH))) {
1127                printk(KERN_ERR "brcmnand: error attaching to backplane\n");
1128                ret = -EIO;
1129                goto fail;
1130        }
1131
1132        /* Initialize serial flash access */
1133        if (!(nfl = hndnand_init(brcmnand.sih))) {
1134                printk(KERN_ERR "brcmnand: found no supported devices\n");
1135                ret = -ENODEV;
1136                goto fail;
1137        }
1138
1139        brcmnand.nfl = nfl;
1140
1141        /* Software variables init */
1142        mtd = &brcmnand.mtd;
1143        chip = &brcmnand.chip;
1144
1145        mtd->priv = chip;
1146        mtd->owner = THIS_MODULE;
1147        mtd->name = DRV_NAME;
1148
1149        chip->priv = &brcmnand;
1150        chip->controller = nand_hwcontrol_lock_init();
1151        if (!chip->controller) {
1152                ret = -ENOMEM;
1153                goto fail;
1154        }
1155
1156        chip->chip_delay = 5;   /* not used */
1157        chip->IO_ADDR_R = chip->IO_ADDR_W = (void *)~0L;
1158
1159        /* CS0 device width */
1160        if (nfl->width)
1161                chip->options |= NAND_BUSWIDTH_16;
1162
1163        chip->options |= NAND_NO_SUBPAGE_WRITE; /* Subpages unsupported */
1164
1165        chip->ecc.mode = NAND_ECC_HW;
1166
1167        chip->dev_ready = brcmnand_dev_ready;
1168        chip->read_byte = brcmnand_read_byte;
1169        chip->read_word = brcmnand_read_word;
1170        chip->ecc.read_page_raw = brcmnand_read_page_raw;
1171        chip->ecc.write_page_raw = brcmnand_write_page_raw;
1172        chip->ecc.read_page = brcmnand_read_page_ecc;
1173        chip->ecc.write_page = brcmnand_write_page_ecc;
1174        chip->ecc.read_oob = brcmnand_read_oob;
1175        chip->ecc.write_oob = brcmnand_write_oob;
1176        chip->ecc.strength = 1;
1177        chip->select_chip = brcmnand_select_chip;
1178#ifdef CONFIG_MIPS_BRCM
1179        chip->cmdfunc = brcmnand_command;
1180#else
1181        chip->cmdfunc = brcmnand_cmdfunc;
1182#endif
1183        chip->waitfunc = brcmnand_waitfunc;
1184        chip->read_buf = (void *)brcmnand_dummy_func;
1185        chip->write_buf = (void *)brcmnand_dummy_func;
1186
1187        if (brcmnand_scan(mtd)) {
1188                ret = -ENXIO;
1189                goto fail;
1190        }
1191
1192#ifdef CONFIG_MTD
1193        parts = init_brcmnand_mtd_partitions(&brcmnand.mtd, brcmnand.mtd.size);
1194        if (!parts)
1195                goto fail;
1196
1197        for (i = 0; parts[i].name; i++);
1198
1199        ret = add_mtd_partitions(&brcmnand.mtd, parts, i);
1200        if (ret < 0) {
1201                pr_debug( "%s: failed to add mtd partitions\n", __func__);
1202                goto fail;
1203        }
1204
1205        brcmnand.parts = parts;
1206#endif /* CONFIG_MTD_PARTITIONS */
1207
1208        return 0;
1209
1210fail:
1211        return ret;
1212}
1213
1214static void __exit
1215brcmnand_mtd_exit(void)
1216{
1217#ifdef CONFIG_MTD
1218        del_mtd_partitions(&brcmnand.mtd);
1219#else
1220        del_mtd_device(&brcmnand.mtd);
1221#endif
1222}
1223
1224late_initcall(brcmnand_mtd_init);
1225module_exit(brcmnand_mtd_exit);
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