source: src/linux/universal/linux-4.9/drivers/mtd/devices/spiflash.c @ 31630

Last change on this file since 31630 was 31630, checked in by brainslayer, 12 days ago

new fs is compatible with standard squashfs, just smaller

File size: 22.5 KB
Line 
1
2/*
3 * MTD driver for the SPI Flash Memory support.
4 *
5 * Copyright (c) 2005-2006 Atheros Communications Inc.
6 * Copyright (C) 2006-2007 FON Technology, SL.
7 * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
9 * Copyright (C) 2008 Sebastian Gottschall <s.gottschall@newmedia-net.de>
10 *
11 * This code is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17/*===========================================================================
18** !!!!  VERY IMPORTANT NOTICE !!!!  FLASH DATA STORED IN LITTLE ENDIAN FORMAT
19**
20** This module contains the Serial Flash access routines for the Atheros SOC.
21** The Atheros SOC integrates a SPI flash controller that is used to access
22** serial flash parts. The SPI flash controller executes in "Little Endian"
23** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
24** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
25** ONLY byteswapping when accessed via the SPI Flash Alias memory region
26** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
27** flash sectors is stored in "Little Endian" format.
28**
29** The spiflash_write() routine performs byteswapping on all write
30** operations.
31**===========================================================================*/
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/types.h>
36#include <linux/version.h>
37#include <linux/errno.h>
38#include <linux/slab.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/partitions.h>
41#include <linux/platform_device.h>
42#include <linux/sched.h>
43#include <linux/magic.h>
44#include <linux/root_dev.h>
45#include <linux/delay.h>
46#include <linux/proc_fs.h>
47#include <asm/delay.h>
48#include <asm/io.h>
49#include "spiflash.h"
50#include "../mtdcore.h"
51
52#ifndef __BIG_ENDIAN
53#error This driver currently only works with big endian CPU.
54#endif
55
56#define MAX_PARTS 32
57
58#define SPIFLASH "spiflash: "
59
60#define MIN(a,b)        ((a) < (b) ? (a) : (b))
61
62#define busy_wait(condition, wait) \
63        do { \
64                while (condition) { \
65                        spin_unlock_bh(&spidata->mutex); \
66                        if (wait > 1) \
67                                msleep(wait); \
68                        else if ((wait == 1) && need_resched()) \
69                                schedule(); \
70                        else \
71                                udelay(1); \
72                        spin_lock_bh(&spidata->mutex); \
73                } \
74        } while (0)
75               
76
77static __u32 spiflash_regread32(int reg);
78static void spiflash_regwrite32(int reg, __u32 data);
79static __u32 spiflash_sendcmd (int op, u32 addr);
80
81int __init spiflash_init (void);
82void __exit spiflash_exit (void);
83static int spiflash_probe_chip (void);
84static int spiflash_erase (struct mtd_info *mtd,struct erase_info *instr);
85static int spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf);
86static int spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf);
87
88/* Flash configuration table */
89struct flashconfig {
90    __u32 byte_cnt;
91    __u32 sector_cnt;
92    __u32 sector_size;
93    __u32 cs_addrmask;
94} flashconfig_tbl[MAX_FLASH] =
95    {
96        { 0, 0, 0, 0},
97        { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0},
98        { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0},
99        { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0},
100        { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0},
101        { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE, 0x0}
102    };
103
104/* Mapping of generic opcodes to STM serial flash opcodes */
105#define SPI_WRITE_ENABLE    0
106#define SPI_WRITE_DISABLE   1
107#define SPI_RD_STATUS       2
108#define SPI_WR_STATUS       3
109#define SPI_RD_DATA         4
110#define SPI_FAST_RD_DATA    5
111#define SPI_PAGE_PROGRAM    6
112#define SPI_SECTOR_ERASE    7
113#define SPI_BULK_ERASE      8
114#define SPI_DEEP_PWRDOWN    9
115#define SPI_RD_SIG          10
116#define SPI_MAX_OPCODES     11
117
118struct opcodes {
119    __u16 code;
120    __s8 tx_cnt;
121    __s8 rx_cnt;
122} stm_opcodes[] = {
123        {STM_OP_WR_ENABLE, 1, 0},
124        {STM_OP_WR_DISABLE, 1, 0},
125        {STM_OP_RD_STATUS, 1, 1},
126        {STM_OP_WR_STATUS, 1, 0},
127        {STM_OP_RD_DATA, 4, 4},
128        {STM_OP_FAST_RD_DATA, 5, 0},
129        {STM_OP_PAGE_PGRM, 8, 0},
130        {STM_OP_SECTOR_ERASE, 4, 0},
131        {STM_OP_BULK_ERASE, 1, 0},
132        {STM_OP_DEEP_PWRDOWN, 1, 0},
133        {STM_OP_RD_SIG, 4, 1},
134};
135
136/* Driver private data structure */
137struct spiflash_data {
138        struct  mtd_info       *mtd;   
139        struct  mtd_partition  *parsed_parts;     /* parsed partitions */
140        void    *readaddr; /* memory mapped data for read  */
141        void    *mmraddr;  /* memory mapped register space */
142        wait_queue_head_t wq;
143        spinlock_t mutex;
144        int state;
145};
146enum {
147        FL_READY,
148        FL_READING,
149        FL_ERASING,
150        FL_WRITING
151};
152
153static struct spiflash_data *spidata;
154
155extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
156
157#ifdef CONFIG_MTD_SPIFLASH_PP
158/*
159 * With AR2317, WRG-G19, we add the external circuit to implement page
160 * programming. The GPIO 0 is used to control the chip select of the SPI
161 * interface. The chip select is low active.
162 *
163 *                                                              david_hsieh@alphanetworks.com
164 */
165
166/* The following part is cut from arch/mips/ar531x/ar531x.h */
167
168#include <asm/addrspace.h>
169
170#define AR5315_DSLBASE          0xB1000000      /* RESET CONTROL MMR */
171
172/* GPIO */
173#define AR5315_GPIO_DI          (AR5315_DSLBASE + 0x0088)
174#define AR5315_GPIO_DO          (AR5315_DSLBASE + 0x0090)
175#define AR5315_GPIO_CR          (AR5315_DSLBASE + 0x0098)
176#define AR5315_GPIO_INT         (AR5315_DSLBASE + 0x00a0)
177
178/* Chip Select GPIO for Page Programming */
179#ifndef CONFIG_MTD_SPIFLASH_PP_GPIO
180#define CONFIG_MTD_SPIFLASH_PP_GPIO 0
181#endif
182#define SPI_CS_BIT_MASK (1 << CONFIG_MTD_SPIFLASH_PP_GPIO)
183
184typedef unsigned int AR531X_REG;
185#define sysRegRead(phys)                (*(volatile AR531X_REG *)KSEG1ADDR(phys))
186#define sysRegWrite(phys, val)  ((*(volatile AR531X_REG *)KSEG1ADDR(phys)) = (val))
187
188static atomic_t spiflash_cs = ATOMIC_INIT(0);
189
190static inline void chip_select(int value)
191{
192        __u32 reg;
193
194        /* Set GPIO 0 as output. */
195        reg = sysRegRead(AR5315_GPIO_CR);
196        reg |= SPI_CS_BIT_MASK;
197        sysRegWrite(AR5315_GPIO_CR, reg);
198
199        /* Set GPIO 0 data. */
200        reg = sysRegRead(AR5315_GPIO_DO);
201        if (value) reg |= SPI_CS_BIT_MASK;
202        else reg &= ~SPI_CS_BIT_MASK;
203        sysRegWrite(AR5315_GPIO_DO, reg);
204}
205
206#define SET_SPI_ACTIVITY()                                              \
207{                                                                                               \
208}
209
210#define CLEAR_SPI_ACTIVITY()                                    \
211{                                                                                               \
212        chip_select(1);                                                         \
213}
214
215#else
216
217#define SET_SPI_ACTIVITY()
218#define CLEAR_SPI_ACTIVITY()
219
220#endif
221
222
223
224/***************************************************************************************************/
225
226static __u32
227spiflash_regread32(int reg)
228{
229        volatile __u32 *data = (__u32 *)(spidata->mmraddr + reg);
230
231        return (*data);
232}
233
234static void
235spiflash_regwrite32(int reg, __u32 data)
236{
237        volatile __u32 *addr = (__u32 *)(spidata->mmraddr + reg);
238
239        *addr = data;
240        return;
241}
242
243
244static __u32
245spiflash_sendcmd (int op, u32 addr)
246{
247         u32 reg;
248         u32 mask;
249        struct opcodes *ptr_opcode;
250
251        ptr_opcode = &stm_opcodes[op];
252        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
253        spiflash_regwrite32(SPI_FLASH_OPCODE, ((u32) ptr_opcode->code) | (addr << 8));
254
255        reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
256                (ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
257
258        spiflash_regwrite32(SPI_FLASH_CTL, reg);
259
260        busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);
261 
262        if (!ptr_opcode->rx_cnt)
263                return 0;
264
265        reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
266
267        switch (ptr_opcode->rx_cnt) {
268        case 1:
269                        mask = 0x000000ff;
270                        break;
271        case 2:
272                        mask = 0x0000ffff;
273                        break;
274        case 3:
275                        mask = 0x00ffffff;
276                        break;
277        default:
278                        mask = 0xffffffff;
279                        break;
280        }
281        reg &= mask;
282
283        return reg;
284}
285
286
287
288/* Probe SPI flash device
289 * Function returns 0 for failure.
290 * and flashconfig_tbl array index for success.
291 */
292static int
293spiflash_probe_chip (void)
294{
295        __u32 sig;
296        int flash_size;
297       
298        /* Read the signature on the flash device */
299        spin_lock_bh(&spidata->mutex);
300        sig = spiflash_sendcmd(SPI_RD_SIG, 0);
301        spin_unlock_bh(&spidata->mutex);
302
303        switch (sig) {
304        case STM_8MBIT_SIGNATURE:
305                flash_size = FLASH_1MB;
306                break;
307        case STM_16MBIT_SIGNATURE:
308                flash_size = FLASH_2MB;
309                break;
310        case STM_32MBIT_SIGNATURE:
311                flash_size = FLASH_4MB;
312                break;
313        case STM_64MBIT_SIGNATURE:
314                flash_size = FLASH_8MB;
315                break;
316        case STM_128MBIT_SIGNATURE:
317                flash_size = FLASH_16MB;
318                break;
319        default:
320                printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
321                return (0);
322        }
323
324        return (flash_size);
325}
326
327
328/* wait until the flash chip is ready and grab a lock */
329static int spiflash_wait_ready(int state)
330{
331        DECLARE_WAITQUEUE(wait, current);
332
333retry:
334        spin_lock_bh(&spidata->mutex);
335        if (spidata->state != FL_READY) {
336                set_current_state(TASK_UNINTERRUPTIBLE);
337                add_wait_queue(&spidata->wq, &wait);
338                spin_unlock_bh(&spidata->mutex);
339                schedule();
340                remove_wait_queue(&spidata->wq, &wait);
341               
342                if(signal_pending(current))
343                        return 0;
344
345       
346                goto retry;
347        }
348        spidata->state = state;
349
350        return 1;
351}
352
353static inline void spiflash_done(void)
354{
355        spidata->state = FL_READY;
356        spin_unlock_bh(&spidata->mutex);
357        wake_up(&spidata->wq);
358}
359
360static int
361spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
362{
363        struct opcodes *ptr_opcode;
364        __u32 temp, reg;
365        int finished = 0;
366        unsigned int addr = instr->addr;
367
368#ifdef SPIFLASH_DEBUG
369        printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n",__FUNCTION__,instr->addr,instr->len);
370#endif
371
372        /* sanity checks */
373        if (instr->addr + instr->len > mtd->size) return (-EINVAL);
374        if (!spiflash_wait_ready(FL_ERASING))
375                return -EINTR;
376for (addr=instr->addr;addr<instr->addr+instr->len;addr+=mtd->erasesize)
377{
378
379        ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
380
381        temp = ((__u32)addr << 8) | (__u32)(ptr_opcode->code);
382        spiflash_sendcmd(SPI_WRITE_ENABLE,0);
383        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
384
385        spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
386
387        reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
388        spiflash_regwrite32(SPI_FLASH_CTL, reg);
389
390        busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
391}
392        spiflash_done();
393
394        instr->state = MTD_ERASE_DONE;
395        if (instr->callback) instr->callback (instr);
396#ifdef SPIFLASH_DEBUG
397        printk (KERN_DEBUG "%s return\n",__FUNCTION__);
398#endif
399        return (0);
400}
401
402static int
403spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
404{
405        u8 *read_addr;
406       
407        /* sanity checks */
408        if (!len) return (0);
409        if (from + len > mtd->size) return (-EINVAL);
410       
411        /* we always read len bytes */
412        *retlen = len;
413
414        if (!spiflash_wait_ready(FL_READING))
415                return -EINTR;
416        read_addr = (u8 *)(spidata->readaddr + from);
417        memcpy(buf, read_addr, len);
418        spiflash_done();
419
420        return 0;
421}
422
423static int
424spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
425{
426        u32 opcode, bytes_left;
427
428        *retlen = 0;
429
430        /* sanity checks */
431        if (!len) return (0);
432        if (to + len > mtd->size) return (-EINVAL);
433       
434        opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
435        bytes_left = len;
436       
437        do {
438                u32 xact_len, reg, page_offset, spi_data = 0;
439
440                xact_len = MIN(bytes_left, sizeof(__u32));
441
442                /* 32-bit writes cannot span across a page boundary
443                 * (256 bytes). This types of writes require two page
444                 * program operations to handle it correctly. The STM part
445                 * will write the overflow data to the beginning of the
446                 * current page as opposed to the subsequent page.
447                 */
448                page_offset = (to & (STM_PAGE_SIZE - 1)) + xact_len;
449
450                if (page_offset > STM_PAGE_SIZE) {
451                        xact_len -= (page_offset - STM_PAGE_SIZE);
452                }
453
454                if (!spiflash_wait_ready(FL_WRITING))
455                        return -EINTR;
456
457                spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
458                switch (xact_len) {
459                        case 1:
460                                spi_data = (u32) ((u8) *buf);
461                                break;
462                        case 2:
463                                spi_data = (buf[1] << 8) | buf[0];
464                                break;
465                        case 3:
466                                spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
467                                break;
468                        case 4:
469                                spi_data = (buf[3] << 24) | (buf[2] << 16) |
470                                                        (buf[1] << 8) | buf[0];
471                                break;
472                        default:
473                                spi_data = 0;
474                                break;
475                }
476
477                spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
478                opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
479                spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
480
481                reg = spiflash_regread32(SPI_FLASH_CTL);
482                reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
483                spiflash_regwrite32(SPI_FLASH_CTL, reg);
484
485                /* give the chip some time before we start busy waiting */
486                spin_unlock_bh(&spidata->mutex);
487                schedule();
488                spin_lock_bh(&spidata->mutex);
489
490                busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 0);
491                spiflash_done();
492
493                bytes_left -= xact_len;
494                to += xact_len;
495                buf += xact_len;
496
497                *retlen += xact_len;
498        } while (bytes_left != 0);
499
500        return 0;
501}
502
503#ifdef CONFIG_MTD_SPIFLASH_PP
504
505static void page_write(loff_t to, const u_char * buf)
506{
507        __u32   reg, spi_data, opcode;
508        int             i;
509
510
511        /* We are going to write flash now, do write enable first. */
512        spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
513
514        /* we are not really waiting for CPU spiflash activity, just need the value of the register. */
515        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
516
517        /* Prepare SPI opcode, data and control register values. */
518        opcode   = (stm_opcodes[SPI_PAGE_PROGRAM].code & SPI_OPCODE_MASK) | ((__u32)to << 8);
519        spi_data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; buf += 4;
520        reg      = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 0x8 | SPI_CTL_START;
521
522        /* wait and mark our activity */
523        if (!spiflash_wait_ready(FL_WRITING))
524                return -EINTR;
525        SET_SPI_ACTIVITY();
526        chip_select(0);
527
528        /* Send out the the first 4 bytes. */
529        spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
530        spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
531        spiflash_regwrite32(SPI_FLASH_CTL, reg);
532
533        /* 31 loops, each loop send 8 bytes */
534        for (i=0; i<31; i++)
535        {
536                busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
537
538                /*
539                 * The sample code from the application node is:
540                 *
541                 *      spi_data = (UINT32)*((UINT32 *)buf);
542                 *      spi_data = cpi2le32(spi_data);
543                 *      spi_data_swapped =
544                 *                      (((spi_data>>8) & 0xff) << 24) |
545                 *                      (((spi_data>>24)& 0xff) << 8) |
546                 *                      (spi_data & 0x00ff00ff);
547                 */
548                opcode   = (buf[3] <<  8) | (buf[2] << 16) | (buf[1] << 24) | buf[0]; buf += 4;
549                spi_data = (buf[3] << 24) | (buf[2] << 16) | (buf[1] <<  8) | buf[0]; buf += 4;
550                reg      = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 0x8 | SPI_CTL_START;
551
552                spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
553                spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
554                spiflash_regwrite32(SPI_FLASH_CTL, reg);
555        }
556
557        /* send out the last 4 bytes */
558        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
559
560        opcode   = (buf[3] <<  8) | (buf[2] << 16) | (buf[1] << 24) | buf[0]; buf += 4;
561        reg      = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 0x4 | SPI_CTL_START;
562
563        spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
564        spiflash_regwrite32(SPI_FLASH_CTL, reg);
565
566        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
567
568        /* Deactive chip select */
569        chip_select(1);
570        /* clean our activity */
571        CLEAR_SPI_ACTIVITY();
572       
573
574        busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
575        spiflash_done();
576        return;
577}
578
579/*
580 * Do page programming test.
581 * The 'block' should be erase already.
582 * We try to use page programming mode to write flash,
583 * and erase this block again before return.
584 */
585static int test_page_programming(struct mtd_info * mtd, loff_t block)
586{
587        unsigned char   buffer[256];
588        unsigned char * flash;
589        struct opcodes *ptr_opcode;
590        __u32                   opcode, reg;
591        int                             i;
592
593
594        /* write the flash with known pattern */
595        for (i=0; i<256; i++) buffer[i] = (unsigned char)i;
596        page_write(block, buffer);
597        if (!spiflash_wait_ready(FL_WRITING))
598                return -EINTR;
599
600        /* wait and mark our activity */
601        SET_SPI_ACTIVITY();
602       
603        /* read it back and check pattern */
604        flash = (unsigned char *)(spidata->readaddr + block);
605        printk(KERN_EMERG "%s(): checking @ 0x%.8x ...\n",__FUNCTION__,(__u32)flash);
606        for (i = 0; i < 8; i++)
607        {
608                if (flash[i*4] != (unsigned char)(i*4))
609                {
610                        printk(KERN_EMERG "unexpected value @ %d: 0x%02x !!\n", i*4, flash[i*4]);
611                        break;
612                }
613        }
614
615        /* clean our activity */
616        CLEAR_SPI_ACTIVITY();
617        udelay(10);
618       
619        /* erase this block before return */
620        printk(KERN_EMERG "%s(): erasing block 0x%.8x ...\n",__FUNCTION__,(__u32)block);
621
622        /* we are going to erase sector, do write enable first */
623        spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
624
625        /* wait and mark our activity */
626        SET_SPI_ACTIVITY();
627
628        /* we are not really waiting for CPU spiflash activity, just need the value of the register. */
629        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
630
631        /* send sector erase op. */
632        ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
633        opcode = ((__u32)ptr_opcode->code) | ((__u32)block << 8);
634        spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
635        reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
636        spiflash_regwrite32(SPI_FLASH_CTL, reg);
637
638        /* wait for CPU spiflash activity */
639        busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
640        /* clean our activity */
641        CLEAR_SPI_ACTIVITY();
642        udelay(10);
643
644        busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
645        spiflash_done();
646        printk("SPI flash write test done (%d)!, page programming is %s!\n", i, i<8 ? "disabled":"enabled");
647        return (i<8 ? 1:0);
648}
649
650static int pp_mode = -1;
651static int pp_enable = 1;
652
653/* implementation for spiflash page programing. */
654static int spiflash_page_write(struct mtd_info * mtd,
655                loff_t to, size_t len, size_t * retlen, const u_char * buf)
656{
657        size_t bytes_left = len;
658        size_t xact_len;
659        size_t written;
660        size_t offset;
661
662
663        /* If we already test page programming and failed,
664         * fall back to spiflash_write() directly. */
665        if (pp_mode > 0) return spiflash_write(mtd, to, len, retlen, buf);
666
667        *retlen = 0;
668        if (to + len > mtd->size) return (-EINVAL);
669
670        while (bytes_left > 0)
671        {
672                offset = to % STM_PAGE_SIZE;
673                xact_len = MIN(bytes_left, STM_PAGE_SIZE - offset);
674                if (offset > 0 || xact_len < STM_PAGE_SIZE)
675                {
676                        spiflash_write(mtd, to, xact_len, &written, buf);
677                }
678                else
679                {
680                        /* test page program mode, if we did not test it before. */
681                        if (pp_mode < 0) pp_mode = test_page_programming(mtd, to);
682
683                        if (pp_enable && (pp_mode == 0)) page_write(to, buf);
684                        else spiflash_write(mtd, to, xact_len, &written, buf);
685                }
686                to += xact_len;
687                bytes_left -= xact_len;
688                buf += xact_len;
689                *retlen += xact_len;
690        }
691
692        return 0;
693}
694
695static int __my_atoi(const char * buf)
696{
697        int ret = 0;
698        while (*buf)
699        {
700                if (*buf >= '0' && *buf <= '9') ret += (int)(*buf - '0');
701                buf++;
702        }
703        return ret;
704}
705
706static int proc_read_pp_enable(char * buf, char ** start, off_t offset,
707                int len, int * eof, void * data)
708{
709        char * p = buf;
710        p += sprintf(p, "%d\n", pp_enable);
711        *eof = 1;
712        return p - buf;
713}
714
715static int proc_write_pp_enable(struct file * file, const char * buf,
716                unsigned long count, void * data)
717{
718        pp_enable = __my_atoi(buf);
719        printk("spiflash: %s page programming!\n", pp_enable ? "enable" : "disable");
720        if (pp_mode >= 0) printk("spiflash: H/W is %scapable of doing page programming!\n", pp_mode ? "not " : "");
721        return count;
722}
723
724static struct proc_dir_entry * root = NULL;
725static struct proc_dir_entry * pp_enable_entry = NULL;
726
727static int register_spi_proc(void)
728{
729        root = proc_mkdir("spiflash", NULL);
730        if (root == NULL)
731        {
732                printk("spiflash: fail to create /proc/spiflash !!\n");
733                return -1;
734        }
735        pp_enable_entry = create_proc_entry("pp_enable", 0644, root);
736        if (pp_enable_entry == NULL)
737        {
738                printk("spiflash: fail to create /proc/spiflash/pp_enable !!\n");
739                remove_proc_entry("spiflash", root);
740                root = NULL;
741                return -1;
742        }
743        pp_enable_entry->data = 0;
744        pp_enable_entry->read_proc = proc_read_pp_enable;
745        pp_enable_entry->write_proc = proc_write_pp_enable;
746        pp_enable_entry->owner = THIS_MODULE;
747        printk("spiflash: /proc/spiflash/pp_enable created !!\n");
748        return 0;
749}
750
751static void remove_spi_proc(void)
752{
753        if (pp_enable_entry) remove_proc_entry("pp_enable", root);
754        if (root) remove_proc_entry("spiflash", root);
755        pp_enable_entry = NULL;
756        root = NULL;
757}
758
759#endif
760
761#ifdef CONFIG_MTD
762static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
763#endif
764
765
766static int spiflash_probe(struct platform_device *pdev)
767{
768        int result = -1;
769        int index, num_parts;
770        struct mtd_info *mtd;
771
772        spidata->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
773        spin_lock_init(&spidata->mutex);
774        init_waitqueue_head(&spidata->wq);
775        spidata->state = FL_READY;
776       
777        if (!spidata->mmraddr) {
778                printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
779                kfree(spidata);
780                spidata = NULL;
781        }
782
783        mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
784        if (!mtd) {
785                kfree(spidata);
786                return -ENXIO;
787        }
788       
789        if (!(index = spiflash_probe_chip())) {
790        printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
791                goto error;
792        }
793
794        spidata->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
795        if (!spidata->readaddr) {
796                printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
797                goto error;
798        }
799
800        mtd->name = "spiflash";
801        mtd->type = MTD_NORFLASH;
802        mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
803        mtd->size = flashconfig_tbl[index].byte_cnt;
804        mtd->erasesize = flashconfig_tbl[index].sector_size;
805        mtd->writesize = 1;
806        mtd->numeraseregions = 0;
807        mtd->eraseregions = NULL;
808        mtd->_erase = spiflash_erase;
809        mtd->_read = spiflash_read;
810#ifdef CONFIG_MTD_SPIFLASH_PP
811        mtd->_write = spiflash_page_write;
812#else
813        mtd->_write = spiflash_write;
814#endif
815        mtd->owner = THIS_MODULE;
816
817        /* parse redboot partitions */
818        num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
819        if (!num_parts)
820                goto error;
821
822        result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
823
824#ifdef CONFIG_MTD_SPIFLASH_PP
825                register_spi_proc();
826#endif
827
828
829        spidata->mtd = mtd;
830       
831        return (result);
832       
833error:
834        kfree(mtd);
835        kfree(spidata);
836        return -ENXIO;
837}
838
839static int spiflash_remove (struct platform_device *pdev)
840{
841        del_mtd_partitions (spidata->mtd);
842        kfree(spidata->mtd);
843        return 0;
844}
845
846struct platform_driver spiflash_driver = {
847        .driver.name = "spiflash",
848        .probe = spiflash_probe,
849        .remove = spiflash_remove,
850};
851
852int __init
853spiflash_init (void)
854{
855        spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
856        if (!spidata)
857                return (-ENXIO);
858
859        spin_lock_init(&spidata->mutex);
860        platform_driver_register(&spiflash_driver);
861
862        return 0;
863}
864
865void __exit
866spiflash_exit (void)
867{
868        kfree(spidata);
869#ifdef CONFIG_MTD_SPIFLASH_PP
870        remove_spi_proc();
871#endif
872}
873
874module_init (spiflash_init);
875module_exit (spiflash_exit);
876
877MODULE_LICENSE("GPL");
878MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
879MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
880
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