source: src/linux/universal/linux-4.9/drivers/pci/quirks.c @ 31859

Last change on this file since 31859 was 31859, checked in by brainslayer, 6 weeks ago

kernel update

File size: 163.8 KB
Line 
1/*
2 *  This file contains work-arounds for many known PCI hardware
3 *  bugs.  Devices present only on certain architectures (host
4 *  bridges et cetera) should be handled in arch-specific code.
5 *
6 *  Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 *  Init/reset quirks for USB host controllers should be in the
11 *  USB quirks file, where their drivers can access reuse it.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/export.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/acpi.h>
21#include <linux/kallsyms.h>
22#include <linux/dmi.h>
23#include <linux/pci-aspm.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/ktime.h>
27#include <linux/mm.h>
28#include <asm/dma.h>    /* isa_dma_bridge_buggy */
29#include "pci.h"
30
31/*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37static void quirk_mmio_always_on(struct pci_dev *dev)
38{
39        dev->mmio_always_on = 1;
40}
41DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42                                PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
45/* The Mellanox Tavor device gives false positive parity errors
46 * Mark this device with a broken_parity_status, to allow
47 * PCI scanning code to "skip" this now blacklisted device.
48 */
49static void quirk_mellanox_tavor(struct pci_dev *dev)
50{
51        dev->broken_parity_status = 1;  /* This device gives false positives */
52}
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
54DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
55
56/* Deal with broken BIOSes that neglect to enable passive release,
57   which can cause problems in combination with the 82441FX/PPro MTRRs */
58static void quirk_passive_release(struct pci_dev *dev)
59{
60        struct pci_dev *d = NULL;
61        unsigned char dlc;
62
63        /* We have to make sure a particular bit is set in the PIIX3
64           ISA bridge, so we have to go out and find it. */
65        while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
66                pci_read_config_byte(d, 0x82, &dlc);
67                if (!(dlc & 1<<1)) {
68                        dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
69                        dlc |= 1<<1;
70                        pci_write_config_byte(d, 0x82, dlc);
71                }
72        }
73}
74DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
75DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
76
77/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
78    but VIA don't answer queries. If you happen to have good contacts at VIA
79    ask them for me please -- Alan
80
81    This appears to be BIOS not version dependent. So presumably there is a
82    chipset level fix */
83
84static void quirk_isa_dma_hangs(struct pci_dev *dev)
85{
86        if (!isa_dma_bridge_buggy) {
87                isa_dma_bridge_buggy = 1;
88                dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
89        }
90}
91        /*
92         * Its not totally clear which chipsets are the problematic ones
93         * We know 82C586 and 82C596 variants are affected.
94         */
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs);
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1533,         quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs);
102
103/*
104 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
105 * for some HT machines to use C4 w/o hanging.
106 */
107static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
108{
109        u32 pmbase;
110        u16 pm1a;
111
112        pci_read_config_dword(dev, 0x40, &pmbase);
113        pmbase = pmbase & 0xff80;
114        pm1a = inw(pmbase);
115
116        if (pm1a & 0x10) {
117                dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
118                outw(0x10, pmbase);
119        }
120}
121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
122
123/*
124 *      Chipsets where PCI->PCI transfers vanish or hang
125 */
126static void quirk_nopcipci(struct pci_dev *dev)
127{
128        if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
129                dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
130                pci_pci_problems |= PCIPCI_FAIL;
131        }
132}
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci);
134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci);
135
136static void quirk_nopciamd(struct pci_dev *dev)
137{
138        u8 rev;
139        pci_read_config_byte(dev, 0x08, &rev);
140        if (rev == 0x13) {
141                /* Erratum 24 */
142                dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
143                pci_pci_problems |= PCIAGP_FAIL;
144        }
145}
146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8151_0,       quirk_nopciamd);
147
148/*
149 *      Triton requires workarounds to be used by the drivers
150 */
151static void quirk_triton(struct pci_dev *dev)
152{
153        if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
154                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
155                pci_pci_problems |= PCIPCI_TRITON;
156        }
157}
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton);
162
163/*
164 *      VIA Apollo KT133 needs PCI latency patch
165 *      Made according to a windows driver based patch by George E. Breese
166 *      see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
167 *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 *      the info on which Mr Breese based his work.
169 *
170 *      Updated based on further information from the site and also on
171 *      information provided by VIA
172 */
173static void quirk_vialatency(struct pci_dev *dev)
174{
175        struct pci_dev *p;
176        u8 busarb;
177        /* Ok we have a potential problem chipset here. Now see if we have
178           a buggy southbridge */
179
180        p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
181        if (p != NULL) {
182                /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183                /* Check for buggy part revisions */
184                if (p->revision < 0x40 || p->revision > 0x42)
185                        goto exit;
186        } else {
187                p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
188                if (p == NULL)  /* No problem parts */
189                        goto exit;
190                /* Check for buggy part revisions */
191                if (p->revision < 0x10 || p->revision > 0x12)
192                        goto exit;
193        }
194
195        /*
196         *      Ok we have the problem. Now set the PCI master grant to
197         *      occur every master grant. The apparent bug is that under high
198         *      PCI load (quite common in Linux of course) you can get data
199         *      loss when the CPU is held off the bus for 3 bus master requests
200         *      This happens to include the IDE controllers....
201         *
202         *      VIA only apply this fix when an SB Live! is present but under
203         *      both Linux and Windows this isn't enough, and we have seen
204         *      corruption without SB Live! but with things like 3 UDMA IDE
205         *      controllers. So we ignore that bit of the VIA recommendation..
206         */
207
208        pci_read_config_byte(dev, 0x76, &busarb);
209        /* Set bit 4 and bi 5 of byte 76 to 0x01
210           "Master priority rotation on every PCI master grant */
211        busarb &= ~(1<<5);
212        busarb |= (1<<4);
213        pci_write_config_byte(dev, 0x76, busarb);
214        dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
215exit:
216        pci_dev_put(p);
217}
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
221/* Must restore this on a resume from RAM */
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
225
226/*
227 *      VIA Apollo VP3 needs ETBF on BT848/878
228 */
229static void quirk_viaetbf(struct pci_dev *dev)
230{
231        if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
232                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
233                pci_pci_problems |= PCIPCI_VIAETBF;
234        }
235}
236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf);
237
238static void quirk_vsfx(struct pci_dev *dev)
239{
240        if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
241                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
242                pci_pci_problems |= PCIPCI_VSFX;
243        }
244}
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx);
246
247/*
248 *      Ali Magik requires workarounds to be used by the drivers
249 *      that DMA to AGP space. Latency must be set to 0xA and triton
250 *      workaround applied too
251 *      [Info kindly provided by ALi]
252 */
253static void quirk_alimagik(struct pci_dev *dev)
254{
255        if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
256                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
257                pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
258        }
259}
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik);
261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik);
262
263/*
264 *      Natoma has some interesting boundary conditions with Zoran stuff
265 *      at least
266 */
267static void quirk_natoma(struct pci_dev *dev)
268{
269        if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
270                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
271                pci_pci_problems |= PCIPCI_NATOMA;
272        }
273}
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma);
280
281/*
282 *  This chip can cause PCI parity errors if config register 0xA0 is read
283 *  while DMAs are occurring.
284 */
285static void quirk_citrine(struct pci_dev *dev)
286{
287        dev->cfg_size = 0xA0;
288}
289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CITRINE,      quirk_citrine);
290
291/*
292 * This chip can cause bus lockups if config addresses above 0x600
293 * are read or written.
294 */
295static void quirk_nfp6000(struct pci_dev *dev)
296{
297        dev->cfg_size = 0x600;
298}
299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP4000,        quirk_nfp6000);
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP6000,        quirk_nfp6000);
301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,       PCI_DEVICE_ID_NETRONOME_NFP6000_VF,     quirk_nfp6000);
302
303/*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
304static void quirk_extend_bar_to_page(struct pci_dev *dev)
305{
306        int i;
307
308        for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
309                struct resource *r = &dev->resource[i];
310
311                if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
312                        r->end = PAGE_SIZE - 1;
313                        r->start = 0;
314                        r->flags |= IORESOURCE_UNSET;
315                        dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
316                                 i, r);
317                }
318        }
319}
320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
321
322/*
323 *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
324 *  If it's needed, re-allocate the region.
325 */
326static void quirk_s3_64M(struct pci_dev *dev)
327{
328        struct resource *r = &dev->resource[0];
329
330        if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
331                r->flags |= IORESOURCE_UNSET;
332                r->start = 0;
333                r->end = 0x3ffffff;
334        }
335}
336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_868,           quirk_s3_64M);
337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_968,           quirk_s3_64M);
338
339static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
340                     const char *name)
341{
342        u32 region;
343        struct pci_bus_region bus_region;
344        struct resource *res = dev->resource + pos;
345
346        pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
347
348        if (!region)
349                return;
350
351        res->name = pci_name(dev);
352        res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
353        res->flags |=
354                (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
355        region &= ~(size - 1);
356
357        /* Convert from PCI bus to resource space */
358        bus_region.start = region;
359        bus_region.end = region + size - 1;
360        pcibios_bus_to_resource(dev->bus, res, &bus_region);
361
362        dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
363                 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
364}
365
366/*
367 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
368 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
369 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
370 * (which conflicts w/ BAR1's memory range).
371 *
372 * CS553x's ISA PCI BARs may also be read-only (ref:
373 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
374 */
375static void quirk_cs5536_vsa(struct pci_dev *dev)
376{
377        static char *name = "CS5536 ISA bridge";
378
379        if (pci_resource_len(dev, 0) != 8) {
380                quirk_io(dev, 0,   8, name);    /* SMB */
381                quirk_io(dev, 1, 256, name);    /* GPIO */
382                quirk_io(dev, 2,  64, name);    /* MFGPT */
383                dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
384                         name);
385        }
386}
387DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
388
389static void quirk_io_region(struct pci_dev *dev, int port,
390                                unsigned size, int nr, const char *name)
391{
392        u16 region;
393        struct pci_bus_region bus_region;
394        struct resource *res = dev->resource + nr;
395
396        pci_read_config_word(dev, port, &region);
397        region &= ~(size - 1);
398
399        if (!region)
400                return;
401
402        res->name = pci_name(dev);
403        res->flags = IORESOURCE_IO;
404
405        /* Convert from PCI bus to resource space */
406        bus_region.start = region;
407        bus_region.end = region + size - 1;
408        pcibios_bus_to_resource(dev->bus, res, &bus_region);
409
410        if (!pci_claim_resource(dev, nr))
411                dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
412}
413
414/*
415 *      ATI Northbridge setups MCE the processor if you even
416 *      read somewhere between 0x3b0->0x3bb or read 0x3d3
417 */
418static void quirk_ati_exploding_mce(struct pci_dev *dev)
419{
420        dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
421        /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
422        request_region(0x3b0, 0x0C, "RadeonIGP");
423        request_region(0x3d3, 0x01, "RadeonIGP");
424}
425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
426
427/*
428 * In the AMD NL platform, this device ([1022:7912]) has a class code of
429 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
430 * claim it.
431 * But the dwc3 driver is a more specific driver for this device, and we'd
432 * prefer to use it instead of xhci. To prevent xhci from claiming the
433 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
434 * defines as "USB device (not host controller)". The dwc3 driver can then
435 * claim it based on its Vendor and Device ID.
436 */
437static void quirk_amd_nl_class(struct pci_dev *pdev)
438{
439        u32 class = pdev->class;
440
441        /* Use "USB Device (not host controller)" class */
442        pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
443        dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
444                 class, pdev->class);
445}
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
447                quirk_amd_nl_class);
448
449/*
450 * Let's make the southbridge information explicit instead
451 * of having to worry about people probing the ACPI areas,
452 * for example.. (Yes, it happens, and if you read the wrong
453 * ACPI register it will put the machine to sleep with no
454 * way of waking it up again. Bummer).
455 *
456 * ALI M7101: Two IO regions pointed to by words at
457 *      0xE0 (64 bytes of ACPI registers)
458 *      0xE2 (32 bytes of SMB registers)
459 */
460static void quirk_ali7101_acpi(struct pci_dev *dev)
461{
462        quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
463        quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
464}
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi);
466
467static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
468{
469        u32 devres;
470        u32 mask, size, base;
471
472        pci_read_config_dword(dev, port, &devres);
473        if ((devres & enable) != enable)
474                return;
475        mask = (devres >> 16) & 15;
476        base = devres & 0xffff;
477        size = 16;
478        for (;;) {
479                unsigned bit = size >> 1;
480                if ((bit & mask) == bit)
481                        break;
482                size = bit;
483        }
484        /*
485         * For now we only print it out. Eventually we'll want to
486         * reserve it (at least if it's in the 0x1000+ range), but
487         * let's get enough confirmation reports first.
488         */
489        base &= -size;
490        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
491                 base + size - 1);
492}
493
494static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
495{
496        u32 devres;
497        u32 mask, size, base;
498
499        pci_read_config_dword(dev, port, &devres);
500        if ((devres & enable) != enable)
501                return;
502        base = devres & 0xffff0000;
503        mask = (devres & 0x3f) << 16;
504        size = 128 << 16;
505        for (;;) {
506                unsigned bit = size >> 1;
507                if ((bit & mask) == bit)
508                        break;
509                size = bit;
510        }
511        /*
512         * For now we only print it out. Eventually we'll want to
513         * reserve it, but let's get enough confirmation reports first.
514         */
515        base &= -size;
516        dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
517                 base + size - 1);
518}
519
520/*
521 * PIIX4 ACPI: Two IO regions pointed to by longwords at
522 *      0x40 (64 bytes of ACPI registers)
523 *      0x90 (16 bytes of SMB registers)
524 * and a few strange programmable PIIX4 device resources.
525 */
526static void quirk_piix4_acpi(struct pci_dev *dev)
527{
528        u32 res_a;
529
530        quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
531        quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
532
533        /* Device resource A has enables for some of the other ones */
534        pci_read_config_dword(dev, 0x5c, &res_a);
535
536        piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
537        piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
538
539        /* Device resource D is just bitfields for static resources */
540
541        /* Device 12 enabled? */
542        if (res_a & (1 << 29)) {
543                piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
544                piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
545        }
546        /* Device 13 enabled? */
547        if (res_a & (1 << 30)) {
548                piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
549                piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
550        }
551        piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
552        piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
553}
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
555DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
556
557#define ICH_PMBASE      0x40
558#define ICH_ACPI_CNTL   0x44
559#define  ICH4_ACPI_EN   0x10
560#define  ICH6_ACPI_EN   0x80
561#define ICH4_GPIOBASE   0x58
562#define ICH4_GPIO_CNTL  0x5c
563#define  ICH4_GPIO_EN   0x10
564#define ICH6_GPIOBASE   0x48
565#define ICH6_GPIO_CNTL  0x4c
566#define  ICH6_GPIO_EN   0x10
567
568/*
569 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
570 *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
571 *      0x58 (64 bytes of GPIO I/O space)
572 */
573static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
574{
575        u8 enable;
576
577        /*
578         * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
579         * with low legacy (and fixed) ports. We don't know the decoding
580         * priority and can't tell whether the legacy device or the one created
581         * here is really at that address.  This happens on boards with broken
582         * BIOSes.
583        */
584
585        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
586        if (enable & ICH4_ACPI_EN)
587                quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
588                                 "ICH4 ACPI/GPIO/TCO");
589
590        pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
591        if (enable & ICH4_GPIO_EN)
592                quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
593                                "ICH4 GPIO");
594}
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,         quirk_ich4_lpc_acpi);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,         quirk_ich4_lpc_acpi);
597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,         quirk_ich4_lpc_acpi);
598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,        quirk_ich4_lpc_acpi);
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,         quirk_ich4_lpc_acpi);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,        quirk_ich4_lpc_acpi);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,         quirk_ich4_lpc_acpi);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,        quirk_ich4_lpc_acpi);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,         quirk_ich4_lpc_acpi);
604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,             quirk_ich4_lpc_acpi);
605
606static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
607{
608        u8 enable;
609
610        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
611        if (enable & ICH6_ACPI_EN)
612                quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
613                                 "ICH6 ACPI/GPIO/TCO");
614
615        pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
616        if (enable & ICH6_GPIO_EN)
617                quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
618                                "ICH6 GPIO");
619}
620
621static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
622{
623        u32 val;
624        u32 size, base;
625
626        pci_read_config_dword(dev, reg, &val);
627
628        /* Enabled? */
629        if (!(val & 1))
630                return;
631        base = val & 0xfffc;
632        if (dynsize) {
633                /*
634                 * This is not correct. It is 16, 32 or 64 bytes depending on
635                 * register D31:F0:ADh bits 5:4.
636                 *
637                 * But this gets us at least _part_ of it.
638                 */
639                size = 16;
640        } else {
641                size = 128;
642        }
643        base &= ~(size-1);
644
645        /* Just print it out for now. We should reserve it after more debugging */
646        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
647}
648
649static void quirk_ich6_lpc(struct pci_dev *dev)
650{
651        /* Shared ACPI/GPIO decode with all ICH6+ */
652        ich6_lpc_acpi_gpio(dev);
653
654        /* ICH6-specific generic IO decode */
655        ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
656        ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
657}
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
660
661static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
662{
663        u32 val;
664        u32 mask, base;
665
666        pci_read_config_dword(dev, reg, &val);
667
668        /* Enabled? */
669        if (!(val & 1))
670                return;
671
672        /*
673         * IO base in bits 15:2, mask in bits 23:18, both
674         * are dword-based
675         */
676        base = val & 0xfffc;
677        mask = (val >> 16) & 0xfc;
678        mask |= 3;
679
680        /* Just print it out for now. We should reserve it after more debugging */
681        dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
682}
683
684/* ICH7-10 has the same common LPC generic IO decode registers */
685static void quirk_ich7_lpc(struct pci_dev *dev)
686{
687        /* We share the common ACPI/GPIO decode with ICH6 */
688        ich6_lpc_acpi_gpio(dev);
689
690        /* And have 4 ICH7+ generic decodes */
691        ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
692        ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
693        ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
694        ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
695}
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
709
710/*
711 * VIA ACPI: One IO region pointed to by longword at
712 *      0x48 or 0x20 (256 bytes of ACPI registers)
713 */
714static void quirk_vt82c586_acpi(struct pci_dev *dev)
715{
716        if (dev->revision & 0x10)
717                quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
718                                "vt82c586 ACPI");
719}
720DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi);
721
722/*
723 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
724 *      0x48 (256 bytes of ACPI registers)
725 *      0x70 (128 bytes of hardware monitoring register)
726 *      0x90 (16 bytes of SMB registers)
727 */
728static void quirk_vt82c686_acpi(struct pci_dev *dev)
729{
730        quirk_vt82c586_acpi(dev);
731
732        quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
733                                 "vt82c686 HW-mon");
734
735        quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
736}
737DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi);
738
739/*
740 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
741 *      0x88 (128 bytes of power management registers)
742 *      0xd0 (16 bytes of SMB registers)
743 */
744static void quirk_vt8235_acpi(struct pci_dev *dev)
745{
746        quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
747        quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
748}
749DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
750
751/*
752 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
753 *      Disable fast back-to-back on the secondary bus segment
754 */
755static void quirk_xio2000a(struct pci_dev *dev)
756{
757        struct pci_dev *pdev;
758        u16 command;
759
760        dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
761        list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
762                pci_read_config_word(pdev, PCI_COMMAND, &command);
763                if (command & PCI_COMMAND_FAST_BACK)
764                        pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
765        }
766}
767DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
768                        quirk_xio2000a);
769
770#ifdef CONFIG_X86_IO_APIC
771
772#include <asm/io_apic.h>
773
774/*
775 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
776 * devices to the external APIC.
777 *
778 * TODO: When we have device-specific interrupt routers,
779 * this code will go away from quirks.
780 */
781static void quirk_via_ioapic(struct pci_dev *dev)
782{
783        u8 tmp;
784
785        if (nr_ioapics < 1)
786                tmp = 0;    /* nothing routed to external APIC */
787        else
788                tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
789
790        dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
791               tmp == 0 ? "Disa" : "Ena");
792
793        /* Offset 0x58: External APIC IRQ output control */
794        pci_write_config_byte(dev, 0x58, tmp);
795}
796DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
797DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
798
799/*
800 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
801 * This leads to doubled level interrupt rates.
802 * Set this bit to get rid of cycle wastage.
803 * Otherwise uncritical.
804 */
805static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
806{
807        u8 misc_control2;
808#define BYPASS_APIC_DEASSERT 8
809
810        pci_read_config_byte(dev, 0x5B, &misc_control2);
811        if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
812                dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
813                pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
814        }
815}
816DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
817DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
818
819/*
820 * The AMD io apic can hang the box when an apic irq is masked.
821 * We check all revs >= B0 (yet not in the pre production!) as the bug
822 * is currently marked NoFix
823 *
824 * We have multiple reports of hangs with this chipset that went away with
825 * noapic specified. For the moment we assume it's the erratum. We may be wrong
826 * of course. However the advice is demonstrably good even if so..
827 */
828static void quirk_amd_ioapic(struct pci_dev *dev)
829{
830        if (dev->revision >= 0x02) {
831                dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
832                dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
833        }
834}
835DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
836#endif /* CONFIG_X86_IO_APIC */
837
838#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
839
840static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
841{
842        /* Fix for improper SRIOV configuration on Cavium cn88xx  RNM device */
843        if (dev->subsystem_device == 0xa118)
844                dev->sriov->link = dev->devfn;
845}
846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
847#endif
848
849/*
850 * Some settings of MMRBC can lead to data corruption so block changes.
851 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
852 */
853static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
854{
855        if (dev->subordinate && dev->revision <= 0x12) {
856                dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
857                         dev->revision);
858                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
859        }
860}
861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
862
863/*
864 * FIXME: it is questionable that quirk_via_acpi
865 * is needed.  It shows up as an ISA bridge, and does not
866 * support the PCI_INTERRUPT_LINE register at all.  Therefore
867 * it seems like setting the pci_dev's 'irq' to the
868 * value of the ACPI SCI interrupt is only done for convenience.
869 *      -jgarzik
870 */
871static void quirk_via_acpi(struct pci_dev *d)
872{
873        /*
874         * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
875         */
876        u8 irq;
877        pci_read_config_byte(d, 0x42, &irq);
878        irq &= 0xf;
879        if (irq && (irq != 2))
880                d->irq = irq;
881}
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_via_acpi);
883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_via_acpi);
884
885
886/*
887 *      VIA bridges which have VLink
888 */
889
890static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
891
892static void quirk_via_bridge(struct pci_dev *dev)
893{
894        /* See what bridge we have and find the device ranges */
895        switch (dev->device) {
896        case PCI_DEVICE_ID_VIA_82C686:
897                /* The VT82C686 is special, it attaches to PCI and can have
898                   any device number. All its subdevices are functions of
899                   that single device. */
900                via_vlink_dev_lo = PCI_SLOT(dev->devfn);
901                via_vlink_dev_hi = PCI_SLOT(dev->devfn);
902                break;
903        case PCI_DEVICE_ID_VIA_8237:
904        case PCI_DEVICE_ID_VIA_8237A:
905                via_vlink_dev_lo = 15;
906                break;
907        case PCI_DEVICE_ID_VIA_8235:
908                via_vlink_dev_lo = 16;
909                break;
910        case PCI_DEVICE_ID_VIA_8231:
911        case PCI_DEVICE_ID_VIA_8233_0:
912        case PCI_DEVICE_ID_VIA_8233A:
913        case PCI_DEVICE_ID_VIA_8233C_0:
914                via_vlink_dev_lo = 17;
915                break;
916        }
917}
918DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686,       quirk_via_bridge);
919DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8231,         quirk_via_bridge);
920DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233_0,       quirk_via_bridge);
921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233A,        quirk_via_bridge);
922DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233C_0,      quirk_via_bridge);
923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235,         quirk_via_bridge);
924DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237,         quirk_via_bridge);
925DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237A,        quirk_via_bridge);
926
927/**
928 *      quirk_via_vlink         -       VIA VLink IRQ number update
929 *      @dev: PCI device
930 *
931 *      If the device we are dealing with is on a PIC IRQ we need to
932 *      ensure that the IRQ line register which usually is not relevant
933 *      for PCI cards, is actually written so that interrupts get sent
934 *      to the right place.
935 *      We only do this on systems where a VIA south bridge was detected,
936 *      and only for VIA devices on the motherboard (see quirk_via_bridge
937 *      above).
938 */
939
940static void quirk_via_vlink(struct pci_dev *dev)
941{
942        u8 irq, new_irq;
943
944        /* Check if we have VLink at all */
945        if (via_vlink_dev_lo == -1)
946                return;
947
948        new_irq = dev->irq;
949
950        /* Don't quirk interrupts outside the legacy IRQ range */
951        if (!new_irq || new_irq > 15)
952                return;
953
954        /* Internal device ? */
955        if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
956            PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
957                return;
958
959        /* This is an internal VLink device on a PIC interrupt. The BIOS
960           ought to have set this but may not have, so we redo it */
961
962        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
963        if (new_irq != irq) {
964                dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
965                        irq, new_irq);
966                udelay(15);     /* unknown if delay really needed */
967                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
968        }
969}
970DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
971
972/*
973 * VIA VT82C598 has its device ID settable and many BIOSes
974 * set it to the ID of VT82C597 for backward compatibility.
975 * We need to switch it off to be able to recognize the real
976 * type of the chip.
977 */
978static void quirk_vt82c598_id(struct pci_dev *dev)
979{
980        pci_write_config_byte(dev, 0xfc, 0);
981        pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
982}
983DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id);
984
985/*
986 * CardBus controllers have a legacy base address that enables them
987 * to respond as i82365 pcmcia controllers.  We don't want them to
988 * do this even if the Linux CardBus driver is not loaded, because
989 * the Linux i82365 driver does not (and should not) handle CardBus.
990 */
991static void quirk_cardbus_legacy(struct pci_dev *dev)
992{
993        pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
994}
995DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
996                        PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
997DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
998                        PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
999
1000/*
1001 * Following the PCI ordering rules is optional on the AMD762. I'm not
1002 * sure what the designers were smoking but let's not inhale...
1003 *
1004 * To be fair to AMD, it follows the spec by default, its BIOS people
1005 * who turn it off!
1006 */
1007static void quirk_amd_ordering(struct pci_dev *dev)
1008{
1009        u32 pcic;
1010        pci_read_config_dword(dev, 0x4C, &pcic);
1011        if ((pcic & 6) != 6) {
1012                pcic |= 6;
1013                dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1014                pci_write_config_dword(dev, 0x4C, pcic);
1015                pci_read_config_dword(dev, 0x84, &pcic);
1016                pcic |= (1 << 23);      /* Required in this mode */
1017                pci_write_config_dword(dev, 0x84, pcic);
1018        }
1019}
1020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1021DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,       PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1022
1023/*
1024 *      DreamWorks provided workaround for Dunord I-3000 problem
1025 *
1026 *      This card decodes and responds to addresses not apparently
1027 *      assigned to it. We force a larger allocation to ensure that
1028 *      nothing gets put too close to it.
1029 */
1030static void quirk_dunord(struct pci_dev *dev)
1031{
1032        struct resource *r = &dev->resource[1];
1033
1034        r->flags |= IORESOURCE_UNSET;
1035        r->start = 0;
1036        r->end = 0xffffff;
1037}
1038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,  PCI_DEVICE_ID_DUNORD_I3000,     quirk_dunord);
1039
1040/*
1041 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1042 * is subtractive decoding (transparent), and does indicate this
1043 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1044 * instead of 0x01.
1045 */
1046static void quirk_transparent_bridge(struct pci_dev *dev)
1047{
1048        dev->transparent = 1;
1049}
1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82380FB,    quirk_transparent_bridge);
1051DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605,  quirk_transparent_bridge);
1052
1053/*
1054 * Common misconfiguration of the MediaGX/Geode PCI master that will
1055 * reduce PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1
1056 * datasheets found at http://www.national.com/analog for info on what
1057 * these bits do.  <christer@weinigel.se>
1058 */
1059static void quirk_mediagx_master(struct pci_dev *dev)
1060{
1061        u8 reg;
1062
1063        pci_read_config_byte(dev, 0x41, &reg);
1064        if (reg & 2) {
1065                reg &= ~2;
1066                dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1067                         reg);
1068                pci_write_config_byte(dev, 0x41, reg);
1069        }
1070}
1071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1072DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,   PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1073
1074/*
1075 *      Ensure C0 rev restreaming is off. This is normally done by
1076 *      the BIOS but in the odd case it is not the results are corruption
1077 *      hence the presence of a Linux check
1078 */
1079static void quirk_disable_pxb(struct pci_dev *pdev)
1080{
1081        u16 config;
1082
1083        if (pdev->revision != 0x04)             /* Only C0 requires this */
1084                return;
1085        pci_read_config_word(pdev, 0x40, &config);
1086        if (config & (1<<6)) {
1087                config &= ~(1<<6);
1088                pci_write_config_word(pdev, 0x40, config);
1089                dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1090        }
1091}
1092DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1093DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1094
1095static void quirk_amd_ide_mode(struct pci_dev *pdev)
1096{
1097        /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1098        u8 tmp;
1099
1100        pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1101        if (tmp == 0x01) {
1102                pci_read_config_byte(pdev, 0x40, &tmp);
1103                pci_write_config_byte(pdev, 0x40, tmp|1);
1104                pci_write_config_byte(pdev, 0x9, 1);
1105                pci_write_config_byte(pdev, 0xa, 6);
1106                pci_write_config_byte(pdev, 0x40, tmp);
1107
1108                pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1109                dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1110        }
1111}
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1113DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1115DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1117DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1119DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1120
1121/*
1122 *      Serverworks CSB5 IDE does not fully support native mode
1123 */
1124static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1125{
1126        u8 prog;
1127        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1128        if (prog & 5) {
1129                prog &= ~5;
1130                pdev->class &= ~5;
1131                pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1132                /* PCI layer will sort out resources */
1133        }
1134}
1135DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1136
1137/*
1138 *      Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1139 */
1140static void quirk_ide_samemode(struct pci_dev *pdev)
1141{
1142        u8 prog;
1143
1144        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1145
1146        if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1147                dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1148                prog &= ~5;
1149                pdev->class &= ~5;
1150                pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1151        }
1152}
1153DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1154
1155/*
1156 * Some ATA devices break if put into D3
1157 */
1158
1159static void quirk_no_ata_d3(struct pci_dev *pdev)
1160{
1161        pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1162}
1163/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1164DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1165                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1166DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1167                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1168/* ALi loses some register settings that we cannot then restore */
1169DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1170                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1171/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1172   occur when mode detecting */
1173DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1174                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1175
1176/* This was originally an Alpha specific thing, but it really fits here.
1177 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1178 */
1179static void quirk_eisa_bridge(struct pci_dev *dev)
1180{
1181        dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1182}
1183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82375,      quirk_eisa_bridge);
1184
1185
1186/*
1187 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1188 * is not activated. The myth is that Asus said that they do not want the
1189 * users to be irritated by just another PCI Device in the Win98 device
1190 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1191 * package 2.7.0 for details)
1192 *
1193 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1194 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1195 * becomes necessary to do this tweak in two steps -- the chosen trigger
1196 * is either the Host bridge (preferred) or on-board VGA controller.
1197 *
1198 * Note that we used to unhide the SMBus that way on Toshiba laptops
1199 * (Satellite A40 and Tecra M2) but then found that the thermal management
1200 * was done by SMM code, which could cause unsynchronized concurrent
1201 * accesses to the SMBus registers, with potentially bad effects. Thus you
1202 * should be very careful when adding new entries: if SMM is accessing the
1203 * Intel SMBus, this is a very good reason to leave it hidden.
1204 *
1205 * Likewise, many recent laptops use ACPI for thermal management. If the
1206 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1207 * natively, and keeping the SMBus hidden is the right thing to do. If you
1208 * are about to add an entry in the table below, please first disassemble
1209 * the DSDT and double-check that there is no code accessing the SMBus.
1210 */
1211static int asus_hides_smbus;
1212
1213static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1214{
1215        if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1216                if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1217                        switch (dev->subsystem_device) {
1218                        case 0x8025: /* P4B-LX */
1219                        case 0x8070: /* P4B */
1220                        case 0x8088: /* P4B533 */
1221                        case 0x1626: /* L3C notebook */
1222                                asus_hides_smbus = 1;
1223                        }
1224                else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1225                        switch (dev->subsystem_device) {
1226                        case 0x80b1: /* P4GE-V */
1227                        case 0x80b2: /* P4PE */
1228                        case 0x8093: /* P4B533-V */
1229                                asus_hides_smbus = 1;
1230                        }
1231                else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1232                        switch (dev->subsystem_device) {
1233                        case 0x8030: /* P4T533 */
1234                                asus_hides_smbus = 1;
1235                        }
1236                else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1237                        switch (dev->subsystem_device) {
1238                        case 0x8070: /* P4G8X Deluxe */
1239                                asus_hides_smbus = 1;
1240                        }
1241                else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1242                        switch (dev->subsystem_device) {
1243                        case 0x80c9: /* PU-DLS */
1244                                asus_hides_smbus = 1;
1245                        }
1246                else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1247                        switch (dev->subsystem_device) {
1248                        case 0x1751: /* M2N notebook */
1249                        case 0x1821: /* M5N notebook */
1250                        case 0x1897: /* A6L notebook */
1251                                asus_hides_smbus = 1;
1252                        }
1253                else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1254                        switch (dev->subsystem_device) {
1255                        case 0x184b: /* W1N notebook */
1256                        case 0x186a: /* M6Ne notebook */
1257                                asus_hides_smbus = 1;
1258                        }
1259                else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1260                        switch (dev->subsystem_device) {
1261                        case 0x80f2: /* P4P800-X */
1262                                asus_hides_smbus = 1;
1263                        }
1264                else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1265                        switch (dev->subsystem_device) {
1266                        case 0x1882: /* M6V notebook */
1267                        case 0x1977: /* A6VA notebook */
1268                                asus_hides_smbus = 1;
1269                        }
1270        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1271                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1272                        switch (dev->subsystem_device) {
1273                        case 0x088C: /* HP Compaq nc8000 */
1274                        case 0x0890: /* HP Compaq nc6000 */
1275                                asus_hides_smbus = 1;
1276                        }
1277                else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1278                        switch (dev->subsystem_device) {
1279                        case 0x12bc: /* HP D330L */
1280                        case 0x12bd: /* HP D530 */
1281                        case 0x006a: /* HP Compaq nx9500 */
1282                                asus_hides_smbus = 1;
1283                        }
1284                else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1285                        switch (dev->subsystem_device) {
1286                        case 0x12bf: /* HP xw4100 */
1287                                asus_hides_smbus = 1;
1288                        }
1289        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1290                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1291                        switch (dev->subsystem_device) {
1292                        case 0xC00C: /* Samsung P35 notebook */
1293                                asus_hides_smbus = 1;
1294                }
1295        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1296                if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1297                        switch (dev->subsystem_device) {
1298                        case 0x0058: /* Compaq Evo N620c */
1299                                asus_hides_smbus = 1;
1300                        }
1301                else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1302                        switch (dev->subsystem_device) {
1303                        case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1304                                /* Motherboard doesn't have Host bridge
1305                                 * subvendor/subdevice IDs, therefore checking
1306                                 * its on-board VGA controller */
1307                                asus_hides_smbus = 1;
1308                        }
1309                else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1310                        switch (dev->subsystem_device) {
1311                        case 0x00b8: /* Compaq Evo D510 CMT */
1312                        case 0x00b9: /* Compaq Evo D510 SFF */
1313                        case 0x00ba: /* Compaq Evo D510 USDT */
1314                                /* Motherboard doesn't have Host bridge
1315                                 * subvendor/subdevice IDs and on-board VGA
1316                                 * controller is disabled if an AGP card is
1317                                 * inserted, therefore checking USB UHCI
1318                                 * Controller #1 */
1319                                asus_hides_smbus = 1;
1320                        }
1321                else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1322                        switch (dev->subsystem_device) {
1323                        case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1324                                /* Motherboard doesn't have host bridge
1325                                 * subvendor/subdevice IDs, therefore checking
1326                                 * its on-board VGA controller */
1327                                asus_hides_smbus = 1;
1328                        }
1329        }
1330}
1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845_HB,   asus_hides_smbus_hostbridge);
1332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_HB,  asus_hides_smbus_hostbridge);
1333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82850_HB,   asus_hides_smbus_hostbridge);
1334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82865_HB,   asus_hides_smbus_hostbridge);
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82875_HB,   asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_7205_0,     asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_E7501_MCH,  asus_hides_smbus_hostbridge);
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1341
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82810_IG3,  asus_hides_smbus_hostbridge);
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_2,  asus_hides_smbus_hostbridge);
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82815_CGC,  asus_hides_smbus_hostbridge);
1345
1346static void asus_hides_smbus_lpc(struct pci_dev *dev)
1347{
1348        u16 val;
1349
1350        if (likely(!asus_hides_smbus))
1351                return;
1352
1353        pci_read_config_word(dev, 0xF2, &val);
1354        if (val & 0x8) {
1355                pci_write_config_word(dev, 0xF2, val & (~0x8));
1356                pci_read_config_word(dev, 0xF2, &val);
1357                if (val & 0x8)
1358                        dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1359                                 val);
1360                else
1361                        dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1362        }
1363}
1364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1378
1379/* It appears we just have one such device. If not, we have a warning */
1380static void __iomem *asus_rcba_base;
1381static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1382{
1383        u32 rcba;
1384
1385        if (likely(!asus_hides_smbus))
1386                return;
1387        WARN_ON(asus_rcba_base);
1388
1389        pci_read_config_dword(dev, 0xF0, &rcba);
1390        /* use bits 31:14, 16 kB aligned */
1391        asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1392        if (asus_rcba_base == NULL)
1393                return;
1394}
1395
1396static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1397{
1398        u32 val;
1399
1400        if (likely(!asus_hides_smbus || !asus_rcba_base))
1401                return;
1402        /* read the Function Disable register, dword mode only */
1403        val = readl(asus_rcba_base + 0x3418);
1404        writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1405}
1406
1407static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1408{
1409        if (likely(!asus_hides_smbus || !asus_rcba_base))
1410                return;
1411        iounmap(asus_rcba_base);
1412        asus_rcba_base = NULL;
1413        dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1414}
1415
1416static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1417{
1418        asus_hides_smbus_lpc_ich6_suspend(dev);
1419        asus_hides_smbus_lpc_ich6_resume_early(dev);
1420        asus_hides_smbus_lpc_ich6_resume(dev);
1421}
1422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6);
1423DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_suspend);
1424DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume);
1425DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume_early);
1426
1427/*
1428 * SiS 96x south bridge: BIOS typically hides SMBus device...
1429 */
1430static void quirk_sis_96x_smbus(struct pci_dev *dev)
1431{
1432        u8 val = 0;
1433        pci_read_config_byte(dev, 0x77, &val);
1434        if (val & 0x10) {
1435                dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1436                pci_write_config_byte(dev, 0x77, val & ~0x10);
1437        }
1438}
1439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1446DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1447
1448/*
1449 * ... This is further complicated by the fact that some SiS96x south
1450 * bridges pretend to be 85C503/5513 instead.  In that case see if we
1451 * spotted a compatible north bridge to make sure.
1452 * (pci_find_device doesn't work yet)
1453 *
1454 * We can also enable the sis96x bit in the discovery register..
1455 */
1456#define SIS_DETECT_REGISTER 0x40
1457
1458static void quirk_sis_503(struct pci_dev *dev)
1459{
1460        u8 reg;
1461        u16 devid;
1462
1463        pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1464        pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1465        pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1466        if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1467                pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1468                return;
1469        }
1470
1471        /*
1472         * Ok, it now shows up as a 96x.. run the 96x quirk by
1473         * hand in case it has already been processed.
1474         * (depends on link order, which is apparently not guaranteed)
1475         */
1476        dev->device = devid;
1477        quirk_sis_96x_smbus(dev);
1478}
1479DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1480DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1481
1482
1483/*
1484 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1485 * and MC97 modem controller are disabled when a second PCI soundcard is
1486 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1487 * -- bjd
1488 */
1489static void asus_hides_ac97_lpc(struct pci_dev *dev)
1490{
1491        u8 val;
1492        int asus_hides_ac97 = 0;
1493
1494        if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1495                if (dev->device == PCI_DEVICE_ID_VIA_8237)
1496                        asus_hides_ac97 = 1;
1497        }
1498
1499        if (!asus_hides_ac97)
1500                return;
1501
1502        pci_read_config_byte(dev, 0x50, &val);
1503        if (val & 0xc0) {
1504                pci_write_config_byte(dev, 0x50, val & (~0xc0));
1505                pci_read_config_byte(dev, 0x50, &val);
1506                if (val & 0xc0)
1507                        dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1508                                 val);
1509                else
1510                        dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1511        }
1512}
1513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1515
1516#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1517
1518/*
1519 *      If we are using libata we can drive this chip properly but must
1520 *      do this early on to make the additional device appear during
1521 *      the PCI scanning.
1522 */
1523static void quirk_jmicron_ata(struct pci_dev *pdev)
1524{
1525        u32 conf1, conf5, class;
1526        u8 hdr;
1527
1528        /* Only poke fn 0 */
1529        if (PCI_FUNC(pdev->devfn))
1530                return;
1531
1532        pci_read_config_dword(pdev, 0x40, &conf1);
1533        pci_read_config_dword(pdev, 0x80, &conf5);
1534
1535        conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1536        conf5 &= ~(1 << 24);  /* Clear bit 24 */
1537
1538        switch (pdev->device) {
1539        case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1540        case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1541        case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1542                /* The controller should be in single function ahci mode */
1543                conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1544                break;
1545
1546        case PCI_DEVICE_ID_JMICRON_JMB365:
1547        case PCI_DEVICE_ID_JMICRON_JMB366:
1548                /* Redirect IDE second PATA port to the right spot */
1549                conf5 |= (1 << 24);
1550                /* Fall through */
1551        case PCI_DEVICE_ID_JMICRON_JMB361:
1552        case PCI_DEVICE_ID_JMICRON_JMB363:
1553        case PCI_DEVICE_ID_JMICRON_JMB369:
1554                /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1555                /* Set the class codes correctly and then direct IDE 0 */
1556                conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1557                break;
1558
1559        case PCI_DEVICE_ID_JMICRON_JMB368:
1560                /* The controller should be in single function IDE mode */
1561                conf1 |= 0x00C00000; /* Set 22, 23 */
1562                break;
1563        }
1564
1565        pci_write_config_dword(pdev, 0x40, conf1);
1566        pci_write_config_dword(pdev, 0x80, conf5);
1567
1568        /* Update pdev accordingly */
1569        pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1570        pdev->hdr_type = hdr & 0x7f;
1571        pdev->multifunction = !!(hdr & 0x80);
1572
1573        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1574        pdev->class = class >> 8;
1575}
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1585DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1594
1595#endif
1596
1597static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1598{
1599        if (dev->multifunction) {
1600                device_disable_async_suspend(&dev->dev);
1601                dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1602        }
1603}
1604DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1605DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1608
1609#ifdef CONFIG_X86_IO_APIC
1610static void quirk_alder_ioapic(struct pci_dev *pdev)
1611{
1612        int i;
1613
1614        if ((pdev->class >> 8) != 0xff00)
1615                return;
1616
1617        /* the first BAR is the location of the IO APIC...we must
1618         * not touch this (and it's already covered by the fixmap), so
1619         * forcibly insert it into the resource tree */
1620        if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1621                insert_resource(&iomem_resource, &pdev->resource[0]);
1622
1623        /* The next five BARs all seem to be rubbish, so just clean
1624         * them out */
1625        for (i = 1; i < 6; i++)
1626                memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1627}
1628DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_EESSC,      quirk_alder_ioapic);
1629#endif
1630
1631static void quirk_pcie_mch(struct pci_dev *pdev)
1632{
1633        pdev->no_msi = 1;
1634}
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
1637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,   0x1610, quirk_pcie_mch);
1639
1640
1641/*
1642 * It's possible for the MSI to get corrupted if shpc and acpi
1643 * are used together on certain PXH-based systems.
1644 */
1645static void quirk_pcie_pxh(struct pci_dev *dev)
1646{
1647        dev->no_msi = 1;
1648        dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1649}
1650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
1652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_pcie_pxh);
1653DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_pcie_pxh);
1654DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_pcie_pxh);
1655
1656/*
1657 * Some Intel PCI Express chipsets have trouble with downstream
1658 * device power management.
1659 */
1660static void quirk_intel_pcie_pm(struct pci_dev *dev)
1661{
1662        pci_pm_d3_delay = 120;
1663        dev->no_d1d2 = 1;
1664}
1665
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e2, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e3, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e4, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e5, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e6, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e7, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f7, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f8, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f9, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25fa, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2601, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2602, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2603, quirk_intel_pcie_pm);
1679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2604, quirk_intel_pcie_pm);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2605, quirk_intel_pcie_pm);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2606, quirk_intel_pcie_pm);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2607, quirk_intel_pcie_pm);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2608, quirk_intel_pcie_pm);
1684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2609, quirk_intel_pcie_pm);
1685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
1686DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
1687
1688#ifdef CONFIG_X86_IO_APIC
1689/*
1690 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1691 * remap the original interrupt in the linux kernel to the boot interrupt, so
1692 * that a PCI device's interrupt handler is installed on the boot interrupt
1693 * line instead.
1694 */
1695static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1696{
1697        if (noioapicquirk || noioapicreroute)
1698                return;
1699
1700        dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1701        dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1702                 dev->vendor, dev->device);
1703}
1704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1713DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1714DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1716DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1717DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1718DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1719DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1720
1721/*
1722 * On some chipsets we can disable the generation of legacy INTx boot
1723 * interrupts.
1724 */
1725
1726/*
1727 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1728 * 300641-004US, section 5.7.3.
1729 */
1730#define INTEL_6300_IOAPIC_ABAR          0x40
1731#define INTEL_6300_DISABLE_BOOT_IRQ     (1<<14)
1732
1733static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1734{
1735        u16 pci_config_word;
1736
1737        if (noioapicquirk)
1738                return;
1739
1740        pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1741        pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1742        pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1743
1744        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745                 dev->vendor, dev->device);
1746}
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,     quirk_disable_intel_boot_interrupt);
1749
1750/*
1751 * disable boot interrupts on HT-1000
1752 */
1753#define BC_HT1000_FEATURE_REG           0x64
1754#define BC_HT1000_PIC_REGS_ENABLE       (1<<0)
1755#define BC_HT1000_MAP_IDX               0xC00
1756#define BC_HT1000_MAP_DATA              0xC01
1757
1758static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1759{
1760        u32 pci_config_dword;
1761        u8 irq;
1762
1763        if (noioapicquirk)
1764                return;
1765
1766        pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1767        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1768                        BC_HT1000_PIC_REGS_ENABLE);
1769
1770        for (irq = 0x10; irq < 0x10 + 32; irq++) {
1771                outb(irq, BC_HT1000_MAP_IDX);
1772                outb(0x00, BC_HT1000_MAP_DATA);
1773        }
1774
1775        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1776
1777        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1778                 dev->vendor, dev->device);
1779}
1780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
1781DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,       quirk_disable_broadcom_boot_interrupt);
1782
1783/*
1784 * disable boot interrupts on AMD and ATI chipsets
1785 */
1786/*
1787 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1788 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1789 * (due to an erratum).
1790 */
1791#define AMD_813X_MISC                   0x40
1792#define AMD_813X_NOIOAMODE              (1<<0)
1793#define AMD_813X_REV_B1                 0x12
1794#define AMD_813X_REV_B2                 0x13
1795
1796static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1797{
1798        u32 pci_config_dword;
1799
1800        if (noioapicquirk)
1801                return;
1802        if ((dev->revision == AMD_813X_REV_B1) ||
1803            (dev->revision == AMD_813X_REV_B2))
1804                return;
1805
1806        pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1807        pci_config_dword &= ~AMD_813X_NOIOAMODE;
1808        pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1809
1810        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1811                 dev->vendor, dev->device);
1812}
1813DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1814DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1816DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1817
1818#define AMD_8111_PCI_IRQ_ROUTING        0x56
1819
1820static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1821{
1822        u16 pci_config_word;
1823
1824        if (noioapicquirk)
1825                return;
1826
1827        pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1828        if (!pci_config_word) {
1829                dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1830                         dev->vendor, dev->device);
1831                return;
1832        }
1833        pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1834        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1835                 dev->vendor, dev->device);
1836}
1837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
1838DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,     quirk_disable_amd_8111_boot_interrupt);
1839#endif /* CONFIG_X86_IO_APIC */
1840
1841/*
1842 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1843 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1844 * Re-allocate the region if needed...
1845 */
1846static void quirk_tc86c001_ide(struct pci_dev *dev)
1847{
1848        struct resource *r = &dev->resource[0];
1849
1850        if (r->start & 0x8) {
1851                r->flags |= IORESOURCE_UNSET;
1852                r->start = 0;
1853                r->end = 0xf;
1854        }
1855}
1856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1857                         PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1858                         quirk_tc86c001_ide);
1859
1860/*
1861 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1862 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1863 * being read correctly if bit 7 of the base address is set.
1864 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1865 * Re-allocate the regions to a 256-byte boundary if necessary.
1866 */
1867static void quirk_plx_pci9050(struct pci_dev *dev)
1868{
1869        unsigned int bar;
1870
1871        /* Fixed in revision 2 (PCI 9052). */
1872        if (dev->revision >= 2)
1873                return;
1874        for (bar = 0; bar <= 1; bar++)
1875                if (pci_resource_len(dev, bar) == 0x80 &&
1876                    (pci_resource_start(dev, bar) & 0x80)) {
1877                        struct resource *r = &dev->resource[bar];
1878                        dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1879                                 bar);
1880                        r->flags |= IORESOURCE_UNSET;
1881                        r->start = 0;
1882                        r->end = 0xff;
1883                }
1884}
1885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1886                         quirk_plx_pci9050);
1887/*
1888 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1889 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1890 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1891 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1892 *
1893 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1894 * driver.
1895 */
1896DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1897DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1898
1899static void quirk_netmos(struct pci_dev *dev)
1900{
1901        unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1902        unsigned int num_serial = dev->subsystem_device & 0xf;
1903
1904        /*
1905         * These Netmos parts are multiport serial devices with optional
1906         * parallel ports.  Even when parallel ports are present, they
1907         * are identified as class SERIAL, which means the serial driver
1908         * will claim them.  To prevent this, mark them as class OTHER.
1909         * These combo devices should be claimed by parport_serial.
1910         *
1911         * The subdevice ID is of the form 0x00PS, where <P> is the number
1912         * of parallel ports and <S> is the number of serial ports.
1913         */
1914        switch (dev->device) {
1915        case PCI_DEVICE_ID_NETMOS_9835:
1916                /* Well, this rule doesn't hold for the following 9835 device */
1917                if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1918                                dev->subsystem_device == 0x0299)
1919                        return;
1920        case PCI_DEVICE_ID_NETMOS_9735:
1921        case PCI_DEVICE_ID_NETMOS_9745:
1922        case PCI_DEVICE_ID_NETMOS_9845:
1923        case PCI_DEVICE_ID_NETMOS_9855:
1924                if (num_parallel) {
1925                        dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1926                                dev->device, num_parallel, num_serial);
1927                        dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1928                            (dev->class & 0xff);
1929                }
1930        }
1931}
1932DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1933                         PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1934
1935/*
1936 * Quirk non-zero PCI functions to route VPD access through function 0 for
1937 * devices that share VPD resources between functions.  The functions are
1938 * expected to be identical devices.
1939 */
1940static void quirk_f0_vpd_link(struct pci_dev *dev)
1941{
1942        struct pci_dev *f0;
1943
1944        if (!PCI_FUNC(dev->devfn))
1945                return;
1946
1947        f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1948        if (!f0)
1949                return;
1950
1951        if (f0->vpd && dev->class == f0->class &&
1952            dev->vendor == f0->vendor && dev->device == f0->device)
1953                dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1954
1955        pci_dev_put(f0);
1956}
1957DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1958                              PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1959
1960static void quirk_e100_interrupt(struct pci_dev *dev)
1961{
1962        u16 command, pmcsr;
1963        u8 __iomem *csr;
1964        u8 cmd_hi;
1965
1966        switch (dev->device) {
1967        /* PCI IDs taken from drivers/net/e100.c */
1968        case 0x1029:
1969        case 0x1030 ... 0x1034:
1970        case 0x1038 ... 0x103E:
1971        case 0x1050 ... 0x1057:
1972        case 0x1059:
1973        case 0x1064 ... 0x106B:
1974        case 0x1091 ... 0x1095:
1975        case 0x1209:
1976        case 0x1229:
1977        case 0x2449:
1978        case 0x2459:
1979        case 0x245D:
1980        case 0x27DC:
1981                break;
1982        default:
1983                return;
1984        }
1985
1986        /*
1987         * Some firmware hands off the e100 with interrupts enabled,
1988         * which can cause a flood of interrupts if packets are
1989         * received before the driver attaches to the device.  So
1990         * disable all e100 interrupts here.  The driver will
1991         * re-enable them when it's ready.
1992         */
1993        pci_read_config_word(dev, PCI_COMMAND, &command);
1994
1995        if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1996                return;
1997
1998        /*
1999         * Check that the device is in the D0 power state. If it's not,
2000         * there is no point to look any further.
2001         */
2002        if (dev->pm_cap) {
2003                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2004                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2005                        return;
2006        }
2007
2008        /* Convert from PCI bus to resource space.  */
2009        csr = ioremap(pci_resource_start(dev, 0), 8);
2010        if (!csr) {
2011                dev_warn(&dev->dev, "Can't map e100 registers\n");
2012                return;
2013        }
2014
2015        cmd_hi = readb(csr + 3);
2016        if (cmd_hi == 0) {
2017                dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2018                writeb(1, csr + 3);
2019        }
2020
2021        iounmap(csr);
2022}
2023DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2024                        PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2025
2026/*
2027 * The 82575 and 82598 may experience data corruption issues when transitioning
2028 * out of L0S.  To prevent this we need to disable L0S on the pci-e link
2029 */
2030static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2031{
2032        dev_info(&dev->dev, "Disabling L0s\n");
2033        pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2034}
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2045DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2049
2050static void fixup_rev1_53c810(struct pci_dev *dev)
2051{
2052        u32 class = dev->class;
2053
2054        /*
2055         * rev 1 ncr53c810 chips don't set the class at all which means
2056         * they don't get their resources remapped. Fix that here.
2057         */
2058        if (class)
2059                return;
2060
2061        dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2062        dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2063                 class, dev->class);
2064}
2065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2066
2067/* Enable 1k I/O space granularity on the Intel P64H2 */
2068static void quirk_p64h2_1k_io(struct pci_dev *dev)
2069{
2070        u16 en1k;
2071
2072        pci_read_config_word(dev, 0x40, &en1k);
2073
2074        if (en1k & 0x200) {
2075                dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2076                dev->io_window_1k = 1;
2077        }
2078}
2079DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   0x1460,         quirk_p64h2_1k_io);
2080
2081/* Under some circumstances, AER is not linked with extended capabilities.
2082 * Force it to be linked by setting the corresponding control bit in the
2083 * config space.
2084 */
2085static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2086{
2087        uint8_t b;
2088        if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2089                if (!(b & 0x20)) {
2090                        pci_write_config_byte(dev, 0xf41, b | 0x20);
2091                        dev_info(&dev->dev, "Linking AER extended capability\n");
2092                }
2093        }
2094}
2095DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2096                        quirk_nvidia_ck804_pcie_aer_ext_cap);
2097DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2098                        quirk_nvidia_ck804_pcie_aer_ext_cap);
2099
2100static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2101{
2102        /*
2103         * Disable PCI Bus Parking and PCI Master read caching on CX700
2104         * which causes unspecified timing errors with a VT6212L on the PCI
2105         * bus leading to USB2.0 packet loss.
2106         *
2107         * This quirk is only enabled if a second (on the external PCI bus)
2108         * VT6212L is found -- the CX700 core itself also contains a USB
2109         * host controller with the same PCI ID as the VT6212L.
2110         */
2111
2112        /* Count VT6212L instances */
2113        struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2114                PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2115        uint8_t b;
2116
2117        /* p should contain the first (internal) VT6212L -- see if we have
2118           an external one by searching again */
2119        p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2120        if (!p)
2121                return;
2122        pci_dev_put(p);
2123
2124        if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2125                if (b & 0x40) {
2126                        /* Turn off PCI Bus Parking */
2127                        pci_write_config_byte(dev, 0x76, b ^ 0x40);
2128
2129                        dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2130                }
2131        }
2132
2133        if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2134                if (b != 0) {
2135                        /* Turn off PCI Master read caching */
2136                        pci_write_config_byte(dev, 0x72, 0x0);
2137
2138                        /* Set PCI Master Bus time-out to "1x16 PCLK" */
2139                        pci_write_config_byte(dev, 0x75, 0x1);
2140
2141                        /* Disable "Read FIFO Timer" */
2142                        pci_write_config_byte(dev, 0x77, 0x0);
2143
2144                        dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2145                }
2146        }
2147}
2148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2149
2150/*
2151 * If a device follows the VPD format spec, the PCI core will not read or
2152 * write past the VPD End Tag.  But some vendors do not follow the VPD
2153 * format spec, so we can't tell how much data is safe to access.  Devices
2154 * may behave unpredictably if we access too much.  Blacklist these devices
2155 * so we don't touch VPD at all.
2156 */
2157static void quirk_blacklist_vpd(struct pci_dev *dev)
2158{
2159        if (dev->vpd) {
2160                dev->vpd->len = 0;
2161                dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2162        }
2163}
2164
2165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2177                quirk_blacklist_vpd);
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2179
2180/*
2181 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2182 * VPD end tag will hang the device.  This problem was initially
2183 * observed when a vpd entry was created in sysfs
2184 * ('/sys/bus/pci/devices/<id>/vpd').   A read to this sysfs entry
2185 * will dump 32k of data.  Reading a full 32k will cause an access
2186 * beyond the VPD end tag causing the device to hang.  Once the device
2187 * is hung, the bnx2 driver will not be able to reset the device.
2188 * We believe that it is legal to read beyond the end tag and
2189 * therefore the solution is to limit the read/write length.
2190 */
2191static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2192{
2193        /*
2194         * Only disable the VPD capability for 5706, 5706S, 5708,
2195         * 5708S and 5709 rev. A
2196         */
2197        if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2198            (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2199            (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2200            (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2201            ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2202             (dev->revision & 0xf0) == 0x0)) {
2203                if (dev->vpd)
2204                        dev->vpd->len = 0x80;
2205        }
2206}
2207
2208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2209                        PCI_DEVICE_ID_NX2_5706,
2210                        quirk_brcm_570x_limit_vpd);
2211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2212                        PCI_DEVICE_ID_NX2_5706S,
2213                        quirk_brcm_570x_limit_vpd);
2214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2215                        PCI_DEVICE_ID_NX2_5708,
2216                        quirk_brcm_570x_limit_vpd);
2217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2218                        PCI_DEVICE_ID_NX2_5708S,
2219                        quirk_brcm_570x_limit_vpd);
2220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2221                        PCI_DEVICE_ID_NX2_5709,
2222                        quirk_brcm_570x_limit_vpd);
2223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2224                        PCI_DEVICE_ID_NX2_5709S,
2225                        quirk_brcm_570x_limit_vpd);
2226
2227static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2228{
2229        u32 rev;
2230
2231        pci_read_config_dword(dev, 0xf4, &rev);
2232
2233        /* Only CAP the MRRS if the device is a 5719 A0 */
2234        if (rev == 0x05719000) {
2235                int readrq = pcie_get_readrq(dev);
2236                if (readrq > 2048)
2237                        pcie_set_readrq(dev, 2048);
2238        }
2239}
2240
2241DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2242                         PCI_DEVICE_ID_TIGON3_5719,
2243                         quirk_brcm_5719_limit_mrrs);
2244
2245#ifdef CONFIG_PCIE_IPROC_PLATFORM
2246static void quirk_paxc_bridge(struct pci_dev *pdev)
2247{
2248        /* The PCI config space is shared with the PAXC root port and the first
2249         * Ethernet device.  So, we need to workaround this by telling the PCI
2250         * code that the bridge is not an Ethernet device.
2251         */
2252        if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2253                pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2254
2255        /* MPSS is not being set properly (as it is currently 0).  This is
2256         * because that area of the PCI config space is hard coded to zero, and
2257         * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
2258         * so that the MPS can be set to the real max value.
2259         */
2260        pdev->pcie_mpss = 2;
2261}
2262DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2263DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2264#endif
2265
2266/* Originally in EDAC sources for i82875P:
2267 * Intel tells BIOS developers to hide device 6 which
2268 * configures the overflow device access containing
2269 * the DRBs - this is where we expose device 6.
2270 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2271 */
2272static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2273{
2274        u8 reg;
2275
2276        if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2277                dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2278                pci_write_config_byte(dev, 0xF4, reg | 0x02);
2279        }
2280}
2281
2282DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2283                        quirk_unhide_mch_dev6);
2284DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2285                        quirk_unhide_mch_dev6);
2286
2287#ifdef CONFIG_TILEPRO
2288/*
2289 * The Tilera TILEmpower tilepro platform needs to set the link speed
2290 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2291 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2292 * capability register of the PEX8624 PCIe switch. The switch
2293 * supports link speed auto negotiation, but falsely sets
2294 * the link speed to 5GT/s.
2295 */
2296static void quirk_tile_plx_gen1(struct pci_dev *dev)
2297{
2298        if (tile_plx_gen1) {
2299                pci_write_config_dword(dev, 0x98, 0x1);
2300                mdelay(50);
2301        }
2302}
2303DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2304#endif /* CONFIG_TILEPRO */
2305
2306#ifdef CONFIG_PCI_MSI
2307/* Some chipsets do not support MSI. We cannot easily rely on setting
2308 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2309 * some other buses controlled by the chipset even if Linux is not
2310 * aware of it.  Instead of setting the flag on all buses in the
2311 * machine, simply disable MSI globally.
2312 */
2313static void quirk_disable_all_msi(struct pci_dev *dev)
2314{
2315        pci_no_msi();
2316        dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2317}
2318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2326
2327/* Disable MSI on chipsets that are known to not support it */
2328static void quirk_disable_msi(struct pci_dev *dev)
2329{
2330        if (dev->subordinate) {
2331                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2332                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2333        }
2334}
2335DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2338
2339/*
2340 * The APC bridge device in AMD 780 family northbridges has some random
2341 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2342 * we use the possible vendor/device IDs of the host bridge for the
2343 * declared quirk, and search for the APC bridge by slot number.
2344 */
2345static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2346{
2347        struct pci_dev *apc_bridge;
2348
2349        apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2350        if (apc_bridge) {
2351                if (apc_bridge->device == 0x9602)
2352                        quirk_disable_msi(apc_bridge);
2353                pci_dev_put(apc_bridge);
2354        }
2355}
2356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2357DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2358
2359/* Go through the list of Hypertransport capabilities and
2360 * return 1 if a HT MSI capability is found and enabled */
2361static int msi_ht_cap_enabled(struct pci_dev *dev)
2362{
2363        int pos, ttl = PCI_FIND_CAP_TTL;
2364
2365        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2366        while (pos && ttl--) {
2367                u8 flags;
2368
2369                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2370                                         &flags) == 0) {
2371                        dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2372                                flags & HT_MSI_FLAGS_ENABLE ?
2373                                "enabled" : "disabled");
2374                        return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2375                }
2376
2377                pos = pci_find_next_ht_capability(dev, pos,
2378                                                  HT_CAPTYPE_MSI_MAPPING);
2379        }
2380        return 0;
2381}
2382
2383/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2384static void quirk_msi_ht_cap(struct pci_dev *dev)
2385{
2386        if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2387                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2388                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2389        }
2390}
2391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2392                        quirk_msi_ht_cap);
2393
2394/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2395 * MSI are supported if the MSI capability set in any of these mappings.
2396 */
2397static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2398{
2399        struct pci_dev *pdev;
2400
2401        if (!dev->subordinate)
2402                return;
2403
2404        /* check HT MSI cap on this chipset and the root one.
2405         * a single one having MSI is enough to be sure that MSI are supported.
2406         */
2407        pdev = pci_get_slot(dev->bus, 0);
2408        if (!pdev)
2409                return;
2410        if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2411                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2412                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2413        }
2414        pci_dev_put(pdev);
2415}
2416DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2417                        quirk_nvidia_ck804_msi_ht_cap);
2418
2419/* Force enable MSI mapping capability on HT bridges */
2420static void ht_enable_msi_mapping(struct pci_dev *dev)
2421{
2422        int pos, ttl = PCI_FIND_CAP_TTL;
2423
2424        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2425        while (pos && ttl--) {
2426                u8 flags;
2427
2428                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2429                                         &flags) == 0) {
2430                        dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2431
2432                        pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2433                                              flags | HT_MSI_FLAGS_ENABLE);
2434                }
2435                pos = pci_find_next_ht_capability(dev, pos,
2436                                                  HT_CAPTYPE_MSI_MAPPING);
2437        }
2438}
2439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2440                         PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2441                         ht_enable_msi_mapping);
2442
2443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2444                         ht_enable_msi_mapping);
2445
2446/* The P5N32-SLI motherboards from Asus have a problem with msi
2447 * for the MCP55 NIC. It is not yet determined whether the msi problem
2448 * also affects other devices. As for now, turn off msi for this device.
2449 */
2450static void nvenet_msi_disable(struct pci_dev *dev)
2451{
2452        const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2453
2454        if (board_name &&
2455            (strstr(board_name, "P5N32-SLI PREMIUM") ||
2456             strstr(board_name, "P5N32-E SLI"))) {
2457                dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2458                dev->no_msi = 1;
2459        }
2460}
2461DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2462                        PCI_DEVICE_ID_NVIDIA_NVENET_15,
2463                        nvenet_msi_disable);
2464
2465/*
2466 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2467 * config register.  This register controls the routing of legacy
2468 * interrupts from devices that route through the MCP55.  If this register
2469 * is misprogrammed, interrupts are only sent to the BSP, unlike
2470 * conventional systems where the IRQ is broadcast to all online CPUs.  Not
2471 * having this register set properly prevents kdump from booting up
2472 * properly, so let's make sure that we have it set correctly.
2473 * Note that this is an undocumented register.
2474 */
2475static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2476{
2477        u32 cfg;
2478
2479        if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2480                return;
2481
2482        pci_read_config_dword(dev, 0x74, &cfg);
2483
2484        if (cfg & ((1 << 2) | (1 << 15))) {
2485                printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2486                cfg &= ~((1 << 2) | (1 << 15));
2487                pci_write_config_dword(dev, 0x74, cfg);
2488        }
2489}
2490
2491DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2492                        PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2493                        nvbridge_check_legacy_irq_routing);
2494
2495DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2496                        PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2497                        nvbridge_check_legacy_irq_routing);
2498
2499static int ht_check_msi_mapping(struct pci_dev *dev)
2500{
2501        int pos, ttl = PCI_FIND_CAP_TTL;
2502        int found = 0;
2503
2504        /* check if there is HT MSI cap or enabled on this device */
2505        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2506        while (pos && ttl--) {
2507                u8 flags;
2508
2509                if (found < 1)
2510                        found = 1;
2511                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2512                                         &flags) == 0) {
2513                        if (flags & HT_MSI_FLAGS_ENABLE) {
2514                                if (found < 2) {
2515                                        found = 2;
2516                                        break;
2517                                }
2518                        }
2519                }
2520                pos = pci_find_next_ht_capability(dev, pos,
2521                                                  HT_CAPTYPE_MSI_MAPPING);
2522        }
2523
2524        return found;
2525}
2526
2527static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2528{
2529        struct pci_dev *dev;
2530        int pos;
2531        int i, dev_no;
2532        int found = 0;
2533
2534        dev_no = host_bridge->devfn >> 3;
2535        for (i = dev_no + 1; i < 0x20; i++) {
2536                dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2537                if (!dev)
2538                        continue;
2539
2540                /* found next host bridge ?*/
2541                pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2542                if (pos != 0) {
2543                        pci_dev_put(dev);
2544                        break;
2545                }
2546
2547                if (ht_check_msi_mapping(dev)) {
2548                        found = 1;
2549                        pci_dev_put(dev);
2550                        break;
2551                }
2552                pci_dev_put(dev);
2553        }
2554
2555        return found;
2556}
2557
2558#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
2559#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
2560
2561static int is_end_of_ht_chain(struct pci_dev *dev)
2562{
2563        int pos, ctrl_off;
2564        int end = 0;
2565        u16 flags, ctrl;
2566
2567        pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2568
2569        if (!pos)
2570                goto out;
2571
2572        pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2573
2574        ctrl_off = ((flags >> 10) & 1) ?
2575                        PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2576        pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2577
2578        if (ctrl & (1 << 6))
2579                end = 1;
2580
2581out:
2582        return end;
2583}
2584
2585static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2586{
2587        struct pci_dev *host_bridge;
2588        int pos;
2589        int i, dev_no;
2590        int found = 0;
2591
2592        dev_no = dev->devfn >> 3;
2593        for (i = dev_no; i >= 0; i--) {
2594                host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2595                if (!host_bridge)
2596                        continue;
2597
2598                pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2599                if (pos != 0) {
2600                        found = 1;
2601                        break;
2602                }
2603                pci_dev_put(host_bridge);
2604        }
2605
2606        if (!found)
2607                return;
2608
2609        /* don't enable end_device/host_bridge with leaf directly here */
2610        if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2611            host_bridge_with_leaf(host_bridge))
2612                goto out;
2613
2614        /* root did that ! */
2615        if (msi_ht_cap_enabled(host_bridge))
2616                goto out;
2617
2618        ht_enable_msi_mapping(dev);
2619
2620out:
2621        pci_dev_put(host_bridge);
2622}
2623
2624static void ht_disable_msi_mapping(struct pci_dev *dev)
2625{
2626        int pos, ttl = PCI_FIND_CAP_TTL;
2627
2628        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2629        while (pos && ttl--) {
2630                u8 flags;
2631
2632                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2633                                         &flags) == 0) {
2634                        dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2635
2636                        pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2637                                              flags & ~HT_MSI_FLAGS_ENABLE);
2638                }
2639                pos = pci_find_next_ht_capability(dev, pos,
2640                                                  HT_CAPTYPE_MSI_MAPPING);
2641        }
2642}
2643
2644static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2645{
2646        struct pci_dev *host_bridge;
2647        int pos;
2648        int found;
2649
2650        if (!pci_msi_enabled())
2651                return;
2652
2653        /* check if there is HT MSI cap or enabled on this device */
2654        found = ht_check_msi_mapping(dev);
2655
2656        /* no HT MSI CAP */
2657        if (found == 0)
2658                return;
2659
2660        /*
2661         * HT MSI mapping should be disabled on devices that are below
2662         * a non-Hypertransport host bridge. Locate the host bridge...
2663         */
2664        host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2665        if (host_bridge == NULL) {
2666                dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2667                return;
2668        }
2669
2670        pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2671        if (pos != 0) {
2672                /* Host bridge is to HT */
2673                if (found == 1) {
2674                        /* it is not enabled, try to enable it */
2675                        if (all)
2676                                ht_enable_msi_mapping(dev);
2677                        else
2678                                nv_ht_enable_msi_mapping(dev);
2679                }
2680                goto out;
2681        }
2682
2683        /* HT MSI is not enabled */
2684        if (found == 1)
2685                goto out;
2686
2687        /* Host bridge is not to HT, disable HT MSI mapping on this device */
2688        ht_disable_msi_mapping(dev);
2689
2690out:
2691        pci_dev_put(host_bridge);
2692}
2693
2694static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2695{
2696        return __nv_msi_ht_cap_quirk(dev, 1);
2697}
2698
2699static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2700{
2701        return __nv_msi_ht_cap_quirk(dev, 0);
2702}
2703
2704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2705DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2706
2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2708DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2709
2710static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2711{
2712        dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2713}
2714static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2715{
2716        struct pci_dev *p;
2717
2718        /* SB700 MSI issue will be fixed at HW level from revision A21,
2719         * we need check PCI REVISION ID of SMBus controller to get SB700
2720         * revision.
2721         */
2722        p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2723                           NULL);
2724        if (!p)
2725                return;
2726
2727        if ((p->revision < 0x3B) && (p->revision >= 0x30))
2728                dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2729        pci_dev_put(p);
2730}
2731static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2732{
2733        /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2734        if (dev->revision < 0x18) {
2735                dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2736                dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2737        }
2738}
2739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ANNAPURNA_LABS,
2740                        PCI_DEVICE_ID_AL_ETH,
2741                        quirk_msi_intx_disable_bug);
2742DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ANNAPURNA_LABS,
2743                        PCI_DEVICE_ID_AL_CRYPTO,
2744                        quirk_msi_intx_disable_bug);
2745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ANNAPURNA_LABS,
2746                        PCI_DEVICE_ID_AL_RAID_DMA,
2747                        quirk_msi_intx_disable_bug);
2748
2749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2750                        PCI_DEVICE_ID_TIGON3_5780,
2751                        quirk_msi_intx_disable_bug);
2752DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2753                        PCI_DEVICE_ID_TIGON3_5780S,
2754                        quirk_msi_intx_disable_bug);
2755DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2756                        PCI_DEVICE_ID_TIGON3_5714,
2757                        quirk_msi_intx_disable_bug);
2758DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2759                        PCI_DEVICE_ID_TIGON3_5714S,
2760                        quirk_msi_intx_disable_bug);
2761DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2762                        PCI_DEVICE_ID_TIGON3_5715,
2763                        quirk_msi_intx_disable_bug);
2764DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2765                        PCI_DEVICE_ID_TIGON3_5715S,
2766                        quirk_msi_intx_disable_bug);
2767
2768DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2769                        quirk_msi_intx_disable_ati_bug);
2770DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2771                        quirk_msi_intx_disable_ati_bug);
2772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2773                        quirk_msi_intx_disable_ati_bug);
2774DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2775                        quirk_msi_intx_disable_ati_bug);
2776DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2777                        quirk_msi_intx_disable_ati_bug);
2778
2779DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2780                        quirk_msi_intx_disable_bug);
2781DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2782                        quirk_msi_intx_disable_bug);
2783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2784                        quirk_msi_intx_disable_bug);
2785
2786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2787                        quirk_msi_intx_disable_bug);
2788DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2789                        quirk_msi_intx_disable_bug);
2790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2791                        quirk_msi_intx_disable_bug);
2792DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2793                        quirk_msi_intx_disable_bug);
2794DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2795                        quirk_msi_intx_disable_bug);
2796DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2797                        quirk_msi_intx_disable_bug);
2798DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2799                        quirk_msi_intx_disable_qca_bug);
2800DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2801                        quirk_msi_intx_disable_qca_bug);
2802DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2803                        quirk_msi_intx_disable_qca_bug);
2804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2805                        quirk_msi_intx_disable_qca_bug);
2806DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2807                        quirk_msi_intx_disable_qca_bug);
2808#endif /* CONFIG_PCI_MSI */
2809
2810/* Allow manual resource allocation for PCI hotplug bridges
2811 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2812 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2813 * kernel fails to allocate resources when hotplug device is
2814 * inserted and PCI bus is rescanned.
2815 */
2816static void quirk_hotplug_bridge(struct pci_dev *dev)
2817{
2818        dev->is_hotplug_bridge = 1;
2819}
2820
2821DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2822
2823/*
2824 * This is a quirk for the Ricoh MMC controller found as a part of
2825 * some mulifunction chips.
2826
2827 * This is very similar and based on the ricoh_mmc driver written by
2828 * Philip Langdale. Thank you for these magic sequences.
2829 *
2830 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2831 * and one or both of cardbus or firewire.
2832 *
2833 * It happens that they implement SD and MMC
2834 * support as separate controllers (and PCI functions). The linux SDHCI
2835 * driver supports MMC cards but the chip detects MMC cards in hardware
2836 * and directs them to the MMC controller - so the SDHCI driver never sees
2837 * them.
2838 *
2839 * To get around this, we must disable the useless MMC controller.
2840 * At that point, the SDHCI controller will start seeing them
2841 * It seems to be the case that the relevant PCI registers to deactivate the
2842 * MMC controller live on PCI function 0, which might be the cardbus controller
2843 * or the firewire controller, depending on the particular chip in question
2844 *
2845 * This has to be done early, because as soon as we disable the MMC controller
2846 * other pci functions shift up one level, e.g. function #2 becomes function
2847 * #1, and this will confuse the pci core.
2848 */
2849
2850#ifdef CONFIG_MMC_RICOH_MMC
2851static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2852{
2853        /* disable via cardbus interface */
2854        u8 write_enable;
2855        u8 write_target;
2856        u8 disable;
2857
2858        /* disable must be done via function #0 */
2859        if (PCI_FUNC(dev->devfn))
2860                return;
2861
2862        pci_read_config_byte(dev, 0xB7, &disable);
2863        if (disable & 0x02)
2864                return;
2865
2866        pci_read_config_byte(dev, 0x8E, &write_enable);
2867        pci_write_config_byte(dev, 0x8E, 0xAA);
2868        pci_read_config_byte(dev, 0x8D, &write_target);
2869        pci_write_config_byte(dev, 0x8D, 0xB7);
2870        pci_write_config_byte(dev, 0xB7, disable | 0x02);
2871        pci_write_config_byte(dev, 0x8E, write_enable);
2872        pci_write_config_byte(dev, 0x8D, write_target);
2873
2874        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2875        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2876}
2877DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2878DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2879
2880static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2881{
2882        /* disable via firewire interface */
2883        u8 write_enable;
2884        u8 disable;
2885
2886        /* disable must be done via function #0 */
2887        if (PCI_FUNC(dev->devfn))
2888                return;
2889        /*
2890         * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2891         * certain types of SD/MMC cards. Lowering the SD base
2892         * clock frequency from 200Mhz to 50Mhz fixes this issue.
2893         *
2894         * 0x150 - SD2.0 mode enable for changing base clock
2895         *         frequency to 50Mhz
2896         * 0xe1  - Base clock frequency
2897         * 0x32  - 50Mhz new clock frequency
2898         * 0xf9  - Key register for 0x150
2899         * 0xfc  - key register for 0xe1
2900         */
2901        if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2902            dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2903                pci_write_config_byte(dev, 0xf9, 0xfc);
2904                pci_write_config_byte(dev, 0x150, 0x10);
2905                pci_write_config_byte(dev, 0xf9, 0x00);
2906                pci_write_config_byte(dev, 0xfc, 0x01);
2907                pci_write_config_byte(dev, 0xe1, 0x32);
2908                pci_write_config_byte(dev, 0xfc, 0x00);
2909
2910                dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2911        }
2912
2913        pci_read_config_byte(dev, 0xCB, &disable);
2914
2915        if (disable & 0x02)
2916                return;
2917
2918        pci_read_config_byte(dev, 0xCA, &write_enable);
2919        pci_write_config_byte(dev, 0xCA, 0x57);
2920        pci_write_config_byte(dev, 0xCB, disable | 0x02);
2921        pci_write_config_byte(dev, 0xCA, write_enable);
2922
2923        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2924        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2925
2926}
2927DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2928DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2929DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2930DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2931DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2932DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2933#endif /*CONFIG_MMC_RICOH_MMC*/
2934
2935#ifdef CONFIG_DMAR_TABLE
2936#define VTUNCERRMSK_REG 0x1ac
2937#define VTD_MSK_SPEC_ERRORS     (1 << 31)
2938/*
2939 * This is a quirk for masking vt-d spec defined errors to platform error
2940 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2941 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2942 * on the RAS config settings of the platform) when a vt-d fault happens.
2943 * The resulting SMI caused the system to hang.
2944 *
2945 * VT-d spec related errors are already handled by the VT-d OS code, so no
2946 * need to report the same error through other channels.
2947 */
2948static void vtd_mask_spec_errors(struct pci_dev *dev)
2949{
2950        u32 word;
2951
2952        pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2953        pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2954}
2955DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2956DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2957#endif
2958
2959static void fixup_ti816x_class(struct pci_dev *dev)
2960{
2961        u32 class = dev->class;
2962
2963        /* TI 816x devices do not have class code set when in PCIe boot mode */
2964        dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2965        dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2966                 class, dev->class);
2967}
2968DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2969                              PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2970
2971/* Some PCIe devices do not work reliably with the claimed maximum
2972 * payload size supported.
2973 */
2974static void fixup_mpss_256(struct pci_dev *dev)
2975{
2976        dev->pcie_mpss = 1; /* 256 bytes */
2977}
2978DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2979                         PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2980DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2981                         PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2983                         PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2984
2985/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2986 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2987 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2988 * until all of the devices are discovered and buses walked, read completion
2989 * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
2990 * it is possible to hotplug a device with MPS of 256B.
2991 */
2992static void quirk_intel_mc_errata(struct pci_dev *dev)
2993{
2994        int err;
2995        u16 rcc;
2996
2997        if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2998            pcie_bus_config == PCIE_BUS_DEFAULT)
2999                return;
3000
3001        /* Intel errata specifies bits to change but does not say what they are.
3002         * Keeping them magical until such time as the registers and values can
3003         * be explained.
3004         */
3005        err = pci_read_config_word(dev, 0x48, &rcc);
3006        if (err) {
3007                dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3008                return;
3009        }
3010
3011        if (!(rcc & (1 << 10)))
3012                return;
3013
3014        rcc &= ~(1 << 10);
3015
3016        err = pci_write_config_word(dev, 0x48, rcc);
3017        if (err) {
3018                dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3019                return;
3020        }
3021
3022        pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3023}
3024/* Intel 5000 series memory controllers and ports 2-7 */
3025DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3035DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3036DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3039/* Intel 5100 series memory controllers and ports 2-7 */
3040DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3041DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3042DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3043DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3044DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3045DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3046DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3047DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3048DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3049DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3051
3052#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
3053
3054/*
3055 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.  To
3056 * work around this, query the size it should be configured to by the device and
3057 * modify the resource end to correspond to this new size.
3058 */
3059static void quirk_intel_ntb(struct pci_dev *dev)
3060{
3061        int rc;
3062        u8 val;
3063
3064        rc = pci_read_config_byte(dev, 0x00D0, &val);
3065        if (rc)
3066                return;
3067
3068        dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3069
3070        rc = pci_read_config_byte(dev, 0x00D1, &val);
3071        if (rc)
3072                return;
3073
3074        dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3075}
3076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3078
3079static ktime_t fixup_debug_start(struct pci_dev *dev,
3080                                 void (*fn)(struct pci_dev *dev))
3081{
3082        ktime_t calltime = ktime_set(0, 0);
3083
3084        dev_dbg(&dev->dev, "calling %pF\n", fn);
3085        if (initcall_debug) {
3086                pr_debug("calling  %pF @ %i for %s\n",
3087                         fn, task_pid_nr(current), dev_name(&dev->dev));
3088                calltime = ktime_get();
3089        }
3090
3091        return calltime;
3092}
3093
3094static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3095                               void (*fn)(struct pci_dev *dev))
3096{
3097        ktime_t delta, rettime;
3098        unsigned long long duration;
3099
3100        if (initcall_debug) {
3101                rettime = ktime_get();
3102                delta = ktime_sub(rettime, calltime);
3103                duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3104                pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3105                         fn, duration, dev_name(&dev->dev));
3106        }
3107}
3108
3109#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
3110
3111/*
3112 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3113 * even though no one is handling them (f.e. i915 driver is never loaded).
3114 * Additionally the interrupt destination is not set up properly
3115 * and the interrupt ends up -somewhere-.
3116 *
3117 * These spurious interrupts are "sticky" and the kernel disables
3118 * the (shared) interrupt line after 100.000+ generated interrupts.
3119 *
3120 * Fix it by disabling the still enabled interrupts.
3121 * This resolves crashes often seen on monitor unplug.
3122 */
3123#define I915_DEIER_REG 0x4400c
3124static void disable_igfx_irq(struct pci_dev *dev)
3125{
3126        void __iomem *regs = pci_iomap(dev, 0, 0);
3127        if (regs == NULL) {
3128                dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3129                return;
3130        }
3131
3132        /* Check if any interrupt line is still enabled */
3133        if (readl(regs + I915_DEIER_REG) != 0) {
3134                dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3135
3136                writel(0, regs + I915_DEIER_REG);
3137        }
3138
3139        pci_iounmap(dev, regs);
3140}
3141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3144
3145#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
3146
3147/*
3148 * PCI devices which are on Intel chips can skip the 10ms delay
3149 * before entering D3 mode.
3150 */
3151static void quirk_remove_d3_delay(struct pci_dev *dev)
3152{
3153        dev->d3_delay = 0;
3154}
3155/* C600 Series devices do not need 10ms d3_delay */
3156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3159/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3171/* Intel Cherrytrail devices do not need 10ms d3_delay */
3172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3181
3182/*
3183 * Some devices may pass our check in pci_intx_mask_supported() if
3184 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3185 * support this feature.
3186 */
3187static void quirk_broken_intx_masking(struct pci_dev *dev)
3188{
3189        dev->broken_intx_masking = 1;
3190}
3191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3192                        quirk_broken_intx_masking);
3193DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3194                        quirk_broken_intx_masking);
3195
3196/*
3197 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3198 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3199 *
3200 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3201 */
3202DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3203                        quirk_broken_intx_masking);
3204
3205/*
3206 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3207 * DisINTx can be set but the interrupt status bit is non-functional.
3208 */
3209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3210                        quirk_broken_intx_masking);
3211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3212                        quirk_broken_intx_masking);
3213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3214                        quirk_broken_intx_masking);
3215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3216                        quirk_broken_intx_masking);
3217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3218                        quirk_broken_intx_masking);
3219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3220                        quirk_broken_intx_masking);
3221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3222                        quirk_broken_intx_masking);
3223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3224                        quirk_broken_intx_masking);
3225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3226                        quirk_broken_intx_masking);
3227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3228                        quirk_broken_intx_masking);
3229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3230                        quirk_broken_intx_masking);
3231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3232                        quirk_broken_intx_masking);
3233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3234                        quirk_broken_intx_masking);
3235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3236                        quirk_broken_intx_masking);
3237
3238static u16 mellanox_broken_intx_devs[] = {
3239        PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3240        PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3241        PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3242        PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3243        PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3244        PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3245        PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3246        PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3247        PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3248        PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3249        PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3250        PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3251        PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3252        PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3253};
3254
3255#define CONNECTX_4_CURR_MAX_MINOR 99
3256#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3257
3258/*
3259 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3260 * If so, don't mark it as broken.
3261 * FW minor > 99 means older FW version format and no INTx masking support.
3262 * FW minor < 14 means new FW version format and no INTx masking support.
3263 */
3264static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3265{
3266        __be32 __iomem *fw_ver;
3267        u16 fw_major;
3268        u16 fw_minor;
3269        u16 fw_subminor;
3270        u32 fw_maj_min;
3271        u32 fw_sub_min;
3272        int i;
3273
3274        for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3275                if (pdev->device == mellanox_broken_intx_devs[i]) {
3276                        pdev->broken_intx_masking = 1;
3277                        return;
3278                }
3279        }
3280
3281        /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3282         * support so shouldn't be checked further
3283         */
3284        if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3285                return;
3286
3287        if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3288            pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3289                return;
3290
3291        /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3292        if (pci_enable_device_mem(pdev)) {
3293                dev_warn(&pdev->dev, "Can't enable device memory\n");
3294                return;
3295        }
3296
3297        fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3298        if (!fw_ver) {
3299                dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3300                goto out;
3301        }
3302
3303        /* Reading from resource space should be 32b aligned */
3304        fw_maj_min = ioread32be(fw_ver);
3305        fw_sub_min = ioread32be(fw_ver + 1);
3306        fw_major = fw_maj_min & 0xffff;
3307        fw_minor = fw_maj_min >> 16;
3308        fw_subminor = fw_sub_min & 0xffff;
3309        if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3310            fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3311                dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3312                         fw_major, fw_minor, fw_subminor, pdev->device ==
3313                         PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3314                pdev->broken_intx_masking = 1;
3315        }
3316
3317        iounmap(fw_ver);
3318
3319out:
3320        pci_disable_device(pdev);
3321}
3322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3323                        mellanox_check_broken_intx_masking);
3324
3325static void quirk_no_bus_reset(struct pci_dev *dev)
3326{
3327        dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3328}
3329
3330/*
3331 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3332 * The device will throw a Link Down error on AER-capable systems and
3333 * regardless of AER, config space of the device is never accessible again
3334 * and typically causes the system to hang or reset when access is attempted.
3335 * http://www.spinics.net/lists/linux-pci/msg34797.html
3336 */
3337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3341
3342static void quirk_no_pm_reset(struct pci_dev *dev)
3343{
3344        /*
3345         * We can't do a bus reset on root bus devices, but an ineffective
3346         * PM reset may be better than nothing.
3347         */
3348        if (!pci_is_root_bus(dev->bus))
3349                dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3350}
3351
3352/*
3353 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3354 * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
3355 * to have no effect on the device: it retains the framebuffer contents and
3356 * monitor sync.  Advertising this support makes other layers, like VFIO,
3357 * assume pci_reset_function() is viable for this device.  Mark it as
3358 * unavailable to skip it when testing reset methods.
3359 */
3360DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3361                               PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3362
3363/*
3364 * Thunderbolt controllers with broken MSI hotplug signaling:
3365 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3366 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3367 */
3368static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3369{
3370        if (pdev->is_hotplug_bridge &&
3371            (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3372             pdev->revision <= 1))
3373                pdev->no_msi = 1;
3374}
3375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3376                        quirk_thunderbolt_hotplug_msi);
3377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3378                        quirk_thunderbolt_hotplug_msi);
3379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3380                        quirk_thunderbolt_hotplug_msi);
3381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3382                        quirk_thunderbolt_hotplug_msi);
3383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3384                        quirk_thunderbolt_hotplug_msi);
3385
3386static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3387{
3388        pci_set_vpd_size(dev, 8192);
3389}
3390
3391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3404
3405#ifdef CONFIG_ACPI
3406/*
3407 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3408 *
3409 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3410 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3411 * be present after resume if a device was plugged in before suspend.
3412 *
3413 * The thunderbolt controller consists of a pcie switch with downstream
3414 * bridges leading to the NHI and to the tunnel pci bridges.
3415 *
3416 * This quirk cuts power to the whole chip. Therefore we have to apply it
3417 * during suspend_noirq of the upstream bridge.
3418 *
3419 * Power is automagically restored before resume. No action is needed.
3420 */
3421static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3422{
3423        acpi_handle bridge, SXIO, SXFP, SXLV;
3424
3425        if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3426                return;
3427        if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3428                return;
3429        bridge = ACPI_HANDLE(&dev->dev);
3430        if (!bridge)
3431                return;
3432        /*
3433         * SXIO and SXLV are present only on machines requiring this quirk.
3434         * TB bridges in external devices might have the same device id as those
3435         * on the host, but they will not have the associated ACPI methods. This
3436         * implicitly checks that we are at the right bridge.
3437         */
3438        if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3439            || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3440            || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3441                return;
3442        dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3443
3444        /* magic sequence */
3445        acpi_execute_simple_method(SXIO, NULL, 1);
3446        acpi_execute_simple_method(SXFP, NULL, 0);
3447        msleep(300);
3448        acpi_execute_simple_method(SXLV, NULL, 0);
3449        acpi_execute_simple_method(SXIO, NULL, 0);
3450        acpi_execute_simple_method(SXLV, NULL, 0);
3451}
3452DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3453                               PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3454                               quirk_apple_poweroff_thunderbolt);
3455
3456/*
3457 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3458 *
3459 * During suspend the thunderbolt controller is reset and all pci
3460 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3461 * during resume. We have to manually wait for the NHI since there is
3462 * no parent child relationship between the NHI and the tunneled
3463 * bridges.
3464 */
3465static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3466{
3467        struct pci_dev *sibling = NULL;
3468        struct pci_dev *nhi = NULL;
3469
3470        if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3471                return;
3472        if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3473                return;
3474        /*
3475         * Find the NHI and confirm that we are a bridge on the tb host
3476         * controller and not on a tb endpoint.
3477         */
3478        sibling = pci_get_slot(dev->bus, 0x0);
3479        if (sibling == dev)
3480                goto out; /* we are the downstream bridge to the NHI */
3481        if (!sibling || !sibling->subordinate)
3482                goto out;
3483        nhi = pci_get_slot(sibling->subordinate, 0x0);
3484        if (!nhi)
3485                goto out;
3486        if (nhi->vendor != PCI_VENDOR_ID_INTEL
3487                    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3488                        nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3489                        nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3490                        nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3491                    || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3492                goto out;
3493        dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3494        device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3495out:
3496        pci_dev_put(nhi);
3497        pci_dev_put(sibling);
3498}
3499DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3500                               PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3501                               quirk_apple_wait_for_thunderbolt);
3502DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3503                               PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3504                               quirk_apple_wait_for_thunderbolt);
3505DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3506                               PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3507                               quirk_apple_wait_for_thunderbolt);
3508DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3509                               PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3510                               quirk_apple_wait_for_thunderbolt);
3511#endif
3512
3513static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3514                          struct pci_fixup *end)
3515{
3516        ktime_t calltime;
3517
3518        for (; f < end; f++)
3519                if ((f->class == (u32) (dev->class >> f->class_shift) ||
3520                     f->class == (u32) PCI_ANY_ID) &&
3521                    (f->vendor == dev->vendor ||
3522                     f->vendor == (u16) PCI_ANY_ID) &&
3523                    (f->device == dev->device ||
3524                     f->device == (u16) PCI_ANY_ID)) {
3525                        calltime = fixup_debug_start(dev, f->hook);
3526                        f->hook(dev);
3527                        fixup_debug_report(dev, calltime, f->hook);
3528                }
3529}
3530
3531extern struct pci_fixup __start_pci_fixups_early[];
3532extern struct pci_fixup __end_pci_fixups_early[];
3533extern struct pci_fixup __start_pci_fixups_header[];
3534extern struct pci_fixup __end_pci_fixups_header[];
3535extern struct pci_fixup __start_pci_fixups_final[];
3536extern struct pci_fixup __end_pci_fixups_final[];
3537extern struct pci_fixup __start_pci_fixups_enable[];
3538extern struct pci_fixup __end_pci_fixups_enable[];
3539extern struct pci_fixup __start_pci_fixups_resume[];
3540extern struct pci_fixup __end_pci_fixups_resume[];
3541extern struct pci_fixup __start_pci_fixups_resume_early[];
3542extern struct pci_fixup __end_pci_fixups_resume_early[];
3543extern struct pci_fixup __start_pci_fixups_suspend[];
3544extern struct pci_fixup __end_pci_fixups_suspend[];
3545extern struct pci_fixup __start_pci_fixups_suspend_late[];
3546extern struct pci_fixup __end_pci_fixups_suspend_late[];
3547
3548static bool pci_apply_fixup_final_quirks;
3549
3550void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3551{
3552        struct pci_fixup *start, *end;
3553
3554        switch (pass) {
3555        case pci_fixup_early:
3556                start = __start_pci_fixups_early;
3557                end = __end_pci_fixups_early;
3558                break;
3559
3560        case pci_fixup_header:
3561                start = __start_pci_fixups_header;
3562                end = __end_pci_fixups_header;
3563                break;
3564
3565        case pci_fixup_final:
3566                if (!pci_apply_fixup_final_quirks)
3567                        return;
3568                start = __start_pci_fixups_final;
3569                end = __end_pci_fixups_final;
3570                break;
3571
3572        case pci_fixup_enable:
3573                start = __start_pci_fixups_enable;
3574                end = __end_pci_fixups_enable;
3575                break;
3576
3577        case pci_fixup_resume:
3578                start = __start_pci_fixups_resume;
3579                end = __end_pci_fixups_resume;
3580                break;
3581
3582        case pci_fixup_resume_early:
3583                start = __start_pci_fixups_resume_early;
3584                end = __end_pci_fixups_resume_early;
3585                break;
3586
3587        case pci_fixup_suspend:
3588                start = __start_pci_fixups_suspend;
3589                end = __end_pci_fixups_suspend;
3590                break;
3591
3592        case pci_fixup_suspend_late:
3593                start = __start_pci_fixups_suspend_late;
3594                end = __end_pci_fixups_suspend_late;
3595                break;
3596
3597        default:
3598                /* stupid compiler warning, you would think with an enum... */
3599                return;
3600        }
3601        pci_do_fixups(dev, start, end);
3602}
3603EXPORT_SYMBOL(pci_fixup_device);
3604
3605
3606static int __init pci_apply_final_quirks(void)
3607{
3608        struct pci_dev *dev = NULL;
3609        u8 cls = 0;
3610        u8 tmp;
3611
3612        if (pci_cache_line_size)
3613                printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3614                       pci_cache_line_size << 2);
3615
3616        pci_apply_fixup_final_quirks = true;
3617        for_each_pci_dev(dev) {
3618                pci_fixup_device(pci_fixup_final, dev);
3619                /*
3620                 * If arch hasn't set it explicitly yet, use the CLS
3621                 * value shared by all PCI devices.  If there's a
3622                 * mismatch, fall back to the default value.
3623                 */
3624                if (!pci_cache_line_size) {
3625                        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3626                        if (!cls)
3627                                cls = tmp;
3628                        if (!tmp || cls == tmp)
3629                                continue;
3630
3631                        printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3632                               cls << 2, tmp << 2,
3633                               pci_dfl_cache_line_size << 2);
3634                        pci_cache_line_size = pci_dfl_cache_line_size;
3635                }
3636        }
3637
3638        if (!pci_cache_line_size) {
3639                printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3640                       cls << 2, pci_dfl_cache_line_size << 2);
3641                pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3642        }
3643
3644        return 0;
3645}
3646
3647fs_initcall_sync(pci_apply_final_quirks);
3648
3649/*
3650 * Followings are device-specific reset methods which can be used to
3651 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3652 * not available.
3653 */
3654static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3655{
3656        /*
3657         * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3658         *
3659         * The 82599 supports FLR on VFs, but FLR support is reported only
3660         * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3661         * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3662         */
3663
3664        if (probe)
3665                return 0;
3666
3667        if (!pci_wait_for_pending_transaction(dev))
3668                dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3669
3670        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3671
3672        msleep(100);
3673
3674        return 0;
3675}
3676
3677#define SOUTH_CHICKEN2          0xc2004
3678#define PCH_PP_STATUS           0xc7200
3679#define PCH_PP_CONTROL          0xc7204
3680#define MSG_CTL                 0x45010
3681#define NSDE_PWR_STATE          0xd0100
3682#define IGD_OPERATION_TIMEOUT   10000     /* set timeout 10 seconds */
3683
3684static int reset_ivb_igd(struct pci_dev *dev, int probe)
3685{
3686        void __iomem *mmio_base;
3687        unsigned long timeout;
3688        u32 val;
3689
3690        if (probe)
3691                return 0;
3692
3693        mmio_base = pci_iomap(dev, 0, 0);
3694        if (!mmio_base)
3695                return -ENOMEM;
3696
3697        iowrite32(0x00000002, mmio_base + MSG_CTL);
3698
3699        /*
3700         * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3701         * driver loaded sets the right bits. However, this's a reset and
3702         * the bits have been set by i915 previously, so we clobber
3703         * SOUTH_CHICKEN2 register directly here.
3704         */
3705        iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3706
3707        val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3708        iowrite32(val, mmio_base + PCH_PP_CONTROL);
3709
3710        timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3711        do {
3712                val = ioread32(mmio_base + PCH_PP_STATUS);
3713                if ((val & 0xb0000000) == 0)
3714                        goto reset_complete;
3715                msleep(10);
3716        } while (time_before(jiffies, timeout));
3717        dev_warn(&dev->dev, "timeout during reset\n");
3718
3719reset_complete:
3720        iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3721
3722        pci_iounmap(dev, mmio_base);
3723        return 0;
3724}
3725
3726/*
3727 * Device-specific reset method for Chelsio T4-based adapters.
3728 */
3729static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3730{
3731        u16 old_command;
3732        u16 msix_flags;
3733
3734        /*
3735         * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3736         * that we have no device-specific reset method.
3737         */
3738        if ((dev->device & 0xf000) != 0x4000)
3739                return -ENOTTY;
3740
3741        /*
3742         * If this is the "probe" phase, return 0 indicating that we can
3743         * reset this device.
3744         */
3745        if (probe)
3746                return 0;
3747
3748        /*
3749         * T4 can wedge if there are DMAs in flight within the chip and Bus
3750         * Master has been disabled.  We need to have it on till the Function
3751         * Level Reset completes.  (BUS_MASTER is disabled in
3752         * pci_reset_function()).
3753         */
3754        pci_read_config_word(dev, PCI_COMMAND, &old_command);
3755        pci_write_config_word(dev, PCI_COMMAND,
3756                              old_command | PCI_COMMAND_MASTER);
3757
3758        /*
3759         * Perform the actual device function reset, saving and restoring
3760         * configuration information around the reset.
3761         */
3762        pci_save_state(dev);
3763
3764        /*
3765         * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3766         * are disabled when an MSI-X interrupt message needs to be delivered.
3767         * So we briefly re-enable MSI-X interrupts for the duration of the
3768         * FLR.  The pci_restore_state() below will restore the original
3769         * MSI-X state.
3770         */
3771        pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3772        if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3773                pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3774                                      msix_flags |
3775                                      PCI_MSIX_FLAGS_ENABLE |
3776                                      PCI_MSIX_FLAGS_MASKALL);
3777
3778        /*
3779         * Start of pcie_flr() code sequence.  This reset code is a copy of
3780         * the guts of pcie_flr() because that's not an exported function.
3781         */
3782
3783        if (!pci_wait_for_pending_transaction(dev))
3784                dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3785
3786        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3787        msleep(100);
3788
3789        /*
3790         * End of pcie_flr() code sequence.
3791         */
3792
3793        /*
3794         * Restore the configuration information (BAR values, etc.) including
3795         * the original PCI Configuration Space Command word, and return
3796         * success.
3797         */
3798        pci_restore_state(dev);
3799        pci_write_config_word(dev, PCI_COMMAND, old_command);
3800        return 0;
3801}
3802
3803#define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
3804#define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
3805#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166
3806
3807static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3808        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3809                 reset_intel_82599_sfp_virtfn },
3810        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3811                reset_ivb_igd },
3812        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3813                reset_ivb_igd },
3814        { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3815                reset_chelsio_generic_dev },
3816        { 0 }
3817};
3818
3819/*
3820 * These device-specific reset methods are here rather than in a driver
3821 * because when a host assigns a device to a guest VM, the host may need
3822 * to reset the device but probably doesn't have a driver for it.
3823 */
3824int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3825{
3826        const struct pci_dev_reset_methods *i;
3827
3828        for (i = pci_dev_reset_methods; i->reset; i++) {
3829                if ((i->vendor == dev->vendor ||
3830                     i->vendor == (u16)PCI_ANY_ID) &&
3831                    (i->device == dev->device ||
3832                     i->device == (u16)PCI_ANY_ID))
3833                        return i->reset(dev, probe);
3834        }
3835
3836        return -ENOTTY;
3837}
3838
3839static void quirk_dma_func0_alias(struct pci_dev *dev)
3840{
3841        if (PCI_FUNC(dev->devfn) != 0)
3842                pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3843}
3844
3845/*
3846 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3847 *
3848 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3849 */
3850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3852
3853static void quirk_dma_func1_alias(struct pci_dev *dev)
3854{
3855        if (PCI_FUNC(dev->devfn) != 1)
3856                pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3857}
3858
3859/*
3860 * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
3861 * SKUs function 1 is present and is a legacy IDE controller, in other
3862 * SKUs this function is not present, making this a ghost requester.
3863 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3864 */
3865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3866                         quirk_dma_func1_alias);
3867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3868                         quirk_dma_func1_alias);
3869/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3871                         quirk_dma_func1_alias);
3872/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3874                         quirk_dma_func1_alias);
3875/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3877                         quirk_dma_func1_alias);
3878/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3880                         quirk_dma_func1_alias);
3881/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3883                         quirk_dma_func1_alias);
3884/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3886                         quirk_dma_func1_alias);
3887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3888                         quirk_dma_func1_alias);
3889/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3891                         PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3892                         quirk_dma_func1_alias);
3893/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3894DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3895                         0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3896                         quirk_dma_func1_alias);
3897
3898/*
3899 * Some devices DMA with the wrong devfn, not just the wrong function.
3900 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3901 * the alias is "fixed" and independent of the device devfn.
3902 *
3903 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3904 * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
3905 * single device on the secondary bus.  In reality, the single exposed
3906 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3907 * that provides a bridge to the internal bus of the I/O processor.  The
3908 * controller supports private devices, which can be hidden from PCI config
3909 * space.  In the case of the Adaptec 3405, a private device at 01.0
3910 * appears to be the DMA engine, which therefore needs to become a DMA
3911 * alias for the device.
3912 */
3913static const struct pci_device_id fixed_dma_alias_tbl[] = {
3914        { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3915                         PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3916          .driver_data = PCI_DEVFN(1, 0) },
3917        { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3918                         PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3919          .driver_data = PCI_DEVFN(1, 0) },
3920        { 0 }
3921};
3922
3923static void quirk_fixed_dma_alias(struct pci_dev *dev)
3924{
3925        const struct pci_device_id *id;
3926
3927        id = pci_match_id(fixed_dma_alias_tbl, dev);
3928        if (id)
3929                pci_add_dma_alias(dev, id->driver_data);
3930}
3931
3932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3933
3934/*
3935 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3936 * using the wrong DMA alias for the device.  Some of these devices can be
3937 * used as either forward or reverse bridges, so we need to test whether the
3938 * device is operating in the correct mode.  We could probably apply this
3939 * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
3940 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3941 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3942 */
3943static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3944{
3945        if (!pci_is_root_bus(pdev->bus) &&
3946            pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3947            !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3948            pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3949                pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3950}
3951/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3953                         quirk_use_pcie_bridge_dma_alias);
3954/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3955DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3956/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3957DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3958/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3959DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3960
3961/*
3962 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3963 * be added as aliases to the DMA device in order to allow buffer access
3964 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3965 * programmed in the EEPROM.
3966 */
3967static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3968{
3969        pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3970        pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3971        pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3972}
3973DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3975
3976/*
3977 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3978 * class code.  Fix it.
3979 */
3980static void quirk_tw686x_class(struct pci_dev *pdev)
3981{
3982        u32 class = pdev->class;
3983
3984        /* Use "Multimedia controller" class */
3985        pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3986        dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3987                 class, pdev->class);
3988}
3989DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3990                              quirk_tw686x_class);
3991DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3992                              quirk_tw686x_class);
3993DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3994                              quirk_tw686x_class);
3995DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3996                              quirk_tw686x_class);
3997
3998/*
3999 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4000 * values for the Attribute as were supplied in the header of the
4001 * corresponding Request, except as explicitly allowed when IDO is used."
4002 *
4003 * If a non-compliant device generates a completion with a different
4004 * attribute than the request, the receiver may accept it (which itself
4005 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4006 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4007 * device access timeout.
4008 *
4009 * If the non-compliant device generates completions with zero attributes
4010 * (instead of copying the attributes from the request), we can work around
4011 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4012 * upstream devices so they always generate requests with zero attributes.
4013 *
4014 * This affects other devices under the same Root Port, but since these
4015 * attributes are performance hints, there should be no functional problem.
4016 *
4017 * Note that Configuration Space accesses are never supposed to have TLP
4018 * Attributes, so we're safe waiting till after any Configuration Space
4019 * accesses to do the Root Port fixup.
4020 */
4021static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4022{
4023        struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4024
4025        if (!root_port) {
4026                dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4027                return;
4028        }
4029
4030        dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4031                 dev_name(&pdev->dev));
4032        pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4033                                           PCI_EXP_DEVCTL_RELAX_EN |
4034                                           PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4035}
4036
4037/*
4038 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4039 * Completion it generates.
4040 */
4041static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4042{
4043        /*
4044         * This mask/compare operation selects for Physical Function 4 on a
4045         * T5.  We only need to fix up the Root Port once for any of the
4046         * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4047         * 0x54xx so we use that one,
4048         */
4049        if ((pdev->device & 0xff00) == 0x5400)
4050                quirk_disable_root_port_attributes(pdev);
4051}
4052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4053                         quirk_chelsio_T5_disable_root_port_attributes);
4054
4055/*
4056 * AMD has indicated that the devices below do not support peer-to-peer
4057 * in any system where they are found in the southbridge with an AMD
4058 * IOMMU in the system.  Multifunction devices that do not support
4059 * peer-to-peer between functions can claim to support a subset of ACS.
4060 * Such devices effectively enable request redirect (RR) and completion
4061 * redirect (CR) since all transactions are redirected to the upstream
4062 * root complex.
4063 *
4064 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4065 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4066 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4067 *
4068 * 1002:4385 SBx00 SMBus Controller
4069 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4070 * 1002:4383 SBx00 Azalia (Intel HDA)
4071 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4072 * 1002:4384 SBx00 PCI to PCI Bridge
4073 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4074 *
4075 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4076 *
4077 * 1022:780f [AMD] FCH PCI Bridge
4078 * 1022:7809 [AMD] FCH USB OHCI Controller
4079 */
4080static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4081{
4082#ifdef CONFIG_ACPI
4083        struct acpi_table_header *header = NULL;
4084        acpi_status status;
4085
4086        /* Targeting multifunction devices on the SB (appears on root bus) */
4087        if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4088                return -ENODEV;
4089
4090        /* The IVRS table describes the AMD IOMMU */
4091        status = acpi_get_table("IVRS", 0, &header);
4092        if (ACPI_FAILURE(status))
4093                return -ENODEV;
4094
4095        /* Filter out flags not applicable to multifunction */
4096        acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4097
4098        return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4099#else
4100        return -ENODEV;
4101#endif
4102}
4103
4104static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4105{
4106        /*
4107         * Cavium devices matching this quirk do not perform peer-to-peer
4108         * with other functions, allowing masking out these bits as if they
4109         * were unimplemented in the ACS capability.
4110         */
4111        acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4112                       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4113
4114        return acs_flags ? 0 : 1;
4115}
4116
4117/*
4118 * Many Intel PCH root ports do provide ACS-like features to disable peer
4119 * transactions and validate bus numbers in requests, but do not provide an
4120 * actual PCIe ACS capability.  This is the list of device IDs known to fall
4121 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4122 */
4123static const u16 pci_quirk_intel_pch_acs_ids[] = {
4124        /* Ibexpeak PCH */
4125        0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4126        0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4127        /* Cougarpoint PCH */
4128        0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4129        0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4130        /* Pantherpoint PCH */
4131        0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4132        0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4133        /* Lynxpoint-H PCH */
4134        0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4135        0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4136        /* Lynxpoint-LP PCH */
4137        0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4138        0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4139        /* Wildcat PCH */
4140        0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4141        0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4142        /* Patsburg (X79) PCH */
4143        0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4144        /* Wellsburg (X99) PCH */
4145        0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4146        0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4147        /* Lynx Point (9 series) PCH */
4148        0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4149};
4150
4151static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4152{
4153        int i;
4154
4155        /* Filter out a few obvious non-matches first */
4156        if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4157                return false;
4158
4159        for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4160                if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4161                        return true;
4162
4163        return false;
4164}
4165
4166#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4167
4168static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4169{
4170        u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4171                    INTEL_PCH_ACS_FLAGS : 0;
4172
4173        if (!pci_quirk_intel_pch_acs_match(dev))
4174                return -ENOTTY;
4175
4176        return acs_flags & ~flags ? 0 : 1;
4177}
4178
4179/*
4180 * These QCOM root ports do provide ACS-like features to disable peer
4181 * transactions and validate bus numbers in requests, but do not provide an
4182 * actual PCIe ACS capability.  Hardware supports source validation but it
4183 * will report the issue as Completer Abort instead of ACS Violation.
4184 * Hardware doesn't support peer-to-peer and each root port is a root
4185 * complex with unique segment numbers.  It is not possible for one root
4186 * port to pass traffic to another root port.  All PCIe transactions are
4187 * terminated inside the root port.
4188 */
4189static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4190{
4191        u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4192        int ret = acs_flags & ~flags ? 0 : 1;
4193
4194        dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4195
4196        return ret;
4197}
4198
4199/*
4200 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4201 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4202 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4203 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4204 * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
4205 * control register is at offset 8 instead of 6 and we should probably use
4206 * dword accesses to them.  This applies to the following PCI Device IDs, as
4207 * found in volume 1 of the datasheet[2]:
4208 *
4209 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4210 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4211 *
4212 * N.B. This doesn't fix what lspci shows.
4213 *
4214 * The 100 series chipset specification update includes this as errata #23[3].
4215 *
4216 * The 200 series chipset (Union Point) has the same bug according to the
4217 * specification update (Intel 200 Series Chipset Family Platform Controller
4218 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4219 * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
4220 * chipset include:
4221 *
4222 * 0xa290-0xa29f PCI Express Root port #{0-16}
4223 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4224 *
4225 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4226 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4227 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4228 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4229 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4230 */
4231static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4232{
4233        if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4234                return false;
4235
4236        switch (dev->device) {
4237        case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4238        case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4239                return true;
4240        }
4241
4242        return false;
4243}
4244
4245#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4246
4247static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4248{
4249        int pos;
4250        u32 cap, ctrl;
4251
4252        if (!pci_quirk_intel_spt_pch_acs_match(dev))
4253                return -ENOTTY;
4254
4255        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4256        if (!pos)
4257                return -ENOTTY;
4258
4259        /* see pci_acs_flags_enabled() */
4260        pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4261        acs_flags &= (cap | PCI_ACS_EC);
4262
4263        pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4264
4265        return acs_flags & ~ctrl ? 0 : 1;
4266}
4267
4268static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4269{
4270        /*
4271         * SV, TB, and UF are not relevant to multifunction endpoints.
4272         *
4273         * Multifunction devices are only required to implement RR, CR, and DT
4274         * in their ACS capability if they support peer-to-peer transactions.
4275         * Devices matching this quirk have been verified by the vendor to not
4276         * perform peer-to-peer with other functions, allowing us to mask out
4277         * these bits as if they were unimplemented in the ACS capability.
4278         */
4279        acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4280                       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4281
4282        return acs_flags ? 0 : 1;
4283}
4284
4285static const struct pci_dev_acs_enabled {
4286        u16 vendor;
4287        u16 device;
4288        int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4289} pci_dev_acs_enabled[] = {
4290        { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4291        { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4292        { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4293        { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4294        { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4295        { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4296        { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4297        { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4298        { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4299        { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4300        { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4301        { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4302        { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4303        { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4304        { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4305        { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4306        { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4307        { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4308        { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4309        { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4310        { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4311        { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4312        { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4313        { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4314        { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4315        { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4316        { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4317        { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4318        { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4319        { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4320        { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4321        /* 82580 */
4322        { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4323        { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4324        { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4325        { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4326        { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4327        { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4328        { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4329        /* 82576 */
4330        { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4331        { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4332        { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4333        { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4334        { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4335        { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4336        { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4337        { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4338        /* 82575 */
4339        { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4340        { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4341        { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4342        /* I350 */
4343        { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4344        { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4345        { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4346        { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4347        /* 82571 (Quads omitted due to non-ACS switch) */
4348        { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4349        { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4350        { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4351        { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4352        /* I219 */
4353        { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4354        { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4355        /* QCOM QDF2xxx root ports */
4356        { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4357        { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4358        /* Intel PCH root ports */
4359        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4360        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4361        { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4362        { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4363        /* Cavium ThunderX */
4364        { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4365        { 0 }
4366};
4367
4368int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4369{
4370        const struct pci_dev_acs_enabled *i;
4371        int ret;
4372
4373        /*
4374         * Allow devices that do not expose standard PCIe ACS capabilities
4375         * or control to indicate their support here.  Multi-function express
4376         * devices which do not allow internal peer-to-peer between functions,
4377         * but do not implement PCIe ACS may wish to return true here.
4378         */
4379        for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4380                if ((i->vendor == dev->vendor ||
4381                     i->vendor == (u16)PCI_ANY_ID) &&
4382                    (i->device == dev->device ||
4383                     i->device == (u16)PCI_ANY_ID)) {
4384                        ret = i->acs_enabled(dev, acs_flags);
4385                        if (ret >= 0)
4386                                return ret;
4387                }
4388        }
4389
4390        return -ENOTTY;
4391}
4392
4393/* Config space offset of Root Complex Base Address register */
4394#define INTEL_LPC_RCBA_REG 0xf0
4395/* 31:14 RCBA address */
4396#define INTEL_LPC_RCBA_MASK 0xffffc000
4397/* RCBA Enable */
4398#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4399
4400/* Backbone Scratch Pad Register */
4401#define INTEL_BSPR_REG 0x1104
4402/* Backbone Peer Non-Posted Disable */
4403#define INTEL_BSPR_REG_BPNPD (1 << 8)
4404/* Backbone Peer Posted Disable */
4405#define INTEL_BSPR_REG_BPPD  (1 << 9)
4406
4407/* Upstream Peer Decode Configuration Register */
4408#define INTEL_UPDCR_REG 0x1114
4409/* 5:0 Peer Decode Enable bits */
4410#define INTEL_UPDCR_REG_MASK 0x3f
4411
4412static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4413{
4414        u32 rcba, bspr, updcr;
4415        void __iomem *rcba_mem;
4416
4417        /*
4418         * Read the RCBA register from the LPC (D31:F0).  PCH root ports
4419         * are D28:F* and therefore get probed before LPC, thus we can't
4420         * use pci_get_slot/pci_read_config_dword here.
4421         */
4422        pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4423                                  INTEL_LPC_RCBA_REG, &rcba);
4424        if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4425                return -EINVAL;
4426
4427        rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4428                                   PAGE_ALIGN(INTEL_UPDCR_REG));
4429        if (!rcba_mem)
4430                return -ENOMEM;
4431
4432        /*
4433         * The BSPR can disallow peer cycles, but it's set by soft strap and
4434         * therefore read-only.  If both posted and non-posted peer cycles are
4435         * disallowed, we're ok.  If either are allowed, then we need to use
4436         * the UPDCR to disable peer decodes for each port.  This provides the
4437         * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4438         */
4439        bspr = readl(rcba_mem + INTEL_BSPR_REG);
4440        bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4441        if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4442                updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4443                if (updcr & INTEL_UPDCR_REG_MASK) {
4444                        dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4445                        updcr &= ~INTEL_UPDCR_REG_MASK;
4446                        writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4447                }
4448        }
4449
4450        iounmap(rcba_mem);
4451        return 0;
4452}
4453
4454/* Miscellaneous Port Configuration register */
4455#define INTEL_MPC_REG 0xd8
4456/* MPC: Invalid Receive Bus Number Check Enable */
4457#define INTEL_MPC_REG_IRBNCE (1 << 26)
4458
4459static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4460{
4461        u32 mpc;
4462
4463        /*
4464         * When enabled, the IRBNCE bit of the MPC register enables the
4465         * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4466         * ensures that requester IDs fall within the bus number range
4467         * of the bridge.  Enable if not already.
4468         */
4469        pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4470        if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4471                dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4472                mpc |= INTEL_MPC_REG_IRBNCE;
4473                pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4474        }
4475}
4476
4477static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4478{
4479        if (!pci_quirk_intel_pch_acs_match(dev))
4480                return -ENOTTY;
4481
4482        if (pci_quirk_enable_intel_lpc_acs(dev)) {
4483                dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4484                return 0;
4485        }
4486
4487        pci_quirk_enable_intel_rp_mpc_acs(dev);
4488
4489        dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4490
4491        dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4492
4493        return 0;
4494}
4495
4496static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4497{
4498        int pos;
4499        u32 cap, ctrl;
4500
4501        if (!pci_quirk_intel_spt_pch_acs_match(dev))
4502                return -ENOTTY;
4503
4504        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4505        if (!pos)
4506                return -ENOTTY;
4507
4508        pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4509        pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4510
4511        ctrl |= (cap & PCI_ACS_SV);
4512        ctrl |= (cap & PCI_ACS_RR);
4513        ctrl |= (cap & PCI_ACS_CR);
4514        ctrl |= (cap & PCI_ACS_UF);
4515
4516        pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4517
4518        dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4519
4520        return 0;
4521}
4522
4523static const struct pci_dev_enable_acs {
4524        u16 vendor;
4525        u16 device;
4526        int (*enable_acs)(struct pci_dev *dev);
4527} pci_dev_enable_acs[] = {
4528        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4529        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4530        { 0 }
4531};
4532
4533int pci_dev_specific_enable_acs(struct pci_dev *dev)
4534{
4535        const struct pci_dev_enable_acs *i;
4536        int ret;
4537
4538        for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4539                if ((i->vendor == dev->vendor ||
4540                     i->vendor == (u16)PCI_ANY_ID) &&
4541                    (i->device == dev->device ||
4542                     i->device == (u16)PCI_ANY_ID)) {
4543                        ret = i->enable_acs(dev);
4544                        if (ret >= 0)
4545                                return ret;
4546                }
4547        }
4548
4549        return -ENOTTY;
4550}
4551
4552/*
4553 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4554 * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
4555 * Next Capability pointer in the MSI Capability Structure should point to
4556 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4557 * the list.
4558 */
4559static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4560{
4561        int pos, i = 0;
4562        u8 next_cap;
4563        u16 reg16, *cap;
4564        struct pci_cap_saved_state *state;
4565
4566        /* Bail if the hardware bug is fixed */
4567        if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4568                return;
4569
4570        /* Bail if MSI Capability Structure is not found for some reason */
4571        pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4572        if (!pos)
4573                return;
4574
4575        /*
4576         * Bail if Next Capability pointer in the MSI Capability Structure
4577         * is not the expected incorrect 0x00.
4578         */
4579        pci_read_config_byte(pdev, pos + 1, &next_cap);
4580        if (next_cap)
4581                return;
4582
4583        /*
4584         * PCIe Capability Structure is expected to be at 0x50 and should
4585         * terminate the list (Next Capability pointer is 0x00).  Verify
4586         * Capability Id and Next Capability pointer is as expected.
4587         * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4588         * to correctly set kernel data structures which have already been
4589         * set incorrectly due to the hardware bug.
4590         */
4591        pos = 0x50;
4592        pci_read_config_word(pdev, pos, &reg16);
4593        if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4594                u32 status;
4595#ifndef PCI_EXP_SAVE_REGS
4596#define PCI_EXP_SAVE_REGS     7
4597#endif
4598                int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4599
4600                pdev->pcie_cap = pos;
4601                pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4602                pdev->pcie_flags_reg = reg16;
4603                pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4604                pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4605
4606                pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4607                if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4608                    PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4609                        pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4610
4611                if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4612                        return;
4613
4614                /*
4615                 * Save PCIE cap
4616                 */
4617                state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4618                if (!state)
4619                        return;
4620
4621                state->cap.cap_nr = PCI_CAP_ID_EXP;
4622                state->cap.cap_extended = 0;
4623                state->cap.size = size;
4624                cap = (u16 *)&state->cap.data[0];
4625                pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4626                pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4627                pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4628                pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
4629                pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4630                pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4631                pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4632                hlist_add_head(&state->next, &pdev->saved_cap_space);
4633        }
4634}
4635DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4636
4637/*
4638 * VMD-enabled root ports will change the source ID for all messages
4639 * to the VMD device. Rather than doing device matching with the source
4640 * ID, the AER driver should traverse the child device tree, reading
4641 * AER registers to find the faulting device.
4642 */
4643static void quirk_no_aersid(struct pci_dev *pdev)
4644{
4645        /* VMD Domain */
4646        if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4647                pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4648}
4649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
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