source: src/linux/universal/linux-4.9/drivers/usb/host/xhci.h @ 31859

Last change on this file since 31859 was 31859, checked in by brainslayer, 11 days ago

kernel update

File size: 69.1 KB
Line 
1
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef __LINUX_XHCI_HCD_H
25#define __LINUX_XHCI_HCD_H
26
27#include <linux/usb.h>
28#include <linux/timer.h>
29#include <linux/kernel.h>
30#include <linux/usb/hcd.h>
31#include <linux/io-64-nonatomic-lo-hi.h>
32
33/* Code sharing between pci-quirks and xhci hcd */
34#include        "xhci-ext-caps.h"
35#include "pci-quirks.h"
36
37/* xHCI PCI Configuration Registers */
38#define XHCI_SBRN_OFFSET        (0x60)
39
40/* Max number of USB devices for any host controller - limit in section 6.1 */
41#define MAX_HC_SLOTS            256
42/* Section 5.3.3 - MaxPorts */
43#define MAX_HC_PORTS            127
44
45/*
46 * xHCI register interface.
47 * This corresponds to the eXtensible Host Controller Interface (xHCI)
48 * Revision 0.95 specification
49 */
50
51/**
52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
53 * @hc_capbase:         length of the capabilities register and HC version number
54 * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
55 * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
56 * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
57 * @hcc_params:         HCCPARAMS - Capability Parameters
58 * @db_off:             DBOFF - Doorbell array offset
59 * @run_regs_off:       RTSOFF - Runtime register space offset
60 * @hcc_params2:        HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
61 */
62struct xhci_cap_regs {
63        __le32  hc_capbase;
64        __le32  hcs_params1;
65        __le32  hcs_params2;
66        __le32  hcs_params3;
67        __le32  hcc_params;
68        __le32  db_off;
69        __le32  run_regs_off;
70        __le32  hcc_params2; /* xhci 1.1 */
71        /* Reserved up to (CAPLENGTH - 0x1C) */
72};
73
74/* hc_capbase bitmasks */
75/* bits 7:0 - how long is the Capabilities register */
76#define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
77/* bits 31:16   */
78#define HC_VERSION(p)           (((p) >> 16) & 0xffff)
79
80/* HCSPARAMS1 - hcs_params1 - bitmasks */
81/* bits 0:7, Max Device Slots */
82#define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
83#define HCS_SLOTS_MASK          0xff
84/* bits 8:18, Max Interrupters */
85#define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
86/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
87#define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
88
89/* HCSPARAMS2 - hcs_params2 - bitmasks */
90/* bits 0:3, frames or uframes that SW needs to queue transactions
91 * ahead of the HW to meet periodic deadlines */
92#define HCS_IST(p)              (((p) >> 0) & 0xf)
93/* bits 4:7, max number of Event Ring segments */
94#define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
95/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
96/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
97/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
98#define HCS_MAX_SCRATCHPAD(p)   ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
99
100/* HCSPARAMS3 - hcs_params3 - bitmasks */
101/* bits 0:7, Max U1 to U0 latency for the roothub ports */
102#define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
103/* bits 16:31, Max U2 to U0 latency for the roothub ports */
104#define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
105
106/* HCCPARAMS - hcc_params - bitmasks */
107/* true: HC can use 64-bit address pointers */
108#define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
109/* true: HC can do bandwidth negotiation */
110#define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
111/* true: HC uses 64-byte Device Context structures
112 * FIXME 64-byte context structures aren't supported yet.
113 */
114#define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
115/* true: HC has port power switches */
116#define HCC_PPC(p)              ((p) & (1 << 3))
117/* true: HC has port indicators */
118#define HCS_INDICATOR(p)        ((p) & (1 << 4))
119/* true: HC has Light HC Reset Capability */
120#define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
121/* true: HC supports latency tolerance messaging */
122#define HCC_LTC(p)              ((p) & (1 << 6))
123/* true: no secondary Stream ID Support */
124#define HCC_NSS(p)              ((p) & (1 << 7))
125/* true: HC supports Stopped - Short Packet */
126#define HCC_SPC(p)              ((p) & (1 << 9))
127/* true: HC has Contiguous Frame ID Capability */
128#define HCC_CFC(p)              ((p) & (1 << 11))
129/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
130#define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
131/* Extended Capabilities pointer from PCI base - section 5.3.6 */
132#define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
133
134/* db_off bitmask - bits 0:1 reserved */
135#define DBOFF_MASK      (~0x3)
136
137/* run_regs_off bitmask - bits 0:4 reserved */
138#define RTSOFF_MASK     (~0x1f)
139
140/* HCCPARAMS2 - hcc_params2 - bitmasks */
141/* true: HC supports U3 entry Capability */
142#define HCC2_U3C(p)             ((p) & (1 << 0))
143/* true: HC supports Configure endpoint command Max exit latency too large */
144#define HCC2_CMC(p)             ((p) & (1 << 1))
145/* true: HC supports Force Save context Capability */
146#define HCC2_FSC(p)             ((p) & (1 << 2))
147/* true: HC supports Compliance Transition Capability */
148#define HCC2_CTC(p)             ((p) & (1 << 3))
149/* true: HC support Large ESIT payload Capability > 48k */
150#define HCC2_LEC(p)             ((p) & (1 << 4))
151/* true: HC support Configuration Information Capability */
152#define HCC2_CIC(p)             ((p) & (1 << 5))
153/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
154#define HCC2_ETC(p)             ((p) & (1 << 6))
155
156/* Number of registers per port */
157#define NUM_PORT_REGS   4
158
159#define PORTSC          0
160#define PORTPMSC        1
161#define PORTLI          2
162#define PORTHLPMC       3
163
164/**
165 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
166 * @command:            USBCMD - xHC command register
167 * @status:             USBSTS - xHC status register
168 * @page_size:          This indicates the page size that the host controller
169 *                      supports.  If bit n is set, the HC supports a page size
170 *                      of 2^(n+12), up to a 128MB page size.
171 *                      4K is the minimum page size.
172 * @cmd_ring:           CRP - 64-bit Command Ring Pointer
173 * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
174 * @config_reg:         CONFIG - Configure Register
175 * @port_status_base:   PORTSCn - base address for Port Status and Control
176 *                      Each port has a Port Status and Control register,
177 *                      followed by a Port Power Management Status and Control
178 *                      register, a Port Link Info register, and a reserved
179 *                      register.
180 * @port_power_base:    PORTPMSCn - base address for
181 *                      Port Power Management Status and Control
182 * @port_link_base:     PORTLIn - base address for Port Link Info (current
183 *                      Link PM state and control) for USB 2.1 and USB 3.0
184 *                      devices.
185 */
186struct xhci_op_regs {
187        __le32  command;
188        __le32  status;
189        __le32  page_size;
190        __le32  reserved1;
191        __le32  reserved2;
192        __le32  dev_notification;
193        __le64  cmd_ring;
194        /* rsvd: offset 0x20-2F */
195        __le32  reserved3[4];
196        __le64  dcbaa_ptr;
197        __le32  config_reg;
198        /* rsvd: offset 0x3C-3FF */
199        __le32  reserved4[241];
200        /* port 1 registers, which serve as a base address for other ports */
201        __le32  port_status_base;
202        __le32  port_power_base;
203        __le32  port_link_base;
204        __le32  reserved5;
205        /* registers for ports 2-255 */
206        __le32  reserved6[NUM_PORT_REGS*254];
207};
208
209/* USBCMD - USB command - command bitmasks */
210/* start/stop HC execution - do not write unless HC is halted*/
211#define CMD_RUN         XHCI_CMD_RUN
212/* Reset HC - resets internal HC state machine and all registers (except
213 * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
214 * The xHCI driver must reinitialize the xHC after setting this bit.
215 */
216#define CMD_RESET       (1 << 1)
217/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
218#define CMD_EIE         XHCI_CMD_EIE
219/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
220#define CMD_HSEIE       XHCI_CMD_HSEIE
221/* bits 4:6 are reserved (and should be preserved on writes). */
222/* light reset (port status stays unchanged) - reset completed when this is 0 */
223#define CMD_LRESET      (1 << 7)
224/* host controller save/restore state. */
225#define CMD_CSS         (1 << 8)
226#define CMD_CRS         (1 << 9)
227/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
228#define CMD_EWE         XHCI_CMD_EWE
229/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
231 * '0' means the xHC can power it off if all ports are in the disconnect,
232 * disabled, or powered-off state.
233 */
234#define CMD_PM_INDEX    (1 << 11)
235/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
236#define CMD_ETE         (1 << 14)
237/* bits 15:31 are reserved (and should be preserved on writes). */
238
239/* IMAN - Interrupt Management Register */
240#define IMAN_IE         (1 << 1)
241#define IMAN_IP         (1 << 0)
242
243/* USBSTS - USB status - status bitmasks */
244/* HC not running - set to 1 when run/stop bit is cleared. */
245#define STS_HALT        XHCI_STS_HALT
246/* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
247#define STS_FATAL       (1 << 2)
248/* event interrupt - clear this prior to clearing any IP flags in IR set*/
249#define STS_EINT        (1 << 3)
250/* port change detect */
251#define STS_PORT        (1 << 4)
252/* bits 5:7 reserved and zeroed */
253/* save state status - '1' means xHC is saving state */
254#define STS_SAVE        (1 << 8)
255/* restore state status - '1' means xHC is restoring state */
256#define STS_RESTORE     (1 << 9)
257/* true: save or restore error */
258#define STS_SRE         (1 << 10)
259/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
260#define STS_CNR         XHCI_STS_CNR
261/* true: internal Host Controller Error - SW needs to reset and reinitialize */
262#define STS_HCE         (1 << 12)
263/* bits 13:31 reserved and should be preserved */
264
265/*
266 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
267 * Generate a device notification event when the HC sees a transaction with a
268 * notification type that matches a bit set in this bit field.
269 */
270#define DEV_NOTE_MASK           (0xffff)
271#define ENABLE_DEV_NOTE(x)      (1 << (x))
272/* Most of the device notification types should only be used for debug.
273 * SW does need to pay attention to function wake notifications.
274 */
275#define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
276
277/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
278/* bit 0 is the command ring cycle state */
279/* stop ring operation after completion of the currently executing command */
280#define CMD_RING_PAUSE          (1 << 1)
281/* stop ring immediately - abort the currently executing command */
282#define CMD_RING_ABORT          (1 << 2)
283/* true: command ring is running */
284#define CMD_RING_RUNNING        (1 << 3)
285/* bits 4:5 reserved and should be preserved */
286/* Command Ring pointer - bit mask for the lower 32 bits. */
287#define CMD_RING_RSVD_BITS      (0x3f)
288
289/* CONFIG - Configure Register - config_reg bitmasks */
290/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
291#define MAX_DEVS(p)     ((p) & 0xff)
292/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
293#define CONFIG_U3E              (1 << 8)
294/* bit 9: Configuration Information Enable, xhci 1.1 */
295#define CONFIG_CIE              (1 << 9)
296/* bits 10:31 - reserved and should be preserved */
297
298/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
299/* true: device connected */
300#define PORT_CONNECT    (1 << 0)
301/* true: port enabled */
302#define PORT_PE         (1 << 1)
303/* bit 2 reserved and zeroed */
304/* true: port has an over-current condition */
305#define PORT_OC         (1 << 3)
306/* true: port reset signaling asserted */
307#define PORT_RESET      (1 << 4)
308/* Port Link State - bits 5:8
309 * A read gives the current link PM state of the port,
310 * a write with Link State Write Strobe set sets the link state.
311 */
312#define PORT_PLS_MASK   (0xf << 5)
313#define XDEV_U0         (0x0 << 5)
314#define XDEV_U2         (0x2 << 5)
315#define XDEV_U3         (0x3 << 5)
316#define XDEV_INACTIVE   (0x6 << 5)
317#define XDEV_POLLING    (0x7 << 5)
318#define XDEV_COMP_MODE  (0xa << 5)
319#define XDEV_RESUME     (0xf << 5)
320/* true: port has power (see HCC_PPC) */
321#define PORT_POWER      (1 << 9)
322/* bits 10:13 indicate device speed:
323 * 0 - undefined speed - port hasn't be initialized by a reset yet
324 * 1 - full speed
325 * 2 - low speed
326 * 3 - high speed
327 * 4 - super speed
328 * 5-15 reserved
329 */
330#define DEV_SPEED_MASK          (0xf << 10)
331#define XDEV_FS                 (0x1 << 10)
332#define XDEV_LS                 (0x2 << 10)
333#define XDEV_HS                 (0x3 << 10)
334#define XDEV_SS                 (0x4 << 10)
335#define XDEV_SSP                (0x5 << 10)
336#define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
337#define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
338#define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
339#define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
340#define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
341#define DEV_SUPERSPEEDPLUS(p)   (((p) & DEV_SPEED_MASK) == XDEV_SSP)
342#define DEV_SUPERSPEED_ANY(p)   (((p) & DEV_SPEED_MASK) >= XDEV_SS)
343#define DEV_PORT_SPEED(p)       (((p) >> 10) & 0x0f)
344
345/* Bits 20:23 in the Slot Context are the speed for the device */
346#define SLOT_SPEED_FS           (XDEV_FS << 10)
347#define SLOT_SPEED_LS           (XDEV_LS << 10)
348#define SLOT_SPEED_HS           (XDEV_HS << 10)
349#define SLOT_SPEED_SS           (XDEV_SS << 10)
350#define SLOT_SPEED_SSP          (XDEV_SSP << 10)
351/* Port Indicator Control */
352#define PORT_LED_OFF    (0 << 14)
353#define PORT_LED_AMBER  (1 << 14)
354#define PORT_LED_GREEN  (2 << 14)
355#define PORT_LED_MASK   (3 << 14)
356/* Port Link State Write Strobe - set this when changing link state */
357#define PORT_LINK_STROBE        (1 << 16)
358/* true: connect status change */
359#define PORT_CSC        (1 << 17)
360/* true: port enable change */
361#define PORT_PEC        (1 << 18)
362/* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
363 * into an enabled state, and the device into the default state.  A "warm" reset
364 * also resets the link, forcing the device through the link training sequence.
365 * SW can also look at the Port Reset register to see when warm reset is done.
366 */
367#define PORT_WRC        (1 << 19)
368/* true: over-current change */
369#define PORT_OCC        (1 << 20)
370/* true: reset change - 1 to 0 transition of PORT_RESET */
371#define PORT_RC         (1 << 21)
372/* port link status change - set on some port link state transitions:
373 *  Transition                          Reason
374 *  ------------------------------------------------------------------------------
375 *  - U3 to Resume                      Wakeup signaling from a device
376 *  - Resume to Recovery to U0          USB 3.0 device resume
377 *  - Resume to U0                      USB 2.0 device resume
378 *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
379 *  - U3 to U0                          Software resume of USB 2.0 device complete
380 *  - U2 to U0                          L1 resume of USB 2.1 device complete
381 *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
382 *  - U0 to disabled                    L1 entry error with USB 2.1 device
383 *  - Any state to inactive             Error on USB 3.0 port
384 */
385#define PORT_PLC        (1 << 22)
386/* port configure error change - port failed to configure its link partner */
387#define PORT_CEC        (1 << 23)
388/* Cold Attach Status - xHC can set this bit to report device attached during
389 * Sx state. Warm port reset should be perfomed to clear this bit and move port
390 * to connected state.
391 */
392#define PORT_CAS        (1 << 24)
393/* wake on connect (enable) */
394#define PORT_WKCONN_E   (1 << 25)
395/* wake on disconnect (enable) */
396#define PORT_WKDISC_E   (1 << 26)
397/* wake on over-current (enable) */
398#define PORT_WKOC_E     (1 << 27)
399/* bits 28:29 reserved */
400/* true: device is non-removable - for USB 3.0 roothub emulation */
401#define PORT_DEV_REMOVE (1 << 30)
402/* Initiate a warm port reset - complete when PORT_WRC is '1' */
403#define PORT_WR         (1 << 31)
404
405/* We mark duplicate entries with -1 */
406#define DUPLICATE_ENTRY ((u8)(-1))
407
408/* Port Power Management Status and Control - port_power_base bitmasks */
409/* Inactivity timer value for transitions into U1, in microseconds.
410 * Timeout can be up to 127us.  0xFF means an infinite timeout.
411 */
412#define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
413#define PORT_U1_TIMEOUT_MASK    0xff
414/* Inactivity timer value for transitions into U2 */
415#define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
416#define PORT_U2_TIMEOUT_MASK    (0xff << 8)
417/* Bits 24:31 for port testing */
418
419/* USB2 Protocol PORTSPMSC */
420#define PORT_L1S_MASK           7
421#define PORT_L1S_SUCCESS        1
422#define PORT_RWE                (1 << 3)
423#define PORT_HIRD(p)            (((p) & 0xf) << 4)
424#define PORT_HIRD_MASK          (0xf << 4)
425#define PORT_L1DS_MASK          (0xff << 8)
426#define PORT_L1DS(p)            (((p) & 0xff) << 8)
427#define PORT_HLE                (1 << 16)
428
429/* USB3 Protocol PORTLI  Port Link Information */
430#define PORT_RX_LANES(p)        (((p) >> 16) & 0xf)
431#define PORT_TX_LANES(p)        (((p) >> 20) & 0xf)
432
433/* USB2 Protocol PORTHLPMC */
434#define PORT_HIRDM(p)((p) & 3)
435#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
436#define PORT_BESLD(p)(((p) & 0xf) << 10)
437
438/* use 512 microseconds as USB2 LPM L1 default timeout. */
439#define XHCI_L1_TIMEOUT         512
440
441/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
442 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
443 * by other operating systems.
444 *
445 * XHCI 1.0 errata 8/14/12 Table 13 notes:
446 * "Software should choose xHC BESL/BESLD field values that do not violate a
447 * device's resume latency requirements,
448 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
449 * or not program values < '4' if BLC = '0' and a BESL device is attached.
450 */
451#define XHCI_DEFAULT_BESL       4
452
453/**
454 * struct xhci_intr_reg - Interrupt Register Set
455 * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
456 *                      interrupts and check for pending interrupts.
457 * @irq_control:        IMOD - Interrupt Moderation Register.
458 *                      Used to throttle interrupts.
459 * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
460 * @erst_base:          ERST base address.
461 * @erst_dequeue:       Event ring dequeue pointer.
462 *
463 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
464 * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
465 * multiple segments of the same size.  The HC places events on the ring and
466 * "updates the Cycle bit in the TRBs to indicate to software the current
467 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
468 * updates the dequeue pointer.
469 */
470struct xhci_intr_reg {
471        __le32  irq_pending;
472        __le32  irq_control;
473        __le32  erst_size;
474        __le32  rsvd;
475        __le64  erst_base;
476        __le64  erst_dequeue;
477};
478
479/* irq_pending bitmasks */
480#define ER_IRQ_PENDING(p)       ((p) & 0x1)
481/* bits 2:31 need to be preserved */
482/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
483#define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
484#define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
485#define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
486
487/* irq_control bitmasks */
488/* Minimum interval between interrupts (in 250ns intervals).  The interval
489 * between interrupts will be longer if there are no events on the event ring.
490 * Default is 4000 (1 ms).
491 */
492#define ER_IRQ_INTERVAL_MASK    (0xffff)
493/* Counter used to count down the time to the next interrupt - HW use only */
494#define ER_IRQ_COUNTER_MASK     (0xffff << 16)
495
496/* erst_size bitmasks */
497/* Preserve bits 16:31 of erst_size */
498#define ERST_SIZE_MASK          (0xffff << 16)
499
500/* erst_dequeue bitmasks */
501/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
502 * where the current dequeue pointer lies.  This is an optional HW hint.
503 */
504#define ERST_DESI_MASK          (0x7)
505/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
506 * a work queue (or delayed service routine)?
507 */
508#define ERST_EHB                (1 << 3)
509#define ERST_PTR_MASK           (0xf)
510
511/**
512 * struct xhci_run_regs
513 * @microframe_index:
514 *              MFINDEX - current microframe number
515 *
516 * Section 5.5 Host Controller Runtime Registers:
517 * "Software should read and write these registers using only Dword (32 bit)
518 * or larger accesses"
519 */
520struct xhci_run_regs {
521        __le32                  microframe_index;
522        __le32                  rsvd[7];
523        struct xhci_intr_reg    ir_set[128];
524};
525
526/**
527 * struct doorbell_array
528 *
529 * Bits  0 -  7: Endpoint target
530 * Bits  8 - 15: RsvdZ
531 * Bits 16 - 31: Stream ID
532 *
533 * Section 5.6
534 */
535struct xhci_doorbell_array {
536        __le32  doorbell[256];
537};
538
539#define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
540#define DB_VALUE_HOST           0x00000000
541
542/**
543 * struct xhci_protocol_caps
544 * @revision:           major revision, minor revision, capability ID,
545 *                      and next capability pointer.
546 * @name_string:        Four ASCII characters to say which spec this xHC
547 *                      follows, typically "USB ".
548 * @port_info:          Port offset, count, and protocol-defined information.
549 */
550struct xhci_protocol_caps {
551        u32     revision;
552        u32     name_string;
553        u32     port_info;
554};
555
556#define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
557#define XHCI_EXT_PORT_MINOR(x)  (((x) >> 16) & 0xff)
558#define XHCI_EXT_PORT_PSIC(x)   (((x) >> 28) & 0x0f)
559#define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
560#define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
561
562#define XHCI_EXT_PORT_PSIV(x)   (((x) >> 0) & 0x0f)
563#define XHCI_EXT_PORT_PSIE(x)   (((x) >> 4) & 0x03)
564#define XHCI_EXT_PORT_PLT(x)    (((x) >> 6) & 0x03)
565#define XHCI_EXT_PORT_PFD(x)    (((x) >> 8) & 0x01)
566#define XHCI_EXT_PORT_LP(x)     (((x) >> 14) & 0x03)
567#define XHCI_EXT_PORT_PSIM(x)   (((x) >> 16) & 0xffff)
568
569#define PLT_MASK        (0x03 << 6)
570#define PLT_SYM         (0x00 << 6)
571#define PLT_ASYM_RX     (0x02 << 6)
572#define PLT_ASYM_TX     (0x03 << 6)
573
574/**
575 * struct xhci_container_ctx
576 * @type: Type of context.  Used to calculated offsets to contained contexts.
577 * @size: Size of the context data
578 * @bytes: The raw context data given to HW
579 * @dma: dma address of the bytes
580 *
581 * Represents either a Device or Input context.  Holds a pointer to the raw
582 * memory used for the context (bytes) and dma address of it (dma).
583 */
584struct xhci_container_ctx {
585        unsigned type;
586#define XHCI_CTX_TYPE_DEVICE  0x1
587#define XHCI_CTX_TYPE_INPUT   0x2
588
589        int size;
590
591        u8 *bytes;
592        dma_addr_t dma;
593};
594
595/**
596 * struct xhci_slot_ctx
597 * @dev_info:   Route string, device speed, hub info, and last valid endpoint
598 * @dev_info2:  Max exit latency for device number, root hub port number
599 * @tt_info:    tt_info is used to construct split transaction tokens
600 * @dev_state:  slot state and device address
601 *
602 * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
603 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
604 * reserved at the end of the slot context for HC internal use.
605 */
606struct xhci_slot_ctx {
607        __le32  dev_info;
608        __le32  dev_info2;
609        __le32  tt_info;
610        __le32  dev_state;
611        /* offset 0x10 to 0x1f reserved for HC internal use */
612        __le32  reserved[4];
613};
614
615/* dev_info bitmasks */
616/* Route String - 0:19 */
617#define ROUTE_STRING_MASK       (0xfffff)
618/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
619#define DEV_SPEED       (0xf << 20)
620/* bit 24 reserved */
621/* Is this LS/FS device connected through a HS hub? - bit 25 */
622#define DEV_MTT         (0x1 << 25)
623/* Set if the device is a hub - bit 26 */
624#define DEV_HUB         (0x1 << 26)
625/* Index of the last valid endpoint context in this device context - 27:31 */
626#define LAST_CTX_MASK   (0x1f << 27)
627#define LAST_CTX(p)     ((p) << 27)
628#define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
629#define SLOT_FLAG       (1 << 0)
630#define EP0_FLAG        (1 << 1)
631
632/* dev_info2 bitmasks */
633/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
634#define MAX_EXIT        (0xffff)
635/* Root hub port number that is needed to access the USB device */
636#define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
637#define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
638/* Maximum number of ports under a hub device */
639#define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
640
641/* tt_info bitmasks */
642/*
643 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
644 * The Slot ID of the hub that isolates the high speed signaling from
645 * this low or full-speed device.  '0' if attached to root hub port.
646 */
647#define TT_SLOT         (0xff)
648/*
649 * The number of the downstream facing port of the high-speed hub
650 * '0' if the device is not low or full speed.
651 */
652#define TT_PORT         (0xff << 8)
653#define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
654
655/* dev_state bitmasks */
656/* USB device address - assigned by the HC */
657#define DEV_ADDR_MASK   (0xff)
658/* bits 8:26 reserved */
659/* Slot state */
660#define SLOT_STATE      (0x1f << 27)
661#define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
662
663#define SLOT_STATE_DISABLED     0
664#define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
665#define SLOT_STATE_DEFAULT      1
666#define SLOT_STATE_ADDRESSED    2
667#define SLOT_STATE_CONFIGURED   3
668
669/**
670 * struct xhci_ep_ctx
671 * @ep_info:    endpoint state, streams, mult, and interval information.
672 * @ep_info2:   information on endpoint type, max packet size, max burst size,
673 *              error count, and whether the HC will force an event for all
674 *              transactions.
675 * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
676 *              defines one stream, this points to the endpoint transfer ring.
677 *              Otherwise, it points to a stream context array, which has a
678 *              ring pointer for each flow.
679 * @tx_info:
680 *              Average TRB lengths for the endpoint ring and
681 *              max payload within an Endpoint Service Interval Time (ESIT).
682 *
683 * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
684 * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
685 * reserved at the end of the endpoint context for HC internal use.
686 */
687struct xhci_ep_ctx {
688        __le32  ep_info;
689        __le32  ep_info2;
690        __le64  deq;
691        __le32  tx_info;
692        /* offset 0x14 - 0x1f reserved for HC internal use */
693        __le32  reserved[3];
694};
695
696/* ep_info bitmasks */
697/*
698 * Endpoint State - bits 0:2
699 * 0 - disabled
700 * 1 - running
701 * 2 - halted due to halt condition - ok to manipulate endpoint ring
702 * 3 - stopped
703 * 4 - TRB error
704 * 5-7 - reserved
705 */
706#define EP_STATE_MASK           (0xf)
707#define EP_STATE_DISABLED       0
708#define EP_STATE_RUNNING        1
709#define EP_STATE_HALTED         2
710#define EP_STATE_STOPPED        3
711#define EP_STATE_ERROR          4
712/* Mult - Max number of burtst within an interval, in EP companion desc. */
713#define EP_MULT(p)              (((p) & 0x3) << 8)
714#define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
715/* bits 10:14 are Max Primary Streams */
716/* bit 15 is Linear Stream Array */
717/* Interval - period between requests to an endpoint - 125u increments. */
718#define EP_INTERVAL(p)          (((p) & 0xff) << 16)
719#define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
720#define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
721#define EP_MAXPSTREAMS_MASK     (0x1f << 10)
722#define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
723/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
724#define EP_HAS_LSA              (1 << 15)
725
726/* ep_info2 bitmasks */
727/*
728 * Force Event - generate transfer events for all TRBs for this endpoint
729 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
730 */
731#define FORCE_EVENT     (0x1)
732#define ERROR_COUNT(p)  (((p) & 0x3) << 1)
733#define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
734#define EP_TYPE(p)      ((p) << 3)
735#define ISOC_OUT_EP     1
736#define BULK_OUT_EP     2
737#define INT_OUT_EP      3
738#define CTRL_EP         4
739#define ISOC_IN_EP      5
740#define BULK_IN_EP      6
741#define INT_IN_EP       7
742/* bit 6 reserved */
743/* bit 7 is Host Initiate Disable - for disabling stream selection */
744#define MAX_BURST(p)    (((p)&0xff) << 8)
745#define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
746#define MAX_PACKET(p)   (((p)&0xffff) << 16)
747#define MAX_PACKET_MASK         (0xffff << 16)
748#define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
749
750/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
751 * USB2.0 spec 9.6.6.
752 */
753#define GET_MAX_PACKET(p)       ((p) & 0x7ff)
754
755/* tx_info bitmasks */
756#define EP_AVG_TRB_LENGTH(p)            ((p) & 0xffff)
757#define EP_MAX_ESIT_PAYLOAD_LO(p)       (((p) & 0xffff) << 16)
758#define EP_MAX_ESIT_PAYLOAD_HI(p)       ((((p) >> 16) & 0xff) << 24)
759#define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
760
761/* deq bitmasks */
762#define EP_CTX_CYCLE_MASK               (1 << 0)
763#define SCTX_DEQ_MASK                   (~0xfL)
764
765
766/**
767 * struct xhci_input_control_context
768 * Input control context; see section 6.2.5.
769 *
770 * @drop_context:       set the bit of the endpoint context you want to disable
771 * @add_context:        set the bit of the endpoint context you want to enable
772 */
773struct xhci_input_control_ctx {
774        __le32  drop_flags;
775        __le32  add_flags;
776        __le32  rsvd2[6];
777};
778
779#define EP_IS_ADDED(ctrl_ctx, i) \
780        (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
781#define EP_IS_DROPPED(ctrl_ctx, i)       \
782        (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
783
784/* Represents everything that is needed to issue a command on the command ring.
785 * It's useful to pre-allocate these for commands that cannot fail due to
786 * out-of-memory errors, like freeing streams.
787 */
788struct xhci_command {
789        /* Input context for changing device state */
790        struct xhci_container_ctx       *in_ctx;
791        u32                             status;
792        /* If completion is null, no one is waiting on this command
793         * and the structure can be freed after the command completes.
794         */
795        struct completion               *completion;
796        union xhci_trb                  *command_trb;
797        struct list_head                cmd_list;
798};
799
800/* drop context bitmasks */
801#define DROP_EP(x)      (0x1 << x)
802/* add context bitmasks */
803#define ADD_EP(x)       (0x1 << x)
804
805struct xhci_stream_ctx {
806        /* 64-bit stream ring address, cycle state, and stream type */
807        __le64  stream_ring;
808        /* offset 0x14 - 0x1f reserved for HC internal use */
809        __le32  reserved[2];
810};
811
812/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
813#define SCT_FOR_CTX(p)          (((p) & 0x7) << 1)
814/* Secondary stream array type, dequeue pointer is to a transfer ring */
815#define SCT_SEC_TR              0
816/* Primary stream array type, dequeue pointer is to a transfer ring */
817#define SCT_PRI_TR              1
818/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
819#define SCT_SSA_8               2
820#define SCT_SSA_16              3
821#define SCT_SSA_32              4
822#define SCT_SSA_64              5
823#define SCT_SSA_128             6
824#define SCT_SSA_256             7
825
826/* Assume no secondary streams for now */
827struct xhci_stream_info {
828        struct xhci_ring                **stream_rings;
829        /* Number of streams, including stream 0 (which drivers can't use) */
830        unsigned int                    num_streams;
831        /* The stream context array may be bigger than
832         * the number of streams the driver asked for
833         */
834        struct xhci_stream_ctx          *stream_ctx_array;
835        unsigned int                    num_stream_ctxs;
836        dma_addr_t                      ctx_array_dma;
837        /* For mapping physical TRB addresses to segments in stream rings */
838        struct radix_tree_root          trb_address_map;
839        struct xhci_command             *free_streams_command;
840};
841
842#define SMALL_STREAM_ARRAY_SIZE         256
843#define MEDIUM_STREAM_ARRAY_SIZE        1024
844
845/* Some Intel xHCI host controllers need software to keep track of the bus
846 * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
847 * the full bus bandwidth.  We must also treat TTs (including each port under a
848 * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
849 * (DMI) also limits the total bandwidth (across all domains) that can be used.
850 */
851struct xhci_bw_info {
852        /* ep_interval is zero-based */
853        unsigned int            ep_interval;
854        /* mult and num_packets are one-based */
855        unsigned int            mult;
856        unsigned int            num_packets;
857        unsigned int            max_packet_size;
858        unsigned int            max_esit_payload;
859        unsigned int            type;
860};
861
862/* "Block" sizes in bytes the hardware uses for different device speeds.
863 * The logic in this part of the hardware limits the number of bits the hardware
864 * can use, so must represent bandwidth in a less precise manner to mimic what
865 * the scheduler hardware computes.
866 */
867#define FS_BLOCK        1
868#define HS_BLOCK        4
869#define SS_BLOCK        16
870#define DMI_BLOCK       32
871
872/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
873 * with each byte transferred.  SuperSpeed devices have an initial overhead to
874 * set up bursts.  These are in blocks, see above.  LS overhead has already been
875 * translated into FS blocks.
876 */
877#define DMI_OVERHEAD 8
878#define DMI_OVERHEAD_BURST 4
879#define SS_OVERHEAD 8
880#define SS_OVERHEAD_BURST 32
881#define HS_OVERHEAD 26
882#define FS_OVERHEAD 20
883#define LS_OVERHEAD 128
884/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
885 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
886 * of overhead associated with split transfers crossing microframe boundaries.
887 * 31 blocks is pure protocol overhead.
888 */
889#define TT_HS_OVERHEAD (31 + 94)
890#define TT_DMI_OVERHEAD (25 + 12)
891
892/* Bandwidth limits in blocks */
893#define FS_BW_LIMIT             1285
894#define TT_BW_LIMIT             1320
895#define HS_BW_LIMIT             1607
896#define SS_BW_LIMIT_IN          3906
897#define DMI_BW_LIMIT_IN         3906
898#define SS_BW_LIMIT_OUT         3906
899#define DMI_BW_LIMIT_OUT        3906
900
901/* Percentage of bus bandwidth reserved for non-periodic transfers */
902#define FS_BW_RESERVED          10
903#define HS_BW_RESERVED          20
904#define SS_BW_RESERVED          10
905
906struct xhci_virt_ep {
907        struct xhci_ring                *ring;
908        /* Related to endpoints that are configured to use stream IDs only */
909        struct xhci_stream_info         *stream_info;
910        /* Temporary storage in case the configure endpoint command fails and we
911         * have to restore the device state to the previous state
912         */
913        struct xhci_ring                *new_ring;
914        unsigned int                    ep_state;
915#define SET_DEQ_PENDING         (1 << 0)
916#define EP_HALTED               (1 << 1)        /* For stall handling */
917#define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
918/* Transitioning the endpoint to using streams, don't enqueue URBs */
919#define EP_GETTING_STREAMS      (1 << 3)
920#define EP_HAS_STREAMS          (1 << 4)
921/* Transitioning the endpoint to not using streams, don't enqueue URBs */
922#define EP_GETTING_NO_STREAMS   (1 << 5)
923        /* ----  Related to URB cancellation ---- */
924        struct list_head        cancelled_td_list;
925        struct xhci_td          *stopped_td;
926        unsigned int            stopped_stream;
927        /* Watchdog timer for stop endpoint command to cancel URBs */
928        struct timer_list       stop_cmd_timer;
929        int                     stop_cmds_pending;
930        struct xhci_hcd         *xhci;
931        /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
932         * command.  We'll need to update the ring's dequeue segment and dequeue
933         * pointer after the command completes.
934         */
935        struct xhci_segment     *queued_deq_seg;
936        union xhci_trb          *queued_deq_ptr;
937        /*
938         * Sometimes the xHC can not process isochronous endpoint ring quickly
939         * enough, and it will miss some isoc tds on the ring and generate
940         * a Missed Service Error Event.
941         * Set skip flag when receive a Missed Service Error Event and
942         * process the missed tds on the endpoint ring.
943         */
944        bool                    skip;
945        /* Bandwidth checking storage */
946        struct xhci_bw_info     bw_info;
947        struct list_head        bw_endpoint_list;
948        /* Isoch Frame ID checking storage */
949        int                     next_frame_id;
950        /* Use new Isoch TRB layout needed for extended TBC support */
951        bool                    use_extended_tbc;
952};
953
954enum xhci_overhead_type {
955        LS_OVERHEAD_TYPE = 0,
956        FS_OVERHEAD_TYPE,
957        HS_OVERHEAD_TYPE,
958};
959
960struct xhci_interval_bw {
961        unsigned int            num_packets;
962        /* Sorted by max packet size.
963         * Head of the list is the greatest max packet size.
964         */
965        struct list_head        endpoints;
966        /* How many endpoints of each speed are present. */
967        unsigned int            overhead[3];
968};
969
970#define XHCI_MAX_INTERVAL       16
971
972struct xhci_interval_bw_table {
973        unsigned int            interval0_esit_payload;
974        struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
975        /* Includes reserved bandwidth for async endpoints */
976        unsigned int            bw_used;
977        unsigned int            ss_bw_in;
978        unsigned int            ss_bw_out;
979};
980
981
982struct xhci_virt_device {
983        struct usb_device               *udev;
984        /*
985         * Commands to the hardware are passed an "input context" that
986         * tells the hardware what to change in its data structures.
987         * The hardware will return changes in an "output context" that
988         * software must allocate for the hardware.  We need to keep
989         * track of input and output contexts separately because
990         * these commands might fail and we don't trust the hardware.
991         */
992        struct xhci_container_ctx       *out_ctx;
993        /* Used for addressing devices and configuration changes */
994        struct xhci_container_ctx       *in_ctx;
995        /* Rings saved to ensure old alt settings can be re-instated */
996        struct xhci_ring                **ring_cache;
997        int                             num_rings_cached;
998#define XHCI_MAX_RINGS_CACHED   31
999        struct xhci_virt_ep             eps[31];
1000        struct completion               cmd_completion;
1001        u8                              fake_port;
1002        u8                              real_port;
1003        struct xhci_interval_bw_table   *bw_table;
1004        struct xhci_tt_bw_info          *tt_info;
1005        /* The current max exit latency for the enabled USB3 link states. */
1006        u16                             current_mel;
1007};
1008
1009/*
1010 * For each roothub, keep track of the bandwidth information for each periodic
1011 * interval.
1012 *
1013 * If a high speed hub is attached to the roothub, each TT associated with that
1014 * hub is a separate bandwidth domain.  The interval information for the
1015 * endpoints on the devices under that TT will appear in the TT structure.
1016 */
1017struct xhci_root_port_bw_info {
1018        struct list_head                tts;
1019        unsigned int                    num_active_tts;
1020        struct xhci_interval_bw_table   bw_table;
1021};
1022
1023struct xhci_tt_bw_info {
1024        struct list_head                tt_list;
1025        int                             slot_id;
1026        int                             ttport;
1027        struct xhci_interval_bw_table   bw_table;
1028        int                             active_eps;
1029};
1030
1031
1032/**
1033 * struct xhci_device_context_array
1034 * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
1035 */
1036struct xhci_device_context_array {
1037        /* 64-bit device addresses; we only write 32-bit addresses */
1038        __le64                  dev_context_ptrs[MAX_HC_SLOTS];
1039        /* private xHCD pointers */
1040        dma_addr_t      dma;
1041};
1042/* TODO: write function to set the 64-bit device DMA address */
1043/*
1044 * TODO: change this to be dynamically sized at HC mem init time since the HC
1045 * might not be able to handle the maximum number of devices possible.
1046 */
1047
1048
1049struct xhci_transfer_event {
1050        /* 64-bit buffer address, or immediate data */
1051        __le64  buffer;
1052        __le32  transfer_len;
1053        /* This field is interpreted differently based on the type of TRB */
1054        __le32  flags;
1055};
1056
1057/* Transfer event TRB length bit mask */
1058/* bits 0:23 */
1059#define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
1060
1061/** Transfer Event bit fields **/
1062#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1063
1064/* Completion Code - only applicable for some types of TRBs */
1065#define COMP_CODE_MASK          (0xff << 24)
1066#define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
1067#define COMP_SUCCESS    1
1068/* Data Buffer Error */
1069#define COMP_DB_ERR     2
1070/* Babble Detected Error */
1071#define COMP_BABBLE     3
1072/* USB Transaction Error */
1073#define COMP_TX_ERR     4
1074/* TRB Error - some TRB field is invalid */
1075#define COMP_TRB_ERR    5
1076/* Stall Error - USB device is stalled */
1077#define COMP_STALL      6
1078/* Resource Error - HC doesn't have memory for that device configuration */
1079#define COMP_ENOMEM     7
1080/* Bandwidth Error - not enough room in schedule for this dev config */
1081#define COMP_BW_ERR     8
1082/* No Slots Available Error - HC ran out of device slots */
1083#define COMP_ENOSLOTS   9
1084/* Invalid Stream Type Error */
1085#define COMP_STREAM_ERR 10
1086/* Slot Not Enabled Error - doorbell rung for disabled device slot */
1087#define COMP_EBADSLT    11
1088/* Endpoint Not Enabled Error */
1089#define COMP_EBADEP     12
1090/* Short Packet */
1091#define COMP_SHORT_TX   13
1092/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1093#define COMP_UNDERRUN   14
1094/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1095#define COMP_OVERRUN    15
1096/* Virtual Function Event Ring Full Error */
1097#define COMP_VF_FULL    16
1098/* Parameter Error - Context parameter is invalid */
1099#define COMP_EINVAL     17
1100/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1101#define COMP_BW_OVER    18
1102/* Context State Error - illegal context state transition requested */
1103#define COMP_CTX_STATE  19
1104/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1105#define COMP_PING_ERR   20
1106/* Event Ring is full */
1107#define COMP_ER_FULL    21
1108/* Incompatible Device Error */
1109#define COMP_DEV_ERR    22
1110/* Missed Service Error - HC couldn't service an isoc ep within interval */
1111#define COMP_MISSED_INT 23
1112/* Successfully stopped command ring */
1113#define COMP_CMD_STOP   24
1114/* Successfully aborted current command and stopped command ring */
1115#define COMP_CMD_ABORT  25
1116/* Stopped - transfer was terminated by a stop endpoint command */
1117#define COMP_STOP       26
1118/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1119#define COMP_STOP_INVAL 27
1120/* Same as COMP_EP_STOPPED, but a short packet detected */
1121#define COMP_STOP_SHORT 28
1122/* Max Exit Latency Too Large Error */
1123#define COMP_MEL_ERR    29
1124/* TRB type 30 reserved */
1125/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1126#define COMP_BUFF_OVER  31
1127/* Event Lost Error - xHC has an "internal event overrun condition" */
1128#define COMP_ISSUES     32
1129/* Undefined Error - reported when other error codes don't apply */
1130#define COMP_UNKNOWN    33
1131/* Invalid Stream ID Error */
1132#define COMP_STRID_ERR  34
1133/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1134#define COMP_2ND_BW_ERR 35
1135/* Split Transaction Error */
1136#define COMP_SPLIT_ERR  36
1137
1138struct xhci_link_trb {
1139        /* 64-bit segment pointer*/
1140        __le64 segment_ptr;
1141        __le32 intr_target;
1142        __le32 control;
1143};
1144
1145/* control bitfields */
1146#define LINK_TOGGLE     (0x1<<1)
1147
1148/* Command completion event TRB */
1149struct xhci_event_cmd {
1150        /* Pointer to command TRB, or the value passed by the event data trb */
1151        __le64 cmd_trb;
1152        __le32 status;
1153        __le32 flags;
1154};
1155
1156/* flags bitmasks */
1157
1158/* Address device - disable SetAddress */
1159#define TRB_BSR         (1<<9)
1160enum xhci_setup_dev {
1161        SETUP_CONTEXT_ONLY,
1162        SETUP_CONTEXT_ADDRESS,
1163};
1164
1165/* bits 16:23 are the virtual function ID */
1166/* bits 24:31 are the slot ID */
1167#define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1168#define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1169
1170/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1171#define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1172#define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1173
1174#define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1175#define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1176#define LAST_EP_INDEX                   30
1177
1178/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1179#define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1180#define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1181#define SCT_FOR_TRB(p)                  (((p) << 1) & 0x7)
1182
1183
1184/* Port Status Change Event TRB fields */
1185/* Port ID - bits 31:24 */
1186#define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1187
1188/* Normal TRB fields */
1189/* transfer_len bitmasks - bits 0:16 */
1190#define TRB_LEN(p)              ((p) & 0x1ffff)
1191/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1192#define TRB_TD_SIZE(p)          (min((p), (u32)31) << 17)
1193/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1194#define TRB_TD_SIZE_TBC(p)      (min((p), (u32)31) << 17)
1195/* Interrupter Target - which MSI-X vector to target the completion event at */
1196#define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1197#define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1198/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1199#define TRB_TBC(p)              (((p) & 0x3) << 7)
1200#define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1201
1202/* Cycle bit - indicates TRB ownership by HC or HCD */
1203#define TRB_CYCLE               (1<<0)
1204/*
1205 * Force next event data TRB to be evaluated before task switch.
1206 * Used to pass OS data back after a TD completes.
1207 */
1208#define TRB_ENT                 (1<<1)
1209/* Interrupt on short packet */
1210#define TRB_ISP                 (1<<2)
1211/* Set PCIe no snoop attribute */
1212#define TRB_NO_SNOOP            (1<<3)
1213/* Chain multiple TRBs into a TD */
1214#define TRB_CHAIN               (1<<4)
1215/* Interrupt on completion */
1216#define TRB_IOC                 (1<<5)
1217/* The buffer pointer contains immediate data */
1218#define TRB_IDT                 (1<<6)
1219
1220/* Block Event Interrupt */
1221#define TRB_BEI                 (1<<9)
1222
1223/* Control transfer TRB specific fields */
1224#define TRB_DIR_IN              (1<<16)
1225#define TRB_TX_TYPE(p)          ((p) << 16)
1226#define TRB_DATA_OUT            2
1227#define TRB_DATA_IN             3
1228
1229/* Isochronous TRB specific fields */
1230#define TRB_SIA                 (1<<31)
1231#define TRB_FRAME_ID(p)         (((p) & 0x7ff) << 20)
1232
1233struct xhci_generic_trb {
1234        __le32 field[4];
1235};
1236
1237union xhci_trb {
1238        struct xhci_link_trb            link;
1239        struct xhci_transfer_event      trans_event;
1240        struct xhci_event_cmd           event_cmd;
1241        struct xhci_generic_trb         generic;
1242};
1243
1244/* TRB bit mask */
1245#define TRB_TYPE_BITMASK        (0xfc00)
1246#define TRB_TYPE(p)             ((p) << 10)
1247#define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1248/* TRB type IDs */
1249/* bulk, interrupt, isoc scatter/gather, and control data stage */
1250#define TRB_NORMAL              1
1251/* setup stage for control transfers */
1252#define TRB_SETUP               2
1253/* data stage for control transfers */
1254#define TRB_DATA                3
1255/* status stage for control transfers */
1256#define TRB_STATUS              4
1257/* isoc transfers */
1258#define TRB_ISOC                5
1259/* TRB for linking ring segments */
1260#define TRB_LINK                6
1261#define TRB_EVENT_DATA          7
1262/* Transfer Ring No-op (not for the command ring) */
1263#define TRB_TR_NOOP             8
1264/* Command TRBs */
1265/* Enable Slot Command */
1266#define TRB_ENABLE_SLOT         9
1267/* Disable Slot Command */
1268#define TRB_DISABLE_SLOT        10
1269/* Address Device Command */
1270#define TRB_ADDR_DEV            11
1271/* Configure Endpoint Command */
1272#define TRB_CONFIG_EP           12
1273/* Evaluate Context Command */
1274#define TRB_EVAL_CONTEXT        13
1275/* Reset Endpoint Command */
1276#define TRB_RESET_EP            14
1277/* Stop Transfer Ring Command */
1278#define TRB_STOP_RING           15
1279/* Set Transfer Ring Dequeue Pointer Command */
1280#define TRB_SET_DEQ             16
1281/* Reset Device Command */
1282#define TRB_RESET_DEV           17
1283/* Force Event Command (opt) */
1284#define TRB_FORCE_EVENT         18
1285/* Negotiate Bandwidth Command (opt) */
1286#define TRB_NEG_BANDWIDTH       19
1287/* Set Latency Tolerance Value Command (opt) */
1288#define TRB_SET_LT              20
1289/* Get port bandwidth Command */
1290#define TRB_GET_BW              21
1291/* Force Header Command - generate a transaction or link management packet */
1292#define TRB_FORCE_HEADER        22
1293/* No-op Command - not for transfer rings */
1294#define TRB_CMD_NOOP            23
1295/* TRB IDs 24-31 reserved */
1296/* Event TRBS */
1297/* Transfer Event */
1298#define TRB_TRANSFER            32
1299/* Command Completion Event */
1300#define TRB_COMPLETION          33
1301/* Port Status Change Event */
1302#define TRB_PORT_STATUS         34
1303/* Bandwidth Request Event (opt) */
1304#define TRB_BANDWIDTH_EVENT     35
1305/* Doorbell Event (opt) */
1306#define TRB_DOORBELL            36
1307/* Host Controller Event */
1308#define TRB_HC_EVENT            37
1309/* Device Notification Event - device sent function wake notification */
1310#define TRB_DEV_NOTE            38
1311/* MFINDEX Wrap Event - microframe counter wrapped */
1312#define TRB_MFINDEX_WRAP        39
1313/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1314
1315/* Nec vendor-specific command completion event. */
1316#define TRB_NEC_CMD_COMP        48
1317/* Get NEC firmware revision. */
1318#define TRB_NEC_GET_FW          49
1319
1320#define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1321/* Above, but for __le32 types -- can avoid work by swapping constants: */
1322#define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1323                                 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1324#define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1325                                 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1326
1327#define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1328#define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1329
1330/*
1331 * TRBS_PER_SEGMENT must be a multiple of 4,
1332 * since the command ring is 64-byte aligned.
1333 * It must also be greater than 16.
1334 */
1335#define TRBS_PER_SEGMENT        256
1336/* Allow two commands + a link TRB, along with any reserved command TRBs */
1337#define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1338#define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1339#define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1340/* TRB buffer pointers can't cross 64KB boundaries */
1341#define TRB_MAX_BUFF_SHIFT              16
1342#define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1343/* How much data is left before the 64KB boundary? */
1344#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)       (TRB_MAX_BUFF_SIZE - \
1345                                        (addr & (TRB_MAX_BUFF_SIZE - 1)))
1346
1347struct xhci_segment {
1348        union xhci_trb          *trbs;
1349        /* private to HCD */
1350        struct xhci_segment     *next;
1351        dma_addr_t              dma;
1352        /* Max packet sized bounce buffer for td-fragmant alignment */
1353        dma_addr_t              bounce_dma;
1354        void                    *bounce_buf;
1355        unsigned int            bounce_offs;
1356        unsigned int            bounce_len;
1357};
1358
1359struct xhci_td {
1360        struct list_head        td_list;
1361        struct list_head        cancelled_td_list;
1362        struct urb              *urb;
1363        struct xhci_segment     *start_seg;
1364        union xhci_trb          *first_trb;
1365        union xhci_trb          *last_trb;
1366        struct xhci_segment     *bounce_seg;
1367        /* actual_length of the URB has already been set */
1368        bool                    urb_length_set;
1369};
1370
1371/* xHCI command default timeout value */
1372#define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1373
1374/* command descriptor */
1375struct xhci_cd {
1376        struct xhci_command     *command;
1377        union xhci_trb          *cmd_trb;
1378};
1379
1380struct xhci_dequeue_state {
1381        struct xhci_segment *new_deq_seg;
1382        union xhci_trb *new_deq_ptr;
1383        int new_cycle_state;
1384};
1385
1386enum xhci_ring_type {
1387        TYPE_CTRL = 0,
1388        TYPE_ISOC,
1389        TYPE_BULK,
1390        TYPE_INTR,
1391        TYPE_STREAM,
1392        TYPE_COMMAND,
1393        TYPE_EVENT,
1394};
1395
1396struct xhci_ring {
1397        struct xhci_segment     *first_seg;
1398        struct xhci_segment     *last_seg;
1399        union  xhci_trb         *enqueue;
1400        struct xhci_segment     *enq_seg;
1401        unsigned int            enq_updates;
1402        union  xhci_trb         *dequeue;
1403        struct xhci_segment     *deq_seg;
1404        unsigned int            deq_updates;
1405        struct list_head        td_list;
1406        /*
1407         * Write the cycle state into the TRB cycle field to give ownership of
1408         * the TRB to the host controller (if we are the producer), or to check
1409         * if we own the TRB (if we are the consumer).  See section 4.9.1.
1410         */
1411        u32                     cycle_state;
1412        unsigned int            stream_id;
1413        unsigned int            num_segs;
1414        unsigned int            num_trbs_free;
1415        unsigned int            num_trbs_free_temp;
1416        unsigned int            bounce_buf_len;
1417        enum xhci_ring_type     type;
1418        bool                    last_td_was_short;
1419        struct radix_tree_root  *trb_address_map;
1420};
1421
1422struct xhci_erst_entry {
1423        /* 64-bit event ring segment address */
1424        __le64  seg_addr;
1425        __le32  seg_size;
1426        /* Set to zero */
1427        __le32  rsvd;
1428};
1429
1430struct xhci_erst {
1431        struct xhci_erst_entry  *entries;
1432        unsigned int            num_entries;
1433        /* xhci->event_ring keeps track of segment dma addresses */
1434        dma_addr_t              erst_dma_addr;
1435        /* Num entries the ERST can contain */
1436        unsigned int            erst_size;
1437};
1438
1439struct xhci_scratchpad {
1440        u64 *sp_array;
1441        dma_addr_t sp_dma;
1442        void **sp_buffers;
1443        dma_addr_t *sp_dma_buffers;
1444};
1445
1446struct urb_priv {
1447        int     length;
1448        int     td_cnt;
1449        struct  xhci_td *td[0];
1450};
1451
1452/*
1453 * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1454 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1455 * meaning 64 ring segments.
1456 * Initial allocated size of the ERST, in number of entries */
1457#define ERST_NUM_SEGS   1
1458/* Initial allocated size of the ERST, in number of entries */
1459#define ERST_SIZE       64
1460/* Initial number of event segment rings allocated */
1461#define ERST_ENTRIES    1
1462/* Poll every 60 seconds */
1463#define POLL_TIMEOUT    60
1464/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1465#define XHCI_STOP_EP_CMD_TIMEOUT        5
1466/* XXX: Make these module parameters */
1467
1468struct s3_save {
1469        u32     command;
1470        u32     dev_nt;
1471        u64     dcbaa_ptr;
1472        u32     config_reg;
1473        u32     irq_pending;
1474        u32     irq_control;
1475        u32     erst_size;
1476        u64     erst_base;
1477        u64     erst_dequeue;
1478};
1479
1480/* Use for lpm */
1481struct dev_info {
1482        u32                     dev_id;
1483        struct  list_head       list;
1484};
1485
1486struct xhci_bus_state {
1487        unsigned long           bus_suspended;
1488        unsigned long           next_statechange;
1489
1490        /* Port suspend arrays are indexed by the portnum of the fake roothub */
1491        /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1492        u32                     port_c_suspend;
1493        u32                     suspended_ports;
1494        u32                     port_remote_wakeup;
1495        unsigned long           resume_done[USB_MAXCHILDREN];
1496        /* which ports have started to resume */
1497        unsigned long           resuming_ports;
1498        /* Which ports are waiting on RExit to U0 transition. */
1499        unsigned long           rexit_ports;
1500        struct completion       rexit_done[USB_MAXCHILDREN];
1501};
1502
1503
1504/*
1505 * It can take up to 20 ms to transition from RExit to U0 on the
1506 * Intel Lynx Point LP xHCI host.
1507 */
1508#define XHCI_MAX_REXIT_TIMEOUT  (20 * 1000)
1509
1510static inline unsigned int hcd_index(struct usb_hcd *hcd)
1511{
1512        if (hcd->speed == HCD_USB3)
1513                return 0;
1514        else
1515                return 1;
1516}
1517
1518struct xhci_hub {
1519        u8      maj_rev;
1520        u8      min_rev;
1521        u32     *psi;           /* array of protocol speed ID entries */
1522        u8      psi_count;
1523        u8      psi_uid_count;
1524};
1525
1526/* There is one xhci_hcd structure per controller */
1527struct xhci_hcd {
1528        struct usb_hcd *main_hcd;
1529        struct usb_hcd *shared_hcd;
1530        /* glue to PCI and HCD framework */
1531        struct xhci_cap_regs __iomem *cap_regs;
1532        struct xhci_op_regs __iomem *op_regs;
1533        struct xhci_run_regs __iomem *run_regs;
1534        struct xhci_doorbell_array __iomem *dba;
1535        /* Our HCD's current interrupter register set */
1536        struct  xhci_intr_reg __iomem *ir_set;
1537
1538        /* Cached register copies of read-only HC data */
1539        __u32           hcs_params1;
1540        __u32           hcs_params2;
1541        __u32           hcs_params3;
1542        __u32           hcc_params;
1543        __u32           hcc_params2;
1544
1545        spinlock_t      lock;
1546
1547        /* packed release number */
1548        u8              sbrn;
1549        u16             hci_version;
1550        u8              max_slots;
1551        u8              max_interrupters;
1552        u8              max_ports;
1553        u8              isoc_threshold;
1554        int             event_ring_max;
1555        int             addr_64;
1556        /* 4KB min, 128MB max */
1557        int             page_size;
1558        /* Valid values are 12 to 20, inclusive */
1559        int             page_shift;
1560        /* msi-x vectors */
1561        int             msix_count;
1562        struct msix_entry       *msix_entries;
1563        /* optional clock */
1564        struct clk              *clk;
1565        /* data structures */
1566        struct xhci_device_context_array *dcbaa;
1567        struct xhci_ring        *cmd_ring;
1568        unsigned int            cmd_ring_state;
1569#define CMD_RING_STATE_RUNNING         (1 << 0)
1570#define CMD_RING_STATE_ABORTED         (1 << 1)
1571#define CMD_RING_STATE_STOPPED         (1 << 2)
1572        struct list_head        cmd_list;
1573        unsigned int            cmd_ring_reserved_trbs;
1574        struct delayed_work     cmd_timer;
1575        struct completion       cmd_ring_stop_completion;
1576        struct xhci_command     *current_cmd;
1577        struct xhci_ring        *event_ring;
1578        struct xhci_erst        erst;
1579        /* Scratchpad */
1580        struct xhci_scratchpad  *scratchpad;
1581        /* Store LPM test failed devices' information */
1582        struct list_head        lpm_failed_devs;
1583
1584        /* slot enabling and address device helpers */
1585        /* these are not thread safe so use mutex */
1586        struct mutex mutex;
1587        struct completion       addr_dev;
1588        int slot_id;
1589        /* For USB 3.0 LPM enable/disable. */
1590        struct xhci_command             *lpm_command;
1591        /* Internal mirror of the HW's dcbaa */
1592        struct xhci_virt_device *devs[MAX_HC_SLOTS];
1593        /* For keeping track of bandwidth domains per roothub. */
1594        struct xhci_root_port_bw_info   *rh_bw;
1595
1596        /* DMA pools */
1597        struct dma_pool *device_pool;
1598        struct dma_pool *segment_pool;
1599        struct dma_pool *small_streams_pool;
1600        struct dma_pool *medium_streams_pool;
1601
1602        /* Host controller watchdog timer structures */
1603        unsigned int            xhc_state;
1604
1605        u32                     command;
1606        struct s3_save          s3;
1607/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1608 *
1609 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1610 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1611 * that sees this status (other than the timer that set it) should stop touching
1612 * hardware immediately.  Interrupt handlers should return immediately when
1613 * they see this status (any time they drop and re-acquire xhci->lock).
1614 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1615 * putting the TD on the canceled list, etc.
1616 *
1617 * There are no reports of xHCI host controllers that display this issue.
1618 */
1619#define XHCI_STATE_DYING        (1 << 0)
1620#define XHCI_STATE_HALTED       (1 << 1)
1621#define XHCI_STATE_REMOVING     (1 << 2)
1622        /* Statistics */
1623        int                     error_bitmask;
1624        unsigned int            quirks;
1625#define XHCI_LINK_TRB_QUIRK     (1 << 0)
1626#define XHCI_RESET_EP_QUIRK     (1 << 1)
1627#define XHCI_NEC_HOST           (1 << 2)
1628#define XHCI_AMD_PLL_FIX        (1 << 3)
1629#define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1630/*
1631 * Certain Intel host controllers have a limit to the number of endpoint
1632 * contexts they can handle.  Ideally, they would signal that they can't handle
1633 * anymore endpoint contexts by returning a Resource Error for the Configure
1634 * Endpoint command, but they don't.  Instead they expect software to keep track
1635 * of the number of active endpoints for them, across configure endpoint
1636 * commands, reset device commands, disable slot commands, and address device
1637 * commands.
1638 */
1639#define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1640#define XHCI_BROKEN_MSI         (1 << 6)
1641#define XHCI_RESET_ON_RESUME    (1 << 7)
1642#define XHCI_SW_BW_CHECKING     (1 << 8)
1643#define XHCI_AMD_0x96_HOST      (1 << 9)
1644#define XHCI_TRUST_TX_LENGTH    (1 << 10)
1645#define XHCI_LPM_SUPPORT        (1 << 11)
1646#define XHCI_INTEL_HOST         (1 << 12)
1647#define XHCI_SPURIOUS_REBOOT    (1 << 13)
1648#define XHCI_COMP_MODE_QUIRK    (1 << 14)
1649#define XHCI_AVOID_BEI          (1 << 15)
1650#define XHCI_PLAT               (1 << 16)
1651#define XHCI_SLOW_SUSPEND       (1 << 17)
1652#define XHCI_SPURIOUS_WAKEUP    (1 << 18)
1653/* For controllers with a broken beyond repair streams implementation */
1654#define XHCI_BROKEN_STREAMS     (1 << 19)
1655#define XHCI_PME_STUCK_QUIRK    (1 << 20)
1656#define XHCI_MTK_HOST           (1 << 21)
1657#define XHCI_SSIC_PORT_UNUSED   (1 << 22)
1658#define XHCI_NO_64BIT_SUPPORT   (1 << 23)
1659#define XHCI_MISSING_CAS        (1 << 24)
1660/* For controller with a broken Port Disable implementation */
1661#define XHCI_BROKEN_PORT_PED    (1 << 25)
1662
1663        unsigned int            num_active_eps;
1664        unsigned int            limit_active_eps;
1665        /* There are two roothubs to keep track of bus suspend info for */
1666        struct xhci_bus_state   bus_state[2];
1667        /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1668        u8                      *port_array;
1669        /* Array of pointers to USB 3.0 PORTSC registers */
1670        __le32 __iomem          **usb3_ports;
1671        unsigned int            num_usb3_ports;
1672        /* Array of pointers to USB 2.0 PORTSC registers */
1673        __le32 __iomem          **usb2_ports;
1674        struct xhci_hub         usb2_rhub;
1675        struct xhci_hub         usb3_rhub;
1676        unsigned int            num_usb2_ports;
1677        /* support xHCI 0.96 spec USB2 software LPM */
1678        unsigned                sw_lpm_support:1;
1679        /* support xHCI 1.0 spec USB2 hardware LPM */
1680        unsigned                hw_lpm_support:1;
1681        /* cached usb2 extened protocol capabilites */
1682        u32                     *ext_caps;
1683        unsigned int            num_ext_caps;
1684        /* Compliance Mode Recovery Data */
1685        struct timer_list       comp_mode_recovery_timer;
1686        u32                     port_status_u0;
1687/* Compliance Mode Timer Triggered every 2 seconds */
1688#define COMP_MODE_RCVRY_MSECS 2000
1689
1690        /* platform-specific data -- must come last */
1691        unsigned long           priv[0] __aligned(sizeof(s64));
1692};
1693
1694/* Platform specific overrides to generic XHCI hc_driver ops */
1695struct xhci_driver_overrides {
1696        size_t extra_priv_size;
1697        int (*reset)(struct usb_hcd *hcd);
1698        int (*start)(struct usb_hcd *hcd);
1699};
1700
1701#define XHCI_CFC_DELAY          10
1702
1703/* convert between an HCD pointer and the corresponding EHCI_HCD */
1704static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1705{
1706        struct usb_hcd *primary_hcd;
1707
1708        if (usb_hcd_is_primary_hcd(hcd))
1709                primary_hcd = hcd;
1710        else
1711                primary_hcd = hcd->primary_hcd;
1712
1713        return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1714}
1715
1716static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1717{
1718        return xhci->main_hcd;
1719}
1720
1721#define xhci_dbg(xhci, fmt, args...) \
1722        dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1723#define xhci_err(xhci, fmt, args...) \
1724        dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1725#define xhci_warn(xhci, fmt, args...) \
1726        dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1727#define xhci_warn_ratelimited(xhci, fmt, args...) \
1728        dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1729#define xhci_info(xhci, fmt, args...) \
1730        dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1731
1732/*
1733 * Registers should always be accessed with double word or quad word accesses.
1734 *
1735 * Some xHCI implementations may support 64-bit address pointers.  Registers
1736 * with 64-bit address pointers should be written to with dword accesses by
1737 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1738 * xHCI implementations that do not support 64-bit address pointers will ignore
1739 * the high dword, and write order is irrelevant.
1740 */
1741static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1742                __le64 __iomem *regs)
1743{
1744        return lo_hi_readq(regs);
1745}
1746static inline void xhci_write_64(struct xhci_hcd *xhci,
1747                                 const u64 val, __le64 __iomem *regs)
1748{
1749        lo_hi_writeq(val, regs);
1750}
1751
1752static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1753{
1754        return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1755}
1756
1757/* xHCI debugging */
1758void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1759void xhci_print_registers(struct xhci_hcd *xhci);
1760void xhci_dbg_regs(struct xhci_hcd *xhci);
1761void xhci_print_run_regs(struct xhci_hcd *xhci);
1762void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1763void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1764void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1765void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1766void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1767void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1768void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1769void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1770char *xhci_get_slot_state(struct xhci_hcd *xhci,
1771                struct xhci_container_ctx *ctx);
1772void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1773                unsigned int slot_id, unsigned int ep_index,
1774                struct xhci_virt_ep *ep);
1775void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1776                        const char *fmt, ...);
1777
1778/* xHCI memory management */
1779void xhci_mem_cleanup(struct xhci_hcd *xhci);
1780int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1781void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1782int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1783int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1784void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1785                struct usb_device *udev);
1786unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1787unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1788unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1789unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1790unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1791void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1792void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1793                struct xhci_bw_info *ep_bw,
1794                struct xhci_interval_bw_table *bw_table,
1795                struct usb_device *udev,
1796                struct xhci_virt_ep *virt_ep,
1797                struct xhci_tt_bw_info *tt_info);
1798void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1799                struct xhci_virt_device *virt_dev,
1800                int old_active_eps);
1801void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1802void xhci_update_bw_info(struct xhci_hcd *xhci,
1803                struct xhci_container_ctx *in_ctx,
1804                struct xhci_input_control_ctx *ctrl_ctx,
1805                struct xhci_virt_device *virt_dev);
1806void xhci_endpoint_copy(struct xhci_hcd *xhci,
1807                struct xhci_container_ctx *in_ctx,
1808                struct xhci_container_ctx *out_ctx,
1809                unsigned int ep_index);
1810void xhci_slot_copy(struct xhci_hcd *xhci,
1811                struct xhci_container_ctx *in_ctx,
1812                struct xhci_container_ctx *out_ctx);
1813int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1814                struct usb_device *udev, struct usb_host_endpoint *ep,
1815                gfp_t mem_flags);
1816void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1817int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1818                                unsigned int num_trbs, gfp_t flags);
1819void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1820                struct xhci_virt_device *virt_dev,
1821                unsigned int ep_index);
1822struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1823                unsigned int num_stream_ctxs,
1824                unsigned int num_streams,
1825                unsigned int max_packet, gfp_t flags);
1826void xhci_free_stream_info(struct xhci_hcd *xhci,
1827                struct xhci_stream_info *stream_info);
1828void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1829                struct xhci_ep_ctx *ep_ctx,
1830                struct xhci_stream_info *stream_info);
1831void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1832                struct xhci_virt_ep *ep);
1833void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1834        struct xhci_virt_device *virt_dev, bool drop_control_ep);
1835struct xhci_ring *xhci_dma_to_transfer_ring(
1836                struct xhci_virt_ep *ep,
1837                u64 address);
1838struct xhci_ring *xhci_stream_id_to_ring(
1839                struct xhci_virt_device *dev,
1840                unsigned int ep_index,
1841                unsigned int stream_id);
1842struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1843                bool allocate_in_ctx, bool allocate_completion,
1844                gfp_t mem_flags);
1845void xhci_urb_free_priv(struct urb_priv *urb_priv);
1846void xhci_free_command(struct xhci_hcd *xhci,
1847                struct xhci_command *command);
1848
1849/* xHCI host controller glue */
1850typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1851int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
1852void xhci_quiesce(struct xhci_hcd *xhci);
1853int xhci_halt(struct xhci_hcd *xhci);
1854int xhci_reset(struct xhci_hcd *xhci);
1855int xhci_init(struct usb_hcd *hcd);
1856int xhci_run(struct usb_hcd *hcd);
1857void xhci_stop(struct usb_hcd *hcd);
1858void xhci_shutdown(struct usb_hcd *hcd);
1859int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1860void xhci_init_driver(struct hc_driver *drv,
1861                      const struct xhci_driver_overrides *over);
1862
1863#ifdef  CONFIG_PM
1864int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1865int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1866#else
1867#define xhci_suspend    NULL
1868#define xhci_resume     NULL
1869#endif
1870
1871int xhci_get_frame(struct usb_hcd *hcd);
1872irqreturn_t xhci_irq(struct usb_hcd *hcd);
1873irqreturn_t xhci_msi_irq(int irq, void *hcd);
1874int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1875void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1876int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1877                struct xhci_virt_device *virt_dev,
1878                struct usb_device *hdev,
1879                struct usb_tt *tt, gfp_t mem_flags);
1880int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1881                struct usb_host_endpoint **eps, unsigned int num_eps,
1882                unsigned int num_streams, gfp_t mem_flags);
1883int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1884                struct usb_host_endpoint **eps, unsigned int num_eps,
1885                gfp_t mem_flags);
1886int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1887int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
1888int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1889int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1890                                struct usb_device *udev, int enable);
1891int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1892                        struct usb_tt *tt, gfp_t mem_flags);
1893int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1894int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1895int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1896int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1897void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1898int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1899int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1900void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1901
1902/* xHCI ring, segment, TRB, and TD functions */
1903dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1904struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1905                struct xhci_segment *start_seg, union xhci_trb *start_trb,
1906                union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1907int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1908void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1909int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1910                u32 trb_type, u32 slot_id);
1911int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1912                dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1913int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1914                u32 field1, u32 field2, u32 field3, u32 field4);
1915int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1916                int slot_id, unsigned int ep_index, int suspend);
1917int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1918                int slot_id, unsigned int ep_index);
1919int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1920                int slot_id, unsigned int ep_index);
1921int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1922                int slot_id, unsigned int ep_index);
1923int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1924                struct urb *urb, int slot_id, unsigned int ep_index);
1925int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1926                struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1927                bool command_must_succeed);
1928int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1929                dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1930int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1931                int slot_id, unsigned int ep_index);
1932int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1933                u32 slot_id);
1934void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1935                unsigned int slot_id, unsigned int ep_index,
1936                unsigned int stream_id, struct xhci_td *cur_td,
1937                struct xhci_dequeue_state *state);
1938void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1939                unsigned int slot_id, unsigned int ep_index,
1940                unsigned int stream_id,
1941                struct xhci_dequeue_state *deq_state);
1942void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1943                unsigned int ep_index, struct xhci_td *td);
1944void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1945                unsigned int slot_id, unsigned int ep_index,
1946                struct xhci_dequeue_state *deq_state);
1947void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1948void xhci_handle_command_timeout(struct work_struct *work);
1949
1950void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1951                unsigned int ep_index, unsigned int stream_id);
1952void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1953
1954/* xHCI roothub code */
1955void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1956                                int port_id, u32 link_state);
1957int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1958                        struct usb_device *udev, enum usb3_link_state state);
1959int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1960                        struct usb_device *udev, enum usb3_link_state state);
1961void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1962                                int port_id, u32 port_bit);
1963int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1964                char *buf, u16 wLength);
1965int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1966int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1967
1968#ifdef CONFIG_PM
1969int xhci_bus_suspend(struct usb_hcd *hcd);
1970int xhci_bus_resume(struct usb_hcd *hcd);
1971#else
1972#define xhci_bus_suspend        NULL
1973#define xhci_bus_resume         NULL
1974#endif  /* CONFIG_PM */
1975
1976u32 xhci_port_state_to_neutral(u32 state);
1977int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1978                u16 port);
1979void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1980
1981/* xHCI contexts */
1982struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1983struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1984struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1985
1986struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1987                unsigned int slot_id, unsigned int ep_index,
1988                unsigned int stream_id);
1989static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1990                                                                struct urb *urb)
1991{
1992        return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1993                                        xhci_get_endpoint_index(&urb->ep->desc),
1994                                        urb->stream_id);
1995}
1996
1997#endif /* __LINUX_XHCI_HCD_H */
Note: See TracBrowser for help on using the repository browser.