Changeset 11650

Timestamp:

02/18/09 17:39:58 (4 years ago)

Author:

BrainSlayer

Message:

wrt610n support merge

Location:

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx

Files:

• bcmsrom.c (modified) (2 diffs)
• bcmutils.c (modified) (1 diff)
• hndpci.c (modified) (2 diffs)
• hndpmu.c (modified) (3 diffs)
• include/bcmsrom.h (modified) (1 diff)
• include/pcicfg.h (modified) (1 diff)
• include/sbconfig.h (modified) (1 diff)
• sbutils.c (modified) (3 diffs)
• setup.c (modified) (1 diff)

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/bcmsrom.c

@@ -1405 +1405 @@
   {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
   {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
+        {"tssipos2g",   0xffffff00,     0,              SROM8_FEM2G,    SROM8_FEM_TSSIPOS_MASK},
+        {"extpagain2g", 0xffffff00,     0,              SROM8_FEM2G,    SROM8_FEM_EXTPA_GAIN_MASK},
+        {"pdetrange2g", 0xffffff00,     0,              SROM8_FEM2G,    SROM8_FEM_PDET_RANGE_MASK},
+        {"triso2g",     0xffffff00,     0,              SROM8_FEM2G,    SROM8_FEM_TR_ISO_MASK},
+        {"antswctl2g",  0xffffff00,     0,              SROM8_FEM2G,    SROM8_FEM_ANTSWLUT_MASK},
+        {"tssipos5g",   0xffffff00,     0,              SROM8_FEM5G,    SROM8_FEM_TSSIPOS_MASK},
+        {"extpagain5g", 0xffffff00,     0,              SROM8_FEM5G,    SROM8_FEM_EXTPA_GAIN_MASK},
+        {"pdetrange5g", 0xffffff00,     0,              SROM8_FEM5G,    SROM8_FEM_PDET_RANGE_MASK},
+        {"triso5g",     0xffffff00,     0,              SROM8_FEM5G,    SROM8_FEM_TR_ISO_MASK},
+        {"antswctl5g",  0xffffff00,     0,              SROM8_FEM5G,    SROM8_FEM_ANTSWLUT_MASK},
   {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0xff},
   {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
@@ -1783 +1793 @@
 
   if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
-      ((sbh->buscoretype == SB_PCIE) && (sbh->buscorerev >= 6)))
+      (((sbh->buscoretype == SB_PCIE) && (sbh->buscorerev >= 6)) || ((sbh->buscoretype == SB_PCI) && (sbh->buscorerev >= 0xe))))
     {
       /* sromrev >= 4, read more */

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/bcmutils.c

@@ -45 +45 @@
 static char *nvram_vars = NULL;
 static int vars_len = -1;
+
+/* count segments of a chained packet */
+uint
+pktsegcnt(osl_t *osh, void *p)
+{
+        uint cnt;
+
+        for (cnt = 0; p; p = PKTNEXT(osh, p))
+                cnt++;
+
+        return cnt;
+}
 
 /* copy a pkt buffer chain into a buffer */

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/hndpci.c

@@ -195 +195 @@
   if (pci_disabled)
     val = 0xffffffff;
-  else if (bus == 1 && dev == pci_hbslot && func == 0 &&
+  else if (bus == 1 && dev == pci_hbslot && (func == 0 || func == 1) &&
            sb_pcihb_read_config (sbh, bus, dev, func, off, &reg, &val))
     ;
@@ -244 +244 @@
   if (pci_disabled)
     return 0;
-  else if (bus == 1 && dev == pci_hbslot && func == 0 &&
+  else if (bus == 1 && dev == pci_hbslot && (func == 0 || func == 1) &&
            sb_pcihb_read_config (sbh, bus, dev, func, off, &reg, &val))
     ;

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/hndpmu.c

@@ -47 +47 @@
 static uint32 sb_pmu1_alpclk0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc);
 #endif
+
+void
+sb_pmu_chipcontrol(sb_t *sih, uint reg, uint32 mask, uint32 val)
+{
+        sb_corereg(sih, SB_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0, reg);
+        sb_corereg(sih, SB_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_data), mask, val);
+}
 
 /* Setup switcher voltage */
@@ -179 +186 @@
 }
 
-uint16 BCMINITFN (sb_pmu_fast_pwrup_delay) (sb_t * sbh, osl_t * osh)
-{
-  uint16 delay = PMU_MAX_TRANSITION_DLY;
-
-  ASSERT (sbh->cccaps & CC_CAP_PMU);
-
-  switch (sbh->chip)
-    {
+uint16
+BCMINITFN(sb_pmu_fast_pwrup_delay)(sb_t *sbh, osl_t *osh)
+{
+        uint16 delay = PMU_MAX_TRANSITION_DLY;
+
+        ASSERT(sbh->cccaps & CC_CAP_PMU);
+
+        switch (sbh->chip) {
 #if defined(BCM4328)
-    case BCM4328_CHIP_ID:
-      delay = 7000;
-      break;
-#endif /* BCM4328 */
-
+        case BCM4328_CHIP_ID:
+                delay = 7000;
+                break;
+#endif
 #if defined(BCM4325)
-    case BCM4325_CHIP_ID:
-#ifdef BCMQT
-      delay = 70;
-#else
-      delay = 2800;
-#endif
-      break;
-#endif /* BCM4325 || BCM4312 */
+        case BCM4325_CHIP_ID:
+                delay = ISSIM_ENAB(sbh) ? 70 : 3000;
+                break;
+#endif /* BCM4325 */
 #if defined(BCMPMU)
         case BCM4312_CHIP_ID:
@@ -211 +213 @@
 #endif /* BCMPMU */
 
-    default:
-      PMU_MSG (("No PMU fast power up delay specified "
-                "for chip %x rev %d, using default %d us\n",
-                sbh->chip, sbh->chiprev, delay));
-      break;
-    }
-
-  return delay;
+        default:
+                PMU_MSG(("No PMU fast power up delay specified "
+                        "for chip %x rev %d, using default %d us\n",
+                        sbh->chip, sbh->chiprev, delay));
+                break;
+        }
+
+        return delay;
 }
 

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/include/bcmsrom.h

@@ -294 +294 @@
 #define SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
 
+#define SROM8_FEM2G             87
+#define SROM8_FEM5G             88
+#define SROM8_FEM_ANTSWLUT_MASK         0xf800
+#define SROM8_FEM_ANTSWLUT_SHIFT        11
+#define SROM8_FEM_TR_ISO_MASK           0x0700
+#define SROM8_FEM_TR_ISO_SHIFT          8
+#define SROM8_FEM_PDET_RANGE_MASK       0x00f8
+#define SROM8_FEM_PDET_RANGE_SHIFT      3
+#define SROM8_FEM_EXTPA_GAIN_MASK       0x0006
+#define SROM8_FEM_EXTPA_GAIN_SHIFT      1
+#define SROM8_FEM_TSSIPOS_MASK          0x0001
+#define SROM8_FEM_TSSIPOS_SHIFT         0
+
+
+
 #define SROM8_CRCREV            219
 

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/include/pcicfg.h

@@ -466 +466 @@
 #define PCI_BACKPLANE_ADDR      0xA0    /* address an arbitrary location on the system backplane */
 #define PCI_BACKPLANE_DATA      0xA4    /* data at the location specified by above address */
+#define PCI_CLK_CTL_ST          0xa8    /* pci config space clock control/status (>=rev14) */
 #define PCI_GPIO_IN             0xb0    /* pci config space gpio input (>=rev3) */
 #define PCI_GPIO_OUT            0xb4    /* pci config space gpio output (>=rev3) */

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/include/sbconfig.h

@@ -246 +246 @@
 #define SBTMCL_IM_MASK          0x3000000       /* interrupt mode */
 #define SBTMCL_IM_SHIFT         24
+
+#define SBTML_SICF_SHIFT        16              /* Shift to locate the SI control flags in sbtml */
+#define SBTMH_SISF_SHIFT        16              /* Shift to locate the SI status flags in sbtmh */
+
 
 /* sbtmconfighigh */

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/sbutils.c

@@ -105 +105 @@
 static uint8 sb_find_pci_capability (sb_info_t * si, uint8 req_cap_id,
                                      uchar * buf, uint32 * buflen);
-static int sb_pci_fixcfg (sb_info_t * si);
+int sb_pci_fixcfg (sb_info_t * si);
 /* routines to access mdio slave device registers */
 static int sb_pcie_mdiowrite (sb_info_t * si, uint physmedia, uint readdr,
@@ -4292 +4292 @@
  * The current core may be changed upon return.
  */
-static int
+int
 sb_pci_fixcfg (sb_info_t * si)
 {
@@ -4520 +4520 @@
   return memsize;
 }
+
+
+void
+sb_pcie_war_ovr_disable(sb_t *sih)
+{
+}
+
+void
+sb_core_cflags_wo(sb_t *sih, uint32 mask, uint32 val)
+{
+        sb_info_t *sii;
+        sbconfig_t *sb;
+        uint32 w;
+
+        sii = SB_INFO(sih);
+        sb = REGS2SB(sii->curmap);
+
+        ASSERT((val & ~mask) == 0);
+
+        /* mask and set */
+        w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
+                (val << SBTML_SICF_SHIFT);
+        W_SBREG(sii, &sb->sbtmstatelow, w);
+}
+
+/* set/clear core-specific control flags */
+uint32
+sb_core_cflags(sb_t *sih, uint32 mask, uint32 val)
+{
+        sb_info_t *sii;
+        sbconfig_t *sb;
+        uint32 w;
+
+        sii = SB_INFO(sih);
+        sb = REGS2SB(sii->curmap);
+
+        ASSERT((val & ~mask) == 0);
+
+        /* mask and set */
+        if (mask || val) {
+                w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
+                        (val << SBTML_SICF_SHIFT);
+                W_SBREG(sii, &sb->sbtmstatelow, w);
+        }
+
+        /* return the new value
+         * for write operation, the following readback ensures the completion of write opration.
+         */
+        return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
+}
+
+/* set/clear core-specific status flags */
+uint32
+sb_core_sflags(sb_t *sih, uint32 mask, uint32 val)
+{
+        sb_info_t *sii;
+        sbconfig_t *sb;
+        uint32 w;
+
+        sii = SB_INFO(sih);
+        sb = REGS2SB(sii->curmap);
+
+        ASSERT((val & ~mask) == 0);
+        ASSERT((mask & ~SISF_CORE_BITS) == 0);
+
+        /* mask and set */
+        if (mask || val) {
+                w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
+                        (val << SBTMH_SISF_SHIFT);
+                W_SBREG(sii, &sb->sbtmstatehigh, w);
+        }
+
+        /* return the new value */
+        return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
+}
+void
+sb_pmu_spuravoid(sb_t *sbh, osl_t *osh, bool spuravoid)
+{
+        chipcregs_t *cc;
+        uint origidx;
+        uint32 tmp;
+
+        /* Remember original core before switch to chipc */
+        origidx = sb_coreidx(sbh);
+        cc = sb_setcore(sbh, SB_CC, 0);
+        ASSERT(cc);
+
+        W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+        W_REG(osh, &cc->pllcontrol_data, 0x11100070);
+        W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+        W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
+        W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+        W_REG(osh, &cc->pllcontrol_data, 0x88888854);
+
+        if (spuravoid) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
+                W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+                W_REG(osh, &cc->pllcontrol_data, 0x05201828);
+        } else { /* enable 40/80/160Mhz clock mode */
+                W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+                W_REG(osh, &cc->pllcontrol_data, 0x05001828);
+        }
+
+        tmp = R_REG(osh, &cc->pmucontrol);
+        W_REG(osh, &cc->pmucontrol, tmp | (1 << 10));  
+
+        /* Return to original core */
+        sb_setcoreidx(sbh, origidx);
+}
+
+
+void
+sb_4329_tweak(sb_t *sih, uint32 mask, uint32 val)
+{
+        sb_info_t *sii;
+        chipcregs_t *cc;
+        uint origidx;
+        uint32 temp;
+
+        sii = SB_INFO(sih);
+
+        origidx = sii->curidx;
+        ASSERT(GOODIDX(origidx));
+
+        cc = (chipcregs_t *)sb_setcore(sih, SB_CC, 0);
+
+        W_REG(sii->osh, &cc->chipcontrol_addr, 0);
+        temp = R_REG(sii->osh, &cc->chipcontrol_data);
+        temp = temp & ~mask;
+        temp = temp | val;
+        W_REG(sii->osh, &cc->chipcontrol_data, temp);
+
+        sb_setcoreidx(sih, origidx);
+}
+
+void
+sb_4329_pmu_voltage(sb_t *sih)
+{
+        sb_info_t *sii;
+        chipcregs_t *cc;
+        uint origidx;
+        uint32 temp;
+        /* Function For CHANGING CBUCK,CLDO,LNLDO1 Voltages To Same As BT */
+        sii = SB_INFO(sih);
+        origidx = sii->curidx;
+        ASSERT(GOODIDX(origidx));
+        cc = (chipcregs_t *)sb_setcore(sih, SB_CC, 0);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 3);
+        temp = R_REG(sii->osh, &cc->regcontrol_data);
+        temp = temp | 0x04200000;
+        W_REG(sii->osh, &cc->regcontrol_data, temp);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 5);
+        temp = R_REG(sii->osh, &cc->regcontrol_data);
+        temp = temp | 0x0003fe00;
+        W_REG(sii->osh, &cc->regcontrol_data, temp);
+        sb_setcoreidx(sih, origidx);
+}
+
+void
+sb_4329_vbatmeas_on(sb_t *sih, uint32 *save_reg0, uint32 *save_reg5)
+{
+        sb_info_t *sii;
+        chipcregs_t *cc;
+        uint origidx;
+        uint32 temp;
+
+        return;
+
+        sii = SB_INFO(sih);
+
+        origidx = sii->curidx;
+        ASSERT(GOODIDX(origidx));
+
+        cc = (chipcregs_t *)sb_setcore(sih, SB_CC, 0);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 0);
+        temp = R_REG(sii->osh, &cc->regcontrol_data);
+        *save_reg0 = temp;
+        temp = temp | 0x00000001;
+        W_REG(sii->osh, &cc->regcontrol_data, temp);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 5);
+        temp = R_REG(sii->osh, &cc->regcontrol_data);
+        *save_reg5 = temp;
+        temp = temp | 0x80000000;
+        W_REG(sii->osh, &cc->regcontrol_data, temp);
+
+        sb_setcoreidx(sih, origidx);
+}
+
+void
+sb_4329_vbatmeas_off(sb_t *sih, uint32 save_reg0, uint32 save_reg5)
+{
+        sb_info_t *sii;
+        chipcregs_t *cc;
+        uint origidx;
+
+        return;
+
+        sii = SB_INFO(sih);
+
+        origidx = sii->curidx;
+        ASSERT(GOODIDX(origidx));
+
+        cc = (chipcregs_t *)sb_setcore(sih, SB_CC, 0);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 0);
+        W_REG(sii->osh, &cc->regcontrol_data, save_reg0);
+
+        W_REG(sii->osh, &cc->regcontrol_addr, 5);
+        W_REG(sii->osh, &cc->regcontrol_data, save_reg5);
+
+        sb_setcoreidx(sih, origidx);
+}
+bool
+sb_ldo_war(sb_t *sih, uint devid)
+{
+        sb_info_t *sii = SB_INFO(sih);
+        uint32 w;
+        chipcregs_t *cc;
+        void *regs = sii->curmap;
+        uint32 rev_id, ccst;
+
+        rev_id = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_REV, sizeof(uint32));
+        rev_id &= 0xff;
+        if (!(((devid == BCM4322_CHIP_ID) ||
+              (devid == BCM4322_D11N_ID) ||
+              (devid == BCM4322_D11N2G_ID) ||
+              (devid == BCM4322_D11N5G_ID)) &&
+              (rev_id == 0)))
+                return TRUE;
+
+
+        /* switch to chipcommon */
+        w = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
+        OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
+        cc = (chipcregs_t *)regs;
+
+        /* clear bit 7 to fix LDO
+         * write to register *blindly* WITHOUT read since read may timeout
+         *  because the default clock is 32k ILP
+         */
+        W_REG(sii->osh, &cc->regcontrol_addr, 0);
+        /* AND_REG(sii->osh, &cc->regcontrol_data, ~0x80); */
+        W_REG(sii->osh, &cc->regcontrol_data, 0x3001);
+
+        OSL_DELAY(5000);
+
+        /* request ALP_AVAIL through PMU to move sb out of ILP */
+        W_REG(sii->osh, &cc->min_res_mask, 0x0d);
+
+        SPINWAIT(((ccst = OSL_PCI_READ_CONFIG(sii->osh, PCI_CLK_CTL_ST, 4)) & CCS_ALPAVAIL)
+                 == 0, PMU_MAX_TRANSITION_DLY);
+
+        if ((ccst & CCS_ALPAVAIL) == 0) {
+                SB_ERROR(("ALP never came up clk_ctl_st: 0x%x\n", ccst));
+                return FALSE;
+        }
+
+        OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), w);
+
+        return TRUE;
+}
+
+bool
+BCMINITFN(sb_pci_war16165)(sb_t *sih)
+{
+        sb_info_t *sii;
+
+        sii = SB_INFO(sih);
+
+        return (PCI(sii) && (sih->buscorerev <= 10));
+}
+
+uint32 sb_pcieserdesreg(sb_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val)
+{
+
+}
+
+#define PCI_FORCEHT(si) \
+        (((PCIE(si)) && (si->sb.chip == BCM4311_CHIP_ID) && ((si->sb.chiprev <= 1))) || \
+        ((PCI(si) || PCIE(si)) && (si->sb.chip == BCM4321_CHIP_ID)) || \
+        (PCIE(si)))
+
+bool sb_clkctl_cc(sb_t *sih, uint mode)
+{
+        sb_info_t *sii;
+
+        sii = SB_INFO(sih);
+
+        /* chipcommon cores prior to rev6 don't support dynamic clock control */
+        if (sih->ccrev < 6)
+                return FALSE;
+
+        if (PCI_FORCEHT(sii))
+                return (mode == CLK_FAST);
+
+        return sb_clkctl_clk(sii, mode);
+}

src/linux/brcm/linux.v24_2/arch/mips/bcm947xx/setup.c

@@ -214 +214 @@
 if (boardtype==NULL || strcmp(boardtype,"0x478"))iswrt350n=0;
 if (boothwmodel==NULL || strcmp(boothwmodel,"WRT300N"))iswrt300n11=0;
+if (boothwmodel==NULL || strcmp(boothwmodel,"WRT610N"))
+    {
+    iswrt300n11=0;
+    iswrt350n=0;
+    }
 if (boothwver==NULL || strcmp(boothwver,"1.1"))iswrt300n11=0;
 if (iswrt300n11)