Changeset 12294
- Timestamp:
- 06/16/09 03:47:57 (4 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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ar5315_microredboot/microredboot/boot/src/misc_lzma.c
r12288 r12294 215 215 puts("no bootable image found, try default location 0xbfc10000\r\n"); 216 216 bootoffset = 0x80041000; 217 output_data = 0x80041000;217 output_data = (uch *)0x80041000; 218 218 return 0xbfc10000; 219 219 } … … 230 230 error("ran out of input data"); 231 231 if (resettrigger) { 232 inbuf = linuxaddr;232 inbuf = (uch *)linuxaddr; 233 233 insize = 0x400000; 234 234 inptr = 1; … … 332 332 * 333 333 */ 334 static void delay_us(int us)334 static void udelay(int us) 335 335 { 336 336 unsigned int val1, val2; … … 406 406 #define ARB_RETRY 0x00000100 /* retry policy, debug only */ 407 407 408 #define AR531XPLUS_SPI 0x B1300000 /* SPI FLASH MMR */408 #define AR531XPLUS_SPI 0x11300000 /* SPI FLASH MMR */ 409 409 410 410 #define FLASH_1MB 1 … … 539 539 } 540 540 541 542 #define busy_wait(condition, wait) \ 543 do { \ 544 while (condition) { \ 545 if (!wait) \ 546 udelay(1); \ 547 else \ 548 udelay(wait*1000); \ 549 } \ 550 } while (0) 551 541 552 static __u32 spiflash_sendcmd(int op, u32 addr) 542 553 { … … 546 557 547 558 ptr_opcode = &stm_opcodes[op]; 548 do { 549 reg = spiflash_regread32(SPI_FLASH_CTL); 550 } while (reg & SPI_CTL_BUSY); 559 busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0); 551 560 552 561 spiflash_regwrite32(SPI_FLASH_OPCODE, … … 558 567 spiflash_regwrite32(SPI_FLASH_CTL, reg); 559 568 560 do { 561 reg = spiflash_regread32(SPI_FLASH_CTL); 562 } while (reg & SPI_CTL_BUSY); 569 busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0); 563 570 564 571 if (!ptr_opcode->rx_cnt) … … 621 628 unsigned int res; 622 629 unsigned int offset = flashsize - (blocksize * 3); 623 puts("erasing nvram....\r\n"); 624 spiflash_sendcmd(STM_OP_WR_ENABLE, 0); 625 do { 626 res = spiflash_sendcmd(STM_OP_RD_STATUS, 0); 627 if ((res & 0x3) == 0x2) { 628 break; 629 } 630 delay_us(20); 631 spiflash_sendcmd(STM_OP_WR_ENABLE, 0); 632 } while (1); 633 spiflash_sendcmd(STM_OP_SECTOR_ERASE, offset); 634 while (true) { 635 res = spiflash_sendcmd(STM_OP_RD_STATUS, 0); 636 if ((res & STM_STATUS_WIP) == 0) { 637 break; 638 } 639 } 630 struct opcodes *ptr_opcode; 631 __u32 temp, reg; 632 puts("erasing nvram at "); 633 print_hex(offset); 634 puts("\r\n"); 635 636 637 ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE]; 638 639 temp = ((__u32)offset << 8) | (__u32)(ptr_opcode->code); 640 spiflash_sendcmd(SPI_WRITE_ENABLE,0); 641 busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0); 642 643 spiflash_regwrite32(SPI_FLASH_OPCODE, temp); 644 645 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START; 646 spiflash_regwrite32(SPI_FLASH_CTL, reg); 647 648 busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20); 649 650 640 651 puts("done\r\n"); 641 652 return 0; … … 651 662 arch_decomp_setup(); 652 663 653 puts("MicroRedBoot v1. 1, (c) 2009 DD-WRT.COM (");664 puts("MicroRedBoot v1.2, (c) 2009 DD-WRT.COM ("); 654 665 puts(__DATE__); 655 666 puts(")\r\n"); … … 660 671 if (!resetTouched()) // check if reset button is unpressed again 661 672 break; 662 delay_us(1000000);673 udelay(1000000); 663 674 } 664 675 if (!count) { … … 699 710 regtmp = sysRegRead(AR2316_RESET); 700 711 sysRegWrite(AR2316_RESET, regtmp | mask); 701 delay_us(10000);712 udelay(10000); 702 713 703 714 regtmp = sysRegRead(AR2316_RESET); 704 715 sysRegWrite(AR2316_RESET, regtmp & ~mask); 705 delay_us(10000);716 udelay(10000); 706 717 707 718 regtmp = sysRegRead(AR2316_IF_CTL);
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