Changeset 12322

Timestamp:

06/20/09 02:44:04 (4 years ago)

Author:

BrainSlayer

Message:

nor erase suppport (unfinished)

Location:

ar5315_microredboot/microredboot/boot/src

Files:

• head-ar531x.S (modified) (2 diffs)
• misc_lzma.c (modified) (3 diffs)
• ramconfig.h (modified) (1 diff)

ar5315_microredboot/microredboot/boot/src/head-ar531x.S

@@ -336 +336 @@
 .endm
 
+
 /*
  * romInitFlash - init flash address space in ar531x flash controller
@@ -347 +348 @@
         /* 0x7 == 12.5ns * 8 == 100ns which is typical for flash roms */
         or      t0, FLASHCTL_E | FLASHCTL_AC_8M | FLASHCTL_RBLE | \
-                    FLASHCTL_WP | \
                     (0x01 << FLASHCTL_IDCY_S) | \
                     (0x07 << FLASHCTL_WST1_S) | \

ar5315_microredboot/microredboot/boot/src/misc_lzma.c

@@ -700 +700 @@
 #else
 
+
+
+
+typedef unsigned char                   FLASH_DATA_T;
+#define FLASH_P2V( _a_ ) ((volatile FLASH_DATA_T *)((unsigned int)((_a_))))
+#define FLASH_BLANKVALUE                (FLASH_DATA_T)-111
+#define FLASHWORD(x)                    ((FLASH_DATA_T)(x))
+#define FLASH_POLLING_TIMEOUT   (3000000)
+#define FLASH_READ_ID                   FLASHWORD( 0x90 )
+#define FLASH_WP_STATE                  FLASHWORD( 0x90 )
+#define FLASH_RESET                     FLASHWORD( 0xF0 )
+#define FLASH_PROGRAM                   FLASHWORD( 0xA0 )
+#define FLASH_BLOCK_ERASE               FLASHWORD( 0x30 )
+#define FLASH_Query                                             FLASHWORD( 0x98 ) // Add by Jason for CFI support
+
+#define FLASH_DATA                      FLASHWORD( 0x80 ) // Data complement
+#define FLASH_BUSY                      FLASHWORD( 0x40 ) // "Toggle" bit
+#define FLASH_ERR                       FLASHWORD( 0x20 )
+#define FLASH_SECTOR_ERASE_TIMER        FLASHWORD( 0x08 )
+
+#define FLASH_UNLOCKED                  FLASHWORD( 0x00 )
+#define FLASH_WP_ADDR                   (0x12)
+
+#define FLASH_SETUP_ADDR1               (0x555)
+#define FLASH_SETUP_ADDR2               (0x2AA)
+#define FLASH_VENDORID_ADDR             (0x0)
+#define FLASH_DEVICEID_ADDR             (0x1)
+#define FLASH_DEVICEID_ADDR2            (0xe)
+#define FLASH_DEVICEID_ADDR3            (0xf)
+//#define FLASH_WP_ADDR                         (0x12)
+#define FLASH_SETUP_CODE1               FLASHWORD( 0xAA )
+#define FLASH_SETUP_CODE2               FLASHWORD( 0x55 )
+#define FLASH_SETUP_ERASE               FLASHWORD( 0x80 )
+#define FLASH_ERR_OK                    0x0
+#define FLASH_ERR_DRV_TIMEOUT           -1
+
+static void
+flash_query(void* data)
+{
+    volatile FLASH_DATA_T *ROM;
+    volatile FLASH_DATA_T *f_s1, *f_s2;
+    FLASH_DATA_T* id = (FLASH_DATA_T*) data;
+    FLASH_DATA_T w;
+    long timeout = 50000;
+
+    ROM = (volatile FLASH_DATA_T*) ((unsigned int)nvramdetect & ~(0x800000-1));
+    *(FLASH_P2V(ROM)) = FLASH_RESET;
+
+    f_s1 = FLASH_P2V(ROM+FLASH_SETUP_ADDR1);
+    f_s2 = FLASH_P2V(ROM+FLASH_SETUP_ADDR2);
+
+    *f_s1 = FLASH_RESET;
+    w = *(FLASH_P2V(ROM));
+
+    *f_s1 = FLASH_SETUP_CODE1;
+    *f_s2 = FLASH_SETUP_CODE2;
+    *f_s1 = FLASH_READ_ID;
+
+    id[0] = -1;
+    id[1] = -1;
+
+    // Manufacturers' code
+    id[0] = *(FLASH_P2V(ROM+FLASH_VENDORID_ADDR));
+    // Part number
+    id[1] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR));
+    id[2] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR2));
+    id[3] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR3));
+
+
+    *(FLASH_P2V(ROM)) = FLASH_RESET;
+
+    // Stall, waiting for flash to return to read mode.
+    while ((--timeout != 0) && (w != *(FLASH_P2V(ROM)))) ;
+}
+
+
+#define AR531X_FLASHCTL 0xb8400000
+#define AR531X_FLASHCTL0        (AR531X_FLASHCTL + 0x00)
+#define AR531X_FLASHCTL1        (AR531X_FLASHCTL + 0x04)
+#define AR531X_FLASHCTL2        (AR531X_FLASHCTL + 0x08)
+#define FLASHCTL_IDCY   0x0000000f      /* Idle cycle turn around time */
+#define FLASHCTL_IDCY_S 0
+#define FLASHCTL_WST1   0x000003e0      /* Wait state 1 */
+#define FLASHCTL_WST1_S 5
+#define FLASHCTL_RBLE   0x00000400      /* Read byte lane enable */
+#define FLASHCTL_WST2   0x0000f800      /* Wait state 2 */
+#define FLASHCTL_WST2_S 11
+#define FLASHCTL_AC     0x00070000      /* Flash address check (added) */
+#define FLASHCTL_AC_S   16
+#define FLASHCTL_AC_128K 0x00000000
+#define FLASHCTL_AC_256K 0x00010000
+#define FLASHCTL_AC_512K 0x00020000
+#define FLASHCTL_AC_1M   0x00030000
+#define FLASHCTL_AC_2M   0x00040000
+#define FLASHCTL_AC_4M   0x00050000
+#define FLASHCTL_AC_8M   0x00060000
+#define FLASHCTL_AC_RES  0x00070000     /* 16MB is not supported */
+#define FLASHCTL_E      0x00080000      /* Flash bank enable (added) */
+#define FLASHCTL_BUSERR 0x01000000      /* Bus transfer error status flag */
+#define FLASHCTL_WPERR  0x02000000      /* Write protect error status flag */
+#define FLASHCTL_WP     0x04000000      /* Write protect */
+#define FLASHCTL_BM     0x08000000      /* Burst mode */
+#define FLASHCTL_MW     0x30000000      /* Memory width */
+#define FLASHCTL_MWx8   0x00000000      /* Memory width x8 */
+#define FLASHCTL_MWx16  0x10000000      /* Memory width x16 */
+#define FLASHCTL_MWx32  0x20000000      /* Memory width x32 (not supported) */
+#define FLASHCTL_ATNR   0x00000000      /* Access type == no retry */
+#define FLASHCTL_ATR    0x80000000      /* Access type == retry every */
+#define FLASHCTL_ATR4   0xc0000000      /* Access type == retry every 4 */
+
 static int flash_erase_nvram(unsigned int flashsize, unsigned int blocksize)
 {
@@ -708 +818 @@
                 return;
         }
+    unsigned int flash_ctl = sysRegRead(AR531X_FLASHCTL0);
+
+    flash_ctl &= FLASHCTL_MW;
+
+    /* 
+     * Configure flash bank 0.
+     * We lie about the prom size here in order to allow it to be multiply
+     * mapped.  The heuristics, below, count on that in order to easily 
+     * find configuration data.  The flash drivers know how big the flash
+     * really is.
+     */
+    /*flash_ctl = FLASHCTL_E |
+                FLASHCTL_AC_8M |
+                FLASHCTL_RBLE |
+                (0x01 << FLASHCTL_IDCY_S) |
+                (0x07 << FLASHCTL_WST1_S) |
+                (0x07 << FLASHCTL_WST2_S) |
+                flash_ctl;
+    printf("flashctl0 = 0x%08X\n",flash_ctl);
+
+    sysRegWrite(AR531X_FLASHCTL0, flash_ctl);
+
+    flash_ctl = sysRegRead(AR531X_FLASHCTL1);
+    flash_ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
+    sysRegWrite(AR531X_FLASHCTL1, flash_ctl);
+
+    flash_ctl = sysRegRead(AR531X_FLASHCTL2);
+    flash_ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
+    sysRegWrite(AR531X_FLASHCTL2, flash_ctl);
+*/
+
+
+
+
+
+
+    FLASH_DATA_T id[4];
+    puts("read id\n");
+    flash_query(id);
+    printf("FLASH MANID: %X DEVID: %X DEVID2: %X DEVID3: %X\n",id[0],id[1],id[2],id[3]);
+        
         printf("erasing nvram at [0x%08X]\n", nvramdetect);
+
+    volatile FLASH_DATA_T* ROM, *BANK;
+    volatile FLASH_DATA_T* b_p = (FLASH_DATA_T*) (nvramdetect);
+    volatile FLASH_DATA_T *b_v;
+    volatile FLASH_DATA_T *f_s0, *f_s1, *f_s2;
+    int timeout = 50000;
+    FLASH_DATA_T state;
+    int len;
+    BANK = ROM = (volatile FLASH_DATA_T*)((unsigned long)nvramdetect & ~(0x800000-1));
+    f_s0 = FLASH_P2V(BANK);
+    f_s1 = FLASH_P2V(BANK + FLASH_SETUP_ADDR1);
+    f_s2 = FLASH_P2V(BANK + FLASH_SETUP_ADDR2);
+    len = blocksize;
+    int res = FLASH_ERR_OK;
+
+        {
+#if 0
+                *f_s1 = FLASH_SETUP_CODE1;
+                *f_s2 = FLASH_SETUP_CODE2;
+                *f_s1 = FLASH_WP_STATE;
+                state = *FLASH_P2V(b_p+2);
+                *f_s0 = FLASH_RESET;
+
+                if (FLASH_UNLOCKED != state)
+                {
+                puts("error unprotecting flash\n");
+                *FLASH_P2V(ROM) = FLASH_RESET;
+                return 0;
+                }
+#endif
+        b_v = FLASH_P2V(b_p);
+    
+        *f_s1 = FLASH_SETUP_CODE1;
+        *f_s2 = FLASH_SETUP_CODE2;
+        *f_s1 = FLASH_SETUP_ERASE;
+        *f_s1 = FLASH_SETUP_CODE1;
+        *f_s2 = FLASH_SETUP_CODE2;
+        *b_v  = FLASH_BLOCK_ERASE;
+        timeout = FLASH_POLLING_TIMEOUT;    
+        while (1) {
+            state = *b_v;
+            if ((state & FLASH_SECTOR_ERASE_TIMER)
+                                == FLASH_SECTOR_ERASE_TIMER) break;
+                        udelay(1);
+            if (--timeout == 0) {
+                puts("flash erase timeout\n");                
+                break;
+            }
+        }
+        if (FLASH_ERR_OK == res) {
+            timeout = FLASH_POLLING_TIMEOUT;
+            while (1) {
+                state = *b_v;
+                if (FLASH_BLANKVALUE == state) {
+                    break;
+                }
+                udelay(1);
+                if (--timeout == 0) {
+                puts("flash erase timeout while waiting for erase complete\n");                
+                    res = FLASH_ERR_DRV_TIMEOUT;
+                    break;
+                }
+            }
+        }
+
+        if (FLASH_ERR_OK != res)
+        {
+            *FLASH_P2V(ROM) = FLASH_RESET;
+            return -1;
+        }
+
+        while (len > 0) {
+            b_v = FLASH_P2V(b_p++);
+            if (*b_v != FLASH_BLANKVALUE) {
+                if (FLASH_ERR_OK == res) 
+                    {
+                    puts("erase verify failed\n");
+                    }
+                return 0;
+            }
+            len -= sizeof(*b_p);
+        }
+
+        
+        
+        
+        }
+
+#if 0
+
         volatile unsigned short *block = (unsigned short *)nvramdetect;
         volatile unsigned short *p555 =
@@ -751 +992 @@
         }
         *block = 0xf0;          /* Do reset */
+
+
         puts("erase failed!\n");
         return -1;
+#endif 
 }
 

ar5315_microredboot/microredboot/boot/src/ramconfig.h

@@ -1 +1 @@
 #define RAM_SIZE 0x2000000
 #define AR5312 1
-#define RESETBUTTON 0x06
+#define RESETBUTTON 0x16