Changeset 12328
- Timestamp:
- 06/20/09 21:46:49 (4 years ago)
- Location:
- ar5315_microredboot/microredboot/boot/src
- Files:
-
- 7 added
- 2 deleted
- 4 edited
-
Makefile (modified) (2 diffs)
-
arch (added)
-
arch/ar5312.c (added)
-
arch/ar5315.c (added)
-
arch/mips32.c (added)
-
lib/LzmaDecode.c (modified) (1 diff)
-
lib/printf.c (modified) (1 diff)
-
lib/uncompress-ar5312.h (added)
-
lib/uncompress-ar5315.h (added)
-
lib/uncompress.h (added)
-
misc_lzma.c (modified) (11 diffs)
-
uncompress-ar5312.h (deleted)
-
uncompress-ar5315.h (deleted)
Legend:
- Unmodified
- Added
- Removed
-
ar5315_microredboot/microredboot/boot/src/Makefile
r12325 r12328 29 29 #LD = /home/seg/DEV/broadcom/ar5315_microredboot/microredboot/tools/ecos_build/gnutools/mipsisa32-elf/bin/mipsisa32-elf-ld 30 30 OBJCOPY = /xfs/toolchains/staging_dir_mips/bin/mips-linux-objcopy 31 CFLAGS = -Os -G 0 -mabi=32 -mno-abicalls -fno-pic -pipe -msoft-float -ffreestanding -march=mips32 -Iinclude -I . -Iinclude/asm-mips/mach-atheros -Iinclude/asm/mach-generic -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32 -D__KERNEL__31 CFLAGS = -Os -G 0 -mabi=32 -mno-abicalls -fno-pic -pipe -msoft-float -ffreestanding -march=mips32 -Iinclude -Ilib -I. -Iinclude/asm-mips/mach-atheros -Iinclude/asm/mach-generic -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32 -D__KERNEL__ 32 32 CFLAGS+= -DCONFIG_MIPS_L1_CACHE_SHIFT=5 -DCONFIG_PAGE_SIZE_4KB -DCONFIG_32BIT -DCONFIG_BOOTLOADER 33 33 AFLAGS = -D__ASSEMBLY__ -G 0 -mabi=32 -mno-abicalls -fno-pic -pipe -msoft-float -ffreestanding -march=mips32 -Iinclude -Iinclude/asm-mips/mach-atheros -Iinclude/asm/mach-generic -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32 … … 108 108 sed "$(SEDFLAGS)" < ld.script.in > $@ 109 109 110 clean:; rm -f payload* ld.script *.o *.c~ *.h~ lib/*.o 110 clean:; rm -f payload* ld.script *.o *.c~ *.h~ lib/*.o lib/*.c~ arch/*.c~ 111 111 112 112 .PHONY: clean -
ar5315_microredboot/microredboot/boot/src/lib/LzmaDecode.c
r12325 r12328 168 168 #ifdef _LZMA_LOC_OPT 169 169 CProb *prob = probs + mi; 170 RC_GET_BIT2(prob, mi,;, symbol |= (1 << i)) 170 RC_GET_BIT2(prob, mi,; 171 , symbol |= (1 << i)) 171 172 #else 172 173 int bit = RangeDecoderBitDecode(probs + mi, rd); -
ar5315_microredboot/microredboot/boot/src/lib/printf.c
r12319 r12328 14 14 #include <asm/uaccess.h> 15 15 #include <ramconfig.h> 16 #ifdef AR5312 17 #include "uncompress-ar5312.h" 18 #else 19 #include "uncompress-ar5315.h" 20 #endif 16 #include <uncompress.h> 21 17 22 18 #include "printf.h" -
ar5315_microredboot/microredboot/boot/src/misc_lzma.c
r12325 r12328 20 20 #include <asm/uaccess.h> 21 21 #include "ramconfig.h" 22 #ifdef AR5312 23 #include "uncompress-ar5312.h" 24 #else 25 #include "uncompress-ar5315.h" 26 #endif 22 #include "uncompress.h" 27 23 #include "spiflash.h" 28 24 #include "printf.h" … … 191 187 192 188 #ifdef AR5312 193 static unsigned int sectorsize = 0x10000; 194 static unsigned int linuxaddr = 0xbe010000; 195 static unsigned int flashbase = 0xbe000000; 196 static unsigned int flashsize = 0x800000; 189 #include "arch/ar5312.c" 197 190 #else 198 static unsigned int sectorsize = 0x10000; 199 static unsigned int linuxaddr = 0xbfc10000; 200 static unsigned int flashbase = 0xa8000000; 201 static unsigned int flashsize = 0x800000; 191 #include "arch/ar5315.c" 202 192 #endif 203 193 /* … … 219 209 bootoffset = fis->entry_point; 220 210 output_data = (uch *) fis->mem_base; 221 //#ifdef AR5312222 211 return fis->flash_base; 223 //#else224 // memcpy((unsigned char *)ZCACHEADDR,225 // (unsigned char *)fis->flash_base,226 // 1 * 1024 * 1024);227 // return ZCACHEADDR;228 //#endif229 212 } 230 213 p += 256; … … 278 261 } 279 262 280 /*void __div0(void)281 {282 error("division by zero");283 }*/284 285 #ifdef AR5312286 287 #define AR531X_APBBASE 0xbc000000288 #define AR531X_GPIO (AR531X_APBBASE + 0x2000)289 #define AR531X_GPIO_DI (AR531X_GPIO + 0x04)290 291 static int getGPIO(int nr)292 {293 volatile unsigned int *gpio = (unsigned int *)AR531X_GPIO_DI;294 if ((*gpio & 1 << nr) == (1 << nr))295 return 1;296 return 0;297 }298 299 #else300 301 #define AR2316_DSLBASE 0xB1000000 /* RESET CONTROL MMR */302 #define AR2316_GPIO_DI (AR2316_DSLBASE + 0x0088)303 304 static int getGPIO(int nr)305 {306 volatile unsigned int *gpio = (unsigned int *)AR2316_GPIO_DI;307 if ((*gpio & 1 << nr) == (1 << nr))308 return 1;309 return 0;310 }311 #endif312 263 /* 313 264 * checks if the reset button is pressed, return 1 if the button is pressed and 0 if not … … 321 272 } 322 273 323 #define RTC_DENOMINATOR 100324 #define RTC_PERIOD 110000000 / RTC_DENOMINATOR325 326 #define MACRO_START do {327 #define MACRO_END } while (0)328 static unsigned int cyg_hal_clock_period;329 330 #define HAL_CLOCK_INITIALIZE( _period_ ) \331 MACRO_START \332 asm volatile ( \333 "mtc0 $0,$9\n" \334 "nop; nop; nop\n" \335 "mtc0 %0,$11\n" \336 "nop; nop; nop\n" \337 : \338 : "r"(_period_) \339 ); \340 cyg_hal_clock_period = _period_; \341 MACRO_END342 343 #define HAL_CLOCK_RESET( _vector_, _period_ ) \344 MACRO_START \345 asm volatile ( \346 "mtc0 $0,$9\n" \347 "nop; nop; nop\n" \348 "mtc0 %0,$11\n" \349 "nop; nop; nop\n" \350 : \351 : "r"(_period_) \352 ); \353 MACRO_END354 355 #define HAL_CLOCK_READ( _pvalue_ ) \356 MACRO_START \357 register unsigned int result; \358 asm volatile ( \359 "mfc0 %0,$9\n" \360 : "=r"(result) \361 ); \362 *(_pvalue_) = result; \363 MACRO_END364 365 /*366 * udelay implementation based on cpu cycle counter367 */368 static void udelay(int us)369 {370 unsigned int val1, val2;371 int diff;372 long usticks;373 long ticks;374 375 // Calculate the number of counter register ticks per microsecond.376 377 usticks = (RTC_PERIOD * RTC_DENOMINATOR) / 1000000;378 379 // Make sure that the value is not zero. This will only happen if the380 // CPU is running at < 2MHz.381 if (usticks == 0)382 usticks = 1;383 384 while (us > 0) {385 int us1 = us;386 387 // Wait in bursts of less than 10000us to avoid any overflow388 // problems in the multiply.389 if (us1 > 10000)390 us1 = 10000;391 392 us -= us1;393 394 ticks = us1 * usticks;395 396 HAL_CLOCK_READ(&val1);397 while (ticks > 0) {398 do {399 HAL_CLOCK_READ(&val2);400 }401 while (val1 == val2);402 diff = val2 - val1;403 if (diff < 0)404 diff += RTC_PERIOD;405 ticks -= diff;406 val1 = val2;407 }408 }409 }410 411 #ifndef STANDALONE_DEBUG412 413 typedef unsigned int AR531X_REG;414 415 #undef sysRegRead416 #undef sysRegWrite417 #define sysRegRead(phys) \418 (*(volatile AR531X_REG *)(KSEG1|phys))419 420 #define sysRegWrite(phys, val) \421 ((*(volatile AR531X_REG *)(KSEG1|phys)) = (val))422 423 #ifndef AR5312424 425 #define RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */426 #define RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */427 #define RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */428 #define RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */429 #define RESET_MEMCTL 0x00000010 /* warm reset memory controller */430 #define RESET_LOCAL 0x00000020 /* warm reset local bus */431 #define RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */432 #define RESET_SPI 0x00000080 /* warm reset SPI interface */433 #define RESET_UART0 0x00000100 /* warm reset UART0 */434 #define RESET_IR_RSVD 0x00000200 /* warm reset IR interface */435 #define RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */436 #define RESET_ENET0 0x00000800 /* cold reset ENET0 mac */437 438 #define IF_TS_LOCAL 2439 #define AR2316_DSLBASE 0xB1000000 /* RESET CONTROL MMR */440 #define AR2316_RESET (AR2316_DSLBASE + 0x0004)441 #define AR2316_IF_CTL (AR2316_DSLBASE + 0x0018)442 #define AR2316_ENDIAN_CTL (AR2316_DSLBASE + 0x000c)443 444 #define CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */445 446 #define AR2316_AHB_ARB_CTL (AR2316_DSLBASE + 0x0008)447 #define ARB_CPU 0x00000001 /* CPU, default */448 #define ARB_WLAN 0x00000002 /* WLAN */449 #define ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */450 #define ARB_LOCAL 0x00000008 /* LOCAL */451 #define ARB_PCI 0x00000010 /* PCI */452 #define ARB_ETHERNET 0x00000020 /* Ethernet */453 #define ARB_RETRY 0x00000100 /* retry policy, debug only */454 455 #define AR531XPLUS_SPI 0xB1300000 /* SPI FLASH MMR */456 457 #define FLASH_1MB 1458 #define FLASH_2MB 2459 #define FLASH_4MB 3460 #define FLASH_8MB 4461 #define FLASH_16MB 5462 #define MAX_FLASH 6463 464 #define STM_PAGE_SIZE 256465 466 #define SFI_WRITE_BUFFER_SIZE 4467 #define SFI_FLASH_ADDR_MASK 0x00ffffff468 469 #define STM_8MBIT_SIGNATURE 0x13470 #define STM_M25P80_BYTE_COUNT 1048576471 #define STM_M25P80_SECTOR_COUNT 16472 #define STM_M25P80_SECTOR_SIZE 0x10000473 474 #define STM_16MBIT_SIGNATURE 0x14475 #define STM_M25P16_BYTE_COUNT 2097152476 #define STM_M25P16_SECTOR_COUNT 32477 #define STM_M25P16_SECTOR_SIZE 0x10000478 479 #define STM_32MBIT_SIGNATURE 0x15480 #define STM_M25P32_BYTE_COUNT 4194304481 #define STM_M25P32_SECTOR_COUNT 64482 #define STM_M25P32_SECTOR_SIZE 0x10000483 484 #define STM_64MBIT_SIGNATURE 0x16485 #define STM_M25P64_BYTE_COUNT 8388608486 #define STM_M25P64_SECTOR_COUNT 128487 #define STM_M25P64_SECTOR_SIZE 0x10000488 489 #define STM_128MBIT_SIGNATURE 0x17490 #define STM_M25P128_BYTE_COUNT 16777216491 #define STM_M25P128_SECTOR_COUNT 256492 #define STM_M25P128_SECTOR_SIZE 0x10000493 494 #define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT495 #define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT496 #define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE497 #define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT498 #define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT499 #define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE500 #define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT501 #define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT502 #define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE503 #define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT504 #define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT505 #define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE506 #define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT507 #define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT508 #define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE509 510 #define SPI_FLASH_MMR AR531XPLUS_SPI_MMR511 512 #define SPI_WRITE_ENABLE 0513 #define SPI_WRITE_DISABLE 1514 #define SPI_RD_STATUS 2515 #define SPI_WR_STATUS 3516 #define SPI_RD_DATA 4517 #define SPI_FAST_RD_DATA 5518 #define SPI_PAGE_PROGRAM 6519 #define SPI_SECTOR_ERASE 7520 #define SPI_BULK_ERASE 8521 #define SPI_DEEP_PWRDOWN 9522 #define SPI_RD_SIG 10523 #define SPI_MAX_OPCODES 11524 525 struct flashconfig {526 __u32 byte_cnt;527 __u32 sector_cnt;528 __u32 sector_size;529 __u32 cs_addrmask;530 } static flashconfig_tbl[MAX_FLASH] = {531 {0, 0, 0, 0}, //532 {STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0}, //533 {STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0}, //534 {STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0}, //535 {STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0}, //536 {STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE, 0x0} //537 };538 539 struct opcodes {540 __u16 code;541 __s8 tx_cnt;542 __s8 rx_cnt;543 } static stm_opcodes[] = {544 {STM_OP_WR_ENABLE, 1, 0}, //545 {STM_OP_WR_DISABLE, 1, 0}, //546 {STM_OP_RD_STATUS, 1, 1}, //547 {STM_OP_WR_STATUS, 1, 0}, //548 {STM_OP_RD_DATA, 4, 4}, //549 {STM_OP_FAST_RD_DATA, 5, 0}, //550 {STM_OP_PAGE_PGRM, 8, 0}, //551 {STM_OP_SECTOR_ERASE, 4, 0}, //552 {STM_OP_BULK_ERASE, 1, 0}, //553 {STM_OP_DEEP_PWRDOWN, 1, 0}, //554 {STM_OP_RD_SIG, 4, 1}, //555 };556 557 static __u32 spiflash_regread32(int reg)558 {559 volatile __u32 *data = (__u32 *)(AR531XPLUS_SPI + reg);560 561 return (*data);562 }563 564 static void spiflash_regwrite32(int reg, __u32 data)565 {566 volatile __u32 *addr = (__u32 *)(AR531XPLUS_SPI + reg);567 568 *addr = data;569 return;570 }571 572 #define busy_wait(condition, wait) \573 do { \574 while (condition) { \575 if (!wait) \576 udelay(1); \577 else \578 udelay(wait*1000); \579 } \580 } while (0)581 582 static __u32 spiflash_sendcmd(int op, u32 addr)583 {584 u32 reg;585 u32 mask;586 struct opcodes *ptr_opcode;587 588 ptr_opcode = &stm_opcodes[op];589 busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);590 591 spiflash_regwrite32(SPI_FLASH_OPCODE,592 ((u32)ptr_opcode->code) | (addr << 8));593 594 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |595 (ptr_opcode->rx_cnt << 4) | SPI_CTL_START;596 597 spiflash_regwrite32(SPI_FLASH_CTL, reg);598 599 busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);600 601 if (!ptr_opcode->rx_cnt)602 return 0;603 604 reg = (__u32)spiflash_regread32(SPI_FLASH_DATA);605 606 switch (ptr_opcode->rx_cnt) {607 case 1:608 mask = 0x000000ff;609 break;610 case 2:611 mask = 0x0000ffff;612 break;613 case 3:614 mask = 0x00ffffff;615 break;616 default:617 mask = 0xffffffff;618 break;619 }620 reg &= mask;621 622 return reg;623 }624 625 static int spiflash_probe_chip(void)626 {627 unsigned int sig;628 int flash_size;629 630 sig = spiflash_sendcmd(SPI_RD_SIG, 0);631 632 switch (sig) {633 case STM_8MBIT_SIGNATURE:634 flash_size = FLASH_1MB;635 break;636 case STM_16MBIT_SIGNATURE:637 flash_size = FLASH_2MB;638 break;639 case STM_32MBIT_SIGNATURE:640 flash_size = FLASH_4MB;641 break;642 case STM_64MBIT_SIGNATURE:643 flash_size = FLASH_8MB;644 break;645 case STM_128MBIT_SIGNATURE:646 flash_size = FLASH_16MB;647 break;648 default:649 puts("Read of flash device signature failed!\n");650 return (0);651 }652 653 return (flash_size);654 }655 656 static int flash_erase_nvram(unsigned int flashsize, unsigned int blocksize)657 {658 unsigned int res;659 unsigned int offset = nvramdetect;660 struct opcodes *ptr_opcode;661 __u32 temp, reg;662 if (!nvramdetect) {663 puts("nvram can and will not erased, since nvram was not detected on this device (maybe dd-wrt isnt installed)!\n");664 return;665 }666 printf("erasing nvram at [0x%08X]\n", nvramdetect);667 668 ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];669 670 temp = ((__u32)offset << 8) | (__u32)(ptr_opcode->code);671 spiflash_sendcmd(SPI_WRITE_ENABLE, 0);672 busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);673 674 spiflash_regwrite32(SPI_FLASH_OPCODE, temp);675 676 reg =677 (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |678 SPI_CTL_START;679 spiflash_regwrite32(SPI_FLASH_CTL, reg);680 681 busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);682 683 puts("done\n");684 return 0;685 }686 687 static int flashdetected = 0;688 static int flashdetect(void)689 {690 if (flashdetected)691 return 0;692 flashsize = 8 * 1024 * 1024;693 flashbase = 0xa8000000;694 int index = 0;695 if (!(index = spiflash_probe_chip())) {696 puts("Found no serial flash device, cannot reset to factory defaults\n");697 return -1;698 } else {699 flashsize = flashconfig_tbl[index].byte_cnt;700 sectorsize = flashconfig_tbl[index].sector_size;701 if (flashsize == 8 * 1024 * 1024)702 flashbase = 0xa8000000;703 else704 flashbase = 0xbfc00000;705 printf706 ("Found Flash device SIZE=0x%08X SECTORSIZE=0x%08X FLASHBASE=0x%08X\n",707 flashsize, sectorsize, flashbase);708 }709 flashdetected = 1;710 return 0;711 712 }713 #else714 715 typedef unsigned char FLASH_DATA_T;716 #define FLASH_P2V( _a_ ) ((volatile FLASH_DATA_T *)((unsigned int)((_a_))))717 #define FLASH_BLANKVALUE (FLASH_DATA_T)(0xff)718 #define FLASHWORD(x) ((FLASH_DATA_T)(x))719 #define FLASH_POLLING_TIMEOUT (3000000)720 #define FLASH_READ_ID FLASHWORD( 0x90 )721 #define FLASH_WP_STATE FLASHWORD( 0x90 )722 #define FLASH_RESET FLASHWORD( 0xF0 )723 #define FLASH_PROGRAM FLASHWORD( 0xA0 )724 #define FLASH_BLOCK_ERASE FLASHWORD( 0x30 )725 #define FLASH_Query FLASHWORD( 0x98 ) // Add by Jason for CFI support726 727 #define FLASH_DATA FLASHWORD( 0x80 ) // Data complement728 #define FLASH_BUSY FLASHWORD( 0x40 ) // "Toggle" bit729 #define FLASH_ERR FLASHWORD( 0x20 )730 #define FLASH_SECTOR_ERASE_TIMER FLASHWORD( 0x08 )731 732 #define FLASH_UNLOCKED FLASHWORD( 0x00 )733 #define FLASH_WP_ADDR (4)734 735 #define FLASH_SETUP_ADDR1 (0xAAA)736 #define FLASH_SETUP_ADDR2 (0x555)737 #define FLASH_VENDORID_ADDR (0x0)738 #define FLASH_DEVICEID_ADDR (0x2)739 #define FLASH_DEVICEID_ADDR2 (0x1c)740 #define FLASH_DEVICEID_ADDR3 (0x1e)741 //#define FLASH_WP_ADDR (0x12)742 #define FLASH_SETUP_CODE1 FLASHWORD( 0xAA )743 #define FLASH_SETUP_CODE2 FLASHWORD( 0x55 )744 #define FLASH_SETUP_ERASE FLASHWORD( 0x80 )745 #define FLASH_ERR_OK 0x0746 #define FLASH_ERR_DRV_TIMEOUT -1747 748 /*static void749 flash_query(void* data)750 {751 volatile FLASH_DATA_T *ROM;752 volatile FLASH_DATA_T *f_s1, *f_s2;753 FLASH_DATA_T* id = (FLASH_DATA_T*) data;754 FLASH_DATA_T w;755 long timeout = 50000;756 757 ROM = (volatile FLASH_DATA_T*) ((unsigned int)nvramdetect & ~(0x800000-1));758 *(FLASH_P2V(ROM)) = FLASH_RESET;759 760 f_s1 = FLASH_P2V(ROM+FLASH_SETUP_ADDR1);761 f_s2 = FLASH_P2V(ROM+FLASH_SETUP_ADDR2);762 763 *f_s1 = FLASH_RESET;764 w = *(FLASH_P2V(ROM));765 766 *f_s1 = FLASH_SETUP_CODE1;767 *f_s2 = FLASH_SETUP_CODE2;768 *f_s1 = FLASH_READ_ID;769 770 id[0] = -1;771 id[1] = -1;772 773 // Manufacturers' code774 id[0] = *(FLASH_P2V(ROM+FLASH_VENDORID_ADDR));775 // Part number776 id[1] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR));777 id[2] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR2));778 id[3] = *(FLASH_P2V(ROM+FLASH_DEVICEID_ADDR3));779 780 *(FLASH_P2V(ROM)) = FLASH_RESET;781 782 // Stall, waiting for flash to return to read mode.783 while ((--timeout != 0) && (w != *(FLASH_P2V(ROM)))) ;784 }785 */786 787 #define AR531X_FLASHCTL 0xb8400000788 #define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)789 #define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)790 #define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)791 #define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */792 #define FLASHCTL_IDCY_S 0793 #define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */794 #define FLASHCTL_WST1_S 5795 #define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */796 #define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */797 #define FLASHCTL_WST2_S 11798 #define FLASHCTL_AC 0x00070000 /* Flash address check (added) */799 #define FLASHCTL_AC_S 16800 #define FLASHCTL_AC_128K 0x00000000801 #define FLASHCTL_AC_256K 0x00010000802 #define FLASHCTL_AC_512K 0x00020000803 #define FLASHCTL_AC_1M 0x00030000804 #define FLASHCTL_AC_2M 0x00040000805 #define FLASHCTL_AC_4M 0x00050000806 #define FLASHCTL_AC_8M 0x00060000807 #define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */808 #define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */809 #define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */810 #define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */811 #define FLASHCTL_WP 0x04000000 /* Write protect */812 #define FLASHCTL_BM 0x08000000 /* Burst mode */813 #define FLASHCTL_MW 0x30000000 /* Memory width */814 #define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */815 #define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */816 #define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */817 #define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */818 #define FLASHCTL_ATR 0x80000000 /* Access type == retry every */819 #define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */820 821 static int flash_erase_nvram(unsigned int flashsize, unsigned int blocksize)822 {823 int i, ticks;824 unsigned short val;825 if (!nvramdetect) {826 puts("nvram can and will not erased, since nvram was not detected on this device (maybe dd-wrt isnt installed)!\n");827 return;828 }829 unsigned int flash_ctl = sysRegRead(AR531X_FLASHCTL0);830 831 FLASH_DATA_T id[4];832 // puts("read id\n");833 // flash_query(id);834 // printf("FLASH MANID: %X DEVID: %X DEVID2: %X DEVID3: %X\n",id[0],id[1],id[2],id[3]);835 836 printf("erasing nvram at [0x%08X]\n", nvramdetect);837 838 volatile FLASH_DATA_T *ROM, *BANK;839 volatile FLASH_DATA_T *b_p = (FLASH_DATA_T *) (nvramdetect);840 volatile FLASH_DATA_T *b_v;841 volatile FLASH_DATA_T *f_s0, *f_s1, *f_s2;842 int timeout = 50000;843 FLASH_DATA_T state;844 int len;845 BANK = ROM =846 (volatile FLASH_DATA_T *)((unsigned long)nvramdetect &847 ~(0x800000 - 1));848 f_s0 = FLASH_P2V(BANK);849 f_s1 = FLASH_P2V(BANK + FLASH_SETUP_ADDR1);850 f_s2 = FLASH_P2V(BANK + FLASH_SETUP_ADDR2);851 len = blocksize;852 int res = FLASH_ERR_OK;853 854 *f_s1 = FLASH_SETUP_CODE1;855 *f_s2 = FLASH_SETUP_CODE2;856 *f_s1 = FLASH_WP_STATE;857 state = *FLASH_P2V(b_p + FLASH_WP_ADDR);858 *f_s0 = FLASH_RESET;859 860 if (FLASH_UNLOCKED != state) {861 *FLASH_P2V(ROM) = FLASH_RESET;862 }863 864 b_v = FLASH_P2V(b_p);865 866 *f_s1 = FLASH_SETUP_CODE1;867 *f_s2 = FLASH_SETUP_CODE2;868 *f_s1 = FLASH_SETUP_ERASE;869 *f_s1 = FLASH_SETUP_CODE1;870 *f_s2 = FLASH_SETUP_CODE2;871 *b_v = FLASH_BLOCK_ERASE;872 timeout = FLASH_POLLING_TIMEOUT;873 while (1) {874 state = *b_v;875 if ((state & FLASH_SECTOR_ERASE_TIMER)876 == FLASH_SECTOR_ERASE_TIMER)877 break;878 udelay(1);879 if (--timeout == 0) {880 puts("flash erase timeout\n");881 res = FLASH_ERR_DRV_TIMEOUT;882 break;883 }884 }885 if (FLASH_ERR_OK == res) {886 timeout = FLASH_POLLING_TIMEOUT;887 while (1) {888 state = *b_v;889 if (FLASH_BLANKVALUE == state) {890 break;891 }892 udelay(1);893 if (--timeout == 0) {894 puts("flash erase timeout while waiting for erase complete\n");895 res = FLASH_ERR_DRV_TIMEOUT;896 break;897 }898 }899 }900 901 if (FLASH_ERR_OK != res)902 *FLASH_P2V(ROM) = FLASH_RESET;903 904 b_v = FLASH_P2V(b_p++);905 if (*b_v != FLASH_BLANKVALUE) {906 if (FLASH_ERR_OK == res) {907 puts("erase verify failed\n");908 } else {909 puts("nvram erase done\n");910 }911 return 0;912 }913 914 }915 916 #endif917 274 struct nvram_header { 918 275 __u32 magic; … … 943 300 __u32 off, lim; 944 301 int i; 945 #ifndef AR5312946 302 flashdetect(); 947 #endif948 303 for (i = 0; i < 4; i++) { 949 304 header = … … 997 352 free_mem_ptr = free_mem_ptr_p; 998 353 free_mem_ptr_end = free_mem_ptr_end_p; 999 #ifdef AR5312 1000 #define AR531X_APBBASE 0xbc000000 1001 #define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) 1002 #define AR531X_WDC (AR531X_RESETTMR + 0x0008) 1003 sysRegWrite(AR531X_WDC, 0); 1004 #endif 354 disable_watchdog(); 1005 355 arch_decomp_setup(); 1006 356 printf("MicroRedBoot v1.2, (c) 2009 DD-WRT.COM (%s)\n", __DATE__); … … 1024 374 puts("reset button 5 seconds pushed, erasing nvram\n"); 1025 375 1026 #ifndef AR53121027 376 if (!flashdetect()) 1028 #endif1029 377 flash_erase_nvram(flashsize, sectorsize); 1030 378 } … … 1033 381 resettrigger = 0; 1034 382 } else { 1035 #ifndef AR53121036 383 flashdetect(); 1037 #endif1038 384 linuxaddr = getLinux(); 1039 385 puts("Booting Linux\n"); … … 1043 389 1044 390 /* important, enable ethernet bus, if the following lines are not initialized linux will not be able to use the ethernet mac, taken from redboot source */ 1045 #ifdef AR5312 1046 #define RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ 1047 #define RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ 1048 unsigned int mask = RESET_ENET0 | RESET_EPHY0; 1049 unsigned int regtmp; 1050 #define AR531X_APBBASE 0xbc000000 1051 #define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) 1052 #define AR531X_RESET (AR531X_RESETTMR + 0x0020) 1053 #define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) 1054 #define ENABLE_ENET0 0x0002 1055 1056 regtmp = sysRegRead(AR531X_RESET); 1057 sysRegWrite(AR531X_RESET, regtmp | mask); 1058 udelay(15000); 1059 1060 /* Pull out of reset */ 1061 regtmp = sysRegRead(AR531X_RESET); 1062 sysRegWrite(AR531X_RESET, regtmp & ~mask); 1063 udelay(25); 1064 mask = ENABLE_ENET0; 1065 regtmp = sysRegRead(AR531X_ENABLE); 1066 sysRegWrite(AR531X_ENABLE, regtmp | mask); 1067 1068 #else 1069 unsigned int mask = RESET_ENET0 | RESET_EPHY0; 1070 unsigned int regtmp; 1071 regtmp = sysRegRead(AR2316_AHB_ARB_CTL); 1072 regtmp |= ARB_ETHERNET; 1073 sysRegWrite(AR2316_AHB_ARB_CTL, regtmp); 1074 1075 regtmp = sysRegRead(AR2316_RESET); 1076 sysRegWrite(AR2316_RESET, regtmp | mask); 1077 udelay(10000); 1078 1079 regtmp = sysRegRead(AR2316_RESET); 1080 sysRegWrite(AR2316_RESET, regtmp & ~mask); 1081 udelay(10000); 1082 1083 regtmp = sysRegRead(AR2316_IF_CTL); 1084 regtmp |= IF_TS_LOCAL; 1085 sysRegWrite(AR2316_IF_CTL, regtmp); 1086 1087 regtmp = sysRegRead(AR2316_ENDIAN_CTL); 1088 regtmp &= ~CONFIG_ETHERNET; 1089 sysRegWrite(AR2316_ENDIAN_CTL, regtmp); 1090 #endif 1091 391 enable_ethernet(); 1092 392 } 1093 393 puts("loading"); … … 1097 397 return output_ptr; 1098 398 } 1099 #else1100 1101 char output_buffer[1500 * 1024];1102 1103 int main()1104 {1105 output_data = output_buffer;1106 puts("Uncompressing Linux...");1107 lzma_unzip();1108 puts("done.\r\n");1109 return 0;1110 }1111 #endif
Note: See TracChangeset
for help on using the changeset viewer.
