Changeset 17059


Ignore:
Timestamp:
05/15/11 08:22:12 (2 years ago)
Author:
BrainSlayer
Message:

GCC does not take care if r0 is modified or not by inline assembler code. so move it to a function

Location:
src/linux/laguna/linux-2.6.31.14
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • src/linux/laguna/linux-2.6.31.14/.config_laguna

    r17052 r17059  
    22# Automatically generated make config: don't edit 
    33# Linux kernel version: 2.6.31.14 
    4 # Sat May 14 21:24:29 2011 
     4# Sun May 15 02:10:41 2011 
    55# 
    66CONFIG_ARM=y 
    … …  
    138138# CONFIG_DEFAULT_NOOP is not set 
    139139CONFIG_DEFAULT_IOSCHED="deadline" 
    140 CONFIG_FREEZER=y 
     140# CONFIG_FREEZER is not set 
    141141 
    142142# 
    … …  
    218218# Processor Features 
    219219# 
    220 CONFIG_ARM_THUMB=y 
     220# CONFIG_ARM_THUMB is not set 
    221221# CONFIG_CPU_ICACHE_DISABLE is not set 
    222222# CONFIG_CPU_DCACHE_DISABLE is not set 
    … …  
    343343# 
    344344# CONFIG_PM is not set 
    345 # CONFIG_PM_DEBUG is not set 
    346 CONFIG_PM_SLEEP_SMP=y 
    347 CONFIG_PM_SLEEP=y 
    348 CONFIG_SUSPEND=y 
    349 CONFIG_SUSPEND_FREEZER=y 
    350 # CONFIG_APM_EMULATION is not set 
    351345CONFIG_ARCH_SUSPEND_POSSIBLE=y 
    352346CONFIG_NET=y 
    … …  
    808802# CONFIG_BLK_DEV_SX8 is not set 
    809803# CONFIG_BLK_DEV_UB is not set 
    810 CONFIG_BLK_DEV_RAM=y 
     804# CONFIG_BLK_DEV_RAM is not set 
    811805CONFIG_BLK_DEV_RAM_COUNT=2 
    812806CONFIG_BLK_DEV_RAM_SIZE=32768 
    … …  
    840834# SCSI device support 
    841835# 
    842 CONFIG_RAID_ATTRS=y 
    843 CONFIG_SCSI=y 
     836# CONFIG_RAID_ATTRS is not set 
     837CONFIG_SCSI=m 
    844838CONFIG_SCSI_DMA=y 
    845839# CONFIG_SCSI_TGT is not set 
    … …  
    850844# SCSI support type (disk, tape, CD-ROM) 
    851845# 
    852 CONFIG_BLK_DEV_SD=y 
     846CONFIG_BLK_DEV_SD=m 
    853847# CONFIG_CHR_DEV_ST is not set 
    854848# CONFIG_CHR_DEV_OSST is not set 
    855 CONFIG_BLK_DEV_SR=y 
     849CONFIG_BLK_DEV_SR=m 
    856850# CONFIG_BLK_DEV_SR_VENDOR is not set 
    857 CONFIG_CHR_DEV_SG=y 
     851CONFIG_CHR_DEV_SG=m 
    858852# CONFIG_CHR_DEV_SCH is not set 
    859853CONFIG_SCSI_MULTI_LUN=y 
    … …  
    874868# CONFIG_SCSI_DH is not set 
    875869# CONFIG_SCSI_OSD_INITIATOR is not set 
    876 CONFIG_ATA=y 
     870CONFIG_ATA=m 
    877871# CONFIG_ATA_NONSTANDARD is not set 
    878872# CONFIG_SATA_PMP is not set 
    … …  
    12981292# Sonics Silicon Backplane 
    12991293# 
    1300 CONFIG_SSB=m 
     1294# CONFIG_SSB is not set 
    13011295CONFIG_SSB_SPROM=y 
    13021296CONFIG_SSB_BLOCKIO=y 
    … …  
    13601354# CONFIG_USB_DEVICE_CLASS is not set 
    13611355# CONFIG_USB_DYNAMIC_MINORS is not set 
    1362 # CONFIG_USB_SUSPEND is not set 
    13631356# CONFIG_USB_OTG_WHITELIST is not set 
    13641357# CONFIG_USB_OTG_BLACKLIST_HUB is not set 
    … …  
    14111404# also be needed; see USB_STORAGE Help for more info 
    14121405# 
    1413 CONFIG_USB_STORAGE=y 
     1406CONFIG_USB_STORAGE=m 
    14141407# CONFIG_USB_STORAGE_DEBUG is not set 
    14151408# CONFIG_USB_STORAGE_DATAFAB is not set 
    … …  
    15151508# CONFIG_NOP_USB_XCEIV is not set 
    15161509# CONFIG_UWB is not set 
    1517 CONFIG_MMC=y 
     1510CONFIG_MMC=m 
    15181511# CONFIG_MMC_DEBUG is not set 
    15191512# CONFIG_MMC_UNSAFE_RESUME is not set 
    … …  
    16381631# CONFIG_AUXDISPLAY is not set 
    16391632# CONFIG_REGULATOR is not set 
    1640 CONFIG_UIO=m 
    1641 # CONFIG_UIO_CIF is not set 
    1642 # CONFIG_UIO_PDRV is not set 
    1643 # CONFIG_UIO_PDRV_GENIRQ is not set 
    1644 # CONFIG_UIO_SMX is not set 
    1645 # CONFIG_UIO_AEC is not set 
    1646 # CONFIG_UIO_SERCOS3 is not set 
     1633# CONFIG_UIO is not set 
    16471634# CONFIG_STAGING is not set 
    16481635 

  • src/linux/laguna/linux-2.6.31.14/arch/arm/mach-cns3xxx/core.c

    r17052 r17059  
    501501void __init cns3xxx_sys_init(void) 
    502502{ 
     503#ifdef CONFIG_CACHE_L2X0 
     504        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled 
     505         * Bits:  .... ...0 0111 1001 0000 .... .... .... */ 
     506        l2x0_init((void __iomem *) CNS3XXX_TC11MP_L220_BASE_VIRT, 0x00790000, 0xfe000fff); 
     507#endif 
     508#ifdef CONFIG_CACHE_L2CC 
    503509        l2cc_init((void __iomem *) CNS3XXX_L2C_BASE_VIRT); 
     510#endif 
    504511 
    505512#ifdef CONFIG_CNS3XXX_DMAC 

  • src/linux/laguna/linux-2.6.31.14/arch/arm/mach-cns3xxx/pm.c

    r17038 r17059  
    300300 *              5. Wait PMU to change PLL_CPU and divider and wake up CPU  
    301301 */ 
    302 void cns3xxx_pwr_change_cpu_clock(unsigned int cpu_sel, unsigned int div_sel) 
    303 { 
    304         int old_cpu, old_div; 
    305  
    306         /* sanity check */ 
    307         if ((CNS3XXX_PWR_PLL_CPU_700MHZ < cpu_sel)  
    308                         || (CNS3XXX_PWR_CPU_CLK_DIV_BY4 < div_sel)) { 
    309                 printk("%s: incorrect parameter, cpu_sel:%d, div_sel:%d \n",  
    310                         __FUNCTION__, cpu_sel, div_sel); 
    311                 return; 
    312         } 
    313  
    314         old_cpu = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) &0xf; 
    315         old_div = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; 
    316  
    317         if ((cpu_sel == old_cpu)  
    318                         && (div_sel == old_div)) { 
    319                 return; 
    320         } 
    321                  
    322         /* 1. Set PLL_CPU_SEL */ 
    323         PM_PLL_CPU_SEL(cpu_sel); 
    324         PM_CPU_CLK_DIV(div_sel); 
    325  
    326         /* 2. Set in DFS mode */ 
    327         cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS); 
    328  
    329         //PM_HS_CFG_REG |= ((0x1<<2) | (0x1<<11)); 
    330  
    331         /* 3. disable all interrupt except interrupt ID-32 (clkscale_intr) */ 
    332         GIC_REG_VALUE(0x184) = 0xffffffff; GIC_REG_VALUE(0x188) = 0xffffffff; 
    333         GIC_REG_VALUE(0x104) = 0x00000001; GIC_REG_VALUE(0x108) = 0x80000000; 
    334 #if defined (CNS_PMU_DEBUG) 
    335         clean_wakeup_intr(); 
    336         set_wakeup_intr(IRQ_CNS3XXX_EXTERNAL_PIN2); 
    337         MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27); /* ext intr2 share with GPIOB28*/ 
    338 #endif 
     302void enter_wfi(void) 
     303{ 
     304 
    339305        mb(); 
    340  
    341306        /* 4. Let CPU enter into WFI state */ 
    342307            asm volatile( 
    … …  
    346311            "mcr p15, 0, r0, c7, c0, 4\n" 
    347312            ); 
    348          
     313 
     314} 
     315void cns3xxx_pwr_change_cpu_clock(unsigned int cpu_sel, unsigned int div_sel) 
     316{ 
     317        int old_cpu, old_div; 
     318 
     319        /* sanity check */ 
     320        if ((CNS3XXX_PWR_PLL_CPU_700MHZ < cpu_sel)  
     321                        || (CNS3XXX_PWR_CPU_CLK_DIV_BY4 < div_sel)) { 
     322                printk("%s: incorrect parameter, cpu_sel:%d, div_sel:%d \n",  
     323                        __FUNCTION__, cpu_sel, div_sel); 
     324                return; 
     325        } 
     326 
     327        old_cpu = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) &0xf; 
     328        old_div = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; 
     329 
     330        if ((cpu_sel == old_cpu)  
     331                        && (div_sel == old_div)) { 
     332                return; 
     333        } 
     334                 
     335        /* 1. Set PLL_CPU_SEL */ 
     336        PM_PLL_CPU_SEL(cpu_sel); 
     337        PM_CPU_CLK_DIV(div_sel); 
     338 
     339        /* 2. Set in DFS mode */ 
     340        cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS); 
     341 
     342        //PM_HS_CFG_REG |= ((0x1<<2) | (0x1<<11)); 
     343 
     344        /* 3. disable all interrupt except interrupt ID-32 (clkscale_intr) */ 
     345        GIC_REG_VALUE(0x184) = 0xffffffff;  
     346        GIC_REG_VALUE(0x188) = 0xffffffff; 
     347        GIC_REG_VALUE(0x104) = 0x00000001;  
     348        GIC_REG_VALUE(0x108) = 0x80000000; 
     349#if defined (CNS_PMU_DEBUG) 
     350        clean_wakeup_intr(); 
     351        set_wakeup_intr(IRQ_CNS3XXX_EXTERNAL_PIN2); 
     352        MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27); /* ext intr2 share with GPIOB28*/ 
     353#endif 
     354        enter_wfi(); 
    349355        /* enable interrupts (we disabled before WFI) */ 
    350         GIC_REG_VALUE(0x104) = 0xffffffff; GIC_REG_VALUE(0x108) = 0xffffffff; 
     356        GIC_REG_VALUE(0x104) = 0xffffffff;  
     357        GIC_REG_VALUE(0x108) = 0xffffffff; 
    351358 
    352359#if 1 
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