Changeset 18295

Timestamp:

01/24/12 05:40:42 (17 months ago)

Author:

BrainSlayer

Message:

fix link interrupt

Location:

src/linux/universal/linux-3.2/drivers/net/ethernet/ag7240

Files:

• ag7240.c (modified) (1 diff)
• ar7240_s26_phy.c (modified) (4 diffs)

src/linux/universal/linux-3.2/drivers/net/ethernet/ag7240/ag7240.c

@@ -310 +310 @@
 #endif
     
-    if (is_ar7240() || is_ar7241() || (is_ar7242() && mac->mac_unit == 1))
+    if (is_ar7240() || is_ar7241() || is_ar933x() || (is_ar7242() && mac->mac_unit == 1))
         athrs26_enable_linkIntrs(mac->mac_unit);
 

src/linux/universal/linux-3.2/drivers/net/ethernet/ag7240/ar7240_s26_phy.c

@@ -385 +385 @@
 
     /* Enable WAN mac inside S26 */
-    if (mac_has_flag(mac,ETH_SWONLY_MODE)) 
+    if (mac_has_flag(mac,ETH_SWONLY_MODE) || is_ar933x() ) 
         athrs26_reg_write(PORT_STATUS_REGISTER5,0x200);
 
@@ -579 +579 @@
         athrs26_reg_write(0x104,athrs26_reg_read(0x104)|(0x1<<11));
 
-    if (mac_has_flag(mac,ETH_SWONLY_MODE))
+    if (mac_has_flag(mac,ETH_SWONLY_MODE) || is_ar933x()) 
         athrs26_reg_write(PORT_STATUS_REGISTER5,0x200);
 
@@ -1031 +1031 @@
         unit = 0;
     } 
-    else if(is_ar7241() || is_ar7242()) {
+    else if(is_ar7241() || is_ar7242() || is_ar933x()) {
         unit = 1;
     }
@@ -1065 +1065 @@
         unit = 0;
     } 
-    else if(is_ar7241() || is_ar7242()) {
+    else if(is_ar7241() || is_ar7242() || is_ar933x()) {
         unit = 1;
     }
 
-    phy_reg_write(unit,phy_address, reg_address, data);
-
-    phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
-
-    reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
-    data = s26_write_data >> 16;
-    phy_reg_write(unit,phy_address, reg_address, data);
-    
-    reg_address = ((addr_temp << 1) & 0x1e);
-    data = s26_write_data  & 0xffff;
-    phy_reg_write(unit,phy_address, reg_address, data);
+    if(is_ar933x())
+    {
+        //The writing sequence need special care for register 0x40,0x50,0x98, because the busy bit design
+        //0x98: L->H (write low address first, then high address), 0x40: H->L, 0x50: H->L
+        //Other registers: any sequence is working.
+        if(s26_addr!=0x98)
+        {
+            phy_reg_write(unit, phy_address, reg_address, data);
+
+            phy_address = 0x17 & ((addr_temp >> 4) | 0x10);
+            reg_address = ((addr_temp << 1) & 0x1e) | 0x1;
+            data =  s26_write_data >> 16;
+            phy_reg_write(unit, phy_address, reg_address, data);
+
+            reg_address = reg_address & 0x1e;
+            data = s26_write_data  & 0xffff;
+            phy_reg_write(unit, phy_address, reg_address, data);
+        }
+        else
+        {
+            phy_reg_write(unit, phy_address, reg_address, data);
+
+            phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
+            reg_address = ((addr_temp << 1) & 0x1e);
+
+            data = s26_write_data  & 0xffff;
+            phy_reg_write(unit, phy_address, reg_address, data);
+
+            reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
+            data = s26_write_data >> 16;
+            phy_reg_write(unit, phy_address, reg_address, data);
+
+        }
+    }
+    else
+    {
+        phy_reg_write(unit,phy_address, reg_address, data);
+
+        phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
+
+        reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
+        data = s26_write_data >> 16;
+        phy_reg_write(unit,phy_address, reg_address, data);
+
+        reg_address = ((addr_temp << 1) & 0x1e);
+        data = s26_write_data  & 0xffff;
+        phy_reg_write(unit,phy_address, reg_address, data);
+    }
 }