Ignore:
Timestamp:
Apr 14, 2017, 9:41:36 PM (3 months ago)
Author:
brainslayer
Message:

kernel update

File:
1 edited

Legend:

Unmodified
Added
Removed
  • src/linux/universal/linux-4.9/drivers/clk/nxp/clk-lpc32xx.c

    r31574 r31859  
    12831283        LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
    12841284        LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
    1285                            CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
     1285                           CLK_DIVIDER_ONE_BASED),
    12861286        LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
    12871287        LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
     
    12891289        LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
    12901290        LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
    1291                            CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
     1291                           CLK_DIVIDER_ONE_BASED),
    12921292        LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
    12931293        LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
     
    13361336        LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
    13371337
    1338         LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL,
    1339                            CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
     1338        LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
    13401339        LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
    13411340                           0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
     
    14791478}
    14801479
     1480static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
     1481{
     1482        u32 val;
     1483
     1484        regmap_read(clk_regmap, reg, &val);
     1485
     1486        if (!(val & div_mask)) {
     1487                val &= ~gate;
     1488                val |= BIT(__ffs(div_mask));
     1489        }
     1490
     1491        regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
     1492}
     1493
    14811494static void __init lpc32xx_clk_init(struct device_node *np)
    14821495{
     
    15171530                return;
    15181531        }
     1532
     1533        /*
     1534         * Divider part of PWM and MS clocks requires a quirk to avoid
     1535         * a misinterpretation of formally valid zero value in register
     1536         * bitfield, which indicates another clock gate. Instead of
     1537         * adding complexity to a gate clock ensure that zero value in
     1538         * divider clock is never met in runtime.
     1539         */
     1540        lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0));
     1541        lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2));
     1542        lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9));
    15191543
    15201544        for (i = 1; i < LPC32XX_CLK_MAX; i++) {
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