Ignore:
Timestamp:
Apr 14, 2017, 9:41:36 PM (10 days ago)
Author:
brainslayer
Message:

kernel update

File:
1 edited

Legend:

Unmodified
Added
Removed
  • src/linux/universal/linux-4.9/drivers/pci/quirks.c

    r31687 r31859  
    16361636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
    16371637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
     1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,   0x1610, quirk_pcie_mch);
    16381639
    16391640
     
    21582159        if (dev->vpd) {
    21592160                dev->vpd->len = 0;
    2160                 dev_warn(&dev->dev, FW_BUG "VPD access disabled\n");
     2161                dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
    21612162        }
    21622163}
     
    22412242                         PCI_DEVICE_ID_TIGON3_5719,
    22422243                         quirk_brcm_5719_limit_mrrs);
     2244
     2245#ifdef CONFIG_PCIE_IPROC_PLATFORM
     2246static void quirk_paxc_bridge(struct pci_dev *pdev)
     2247{
     2248        /* The PCI config space is shared with the PAXC root port and the first
     2249         * Ethernet device.  So, we need to workaround this by telling the PCI
     2250         * code that the bridge is not an Ethernet device.
     2251         */
     2252        if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
     2253                pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
     2254
     2255        /* MPSS is not being set properly (as it is currently 0).  This is
     2256         * because that area of the PCI config space is hard coded to zero, and
     2257         * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
     2258         * so that the MPS can be set to the real max value.
     2259         */
     2260        pdev->pcie_mpss = 2;
     2261}
     2262DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
     2263DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
     2264#endif
    22432265
    22442266/* Originally in EDAC sources for i82875P:
     
    31313153        dev->d3_delay = 0;
    31323154}
     3155/* C600 Series devices do not need 10ms d3_delay */
     3156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
    31333157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
    3134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
    31353158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
     3159/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
     3160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
     3161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
     3162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
     3163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
     3164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
     3165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
     3166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
    31363167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
    31373168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
    31383169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
    3139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
    3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
    3141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
    3142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
    3143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
    31443170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
    3145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
    3146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
    31473171/* Intel Cherrytrail devices do not need 10ms d3_delay */
    31483172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
     3173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
     3174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
    31493175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
     3176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
     3177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
    31503178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
    31513179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
    31523180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
    3153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
    3154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
    3155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
    3156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
    31573181
    31583182/*
     
    41544178
    41554179/*
     4180 * These QCOM root ports do provide ACS-like features to disable peer
     4181 * transactions and validate bus numbers in requests, but do not provide an
     4182 * actual PCIe ACS capability.  Hardware supports source validation but it
     4183 * will report the issue as Completer Abort instead of ACS Violation.
     4184 * Hardware doesn't support peer-to-peer and each root port is a root
     4185 * complex with unique segment numbers.  It is not possible for one root
     4186 * port to pass traffic to another root port.  All PCIe transactions are
     4187 * terminated inside the root port.
     4188 */
     4189static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
     4190{
     4191        u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
     4192        int ret = acs_flags & ~flags ? 0 : 1;
     4193
     4194        dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
     4195
     4196        return ret;
     4197}
     4198
     4199/*
    41564200 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
    41574201 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
     
    41684212 * N.B. This doesn't fix what lspci shows.
    41694213 *
     4214 * The 100 series chipset specification update includes this as errata #23[3].
     4215 *
     4216 * The 200 series chipset (Union Point) has the same bug according to the
     4217 * specification update (Intel 200 Series Chipset Family Platform Controller
     4218 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
     4219 * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
     4220 * chipset include:
     4221 *
     4222 * 0xa290-0xa29f PCI Express Root port #{0-16}
     4223 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
     4224 *
    41704225 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
    41714226 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
     4227 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
     4228 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
     4229 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
    41724230 */
    41734231static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
    41744232{
    4175         return pci_is_pcie(dev) &&
    4176                 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
    4177                 ((dev->device & ~0xf) == 0xa110 ||
    4178                  (dev->device >= 0xa167 && dev->device <= 0xa16a));
     4233        if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
     4234                return false;
     4235
     4236        switch (dev->device) {
     4237        case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
     4238        case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
     4239                return true;
     4240        }
     4241
     4242        return false;
    41794243}
    41804244
     
    42894353        { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
    42904354        { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
     4355        /* QCOM QDF2xxx root ports */
     4356        { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
     4357        { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
    42914358        /* Intel PCH root ports */
    42924359        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
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