Ignore:
Timestamp:
Apr 18, 2017, 8:47:31 AM (3 months ago)
Author:
brainslayer
Message:

update kernels

File:
1 edited

Legend:

Unmodified
Added
Removed
  • src/linux/universal/linux-4.9/drivers/gpu/drm/i915/intel_lrc.c

    r31574 r31884  
    21532153void intel_lr_context_resume(struct drm_i915_private *dev_priv)
    21542154{
     2155        struct i915_gem_context *ctx = dev_priv->kernel_context;
    21552156        struct intel_engine_cs *engine;
    2156         struct i915_gem_context *ctx;
    2157 
    2158         /* Because we emit WA_TAIL_DWORDS there may be a disparity
    2159          * between our bookkeeping in ce->ring->head and ce->ring->tail and
    2160          * that stored in context. As we only write new commands from
    2161          * ce->ring->tail onwards, everything before that is junk. If the GPU
    2162          * starts reading from its RING_HEAD from the context, it may try to
    2163          * execute that junk and die.
    2164          *
    2165          * So to avoid that we reset the context images upon resume. For
    2166          * simplicity, we just zero everything out.
    2167          */
    2168         list_for_each_entry(ctx, &dev_priv->context_list, link) {
    2169                 for_each_engine(engine, dev_priv) {
    2170                         struct intel_context *ce = &ctx->engine[engine->id];
    2171                         u32 *reg;
    2172 
    2173                         if (!ce->state)
    2174                                 continue;
    2175 
    2176                         reg = i915_gem_object_pin_map(ce->state->obj,
    2177                                                       I915_MAP_WB);
    2178                         if (WARN_ON(IS_ERR(reg)))
    2179                                 continue;
    2180 
    2181                         reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
    2182                         reg[CTX_RING_HEAD+1] = 0;
    2183                         reg[CTX_RING_TAIL+1] = 0;
    2184 
    2185                         ce->state->obj->dirty = true;
    2186                         i915_gem_object_unpin_map(ce->state->obj);
    2187 
    2188                         ce->ring->head = ce->ring->tail = 0;
    2189                         ce->ring->last_retired_head = -1;
    2190                         intel_ring_update_space(ce->ring);
    2191                 }
    2192         }
    2193 }
     2157
     2158        for_each_engine(engine, dev_priv) {
     2159                struct intel_context *ce = &ctx->engine[engine->id];
     2160                void *vaddr;
     2161                uint32_t *reg_state;
     2162
     2163                if (!ce->state)
     2164                        continue;
     2165
     2166                vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
     2167                if (WARN_ON(IS_ERR(vaddr)))
     2168                        continue;
     2169
     2170                reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
     2171
     2172                reg_state[CTX_RING_HEAD+1] = 0;
     2173                reg_state[CTX_RING_TAIL+1] = 0;
     2174
     2175                ce->state->obj->dirty = true;
     2176                i915_gem_object_unpin_map(ce->state->obj);
     2177
     2178                ce->ring->head = 0;
     2179                ce->ring->tail = 0;
     2180        }
     2181}
Note: See TracChangeset for help on using the changeset viewer.