adm5120sw.c

Revision 12415, 31.4 kB (checked in by BrainSlayer, 5 months ago)
latest adm5120 update incl. remap patch

Line
1	/*
2	* ADM5120 built-in ethernet switch driver
3	*
4	* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
5	*
6	* This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
7	* Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
8	* NAPI extension for the Jeroen's driver
9	* Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
10	* Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
11	* Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
12	* Copyright ADMtek Inc.
13	*
14	* This program is free software; you can redistribute it and/or modify it
15	* under the terms of the GNU General Public License version 2 as published
16	* by the Free Software Foundation.
17	*
18	*/
19
20	#include <linux/kernel.h>
21	#include <linux/module.h>
22	#include <linux/errno.h>
23	#include <linux/interrupt.h>
24	#include <linux/ioport.h>
25	#include <linux/spinlock.h>
26	#include <linux/platform_device.h>
27
28	#include <linux/netdevice.h>
29	#include <linux/etherdevice.h>
30	#include <linux/skbuff.h>
31
32	#include <linux/io.h>
33	#include <linux/irq.h>
34
35	#include <asm/mipsregs.h>
36
37	#include <adm5120_info.h>
38	#include <adm5120_defs.h>
39	#include <adm5120_irq.h>
40	#include <adm5120_switch.h>
41
42	#include "adm5120sw.h"
43
44	#define DRV_NAME "adm5120-switch"
45	#define DRV_DESC "ADM5120 built-in ethernet switch driver"
46	#define DRV_VERSION "0.1.0"
47
48	#define CONFIG_ADM5120_SWITCH_NAPI 1
49	#undef CONFIG_ADM5120_SWITCH_DEBUG
50
51	/* ------------------------------------------------------------------------ */
52
53	#ifdef CONFIG_ADM5120_SWITCH_DEBUG
54	#define SW_DBG(f, a...) printk(KERN_DBG "%s: " f, DRV_NAME , ## a)
55	#else
56	#define SW_DBG(f, a...) do {} while (0)
57	#endif
58	#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
59	#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
60
61	#define SWITCH_NUM_PORTS 6
62	#define ETH_CSUM_LEN 4
63
64	#define RX_MAX_PKTLEN 1550
65	#define RX_RING_SIZE 64
66
67	#define TX_RING_SIZE 32
68	#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
69	#define TX_TIMEOUT HZ*400
70
71	#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
72	#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
73	#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
74	#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
75
76	#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
77	#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
78
79	#define SWITCH_INTS_HIGH (SWITCH_INT_SHD \| SWITCH_INT_RHD \| SWITCH_INT_HDF)
80	#define SWITCH_INTS_LOW (SWITCH_INT_SLD \| SWITCH_INT_RLD \| SWITCH_INT_LDF)
81	#define SWITCH_INTS_ERR (SWITCH_INT_RDE \| SWITCH_INT_SDE \| SWITCH_INT_CPUH)
82	#define SWITCH_INTS_Q (SWITCH_INT_P0QF \| SWITCH_INT_P1QF \| SWITCH_INT_P2QF \| \
83	SWITCH_INT_P3QF \| SWITCH_INT_P4QF \| SWITCH_INT_P5QF \| \
84	SWITCH_INT_CPQF \| SWITCH_INT_GQF)
85
86	#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH \| SWITCH_INTS_LOW \| \
87	SWITCH_INTS_ERR \| SWITCH_INTS_Q \| \
88	SWITCH_INT_MD \| SWITCH_INT_PSC)
89
90	#define SWITCH_INTS_USED (SWITCH_INTS_LOW \| SWITCH_INT_PSC)
91	#define SWITCH_INTS_POLL (SWITCH_INT_RLD \| SWITCH_INT_LDF \| SWITCH_INT_SLD)
92
93	/* ------------------------------------------------------------------------ */
94
95	struct adm5120_if_priv {
96	struct net_device *dev;
97	unsigned int vlan_no;
98	unsigned int port_mask;
99	#ifdef CONFIG_ADM5120_SWITCH_NAPI
100	struct napi_struct napi;
101	#endif
102	};
103
104	struct dma_desc {
105	__u32 buf1;
106	#define DESC_OWN (1UL << 31) /* Owned by the switch */
107	#define DESC_EOR (1UL << 28) /* End of Ring */
108	#define DESC_ADDR_MASK 0x1FFFFFF
109	#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
110	__u32 buf2;
111	#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
112	__u32 buflen;
113	__u32 misc;
114	/* definitions for tx/rx descriptors */
115	#define DESC_PKTLEN_SHIFT 16
116	#define DESC_PKTLEN_MASK 0x7FF
117	/* tx descriptor specific part */
118	#define DESC_CSUM (1UL << 31) /* Append checksum */
119	#define DESC_DSTPORT_SHIFT 8
120	#define DESC_DSTPORT_MASK 0x3F
121	#define DESC_VLAN_MASK 0x3F
122	/* rx descriptor specific part */
123	#define DESC_SRCPORT_SHIFT 12
124	#define DESC_SRCPORT_MASK 0x7
125	#define DESC_DA_MASK 0x3
126	#define DESC_DA_SHIFT 4
127	#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
128	#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
129	#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
130	#define DESC_TYPE_IP 0x0 /* IP packet */
131	#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
132	} __attribute__ ((aligned(16)));
133
134	/* ------------------------------------------------------------------------ */
135
136	static int adm5120_nrdevs;
137
138	static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
139	/* Lookup table port -> device */
140	static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
141
142	static struct dma_desc *txl_descs;
143	static struct dma_desc *rxl_descs;
144
145	static dma_addr_t txl_descs_dma;
146	static dma_addr_t rxl_descs_dma;
147
148	static struct sk_buff **txl_skbuff;
149	static struct sk_buff **rxl_skbuff;
150
151	static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
152	static unsigned int cur_txl, dirty_txl;
153
154	static unsigned int sw_used;
155
156	static spinlock_t tx_lock = SPIN_LOCK_UNLOCKED;
157
158	/* ------------------------------------------------------------------------ */
159
160	static inline u32 sw_read_reg(u32 reg)
161	{
162	return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
163	}
164
165	static inline void sw_write_reg(u32 reg, u32 val)
166	{
167	__raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
168	}
169
170	static inline void sw_int_mask(u32 mask)
171	{
172	u32 t;
173
174	t = sw_read_reg(SWITCH_REG_INT_MASK);
175	t \|= mask;
176	sw_write_reg(SWITCH_REG_INT_MASK, t);
177	}
178
179	static inline void sw_int_unmask(u32 mask)
180	{
181	u32 t;
182
183	t = sw_read_reg(SWITCH_REG_INT_MASK);
184	t &= ~mask;
185	sw_write_reg(SWITCH_REG_INT_MASK, t);
186	}
187
188	static inline void sw_int_ack(u32 mask)
189	{
190	sw_write_reg(SWITCH_REG_INT_STATUS, mask);
191	}
192
193	static inline u32 sw_int_status(void)
194	{
195	u32 t;
196
197	t = sw_read_reg(SWITCH_REG_INT_STATUS);
198	t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
199	return t;
200	}
201
202	static inline u32 desc_get_srcport(struct dma_desc *desc)
203	{
204	return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
205	}
206
207	static inline u32 desc_get_pktlen(struct dma_desc *desc)
208	{
209	return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
210	}
211
212	static inline int desc_ipcsum_fail(struct dma_desc *desc)
213	{
214	return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
215	}
216
217	/* ------------------------------------------------------------------------ */
218
219	static void sw_dump_desc(char label, struct dma_desc desc, int tx)
220	{
221	u32 t;
222
223	SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
224
225	t = desc->buf1;
226	SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
227	t & DESC_ADDR_MASK,
228	desc->buflen,
229	(t & DESC_OWN) ? "SWITCH" : "CPU",
230	(t & DESC_EOR) ? " RE" : "");
231
232	t = desc->buf2;
233	SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
234	t & DESC_ADDR_MASK,
235	(t & DESC_BUF2_EN) ? " EN" : "" );
236
237	t = desc->misc;
238	if (tx)
239	SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
240	(t & DESC_CSUM) ? " CSUM" : "",
241	(t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
242	(t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
243	t & DESC_VLAN_MASK);
244	else
245	SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
246	t,
247	(t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
248	(t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
249	(t >> DESC_DA_SHIFT) & DESC_DA_MASK,
250	(t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
251	(t & DESC_VLAN_TAG) ? " VLAN" : "",
252	(t & DESC_TYPE_MASK));
253	}
254
255	static void sw_dump_intr_mask(char *label, u32 mask)
256	{
257	SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
258	label, mask,
259	(mask & SWITCH_INT_SHD) ? " SHD" : "",
260	(mask & SWITCH_INT_SLD) ? " SLD" : "",
261	(mask & SWITCH_INT_RHD) ? " RHD" : "",
262	(mask & SWITCH_INT_RLD) ? " RLD" : "",
263	(mask & SWITCH_INT_HDF) ? " HDF" : "",
264	(mask & SWITCH_INT_LDF) ? " LDF" : "",
265	(mask & SWITCH_INT_P0QF) ? " P0QF" : "",
266	(mask & SWITCH_INT_P1QF) ? " P1QF" : "",
267	(mask & SWITCH_INT_P2QF) ? " P2QF" : "",
268	(mask & SWITCH_INT_P3QF) ? " P3QF" : "",
269	(mask & SWITCH_INT_P4QF) ? " P4QF" : "",
270	(mask & SWITCH_INT_CPQF) ? " CPQF" : "",
271	(mask & SWITCH_INT_GQF) ? " GQF" : "",
272	(mask & SWITCH_INT_MD) ? " MD" : "",
273	(mask & SWITCH_INT_BCS) ? " BCS" : "",
274	(mask & SWITCH_INT_PSC) ? " PSC" : "",
275	(mask & SWITCH_INT_ID) ? " ID" : "",
276	(mask & SWITCH_INT_W0TE) ? " W0TE" : "",
277	(mask & SWITCH_INT_W1TE) ? " W1TE" : "",
278	(mask & SWITCH_INT_RDE) ? " RDE" : "",
279	(mask & SWITCH_INT_SDE) ? " SDE" : "",
280	(mask & SWITCH_INT_CPUH) ? " CPUH" : "");
281	}
282
283	static void sw_dump_regs(void)
284	{
285	u32 t;
286
287	t = SW_READ_REG(PHY_STATUS);
288	SW_DBG("phy_status: %08X\n", t);
289
290	t = SW_READ_REG(CPUP_CONF);
291	SW_DBG("cpup_conf: %08X%s%s%s\n", t,
292	(t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
293	(t & CPUP_CONF_CRCP) ? " CRCP" : "",
294	(t & CPUP_CONF_BTM) ? " BTM" : "");
295
296	t = SW_READ_REG(PORT_CONF0);
297	SW_DBG("port_conf0: %08X\n", t);
298	t = SW_READ_REG(PORT_CONF1);
299	SW_DBG("port_conf1: %08X\n", t);
300	t = SW_READ_REG(PORT_CONF2);
301	SW_DBG("port_conf2: %08X\n", t);
302
303	t = SW_READ_REG(VLAN_G1);
304	SW_DBG("vlan g1: %08X\n", t);
305	t = SW_READ_REG(VLAN_G2);
306	SW_DBG("vlan g2: %08X\n", t);
307
308	t = SW_READ_REG(BW_CNTL0);
309	SW_DBG("bw_cntl0: %08X\n", t);
310	t = SW_READ_REG(BW_CNTL1);
311	SW_DBG("bw_cntl1: %08X\n", t);
312
313	t = SW_READ_REG(PHY_CNTL0);
314	SW_DBG("phy_cntl0: %08X\n", t);
315	t = SW_READ_REG(PHY_CNTL1);
316	SW_DBG("phy_cntl1: %08X\n", t);
317	t = SW_READ_REG(PHY_CNTL2);
318	SW_DBG("phy_cntl2: %08X\n", t);
319	t = SW_READ_REG(PHY_CNTL3);
320	SW_DBG("phy_cntl3: %08X\n", t);
321	t = SW_READ_REG(PHY_CNTL4);
322	SW_DBG("phy_cntl4: %08X\n", t);
323
324	t = SW_READ_REG(INT_STATUS);
325	sw_dump_intr_mask("int_status: ", t);
326
327	t = SW_READ_REG(INT_MASK);
328	sw_dump_intr_mask("int_mask: ", t);
329
330	t = SW_READ_REG(SHDA);
331	SW_DBG("shda: %08X\n", t);
332	t = SW_READ_REG(SLDA);
333	SW_DBG("slda: %08X\n", t);
334	t = SW_READ_REG(RHDA);
335	SW_DBG("rhda: %08X\n", t);
336	t = SW_READ_REG(RLDA);
337	SW_DBG("rlda: %08X\n", t);
338	}
339
340
341	/* ------------------------------------------------------------------------ */
342
343	static inline void adm5120_rx_dma_update(struct dma_desc *desc,
344	struct sk_buff *skb, int end)
345	{
346	desc->misc = 0;
347	desc->buf2 = 0;
348	desc->buflen = RX_MAX_PKTLEN;
349	desc->buf1 = DESC_ADDR(skb->data) \|
350	DESC_OWN \| (end ? DESC_EOR : 0);
351	}
352
353	static void adm5120_switch_rx_refill(void)
354	{
355	unsigned int entry;
356
357	for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
358	struct dma_desc *desc;
359	struct sk_buff *skb;
360
361	entry = dirty_rxl % RX_RING_SIZE;
362	desc = &rxl_descs[entry];
363
364	skb = rxl_skbuff[entry];
365	if (skb == NULL) {
366	skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
367	if (skb) {
368	skb_reserve(skb, SKB_RESERVE_LEN);
369	rxl_skbuff[entry] = skb;
370	} else {
371	SW_ERR("no memory for skb\n");
372	desc->buflen = 0;
373	desc->buf2 = 0;
374	desc->misc = 0;
375	desc->buf1 = (desc->buf1 & DESC_EOR) \| DESC_OWN;
376	break;
377	}
378	}
379
380	desc->buf2 = 0;
381	desc->buflen = RX_MAX_PKTLEN;
382	desc->misc = 0;
383	desc->buf1 = (desc->buf1 & DESC_EOR) \| DESC_OWN \|
384	DESC_ADDR(skb->data);
385	}
386	}
387
388	static int adm5120_switch_rx(int limit)
389	{
390	unsigned int done = 0;
391
392	SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
393	limit, cur_rxl, dirty_rxl);
394
395	while (done < limit) {
396	int entry = cur_rxl % RX_RING_SIZE;
397	struct dma_desc *desc = &rxl_descs[entry];
398	struct net_device *rdev;
399	unsigned int port;
400
401	if (desc->buf1 & DESC_OWN)
402	break;
403
404	if (dirty_rxl + RX_RING_SIZE == cur_rxl)
405	break;
406
407	port = desc_get_srcport(desc);
408	rdev = adm5120_port[port];
409
410	SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
411	rxl_skbuff[entry]);
412
413	if ((rdev) && netif_running(rdev)) {
414	struct sk_buff *skb = rxl_skbuff[entry];
415	int pktlen;
416
417	pktlen = desc_get_pktlen(desc);
418	pktlen -= ETH_CSUM_LEN;
419
420	if ((pktlen == 0) \|\| desc_ipcsum_fail(desc)) {
421	rdev->stats.rx_errors++;
422	if (pktlen == 0)
423	rdev->stats.rx_length_errors++;
424	if (desc_ipcsum_fail(desc))
425	rdev->stats.rx_crc_errors++;
426	SW_DBG("rx error, recycling skb %u\n", entry);
427	} else {
428	skb_put(skb, pktlen);
429
430	skb->dev = rdev;
431	skb->protocol = eth_type_trans(skb, rdev);
432	skb->ip_summed = CHECKSUM_UNNECESSARY;
433
434	dma_cache_wback_inv((unsigned long)skb->data,
435	skb->len);
436
437	#ifdef CONFIG_ADM5120_SWITCH_NAPI
438	netif_receive_skb(skb);
439	#else
440	netif_rx(skb);
441	#endif
442
443	rdev->last_rx = jiffies;
444	rdev->stats.rx_packets++;
445	rdev->stats.rx_bytes += pktlen;
446
447	rxl_skbuff[entry] = NULL;
448	done++;
449	}
450	} else {
451	SW_DBG("no rx device, recycling skb %u\n", entry);
452	}
453
454	cur_rxl++;
455	if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
456	adm5120_switch_rx_refill();
457	}
458
459	adm5120_switch_rx_refill();
460
461	SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
462	cur_rxl, dirty_rxl, done);
463
464	return done;
465	}
466
467	static void adm5120_switch_tx(void)
468	{
469	unsigned int entry;
470
471	spin_lock(&tx_lock);
472	entry = dirty_txl % TX_RING_SIZE;
473	while (dirty_txl != cur_txl) {
474	struct dma_desc *desc = &txl_descs[entry];
475	struct sk_buff *skb = txl_skbuff[entry];
476
477	if (desc->buf1 & DESC_OWN)
478	break;
479
480	if (netif_running(skb->dev)) {
481	skb->dev->stats.tx_bytes += skb->len;
482	skb->dev->stats.tx_packets++;
483	}
484
485	dev_kfree_skb_irq(skb);
486	txl_skbuff[entry] = NULL;
487	entry = (++dirty_txl) % TX_RING_SIZE;
488	}
489
490	if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
491	int i;
492	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
493	if (!adm5120_devs[i])
494	continue;
495	netif_wake_queue(adm5120_devs[i]);
496	}
497	}
498	spin_unlock(&tx_lock);
499	}
500
501	#ifdef CONFIG_ADM5120_SWITCH_NAPI
502	static int adm5120_if_poll(struct napi_struct *napi, int limit)
503	{
504	struct adm5120_if_priv *priv = container_of(napi,
505	struct adm5120_if_priv, napi);
506	struct net_device *dev = priv->dev;
507	int done;
508	u32 status;
509
510	sw_int_ack(SWITCH_INTS_POLL);
511
512	SW_DBG("%s: processing TX ring\n", dev->name);
513	adm5120_switch_tx();
514
515	SW_DBG("%s: processing RX ring\n", dev->name);
516	done = adm5120_switch_rx(limit);
517
518	status = sw_int_status() & SWITCH_INTS_POLL;
519	if ((done < limit) && (!status)) {
520	SW_DBG("disable polling mode for %s\n", dev->name);
521	netif_rx_complete(dev, napi);
522	sw_int_unmask(SWITCH_INTS_POLL);
523	return 0;
524	}
525
526	SW_DBG("%s still in polling mode, done=%d, status=%x\n",
527	dev->name, done, status);
528	return 1;
529	}
530	#endif /* CONFIG_ADM5120_SWITCH_USE_NAPI */
531
532
533	static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
534	{
535	u32 status;
536
537	status = sw_int_status();
538	status &= SWITCH_INTS_ALL;
539	if (!status)
540	return IRQ_NONE;
541
542	#ifdef CONFIG_ADM5120_SWITCH_NAPI
543	sw_int_ack(status & ~SWITCH_INTS_POLL);
544
545	if (status & SWITCH_INTS_POLL) {
546	struct net_device *dev = dev_id;
547	struct adm5120_if_priv *priv = netdev_priv(dev);
548	sw_dump_intr_mask("poll ints", status);
549	SW_DBG("enable polling mode for %s\n", dev->name);
550	sw_int_mask(SWITCH_INTS_POLL);
551	netif_rx_schedule(dev, &priv->napi);
552	}
553	#else
554	sw_int_ack(status);
555
556	if (status & (SWITCH_INT_RLD \| SWITCH_INT_LDF)) {
557	adm5120_switch_rx(RX_RING_SIZE);
558	}
559
560	if (status & SWITCH_INT_SLD) {
561	adm5120_switch_tx();
562	}
563	#endif
564
565	return IRQ_HANDLED;
566	}
567
568	static void adm5120_set_bw(char *matrix)
569	{
570	unsigned long val;
571
572	/* Port 0 to 3 are set using the bandwidth control 0 register */
573	val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
574	sw_write_reg(SWITCH_REG_BW_CNTL0, val);
575
576	/* Port 4 and 5 are set using the bandwidth control 1 register */
577	val = matrix[4];
578	if (matrix[5] == 1)
579	sw_write_reg(SWITCH_REG_BW_CNTL1, val \| 0x80000000);
580	else
581	sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
582
583	SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
584	sw_read_reg(SWITCH_REG_BW_CNTL1));
585	}
586
587	static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
588	struct sk_buff **skbl, int num)
589	{
590	memset(desc, 0, num * sizeof(*desc));
591	desc[num-1].buf1 \|= DESC_EOR;
592	memset(skbl, 0, sizeof(struct skb)num);
593
594	cur_txl = 0;
595	dirty_txl = 0;
596	}
597
598	static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
599	struct sk_buff **skbl, int num)
600	{
601	int i;
602
603	memset(desc, 0, num * sizeof(*desc));
604	for (i = 0; i < num; i++) {
605	skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
606	if (!skbl[i]) {
607	i = num;
608	break;
609	}
610	skb_reserve(skbl[i], SKB_RESERVE_LEN);
611	adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
612	}
613
614	cur_rxl = 0;
615	dirty_rxl = 0;
616	}
617
618	static int adm5120_switch_tx_ring_alloc(void)
619	{
620	int err;
621
622	txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
623	GFP_ATOMIC);
624	if (!txl_descs) {
625	err = -ENOMEM;
626	goto err;
627	}
628
629	txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
630	if (!txl_skbuff) {
631	err = -ENOMEM;
632	goto err;
633	}
634
635	return 0;
636
637	err:
638	return err;
639	}
640
641	static void adm5120_switch_tx_ring_free(void)
642	{
643	int i;
644
645	if (txl_skbuff) {
646	for (i = 0; i < TX_RING_SIZE; i++)
647	if (txl_skbuff[i])
648	kfree_skb(txl_skbuff[i]);
649	kfree(txl_skbuff);
650	}
651
652	if (txl_descs)
653	dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
654	txl_descs_dma);
655	}
656
657	static int adm5120_switch_rx_ring_alloc(void)
658	{
659	int err;
660	int i;
661
662	/* init RX ring */
663	rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
664	GFP_ATOMIC);
665	if (!rxl_descs) {
666	err = -ENOMEM;
667	goto err;
668	}
669
670	rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
671	if (!rxl_skbuff) {
672	err = -ENOMEM;
673	goto err;
674	}
675
676	for (i = 0; i < RX_RING_SIZE; i++) {
677	struct sk_buff *skb;
678	skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
679	if (!skb) {
680	err = -ENOMEM;
681	goto err;
682	}
683	rxl_skbuff[i] = skb;
684	skb_reserve(skb, SKB_RESERVE_LEN);
685	}
686
687	return 0;
688
689	err:
690	return err;
691	}
692
693	static void adm5120_switch_rx_ring_free(void)
694	{
695	int i;
696
697	if (rxl_skbuff) {
698	for (i = 0; i < RX_RING_SIZE; i++)
699	if (rxl_skbuff[i])
700	kfree_skb(rxl_skbuff[i]);
701	kfree(rxl_skbuff);
702	}
703
704	if (rxl_descs)
705	dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
706	rxl_descs_dma);
707	}
708
709	static void adm5120_write_mac(struct net_device *dev)
710	{
711	struct adm5120_if_priv *priv = netdev_priv(dev);
712	unsigned char *mac = dev->dev_addr;
713	u32 t;
714
715	t = mac[2] \| (mac[3] << MAC_WT1_MAC3_SHIFT) \|
716	(mac[4] << MAC_WT1_MAC4_SHIFT) \| (mac[5] << MAC_WT1_MAC5_SHIFT);
717	sw_write_reg(SWITCH_REG_MAC_WT1, t);
718
719	t = (mac[0] << MAC_WT0_MAC0_SHIFT) \| (mac[1] << MAC_WT0_MAC1_SHIFT) \|
720	MAC_WT0_MAWC \| MAC_WT0_WVE \| (priv->vlan_no<<3);
721
722	sw_write_reg(SWITCH_REG_MAC_WT0, t);
723
724	while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
725	}
726
727	static void adm5120_set_vlan(char *matrix)
728	{
729	unsigned long val;
730	int vlan_port, port;
731
732	val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
733	sw_write_reg(SWITCH_REG_VLAN_G1, val);
734	val = matrix[4] + (matrix[5]<<8);
735	sw_write_reg(SWITCH_REG_VLAN_G2, val);
736
737	/* Now set/update the port vs. device lookup table */
738	for (port=0; port<SWITCH_NUM_PORTS; port++) {
739	for (vlan_port=0; vlan_port<SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
740	if (vlan_port <SWITCH_NUM_PORTS)
741	adm5120_port[port] = adm5120_devs[vlan_port];
742	else
743	adm5120_port[port] = NULL;
744	}
745	}
746
747	static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
748	{
749	u32 t;
750
751	t = mac[2] \| (mac[3] << MAC_WT1_MAC3_SHIFT)
752	\| (mac[4] << MAC_WT1_MAC4_SHIFT)
753	\| (mac[5] << MAC_WT1_MAC5_SHIFT);
754	sw_write_reg(SWITCH_REG_MAC_WT1, t);
755
756	t = (mac[0] << MAC_WT0_MAC0_SHIFT) \| (mac[1] << MAC_WT0_MAC1_SHIFT) \|
757	MAC_WT0_MAWC \| MAC_WT0_WVE \| (vlan << MAC_WT0_WVN_SHIFT) \|
758	(MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
759	sw_write_reg(SWITCH_REG_MAC_WT0, t);
760
761	do {
762	t = sw_read_reg(SWITCH_REG_MAC_WT0);
763	} while ((t & MAC_WT0_MWD) == 0);
764	}
765
766	static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
767	{
768	unsigned int reg;
769	u32 t;
770
771	if (vlan < 4)
772	reg = SWITCH_REG_VLAN_G1;
773	else {
774	vlan -= 4;
775	reg = SWITCH_REG_VLAN_G2;
776	}
777
778	t = sw_read_reg(reg);
779	t &= ~(0xFF << (vlan*8));
780	t \|= (ports << (vlan*8));
781	sw_write_reg(reg, t);
782	}
783
784	#ifdef CONFIG_ADM5120_SWITCH_NAPI
785	static inline void adm5120_if_napi_enable(struct net_device *dev)
786	{
787	struct adm5120_if_priv *priv = netdev_priv(dev);
788	napi_enable(&priv->napi);
789	}
790
791	static inline void adm5120_if_napi_disable(struct net_device *dev)
792	{
793	struct adm5120_if_priv *priv = netdev_priv(dev);
794	napi_disable(&priv->napi);
795	}
796	#else
797	static inline void adm5120_if_napi_enable(struct net_device *dev) {}
798	static inline void adm5120_if_napi_disable(struct net_device *dev) {}
799	#endif /* CONFIG_ADM5120_SWITCH_NAPI */
800	static void adm5120_if_set_multicast_list(struct net_device *dev);
801
802	/* ------------------------------------------------------------------------ */
803	#define SW_DIS_SA_LEARN_MASK 0x0000003F
804
805	static int adm5120_if_open(struct net_device *dev)
806	{
807	u32 t;
808	int err;
809	int i;
810
811	adm5120_if_napi_enable(dev);
812
813	err = request_irq(dev->irq, adm5120_switch_irq,
814	(IRQF_SHARED \| IRQF_DISABLED), dev->name, dev);
815	if (err) {
816	SW_ERR("unable to get irq for %s\n", dev->name);
817	goto err;
818	}
819
820	if (!sw_used++)
821	/* enable interrupts on first open */
822	sw_int_unmask(SWITCH_INTS_USED);
823
824
825	/* enable (additional) port */
826	t = sw_read_reg(SWITCH_REG_PORT_CONF0);
827	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
828	if (dev == adm5120_devs[i])
829	t &= ~adm5120_eth_vlans[i];
830	}
831	sw_write_reg(SWITCH_REG_PORT_CONF0, t);
832
833
834	//wp54g patch
835	sw_write_reg(SWITCH_REG_PORT_CONF1, sw_read_reg(SWITCH_REG_PORT_CONF1) \| SW_DIS_SA_LEARN_MASK);
836	adm5120_if_set_multicast_list(dev);
837	adm5120_write_mac(dev);
838	/*
839	//important: promisc mode
840	#define SW_DIS_UN_SHIFT 9
841	#define SW_DIS_UN_MASK (0x3F << SW_DIS_UN_SHIFT)
842	#define SW_DIS_MC_SHIFT 16
843	#define SW_DIS_MC_MASK (0x3F << SW_DIS_MC_SHIFT)
844	#define SW_DIS_BC_SHIFT 24
845	#define SW_DIS_BC_MASK (0x3F << SW_DIS_BC_SHIFT)
846
847	if (dev->flags & IFF_PROMISC) {
848	printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
849	dev->name);
850	sw_write_reg(SWITCH_REG_CPUP_CONF, sw_read_reg(SWITCH_REG_CPUP_CONF) & ~(SW_DIS_BC_MASK \| SW_DIS_MC_MASK \| SW_DIS_UN_MASK));
851	} else if (dev->mc_count \|\| (dev->flags & IFF_ALLMULTI)) {
852	sw_write_reg(SWITCH_REG_CPUP_CONF, sw_read_reg(SWITCH_REG_CPUP_CONF) & ~(SW_DIS_BC_MASK \| SW_DIS_MC_MASK \| SW_DIS_UN_MASK));
853	} else {
854	sw_write_reg(SWITCH_REG_CPUP_CONF, (sw_read_reg(SWITCH_REG_CPUP_CONF) & ~(SW_DIS_BC_MASK \| SW_DIS_UN_MASK)) \| SW_DIS_MC_MASK);
855	}
856
857	// Sets the switch bridge mode
858	sw_write_reg(SWITCH_REG_CPUP_CONF, sw_read_reg(SWITCH_REG_CPUP_CONF) \| CPUP_CONF_BTM);
859	*/
860	netif_start_queue(dev);
861
862	return 0;
863
864	err:
865	adm5120_if_napi_disable(dev);
866	return err;
867	}
868
869	static int adm5120_if_stop(struct net_device *dev)
870	{
871	u32 t;
872	int i;
873
874	netif_stop_queue(dev);
875	adm5120_if_napi_disable(dev);
876
877	/* disable port if not assigned to other devices */
878	t = sw_read_reg(SWITCH_REG_PORT_CONF0);
879	t \|= SWITCH_PORTS_NOCPU;
880	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
881	if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
882	t &= ~adm5120_eth_vlans[i];
883	}
884	sw_write_reg(SWITCH_REG_PORT_CONF0, t);
885
886	if (!--sw_used)
887	sw_int_mask(SWITCH_INTS_USED);
888
889	free_irq(dev->irq, dev);
890
891	return 0;
892	}
893
894	static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
895	struct net_device *dev)
896	{
897	struct dma_desc *desc;
898	struct adm5120_if_priv *priv = netdev_priv(dev);
899	unsigned int entry;
900	unsigned long data;
901	int i;
902
903	/* lock switch irq */
904	spin_lock_irq(&tx_lock);
905
906	/* calculate the next TX descriptor entry. */
907	entry = cur_txl % TX_RING_SIZE;
908
909	desc = &txl_descs[entry];
910	if (desc->buf1 & DESC_OWN) {
911	/* We want to write a packet but the TX queue is still
912	* occupied by the DMA. We are faster than the DMA... */
913	SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
914	dev_kfree_skb(skb);
915	dev->stats.tx_dropped++;
916	return 0;
917	}
918
919	txl_skbuff[entry] = skb;
920	data = (desc->buf1 & DESC_EOR);
921	data \|= DESC_ADDR(skb->data);
922
923	desc->misc =
924	((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) \|
925	(0x1 << priv->vlan_no);
926
927	desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
928
929	desc->buf1 = data \| DESC_OWN;
930	sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
931
932	cur_txl++;
933	if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
934	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
935	if (!adm5120_devs[i])
936	continue;
937	netif_stop_queue(adm5120_devs[i]);
938	}
939	}
940
941	dev->trans_start = jiffies;
942
943	spin_unlock_irq(&tx_lock);
944
945	return 0;
946	}
947
948	static void adm5120_if_tx_timeout(struct net_device *dev)
949	{
950	SW_INFO("TX timeout on %s\n",dev->name);
951	}
952
953	static void adm5120_if_set_multicast_list(struct net_device *dev)
954	{
955	struct adm5120_if_priv *priv = netdev_priv(dev);
956	u32 ports;
957	u32 t;
958
959	ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
960
961	t = sw_read_reg(SWITCH_REG_CPUP_CONF);
962	if (dev->flags & IFF_PROMISC)
963	/* enable unknown packets */
964	t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
965	else
966	/* disable unknown packets */
967	t \|= (ports << CPUP_CONF_DUNP_SHIFT);
968
969	if (dev->flags & IFF_PROMISC \|\| dev->flags & IFF_ALLMULTI \|\|
970	dev->mc_count)
971	/* enable multicast packets */
972	t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
973	else
974	/* disable multicast packets */
975	t \|= (ports << CPUP_CONF_DMCP_SHIFT);
976
977	/* If there is any port configured to be in promiscuous mode, then the */
978	/* Bridge Test Mode has to be activated. This will result in */
979	/* transporting also packets learned in another VLAN to be forwarded */
980	/* to the CPU. */
981	/* The difficult scenario is when we want to build a bridge on the CPU.*/
982	/* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
983	/* CPU port in VLAN1. Now we build a bridge on the CPU between */
984	/* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
985	/* Now assume a packet with ethernet source address 99 enters port 0 */
986	/* It will be forwarded to the CPU because it is unknown. Then the */
987	/* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
988	/* When now a packet with ethernet destination address 99 comes in at */
989	/* port 1 in VLAN1, then the switch has learned that this address is */
990	/* located at port 0 in VLAN0. Therefore the switch will drop */
991	/* this packet. In order to avoid this and to send the packet still */
992	/* to the CPU, the Bridge Test Mode has to be activated. */
993
994	/* Check if there is any vlan in promisc mode. */
995	if (t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
996	t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
997	else
998	t \|= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
999
1000	sw_write_reg(SWITCH_REG_CPUP_CONF, t);
1001
1002	}
1003
1004	static int adm5120_if_set_mac_address(struct net_device dev, void p)
1005	{
1006	struct sockaddr *addr = p;
1007
1008	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1009	adm5120_write_mac(dev);
1010	return 0;
1011	}
1012
1013	static int adm5120_if_do_ioctl(struct net_device dev, struct ifreq rq,
1014	int cmd)
1015	{
1016	int err;
1017	struct adm5120_sw_info info;
1018	struct adm5120_if_priv *priv = netdev_priv(dev);
1019
1020	switch(cmd) {
1021	case SIOCGADMINFO:
1022	info.magic = 0x5120;
1023	info.ports = adm5120_nrdevs;
1024	info.vlan = priv->vlan_no;
1025	err = copy_to_user(rq->ifr_data, &info, sizeof(info));
1026	if (err)
1027	return -EFAULT;
1028	break;
1029	case SIOCSMATRIX:
1030	if (!capable(CAP_NET_ADMIN))
1031	return -EPERM;
1032	err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
1033	sizeof(adm5120_eth_vlans));
1034	if (err)
1035	return -EFAULT;
1036	adm5120_set_vlan(adm5120_eth_vlans);
1037	break;
1038	case SIOCGMATRIX:
1039	err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
1040	sizeof(adm5120_eth_vlans));
1041	if (err)
1042	return -EFAULT;
1043	break;
1044	default:
1045	return -EOPNOTSUPP;
1046	}
1047	return 0;
1048	}
1049
1050	static struct net_device *adm5120_if_alloc(void)
1051	{
1052	struct net_device *dev;
1053	struct adm5120_if_priv *priv;
1054
1055	dev = alloc_etherdev(sizeof(*priv));
1056	if (!dev)
1057	return NULL;
1058
1059	priv = netdev_priv(dev);
1060	priv->dev = dev;
1061
1062	dev->irq = ADM5120_IRQ_SWITCH;
1063	dev->open = adm5120_if_open;
1064	dev->hard_start_xmit = adm5120_if_hard_start_xmit;
1065	dev->stop = adm5120_if_stop;
1066	dev->set_multicast_list = adm5120_if_set_multicast_list;
1067	dev->do_ioctl = adm5120_if_do_ioctl;
1068	dev->tx_timeout = adm5120_if_tx_timeout;
1069	dev->watchdog_timeo = TX_TIMEOUT;
1070	dev->set_mac_address = adm5120_if_set_mac_address;
1071	#ifdef CONFIG_ADM5120_SWITCH_NAPI
1072	netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64);
1073	#endif
1074
1075	SET_MODULE_OWNER(dev);
1076
1077	return dev;
1078	}
1079
1080	/* ------------------------------------------------------------------------ */
1081
1082	static void adm5120_switch_cleanup(void)
1083	{
1084	int i;
1085
1086	/* disable interrupts */
1087	sw_int_mask(SWITCH_INTS_ALL);
1088
1089	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
1090	struct net_device *dev = adm5120_devs[i];
1091	if (dev) {
1092	unregister_netdev(dev);
1093	free_netdev(dev);
1094	}
1095	}
1096
1097	adm5120_switch_tx_ring_free();
1098	adm5120_switch_rx_ring_free();
1099	}
1100
1101	static int __init adm5120_switch_probe(struct platform_device *pdev)
1102	{
1103	u32 t;
1104	int i, err;
1105
1106	adm5120_nrdevs = adm5120_eth_num_ports;
1107	sw_write_reg(SWITCH_REG_PORT0_LED,(LED_MODE_LINK_ACT << LED0_MODE_SHIFT) \| (LED_MODE_SPEED << LED1_MODE_SHIFT) \| (LED_MODE_LINK << LED2_MODE_SHIFT));
1108	sw_write_reg(SWITCH_REG_PORT1_LED,(LED_MODE_LINK_ACT << LED0_MODE_SHIFT) \| (LED_MODE_SPEED << LED1_MODE_SHIFT) \| (LED_MODE_LINK << LED2_MODE_SHIFT));
1109	sw_write_reg(SWITCH_REG_PORT2_LED,(LED_MODE_LINK_ACT << LED0_MODE_SHIFT) \| (LED_MODE_SPEED << LED1_MODE_SHIFT) \| (LED_MODE_LINK << LED2_MODE_SHIFT));
1110	sw_write_reg(SWITCH_REG_PORT3_LED,(LED_MODE_LINK_ACT << LED0_MODE_SHIFT) \| (LED_MODE_SPEED << LED1_MODE_SHIFT) \| (LED_MODE_LINK << LED2_MODE_SHIFT));
1111	sw_write_reg(SWITCH_REG_PORT4_LED,(LED_MODE_LINK_ACT << LED0_MODE_SHIFT) \| (LED_MODE_SPEED << LED1_MODE_SHIFT) \| (LED_MODE_LINK << LED2_MODE_SHIFT));
1112
1113	t = CPUP_CONF_DCPUP \| CPUP_CONF_CRCP \|
1114	SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT \|
1115	SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
1116	sw_write_reg(SWITCH_REG_CPUP_CONF, t);
1117
1118
1119
1120
1121	t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) \|
1122	(SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) \|
1123	(SWITCH_PORTS_NOCPU);
1124	sw_write_reg(SWITCH_REG_PORT_CONF0, t);
1125
1126	/* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
1127	t = SWITCH_PORTS_PHY \|
1128	(SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) \|
1129	(SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) \|
1130	(SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) \|
1131	(SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) \|
1132	PHY_CNTL2_RMAE;
1133	sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
1134
1135	t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
1136	t \|= PHY_CNTL3_RNT;
1137	sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
1138
1139	/* Force all the packets from all ports are low priority */
1140	sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
1141
1142	sw_int_mask(SWITCH_INTS_ALL);
1143	sw_int_ack(SWITCH_INTS_ALL);
1144
1145	err = adm5120_switch_rx_ring_alloc();
1146	if (err)
1147	goto err;
1148
1149	err = adm5120_switch_tx_ring_alloc();
1150	if (err)
1151	goto err;
1152
1153	adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
1154	adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
1155
1156	sw_write_reg(SWITCH_REG_SHDA, 0);
1157	sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
1158	sw_write_reg(SWITCH_REG_RHDA, 0);
1159	sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
1160
1161	for (i = 0; i < SWITCH_NUM_PORTS; i++) {
1162	struct net_device *dev;
1163	struct adm5120_if_priv *priv;
1164
1165	dev = adm5120_if_alloc();
1166	if (!dev) {
1167	err = -ENOMEM;
1168	goto err;
1169	}
1170
1171	adm5120_devs[i] = dev;
1172	priv = netdev_priv(dev);
1173
1174	priv->vlan_no = i;
1175	priv->port_mask = adm5120_eth_vlans[i];
1176
1177	memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
1178	adm5120_write_mac(dev);
1179
1180	err = register_netdev(dev);
1181	if (err) {
1182	SW_INFO("%s register failed, error=%d\n",
1183	dev->name, err);
1184	goto err;
1185	}
1186	}
1187
1188	/* setup vlan/port mapping after devs are filled up */
1189	adm5120_set_vlan(adm5120_eth_vlans);
1190
1191	/* enable CPU port */
1192	t = sw_read_reg(SWITCH_REG_CPUP_CONF);
1193	t &= ~CPUP_CONF_DCPUP;
1194	sw_write_reg(SWITCH_REG_CPUP_CONF, t);
1195
1196	return 0;
1197
1198	err:
1199	adm5120_switch_cleanup();
1200
1201	SW_ERR("init failed\n");
1202	return err;
1203	}
1204
1205	static int adm5120_switch_remove(struct platform_device *dev)
1206	{
1207	adm5120_switch_cleanup();
1208	return 0;
1209	}
1210
1211	static struct platform_driver adm5120_switch_driver = {
1212	.probe = adm5120_switch_probe,
1213	.remove = adm5120_switch_remove,
1214	.driver = {
1215	.name = DRV_NAME,
1216	},
1217	};
1218
1219	/* -------------------------------------------------------------------------- */
1220
1221	static int __init adm5120_switch_mod_init(void)
1222	{
1223	int err;
1224
1225	pr_info(DRV_DESC " version " DRV_VERSION "\n");
1226	err = platform_driver_register(&adm5120_switch_driver);
1227
1228	return err;
1229	}
1230
1231	static void __exit adm5120_switch_mod_exit(void)
1232	{
1233	platform_driver_unregister(&adm5120_switch_driver);
1234	}
1235
1236	module_init(adm5120_switch_mod_init);
1237	module_exit(adm5120_switch_mod_exit);
1238
1239	MODULE_LICENSE("GPL v2");
1240	MODULE_AUTHOR("Gabor Juhos <juhosg at openwrt.org>");
1241	MODULE_DESCRIPTION(DRV_DESC);
1242	MODULE_VERSION(DRV_VERSION);

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root/src/linux/adm5120/linux-2.6.23/drivers/net/adm5120sw.c

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