board.c

Revision 11759, 8.9 kB (checked in by BrainSlayer, 8 months ago)
napi change

Line
1	/*
2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.
5	*
6	* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7	* Copyright (C) 2006 FON Technology, SL.
8	* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9	* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
10	*/
11
12	/*
13	* Platform devices for Atheros SoCs
14	*/
15
16	#include <linux/autoconf.h>
17	#include <linux/init.h>
18	#include <linux/module.h>
19	#include <linux/types.h>
20	#include <linux/string.h>
21	#include <linux/platform_device.h>
22	#include <linux/kernel.h>
23	#include <linux/delay.h>
24	#include <linux/reboot.h>
25	#include <asm/bootinfo.h>
26	#include <asm/reboot.h>
27	#include <asm/time.h>
28	#include <asm/irq.h>
29	#include <asm/io.h>
30	#include "ar531x.h"
31
32	static int is_5315 = 0;
33
34	static struct resource ar5315_eth_res[] = {
35	{
36	.name = "eth0_membase",
37	.flags = IORESOURCE_MEM,
38	.start = AR5315_ENET0,
39	.end = AR5315_ENET0 + 0x2000,
40	},
41	{
42	.name = "eth0_irq",
43	.flags = IORESOURCE_IRQ,
44	.start = AR5315_IRQ_ENET0_INTRS,
45	.end = AR5315_IRQ_ENET0_INTRS,
46	},
47	};
48
49	static struct ar531x_eth ar5315_eth_data = {
50	.phy = 1,
51	.mac = 0,
52	.reset_base = AR5315_RESET,
53	.reset_mac = AR5315_RESET_ENET0,
54	.reset_phy = AR5315_RESET_EPHY0,
55	.phy_base = AR5315_ENET0
56	};
57
58	static struct platform_device ar5315_eth = {
59	.id = 0,
60	.name = "ar531x-eth",
61	.dev.platform_data = &ar5315_eth_data,
62	.resource = ar5315_eth_res,
63	.num_resources = ARRAY_SIZE(ar5315_eth_res)
64	};
65
66	static struct platform_device ar5315_wmac = {
67	.id = 0,
68	.name = "ar531x-wmac",
69	/* FIXME: add resources */
70	};
71
72	static struct resource ar5315_spiflash_res[] = {
73	{
74	.name = "flash_base",
75	.flags = IORESOURCE_MEM,
76	.start = KSEG1ADDR(AR5315_SPI_READ),
77	.end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
78	},
79	{
80	.name = "flash_regs",
81	.flags = IORESOURCE_MEM,
82	.start = 0x11300000,
83	.end = 0x11300012,
84	},
85	};
86
87	static struct platform_device ar5315_spiflash = {
88	.id = 0,
89	.name = "spiflash",
90	.resource = ar5315_spiflash_res,
91	.num_resources = ARRAY_SIZE(ar5315_spiflash_res)
92	};
93
94	static __initdata struct platform_device *ar5315_devs[4];
95
96
97
98	static void *flash_regs;
99
100	static inline __u32 spiflash_regread32(int reg)
101	{
102	volatile __u32 data = (__u32 )(flash_regs + reg);
103
104	return (*data);
105	}
106
107	static inline void spiflash_regwrite32(int reg, __u32 data)
108	{
109	volatile __u32 addr = (__u32 )(flash_regs + reg);
110
111	*addr = data;
112	}
113
114	#define SPI_FLASH_CTL 0x00
115	#define SPI_FLASH_OPCODE 0x04
116	#define SPI_FLASH_DATA 0x08
117
118	static __u8 spiflash_probe(void)
119	{
120	__u32 reg;
121
122	do {
123	reg = spiflash_regread32(SPI_FLASH_CTL);
124	} while (reg & SPI_CTL_BUSY);
125
126	spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
127
128	reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) \| 4 \|
129	(1 << 4) \| SPI_CTL_START;
130	reg = (reg & ~SPI_CTL_CLK_SEL_MASK);
131	reg = (reg \| (1 << 24)); // use slower clock timing (but still faster than original) since accton mounts crappy spi flash chips
132
133
134	spiflash_regwrite32(SPI_FLASH_CTL, reg);
135
136	do {
137	reg = spiflash_regread32(SPI_FLASH_CTL);
138	} while (reg & SPI_CTL_BUSY);
139
140	reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
141	reg &= 0xff;
142
143	return (u8) reg;
144	}
145
146
147	#define STM_8MBIT_SIGNATURE 0x13
148	#define STM_16MBIT_SIGNATURE 0x14
149	#define STM_32MBIT_SIGNATURE 0x15
150	#define STM_64MBIT_SIGNATURE 0x16
151	#define STM_128MBIT_SIGNATURE 0x17
152
153
154	static char __init *ar5315_flash_limit(void)
155	{
156	u8 sig;
157	u32 flash_size = 0;
158
159	/* probe the flash chip size */
160	flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
161	sig = spiflash_probe();
162	iounmap(flash_regs);
163
164	switch(sig) {
165	case STM_8MBIT_SIGNATURE:
166	flash_size = 0x00100000;
167	break;
168	case STM_16MBIT_SIGNATURE:
169	flash_size = 0x00200000;
170	break;
171	case STM_32MBIT_SIGNATURE:
172	flash_size = 0x00400000;
173	break;
174	case STM_64MBIT_SIGNATURE:
175	flash_size = 0x00800000;
176	break;
177	case STM_128MBIT_SIGNATURE:
178	flash_size = 0x01000000;
179	break;
180	}
181
182	ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
183	return (char *) ar5315_spiflash_res[0].end;
184	}
185
186	int __init ar5315_init_devices(void)
187	{
188	struct ar531x_config *config;
189	struct ar531x_boarddata *bcfg;
190	int dev = 0;
191
192	if (!is_5315)
193	return 0;
194
195	/* Find board configuration */
196	ar531x_find_config(ar5315_flash_limit());
197	bcfg = (struct ar531x_boarddata *) board_config;
198
199
200	config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
201	config->board = board_config;
202	config->radio = radio_config;
203	config->unit = 0;
204	config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
205
206	ar5315_eth_data.board_config = board_config;
207	ar5315_eth_data.macaddr = bcfg->enet0Mac;
208	ar5315_wmac.dev.platform_data = config;
209
210	ar5315_devs[dev++] = &ar5315_eth;
211	ar5315_devs[dev++] = &ar5315_wmac;
212	ar5315_devs[dev++] = &ar5315_spiflash;
213
214
215	return platform_add_devices(ar5315_devs, dev);
216	}
217
218	static void ar5315_halt(void)
219	{
220	while (1);
221	}
222
223	static void ar5315_power_off(void)
224	{
225	ar5315_halt();
226	}
227
228
229	static void ar5315_restart(char *command)
230	{
231	unsigned int reg;
232
233	void (mips_reset_vec)(void) = (void ) 0xbfc00000;
234
235
236	/* reset the system */
237	sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
238	/*
239	* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
240	*/
241	reg = sysRegRead(AR5315_GPIO_DO);
242	reg &= ~(1 << AR5315_RESET_GPIO);
243	sysRegWrite(AR5315_GPIO_DO, reg);
244	(void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
245
246	/* give it some time to attempt a gpio based hardware reset
247	* (atheros reference design workaround) */
248	mdelay(100);
249
250	/* now do GPIO 0 reset, known to be used on Seano devices */
251	reg = sysRegRead(AR5315_GPIO_DO);
252	reg &= ~(1 << 0);
253	sysRegWrite(AR5315_GPIO_DO, reg);
254	(void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
255
256	/* give it some time to attempt a gpio based hardware reset
257	* (atheros reference design workaround) */
258	mdelay(100);
259
260	/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
261	* workaround as in the atheros reference design. Attempt to jump
262	* to the mips reset location - the boot loader might be able to recover
263	* the system on its own
264	*/
265
266	mips_reset_vec();
267	}
268
269
270	/*
271	* This table is indexed by bits 5..4 of the CLOCKCTL1 register
272	* to determine the predevisor value.
273	*/
274	static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
275	1,
276	2,
277	4,
278	5
279	};
280
281	static int __initdata PLLC_DIVIDE_TABLE[5] = {
282	2,
283	3,
284	4,
285	6,
286	3
287	};
288
289	static unsigned int __init
290	ar5315_sys_clk(unsigned int clockCtl)
291	{
292	unsigned int pllcCtrl,cpuDiv;
293	unsigned int pllcOut,refdiv,fdiv,divby2;
294	unsigned int clkDiv;
295
296	pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
297	refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
298	refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
299	fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
300	divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
301	divby2 += 1;
302	pllcOut = (40000000/refdiv)(2divby2)*fdiv;
303
304
305	/* clkm input selected */
306	switch(clockCtl & CPUCLK_CLK_SEL_M) {
307	case 0:
308	case 1:
309	clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
310	break;
311	case 2:
312	clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
313	break;
314	default:
315	pllcOut = 40000000;
316	clkDiv = 1;
317	break;
318	}
319	cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
320	cpuDiv = cpuDiv * 2 ?: 1;
321	return (pllcOut/(clkDiv * cpuDiv));
322	}
323
324	static inline unsigned int ar5315_cpu_frequency(void)
325	{
326	return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
327	}
328
329	static inline unsigned int ar5315_apb_frequency(void)
330	{
331	return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
332	}
333
334	static void __init ar5315_time_init(void)
335	{
336	mips_hpt_frequency = ar5315_cpu_frequency() / 2;
337	}
338
339	void __init ar5315_prom_init(void)
340	{
341	u32 memsize, memcfg, devid;
342
343	is_5315 = 1;
344	memcfg = sysRegRead(AR5315_MEM_CFG);
345	memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
346	memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
347	memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
348	memsize <<= 3;
349	add_memory_region(0, memsize, BOOT_MEM_RAM);
350
351	/* Detect the hardware based on the device ID */
352	devid = sysRegRead(AR5315_SREV) & AR5315_REV_CHIP;
353	printk(KERN_INFO "mips devid = %X\n",devid);
354	switch(devid) {
355	case 0x90:
356	case 0x91:
357	mips_machtype = MACH_ATHEROS_AR2317;
358	break;
359	default:
360	mips_machtype = MACH_ATHEROS_AR2315;
361	break;
362	}
363	}
364
365	void __init ar5315_plat_setup(void)
366	{
367	unsigned int config = read_c0_config();
368
369	/* Clear any lingering AHB errors */
370	write_c0_config(config & ~0x3);
371	sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
372	sysRegRead(AR5315_AHB_ERR1);
373	sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
374
375	board_time_init = ar5315_time_init;
376
377	_machine_restart = ar5315_restart;
378	_machine_halt = ar5315_halt;
379	pm_power_off = ar5315_power_off;
380
381	serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
382	}
383
384	arch_initcall(ar5315_init_devices);

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root/src/linux/ar531x/linux-2.6.23/arch/mips/atheros/ar5315/board.c

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