root/src/linux/ar531x/linux-2.6.23/drivers/net/phy/mvswitch.h

Revision 12398, 4.5 kB (checked in by BrainSlayer, 5 months ago)

ar8216 switch support

Line 
1 /*
2  * Marvell 88E6060 switch driver
3  * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
4  * Copyright (c) 2008 Sebastian Gottschall <s.gottschall@dd-wrt.com> (just 88E6061 support)
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of the GNU General Public License v2 as published by the
8  * Free Software Foundation
9  */
10 #ifndef __MVSWITCH_H
11 #define __MVSWITCH_H
12
13 #define MV_HEADER_SIZE  2
14 #define MV_HEADER_PORTS_M       0x001f
15 #define MV_HEADER_PORTS_S       0
16 #define MV_HEADER_VLAN_M        0xf000
17 #define MV_HEADER_VLAN_S        12
18
19 #define MV_TRAILER_SIZE 4
20 #define MV_TRAILER_PORTS_M      0x1f
21 #define MV_TRAILER_PORTS_S      16
22 #define MV_TRAILER_FLAGS_S      24
23 #define MV_TRAILER_OVERRIDE     0x80
24
25 #define MV_STATUS_REAL_TIME_LINK_UP               0x0400
26 #define MV_STATUS_RESOLVED                        0x0800
27
28
29 #define MV_PORTS        5
30 #ifdef CONFIG_MTD_AR531X
31 #define MV_WANPORT      0
32 #else
33 #define MV_WANPORT      4
34 #endif
35 #define MV_CPUPORT      5
36
37 #define MV_BASE         0x10
38
39 #define MV_PHYPORT_BASE         (MV_BASE + 0x0)
40 #define MV_PHYPORT(_n)          (MV_PHYPORT_BASE + (_n))
41 #define MV_SWITCHPORT_BASE      (MV_BASE + 0x8)
42 #define MV_SWITCHPORT(_n)       (MV_SWITCHPORT_BASE + (_n))
43 #define MV_SWITCHREGS           (MV_BASE + 0xf)
44
45 enum {
46         MV_PHY_CONTROL      = 0x00,
47         MV_PHY_STATUS       = 0x01,
48         MV_PHY_IDENT0       = 0x02,
49         MV_PHY_IDENT1       = 0x03,
50         MV_PHY_ANEG         = 0x04,
51         MV_PHY_LINK_ABILITY = 0x05,
52         MV_PHY_ANEG_EXPAND  = 0x06,
53         MV_PHY_XMIT_NEXTP   = 0x07,
54         MV_PHY_LINK_NEXTP   = 0x08,
55         MV_PHY_CONTROL1     = 0x10,
56         MV_PHY_STATUS1      = 0x11,
57         MV_PHY_INTR_EN      = 0x12,
58         MV_PHY_INTR_STATUS  = 0x13,
59         MV_PHY_INTR_PORT    = 0x14,
60         MV_PHY_RECV_COUNTER = 0x16,
61         MV_PHY_LED_PARALLEL = 0x16,
62         MV_PHY_LED_STREAM   = 0x17,
63         MV_PHY_LED_CTRL     = 0x18,
64         MV_PHY_LED_OVERRIDE = 0x19,
65         MV_PHY_VCT_CTRL     = 0x1a,
66         MV_PHY_VCT_STATUS   = 0x1b,
67         MV_PHY_CONTROL2     = 0x1e
68 };
69 #define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type
70
71 enum {
72         MV_PORT_STATUS      = 0x00,
73         MV_PORT_IDENT       = 0x03,
74         MV_PORT_CONTROL     = 0x04,
75         MV_PORT_VLANMAP     = 0x06,
76         MV_PORT_ASSOC       = 0x0b,
77         MV_PORT_RXCOUNT     = 0x10,
78         MV_PORT_TXCOUNT     = 0x11,
79 };
80 #define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
81
82 enum {
83         MV_PORTCTRL_BLOCK   =  (1 << 0),
84         MV_PORTCTRL_LEARN   =  (2 << 0),
85         MV_PORTCTRL_ENABLED =  (3 << 0),
86         MV_PORTCTRL_EGRESSALL =  (12 << 0),     /* Egress all (E6061 only) */
87         MV_PORTCTRL_VLANTUN =  (1 << 7),        /* Enforce VLANs on packets */
88         MV_PORTCTRL_RXTR    =  (1 << 8),        /* Enable Marvell packet trailer for ingress */
89         MV_PORTCTRL_HEADER      = (1 << 11),    /* Enable Marvell packet header mode for port */
90         MV_PORTCTRL_TXTR    = (1 << 14),        /* Enable Marvell packet trailer for egress */
91         MV_PORTCTRL_FORCEFL = (1 << 15),        /* force flow control */
92 };
93
94 #define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)
95 #define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)
96
97 #define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)
98 #define MV_PORTASSOC_MONITOR    (1 << 15)
99
100 enum {
101         MV_SWITCH_MAC0      = 0x01,
102         MV_SWITCH_MAC1      = 0x02,
103         MV_SWITCH_MAC2      = 0x03,
104         MV_SWITCH_CTRL      = 0x04,
105         MV_SWITCH_ATU_CTRL  = 0x0a,
106         MV_SWITCH_ATU_OP    = 0x0b,
107         MV_SWITCH_ATU_DATA  = 0x0c,
108         MV_SWITCH_ATU_MAC0  = 0x0d,
109         MV_SWITCH_ATU_MAC1  = 0x0e,
110         MV_SWITCH_ATU_MAC2  = 0x0f,
111 };
112 #define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type
113
114 enum {
115         MV_SWITCHCTL_EEIE   =  (1 << 0),        /* EEPROM interrupt enable */
116         MV_SWITCHCTL_PHYIE  =  (1 << 1),        /* PHY interrupt enable */
117         MV_SWITCHCTL_ATUDONE=  (1 << 2),        /* ATU done interrupt enable */
118         MV_SWITCHCTL_ATUIE  =  (1 << 3),        /* ATU interrupt enable */
119         MV_SWITCHCTL_CTRMODE=  (1 << 8),        /* statistics for rx and tx errors */
120         MV_SWITCHCTL_RELOAD =  (1 << 9),        /* reload registers from eeprom */
121         MV_SWITCHCTL_MSIZE  = (1 << 10),        /* increase maximum frame size */
122         MV_SWITCHCTL_DROP   = (1 << 13),        /* discard frames with excessive collisions */
123 };
124
125 enum {
126 #define MV_ATUCTL_AGETIME_MIN   16
127 #define MV_ATUCTL_AGETIME_MAX   4080
128 #define MV_ATUCTL_AGETIME(_n)   ((((_n) / 16) & 0xff) << 4)
129         MV_ATUCTL_ATU_256   = (0 << 12),
130         MV_ATUCTL_ATU_512   = (1 << 12),
131         MV_ATUCTL_ATU_1K        = (2 << 12),
132         MV_ATUCTL_ATUMASK   = (3 << 12),
133         MV_ATUCTL_NO_LEARN  = (1 << 14),
134         MV_ATUCTL_RESET     = (1 << 15),
135 };
136
137 enum {
138 #define MV_ATUOP_DBNUM(_n)      ((_n) & 0x0f)
139
140         MV_ATUOP_NOOP       = (0 << 12),
141         MV_ATUOP_FLUSH_ALL  = (1 << 12),
142         MV_ATUOP_FLUSH_U    = (2 << 12),
143         MV_ATUOP_LOAD_DB    = (3 << 12),
144         MV_ATUOP_GET_NEXT   = (4 << 12),
145         MV_ATUOP_FLUSH_DB   = (5 << 12),
146         MV_ATUOP_FLUSH_DB_UU= (6 << 12),
147
148         MV_ATUOP_INPROGRESS = (1 << 15),
149 };
150
151 #define MV_IDENT_MASK           0xfff0
152 #define MV_IDENT_VALUE          0x0600
153 #define MV_IDENT_VALUE2         0x0610
154
155 #endif
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