dwc_otg_attr.c

Revision 12433, 33.7 kB (checked in by BrainSlayer, 5 months ago)
fixes usb issues with some devices

Line
1	/* ==========================================================================
2	* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
3	* $Revision: 1.2 $
4	* $Date: 2008-11-21 05:39:15 $
5	* $Change: 1064918 $
6	*
7	* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8	* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9	* otherwise expressly agreed to in writing between Synopsys and you.
10	*
11	* The Software IS NOT an item of Licensed Software or Licensed Product under
12	* any End User Software License Agreement or Agreement for Licensed Product
13	* with Synopsys or any supplement thereto. You are permitted to use and
14	* redistribute this Software in source and binary forms, with or without
15	* modification, provided that redistributions of source code must retain this
16	* notice. You may not view, use, disclose, copy or distribute this file or
17	* any information contained herein except pursuant to this license grant from
18	* Synopsys. If you do not agree with this notice, including the disclaimer
19	* below, then you are not authorized to use the Software.
20	*
21	* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24	* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25	* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31	* DAMAGE.
32	* ========================================================================== */
33
34	/** @file
35	*
36	* The diagnostic interface will provide access to the controller for
37	* bringing up the hardware and testing. The Linux driver attributes
38	* feature will be used to provide the Linux Diagnostic
39	* Interface. These attributes are accessed through sysfs.
40	*/
41
42	/** @page "Linux Module Attributes"
43	*
44	* The Linux module attributes feature is used to provide the Linux
45	* Diagnostic Interface. These attributes are accessed through sysfs.
46	* The diagnostic interface will provide access to the controller for
47	* bringing up the hardware and testing.
48
49
50	The following table shows the attributes.
51	<table>
52	<tr>
53	<td><b> Name</b></td>
54	<td><b> Description</b></td>
55	<td><b> Access</b></td>
56	</tr>
57
58	<tr>
59	<td> mode </td>
60	<td> Returns the current mode: 0 for device mode, 1 for host mode</td>
61	<td> Read</td>
62	</tr>
63
64	<tr>
65	<td> hnpcapable </td>
66	<td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
67	Read returns the current value.</td>
68	<td> Read/Write</td>
69	</tr>
70
71	<tr>
72	<td> srpcapable </td>
73	<td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
74	Read returns the current value.</td>
75	<td> Read/Write</td>
76	</tr>
77
78	<tr>
79	<td> hnp </td>
80	<td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
81	<td> Read/Write</td>
82	</tr>
83
84	<tr>
85	<td> srp </td>
86	<td> Initiates the Session Request Protocol. Read returns the status.</td>
87	<td> Read/Write</td>
88	</tr>
89
90	<tr>
91	<td> buspower </td>
92	<td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
93	<td> Read/Write</td>
94	</tr>
95
96	<tr>
97	<td> bussuspend </td>
98	<td> Suspends the USB bus.</td>
99	<td> Read/Write</td>
100	</tr>
101
102	<tr>
103	<td> busconnected </td>
104	<td> Gets the connection status of the bus</td>
105	<td> Read</td>
106	</tr>
107
108	<tr>
109	<td> gotgctl </td>
110	<td> Gets or sets the Core Control Status Register.</td>
111	<td> Read/Write</td>
112	</tr>
113
114	<tr>
115	<td> gusbcfg </td>
116	<td> Gets or sets the Core USB Configuration Register</td>
117	<td> Read/Write</td>
118	</tr>
119
120	<tr>
121	<td> grxfsiz </td>
122	<td> Gets or sets the Receive FIFO Size Register</td>
123	<td> Read/Write</td>
124	</tr>
125
126	<tr>
127	<td> gnptxfsiz </td>
128	<td> Gets or sets the non-periodic Transmit Size Register</td>
129	<td> Read/Write</td>
130	</tr>
131
132	<tr>
133	<td> gpvndctl </td>
134	<td> Gets or sets the PHY Vendor Control Register</td>
135	<td> Read/Write</td>
136	</tr>
137
138	<tr>
139	<td> ggpio </td>
140	<td> Gets the value in the lower 16-bits of the General Purpose IO Register
141	or sets the upper 16 bits.</td>
142	<td> Read/Write</td>
143	</tr>
144
145	<tr>
146	<td> guid </td>
147	<td> Gets or sets the value of the User ID Register</td>
148	<td> Read/Write</td>
149	</tr>
150
151	<tr>
152	<td> gsnpsid </td>
153	<td> Gets the value of the Synopsys ID Regester</td>
154	<td> Read</td>
155	</tr>
156
157	<tr>
158	<td> devspeed </td>
159	<td> Gets or sets the device speed setting in the DCFG register</td>
160	<td> Read/Write</td>
161	</tr>
162
163	<tr>
164	<td> enumspeed </td>
165	<td> Gets the device enumeration Speed.</td>
166	<td> Read</td>
167	</tr>
168
169	<tr>
170	<td> hptxfsiz </td>
171	<td> Gets the value of the Host Periodic Transmit FIFO</td>
172	<td> Read</td>
173	</tr>
174
175	<tr>
176	<td> hprt0 </td>
177	<td> Gets or sets the value in the Host Port Control and Status Register</td>
178	<td> Read/Write</td>
179	</tr>
180
181	<tr>
182	<td> regoffset </td>
183	<td> Sets the register offset for the next Register Access</td>
184	<td> Read/Write</td>
185	</tr>
186
187	<tr>
188	<td> regvalue </td>
189	<td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
190	<td> Read/Write</td>
191	</tr>
192
193	<tr>
194	<td> remote_wakeup </td>
195	<td> On read, shows the status of Remote Wakeup. On write, initiates a remote
196	wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
197	Wakeup signalling bit in the Device Control Register is set for 1
198	milli-second.</td>
199	<td> Read/Write</td>
200	</tr>
201
202	<tr>
203	<td> regdump </td>
204	<td> Dumps the contents of core registers.</td>
205	<td> Read</td>
206	</tr>
207
208	<tr>
209	<td> spramdump </td>
210	<td> Dumps the contents of core registers.</td>
211	<td> Read</td>
212	</tr>
213
214	<tr>
215	<td> hcddump </td>
216	<td> Dumps the current HCD state.</td>
217	<td> Read</td>
218	</tr>
219
220	<tr>
221	<td> hcd_frrem </td>
222	<td> Shows the average value of the Frame Remaining
223	field in the Host Frame Number/Frame Remaining register when an SOF interrupt
224	occurs. This can be used to determine the average interrupt latency. Also
225	shows the average Frame Remaining value for start_transfer and the "a" and
226	"b" sample points. The "a" and "b" sample points may be used during debugging
227	bto determine how long it takes to execute a section of the HCD code.</td>
228	<td> Read</td>
229	</tr>
230
231	<tr>
232	<td> rd_reg_test </td>
233	<td> Displays the time required to read the GNPTXFSIZ register many times
234	(the output shows the number of times the register is read).
235	<td> Read</td>
236	</tr>
237
238	<tr>
239	<td> wr_reg_test </td>
240	<td> Displays the time required to write the GNPTXFSIZ register many times
241	(the output shows the number of times the register is written).
242	<td> Read</td>
243	</tr>
244
245	</table>
246
247	Example usage:
248	To get the current mode:
249	cat /sys/devices/lm0/mode
250
251	To power down the USB:
252	echo 0 > /sys/devices/lm0/buspower
253	*/
254
255	#include <linux/kernel.h>
256	#include <linux/module.h>
257	#include <linux/moduleparam.h>
258	#include <linux/init.h>
259	#include <linux/device.h>
260	#include <linux/errno.h>
261	#include <linux/types.h>
262	#include <linux/stat.h> /* permission constants */
263	#include <linux/version.h>
264
265	//#include <asm/sizes.h>
266	#include <asm/rt2880/sizes.h>
267	#include <asm/io.h>
268	//#include <asm/arch/lm.h>
269	#include <asm/rt2880/lm.h>
270
271	#include "linux/dwc_otg_plat.h"
272	#include "dwc_otg_attr.h"
273	#include "dwc_otg_driver.h"
274	#include "dwc_otg_pcd.h"
275	#include "dwc_otg_hcd.h"
276
277	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
278	/*
279	* MACROs for defining sysfs attribute
280	*/
281	#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
282	static ssize_t _otg_attr_name_##_show (struct device _dev, struct device_attribute attr, char *buf) \
283	{ \
284	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
285	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
286	uint32_t val; \
287	val = dwc_read_reg32 (_addr_); \
288	val = (val & (_mask_)) >> _shift_; \
289	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
290	}
291	#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
292	static ssize_t _otg_attr_name_##_store (struct device _dev, struct device_attribute attr, \
293	const char *buf, size_t count) \
294	{ \
295	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
296	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
297	uint32_t set = simple_strtoul(buf, NULL, 16); \
298	uint32_t clear = set; \
299	clear = ((~clear) << _shift_) & _mask_; \
300	set = (set << _shift_) & _mask_; \
301	dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
302	dwc_modify_reg32(_addr_, clear, set); \
303	return count; \
304	}
305
306	/*
307	* MACROs for defining sysfs attribute for 32-bit registers
308	*/
309	#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
310	static ssize_t _otg_attr_name_##_show (struct device _dev, struct device_attribute attr, char *buf) \
311	{ \
312	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
313	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
314	uint32_t val; \
315	val = dwc_read_reg32 (_addr_); \
316	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
317	}
318	#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
319	static ssize_t _otg_attr_name_##_store (struct device _dev, struct device_attribute attr, \
320	const char *buf, size_t count) \
321	{ \
322	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
323	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
324	uint32_t val = simple_strtoul(buf, NULL, 16); \
325	dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
326	dwc_write_reg32(_addr_, val); \
327	return count; \
328	}
329
330	#else
331
332	/*
333	* MACROs for defining sysfs attribute
334	*/
335	#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
336	static ssize_t _otg_attr_name_##_show (struct device _dev, char buf) \
337	{ \
338	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
339	uint32_t val; \
340	val = dwc_read_reg32 (_addr_); \
341	val = (val & (_mask_)) >> _shift_; \
342	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
343	}
344	#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
345	static ssize_t _otg_attr_name_##_store (struct device _dev, const char buf, size_t count) \
346	{ \
347	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
348	uint32_t set = simple_strtoul(buf, NULL, 16); \
349	uint32_t clear = set; \
350	clear = ((~clear) << _shift_) & _mask_; \
351	set = (set << _shift_) & _mask_; \
352	dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
353	dwc_modify_reg32(_addr_, clear, set); \
354	return count; \
355	}
356
357	/*
358	* MACROs for defining sysfs attribute for 32-bit registers
359	*/
360	#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
361	static ssize_t _otg_attr_name_##_show (struct device _dev, char buf) \
362	{ \
363	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
364	uint32_t val; \
365	val = dwc_read_reg32 (_addr_); \
366	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
367	}
368	#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
369	static ssize_t _otg_attr_name_##_store (struct device _dev, const char buf, size_t count) \
370	{ \
371	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
372	uint32_t val = simple_strtoul(buf, NULL, 16); \
373	dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
374	dwc_write_reg32(_addr_, val); \
375	return count; \
376	}
377
378	#endif
379
380	#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
381	DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
382	DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
383	DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
384
385	#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
386	DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
387	DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
388
389	#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
390	DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
391	DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
392	DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
393
394	#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
395	DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
396	DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
397
398
399	/** @name Functions for Show/Store of Attributes */
400	/*@{/
401
402	/**
403	* Show the register offset of the Register Access.
404	*/
405	static ssize_t regoffset_show( struct device *_dev,
406	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
407	struct device_attribute *attr,
408	#endif
409	char *buf)
410	{
411	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
412	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
413	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
414	#else
415	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
416	#endif
417	return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
418	}
419
420	/**
421	* Set the register offset for the next Register Access Read/Write
422	*/
423	static ssize_t regoffset_store( struct device *_dev,
424	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
425	struct device_attribute *attr,
426	#endif
427	const char *buf,
428	size_t count )
429	{
430	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
431	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
432	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
433	#else
434	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
435	#endif
436	uint32_t offset = simple_strtoul(buf, NULL, 16);
437	//dev_dbg(_dev, "Offset=0x%08x\n", offset);
438	if (offset < SZ_256K ) {
439	otg_dev->reg_offset = offset;
440	}
441	else {
442	dev_err( _dev, "invalid offset\n" );
443	}
444
445	return count;
446	}
447	DEVICE_ATTR(regoffset, S_IRUGO\|S_IWUSR, (void *)regoffset_show, regoffset_store);
448
449
450	/**
451	* Show the value of the register at the offset in the reg_offset
452	* attribute.
453	*/
454	static ssize_t regvalue_show( struct device *_dev,
455	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
456	struct device_attribute *attr,
457	#endif
458	char *buf)
459	{
460	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
461	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
462	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
463	#else
464	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
465	#endif
466	uint32_t val;
467	volatile uint32_t *addr;
468
469	if (otg_dev->reg_offset != 0xFFFFFFFF &&
470	0 != otg_dev->base) {
471	/* Calculate the address */
472	addr = (uint32_t*)(otg_dev->reg_offset +
473	(uint8_t*)otg_dev->base);
474	//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
475	val = dwc_read_reg32( addr );
476	return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
477	"Reg@0x%06x = 0x%08x\n",
478	otg_dev->reg_offset, val);
479	}
480	else {
481	dev_err(_dev, "Invalid offset (0x%0x)\n",
482	otg_dev->reg_offset);
483	return sprintf(buf, "invalid offset\n" );
484	}
485	}
486
487	/**
488	* Store the value in the register at the offset in the reg_offset
489	* attribute.
490	*
491	*/
492	static ssize_t regvalue_store( struct device *_dev,
493	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
494	struct device_attribute *attr,
495	#endif
496	const char *buf,
497	size_t count )
498	{
499	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
500	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
501	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
502	#else
503	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
504	#endif
505	volatile uint32_t * addr;
506	uint32_t val = simple_strtoul(buf, NULL, 16);
507	//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
508	if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
509	/* Calculate the address */
510	addr = (uint32_t*)(otg_dev->reg_offset +
511	(uint8_t*)otg_dev->base);
512	//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
513	dwc_write_reg32( addr, val );
514	}
515	else {
516	dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
517	otg_dev->reg_offset);
518	}
519	return count;
520	}
521	DEVICE_ATTR(regvalue, S_IRUGO\|S_IWUSR, regvalue_show, regvalue_store);
522
523	/*
524	* Attributes
525	*/
526	DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
527	DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
528	DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
529
530	//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
531	//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
532	DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
533
534	DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
535	DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
536	DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
537	DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
538	DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
539	DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
540	DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
541	DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
542	DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
543	DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
544
545	DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
546	DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
547
548
549	/**
550	* @todo Add code to initiate the HNP.
551	*/
552	/**
553	* Show the HNP status bit
554	*/
555	static ssize_t hnp_show( struct device *_dev,
556	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
557	struct device_attribute *attr,
558	#endif
559	char *buf)
560	{
561	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
562	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
563	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
564	#else
565	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
566	#endif
567	gotgctl_data_t val;
568	val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
569	return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
570	}
571
572	/**
573	* Set the HNP Request bit
574	*/
575	static ssize_t hnp_store( struct device *_dev,
576	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
577	struct device_attribute *attr,
578	#endif
579	const char *buf,
580	size_t count )
581	{
582	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
583	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
584	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
585	#else
586	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
587	#endif
588	uint32_t in = simple_strtoul(buf, NULL, 16);
589	uint32_t addr = (uint32_t )&(otg_dev->core_if->core_global_regs->gotgctl);
590	gotgctl_data_t mem;
591	mem.d32 = dwc_read_reg32(addr);
592	mem.b.hnpreq = in;
593	dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
594	dwc_write_reg32(addr, mem.d32);
595	return count;
596	}
597	DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
598
599	/**
600	* @todo Add code to initiate the SRP.
601	*/
602	/**
603	* Show the SRP status bit
604	*/
605	static ssize_t srp_show( struct device *_dev,
606	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
607	struct device_attribute *attr,
608	#endif
609	char *buf)
610	{
611	#ifndef DWC_HOST_ONLY
612	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
613	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
614	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
615	#else
616	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
617	#endif
618	gotgctl_data_t val;
619	val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
620	return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
621	#else
622	return sprintf(buf, "Host Only Mode!\n");
623	#endif
624	}
625
626
627
628	/**
629	* Set the SRP Request bit
630	*/
631	static ssize_t srp_store( struct device *_dev,
632	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
633	struct device_attribute *attr,
634	#endif
635	const char *buf,
636	size_t count )
637	{
638	#ifndef DWC_HOST_ONLY
639	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
640	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
641	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
642	#else
643	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
644	#endif
645	dwc_otg_pcd_initiate_srp(otg_dev->pcd);
646	#endif
647	return count;
648	}
649	DEVICE_ATTR(srp, 0644, srp_show, srp_store);
650
651	/**
652	* @todo Need to do more for power on/off?
653	*/
654	/**
655	* Show the Bus Power status
656	*/
657	static ssize_t buspower_show( struct device *_dev,
658	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
659	struct device_attribute *attr,
660	#endif
661	char *buf)
662	{
663	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
664	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
665	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
666	#else
667	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
668	#endif
669	hprt0_data_t val;
670	val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
671	return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
672	}
673
674
675	/**
676	* Set the Bus Power status
677	*/
678	static ssize_t buspower_store( struct device *_dev,
679	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
680	struct device_attribute *attr,
681	#endif
682	const char *buf,
683	size_t count )
684	{
685	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
686	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
687	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
688	#else
689	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
690	#endif
691	uint32_t on = simple_strtoul(buf, NULL, 16);
692	uint32_t addr = (uint32_t )otg_dev->core_if->host_if->hprt0;
693	hprt0_data_t mem;
694
695	mem.d32 = dwc_read_reg32(addr);
696	mem.b.prtpwr = on;
697
698	//dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
699	dwc_write_reg32(addr, mem.d32);
700
701	return count;
702	}
703	DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
704
705	/**
706	* @todo Need to do more for suspend?
707	*/
708	/**
709	* Show the Bus Suspend status
710	*/
711	static ssize_t bussuspend_show( struct device *_dev,
712	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
713	struct device_attribute *attr,
714	#endif
715	char *buf)
716	{
717	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
718	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
719	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
720	#else
721	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
722	#endif
723	hprt0_data_t val;
724	val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
725	return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
726	}
727
728	/**
729	* Set the Bus Suspend status
730	*/
731	static ssize_t bussuspend_store( struct device *_dev,
732	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
733	struct device_attribute *attr,
734	#endif
735	const char *buf,
736	size_t count )
737	{
738	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
739	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
740	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
741	#else
742	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
743	#endif
744	uint32_t in = simple_strtoul(buf, NULL, 16);
745	uint32_t addr = (uint32_t )otg_dev->core_if->host_if->hprt0;
746	hprt0_data_t mem;
747	mem.d32 = dwc_read_reg32(addr);
748	mem.b.prtsusp = in;
749	dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
750	dwc_write_reg32(addr, mem.d32);
751	return count;
752	}
753	DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
754
755	/**
756	* Show the status of Remote Wakeup.
757	*/
758	static ssize_t remote_wakeup_show( struct device *_dev,
759	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
760	struct device_attribute *attr,
761	#endif
762	char *buf)
763	{
764	#ifndef DWC_HOST_ONLY
765	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
766	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
767	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
768	#else
769	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
770	#endif
771	dctl_data_t val;
772	val.d32 =
773	dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
774	return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
775	val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
776	#else
777	return sprintf(buf, "Host Only Mode!\n");
778	#endif
779	}
780	/**
781	* Initiate a remote wakeup of the host. The Device control register
782	* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
783	* flag is set.
784	*
785	*/
786	static ssize_t remote_wakeup_store( struct device *_dev,
787	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
788	struct device_attribute *attr,
789	#endif
790	const char *buf,
791	size_t count )
792	{
793	#ifndef DWC_HOST_ONLY
794	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
795	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
796	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
797	#else
798	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
799	#endif
800	uint32_t val = simple_strtoul(buf, NULL, 16);
801	if (val&1) {
802	dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
803	}
804	else {
805	dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
806	}
807	#endif
808	return count;
809	}
810	DEVICE_ATTR(remote_wakeup, S_IRUGO\|S_IWUSR, remote_wakeup_show,
811	remote_wakeup_store);
812
813	/**
814	* Dump global registers and either host or device registers (depending on the
815	* current mode of the core).
816	*/
817	static ssize_t regdump_show( struct device *_dev,
818	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
819	struct device_attribute *attr,
820	#endif
821	char *buf)
822	{
823	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
824	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
825	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
826	#else
827	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
828	#endif
829	dwc_otg_dump_global_registers( otg_dev->core_if);
830	if (dwc_otg_is_host_mode(otg_dev->core_if)) {
831	dwc_otg_dump_host_registers( otg_dev->core_if);
832	} else {
833	dwc_otg_dump_dev_registers( otg_dev->core_if);
834
835	}
836	return sprintf( buf, "Register Dump\n" );
837	}
838
839	DEVICE_ATTR(regdump, S_IRUGO\|S_IWUSR, regdump_show, 0);
840
841	/**
842	* Dump global registers and either host or device registers (depending on the
843	* current mode of the core).
844	*/
845	static ssize_t spramdump_show( struct device *_dev,
846	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
847	struct device_attribute *attr,
848	#endif
849	char *buf)
850	{
851	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
852	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
853	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
854	#else
855	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
856	#endif
857	dwc_otg_dump_spram( otg_dev->core_if);
858
859	return sprintf( buf, "SPRAM Dump\n" );
860	}
861
862	DEVICE_ATTR(spramdump, S_IRUGO\|S_IWUSR, spramdump_show, 0);
863
864	/**
865	* Dump the current hcd state.
866	*/
867	static ssize_t hcddump_show( struct device *_dev,
868	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
869	struct device_attribute *attr,
870	#endif
871	char *buf)
872	{
873	#ifndef DWC_DEVICE_ONLY
874	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
875	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
876	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
877	#else
878	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
879	#endif
880	dwc_otg_hcd_dump_state(otg_dev->hcd);
881	#endif
882	return sprintf( buf, "HCD Dump\n" );
883	}
884
885	DEVICE_ATTR(hcddump, S_IRUGO\|S_IWUSR, hcddump_show, 0);
886
887	/**
888	* Dump the average frame remaining at SOF. This can be used to
889	* determine average interrupt latency. Frame remaining is also shown for
890	* start transfer and two additional sample points.
891	*/
892	static ssize_t hcd_frrem_show( struct device *_dev,
893	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
894	struct device_attribute *attr,
895	#endif
896	char *buf)
897	{
898	#ifndef DWC_DEVICE_ONLY
899	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
900	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
901	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
902	#else
903	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
904	#endif
905	dwc_otg_hcd_dump_frrem(otg_dev->hcd);
906	#endif
907	return sprintf( buf, "HCD Dump Frame Remaining\n" );
908	}
909
910	DEVICE_ATTR(hcd_frrem, S_IRUGO\|S_IWUSR, hcd_frrem_show, 0);
911
912	/**
913	* Displays the time required to read the GNPTXFSIZ register many times (the
914	* output shows the number of times the register is read).
915	*/
916	#define RW_REG_COUNT 10000000
917	#define MSEC_PER_JIFFIE 1000/HZ
918	static ssize_t rd_reg_test_show( struct device *_dev,
919	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
920	struct device_attribute *attr,
921	#endif
922	char *buf)
923	{
924	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
925	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
926	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
927	#else
928	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
929	#endif
930	int i;
931	int time;
932	int start_jiffies;
933
934	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
935	HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
936	start_jiffies = jiffies;
937	for (i = 0; i < RW_REG_COUNT; i++) {
938	dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
939	}
940	time = jiffies - start_jiffies;
941	return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
942	RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
943	}
944
945	DEVICE_ATTR(rd_reg_test, S_IRUGO\|S_IWUSR, rd_reg_test_show, 0);
946
947	/**
948	* Displays the time required to write the GNPTXFSIZ register many times (the
949	* output shows the number of times the register is written).
950	*/
951	static ssize_t wr_reg_test_show( struct device *_dev,
952	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
953	struct device_attribute *attr,
954	#endif
955	char *buf)
956	{
957	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
958	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
959	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
960	#else
961	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
962	#endif
963	uint32_t reg_val;
964	int i;
965	int time;
966	int start_jiffies;
967
968	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
969	HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
970	reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
971	start_jiffies = jiffies;
972	for (i = 0; i < RW_REG_COUNT; i++) {
973	dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
974	}
975	time = jiffies - start_jiffies;
976	return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
977	RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
978	}
979
980	DEVICE_ATTR(wr_reg_test, S_IRUGO\|S_IWUSR, wr_reg_test_show, 0);
981	/*@}/
982
983	/**
984	* Create the device files
985	*/
986	void dwc_otg_attr_create (struct lm_device *lmdev)
987	{
988	int error;
989
990	error = device_create_file(&lmdev->dev, &dev_attr_regoffset);
991	error = device_create_file(&lmdev->dev, &dev_attr_regvalue);
992	error = device_create_file(&lmdev->dev, &dev_attr_mode);
993	error = device_create_file(&lmdev->dev, &dev_attr_hnpcapable);
994	error = device_create_file(&lmdev->dev, &dev_attr_srpcapable);
995	error = device_create_file(&lmdev->dev, &dev_attr_hnp);
996	error = device_create_file(&lmdev->dev, &dev_attr_srp);
997	error = device_create_file(&lmdev->dev, &dev_attr_buspower);
998	error = device_create_file(&lmdev->dev, &dev_attr_bussuspend);
999	error = device_create_file(&lmdev->dev, &dev_attr_busconnected);
1000	error = device_create_file(&lmdev->dev, &dev_attr_gotgctl);
1001	error = device_create_file(&lmdev->dev, &dev_attr_gusbcfg);
1002	error = device_create_file(&lmdev->dev, &dev_attr_grxfsiz);
1003	error = device_create_file(&lmdev->dev, &dev_attr_gnptxfsiz);
1004	error = device_create_file(&lmdev->dev, &dev_attr_gpvndctl);
1005	error = device_create_file(&lmdev->dev, &dev_attr_ggpio);
1006	error = device_create_file(&lmdev->dev, &dev_attr_guid);
1007	error = device_create_file(&lmdev->dev, &dev_attr_gsnpsid);
1008	error = device_create_file(&lmdev->dev, &dev_attr_devspeed);
1009	error = device_create_file(&lmdev->dev, &dev_attr_enumspeed);
1010	error = device_create_file(&lmdev->dev, &dev_attr_hptxfsiz);
1011	error = device_create_file(&lmdev->dev, &dev_attr_hprt0);
1012	error = device_create_file(&lmdev->dev, &dev_attr_remote_wakeup);
1013	error = device_create_file(&lmdev->dev, &dev_attr_regdump);
1014	error = device_create_file(&lmdev->dev, &dev_attr_spramdump);
1015	error = device_create_file(&lmdev->dev, &dev_attr_hcddump);
1016	error = device_create_file(&lmdev->dev, &dev_attr_hcd_frrem);
1017	error = device_create_file(&lmdev->dev, &dev_attr_rd_reg_test);
1018	error = device_create_file(&lmdev->dev, &dev_attr_wr_reg_test);
1019	}
1020
1021	/**
1022	* Remove the device files
1023	*/
1024	void dwc_otg_attr_remove (struct lm_device *lmdev)
1025	{
1026	device_remove_file(&lmdev->dev, &dev_attr_regoffset);
1027	device_remove_file(&lmdev->dev, &dev_attr_regvalue);
1028	device_remove_file(&lmdev->dev, &dev_attr_mode);
1029	device_remove_file(&lmdev->dev, &dev_attr_hnpcapable);
1030	device_remove_file(&lmdev->dev, &dev_attr_srpcapable);
1031	device_remove_file(&lmdev->dev, &dev_attr_hnp);
1032	device_remove_file(&lmdev->dev, &dev_attr_srp);
1033	device_remove_file(&lmdev->dev, &dev_attr_buspower);
1034	device_remove_file(&lmdev->dev, &dev_attr_bussuspend);
1035	device_remove_file(&lmdev->dev, &dev_attr_busconnected);
1036	device_remove_file(&lmdev->dev, &dev_attr_gotgctl);
1037	device_remove_file(&lmdev->dev, &dev_attr_gusbcfg);
1038	device_remove_file(&lmdev->dev, &dev_attr_grxfsiz);
1039	device_remove_file(&lmdev->dev, &dev_attr_gnptxfsiz);
1040	device_remove_file(&lmdev->dev, &dev_attr_gpvndctl);
1041	device_remove_file(&lmdev->dev, &dev_attr_ggpio);
1042	device_remove_file(&lmdev->dev, &dev_attr_guid);
1043	device_remove_file(&lmdev->dev, &dev_attr_gsnpsid);
1044	device_remove_file(&lmdev->dev, &dev_attr_devspeed);
1045	device_remove_file(&lmdev->dev, &dev_attr_enumspeed);
1046	device_remove_file(&lmdev->dev, &dev_attr_hptxfsiz);
1047	device_remove_file(&lmdev->dev, &dev_attr_hprt0);
1048	device_remove_file(&lmdev->dev, &dev_attr_remote_wakeup);
1049	device_remove_file(&lmdev->dev, &dev_attr_regdump);
1050	device_remove_file(&lmdev->dev, &dev_attr_spramdump);
1051	device_remove_file(&lmdev->dev, &dev_attr_hcddump);
1052	device_remove_file(&lmdev->dev, &dev_attr_hcd_frrem);
1053	device_remove_file(&lmdev->dev, &dev_attr_rd_reg_test);
1054	device_remove_file(&lmdev->dev, &dev_attr_wr_reg_test);
1055	}

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root/src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c

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