dwc_otg_hcd.c

Revision 12433, 85.0 kB (checked in by BrainSlayer, 5 months ago)
fixes usb issues with some devices

Line
1	/* ==========================================================================
2	* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
3	* $Revision: 1.4 $
4	* $Date: 2008-11-21 05:39:15 $
5	* $Change: 1064940 $
6	*
7	* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8	* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9	* otherwise expressly agreed to in writing between Synopsys and you.
10	*
11	* The Software IS NOT an item of Licensed Software or Licensed Product under
12	* any End User Software License Agreement or Agreement for Licensed Product
13	* with Synopsys or any supplement thereto. You are permitted to use and
14	* redistribute this Software in source and binary forms, with or without
15	* modification, provided that redistributions of source code must retain this
16	* notice. You may not view, use, disclose, copy or distribute this file or
17	* any information contained herein except pursuant to this license grant from
18	* Synopsys. If you do not agree with this notice, including the disclaimer
19	* below, then you are not authorized to use the Software.
20	*
21	* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24	* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25	* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31	* DAMAGE.
32	* ========================================================================== */
33	#ifndef DWC_DEVICE_ONLY
34
35	/**
36	* @file
37	*
38	* This file contains the implementation of the HCD. In Linux, the HCD
39	* implements the hc_driver API.
40	*/
41	#include <linux/kernel.h>
42	#include <linux/module.h>
43	#include <linux/moduleparam.h>
44	#include <linux/init.h>
45	#include <linux/device.h>
46	#include <linux/errno.h>
47	#include <linux/list.h>
48	#include <linux/interrupt.h>
49	#include <linux/string.h>
50	#include <linux/dma-mapping.h>
51	#include <linux/version.h>
52
53	//#include <asm/arch/lm.h>
54	#include <asm/rt2880/lm.h>
55	//#include <asm/arch/irqs.h>
56
57	#include "dwc_otg_driver.h"
58	#include "dwc_otg_hcd.h"
59	#include "dwc_otg_regs.h"
60
61	static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
62
63	static const struct hc_driver dwc_otg_hc_driver = {
64
65	.description = dwc_otg_hcd_name,
66	.product_desc = "DWC OTG Controller",
67	.hcd_priv_size = sizeof(dwc_otg_hcd_t),
68
69	.irq = dwc_otg_hcd_irq,
70
71	.flags = HCD_MEMORY \| HCD_USB2,
72
73	//.reset =
74	.start = dwc_otg_hcd_start,
75	//.suspend =
76	//.resume =
77	.stop = dwc_otg_hcd_stop,
78
79	.urb_enqueue = dwc_otg_hcd_urb_enqueue,
80	.urb_dequeue = dwc_otg_hcd_urb_dequeue,
81	.endpoint_disable = dwc_otg_hcd_endpoint_disable,
82
83	.get_frame_number = dwc_otg_hcd_get_frame_number,
84
85	.hub_status_data = dwc_otg_hcd_hub_status_data,
86	.hub_control = dwc_otg_hcd_hub_control,
87	//.hub_suspend =
88	//.hub_resume =
89	};
90
91	/**
92	* Work queue function for starting the HCD when A-Cable is connected.
93	* The dwc_otg_hcd_start() must be called in a process context.
94	*/
95	static void hcd_start_func(
96	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
97	void *_vp
98	#else
99	struct work_struct *_work
100	#endif
101	)
102	{
103	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
104	struct usb_hcd usb_hcd = (struct usb_hcd )_vp;
105	#else
106	struct delayed_work *dw = container_of(_work, struct delayed_work, work);
107	struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work);
108	struct usb_hcd usb_hcd = container_of((void )otg_hcd, struct usb_hcd, hcd_priv);
109	#endif
110	DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
111	if (usb_hcd) {
112	dwc_otg_hcd_start(usb_hcd);
113	}
114	}
115
116	/**
117	* HCD Callback function for starting the HCD when A-Cable is
118	* connected.
119	*
120	* @param p void pointer to the <code>struct usb_hcd</code>
121	*/
122	static int32_t dwc_otg_hcd_start_cb(void *p)
123	{
124	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
125	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
126	hprt0_data_t hprt0;
127
128	if (core_if->op_state == B_HOST) {
129	/*
130	* Reset the port. During a HNP mode switch the reset
131	* needs to occur within 1ms and have a duration of at
132	* least 50ms.
133	*/
134	hprt0.d32 = dwc_otg_read_hprt0(core_if);
135	hprt0.b.prtrst = 1;
136	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
137	((struct usb_hcd *)p)->self.is_b_host = 1;
138	} else {
139	((struct usb_hcd *)p)->self.is_b_host = 0;
140	}
141
142	/* Need to start the HCD in a non-interrupt context. */
143	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
144	INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
145	// INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p);
146	#else
147	// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
148	INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
149	#endif
150	// schedule_work(&dwc_otg_hcd->start_work);
151	queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000);
152
153	return 1;
154	}
155
156	/**
157	* HCD Callback function for stopping the HCD.
158	*
159	* @param p void pointer to the <code>struct usb_hcd</code>
160	*/
161	static int32_t dwc_otg_hcd_stop_cb(void *p)
162	{
163	struct usb_hcd usb_hcd = (struct usb_hcd )p;
164	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
165	dwc_otg_hcd_stop(usb_hcd);
166	return 1;
167	}
168
169	static void del_xfer_timers(dwc_otg_hcd_t *hcd)
170	{
171	#ifdef DEBUG
172	int i;
173	int num_channels = hcd->core_if->core_params->host_channels;
174	for (i = 0; i < num_channels; i++) {
175	del_timer(&hcd->core_if->hc_xfer_timer[i]);
176	}
177	#endif
178	}
179
180	static void del_timers(dwc_otg_hcd_t *hcd)
181	{
182	del_xfer_timers(hcd);
183	del_timer(&hcd->conn_timer);
184	}
185
186	/**
187	* Processes all the URBs in a single list of QHs. Completes them with
188	* -ETIMEDOUT and frees the QTD.
189	*/
190	static void kill_urbs_in_qh_list(dwc_otg_hcd_t hcd, struct list_head qh_list)
191	{
192	struct list_head *qh_item;
193	dwc_otg_qh_t *qh;
194	struct list_head *qtd_item;
195	dwc_otg_qtd_t *qtd;
196
197	list_for_each(qh_item, qh_list) {
198	qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
199	for (qtd_item = qh->qtd_list.next;
200	qtd_item != &qh->qtd_list;
201	qtd_item = qh->qtd_list.next) {
202	qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
203	if (qtd->urb != NULL) {
204	dwc_otg_hcd_complete_urb(hcd, qtd->urb,
205	-ETIMEDOUT);
206	}
207	dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
208	}
209	}
210	}
211
212	/**
213	* Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
214	* and periodic schedules. The QTD associated with each URB is removed from
215	* the schedule and freed. This function may be called when a disconnect is
216	* detected or when the HCD is being stopped.
217	*/
218	static void kill_all_urbs(dwc_otg_hcd_t *hcd)
219	{
220	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
221	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
222	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
223	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
224	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
225	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
226	}
227
228	/**
229	* HCD Callback function for disconnect of the HCD.
230	*
231	* @param p void pointer to the <code>struct usb_hcd</code>
232	*/
233	static int32_t dwc_otg_hcd_disconnect_cb(void *p)
234	{
235	gintsts_data_t intr;
236	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
237
238	//DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
239
240	/*
241	* Set status flags for the hub driver.
242	*/
243	dwc_otg_hcd->flags.b.port_connect_status_change = 1;
244	dwc_otg_hcd->flags.b.port_connect_status = 0;
245
246	/*
247	* Shutdown any transfers in process by clearing the Tx FIFO Empty
248	* interrupt mask and status bits and disabling subsequent host
249	* channel interrupts.
250	*/
251	intr.d32 = 0;
252	intr.b.nptxfempty = 1;
253	intr.b.ptxfempty = 1;
254	intr.b.hcintr = 1;
255	dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
256	dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
257
258	del_timers(dwc_otg_hcd);
259
260	/*
261	* Turn off the vbus power only if the core has transitioned to device
262	* mode. If still in host mode, need to keep power on to detect a
263	* reconnection.
264	*/
265	if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
266	if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
267	hprt0_data_t hprt0 = { .d32=0 };
268	DWC_PRINT("Disconnect: PortPower off\n");
269	hprt0.b.prtpwr = 0;
270	dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
271	}
272
273	dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
274	}
275
276	/* Respond with an error status to all URBs in the schedule. */
277	kill_all_urbs(dwc_otg_hcd);
278
279	if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
280	/* Clean up any host channels that were in use. */
281	int num_channels;
282	int i;
283	dwc_hc_t *channel;
284	dwc_otg_hc_regs_t *hc_regs;
285	hcchar_data_t hcchar;
286
287	num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
288
289	if (!dwc_otg_hcd->core_if->dma_enable) {
290	/* Flush out any channel requests in slave mode. */
291	for (i = 0; i < num_channels; i++) {
292	channel = dwc_otg_hcd->hc_ptr_array[i];
293	if (list_empty(&channel->hc_list_entry)) {
294	hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
295	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
296	if (hcchar.b.chen) {
297	hcchar.b.chen = 0;
298	hcchar.b.chdis = 1;
299	hcchar.b.epdir = 0;
300	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
301	}
302	}
303	}
304	}
305
306	for (i = 0; i < num_channels; i++) {
307	channel = dwc_otg_hcd->hc_ptr_array[i];
308	if (list_empty(&channel->hc_list_entry)) {
309	hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
310	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
311	if (hcchar.b.chen) {
312	/* Halt the channel. */
313	hcchar.b.chdis = 1;
314	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
315	}
316
317	dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
318	list_add_tail(&channel->hc_list_entry,
319	&dwc_otg_hcd->free_hc_list);
320	}
321	}
322	}
323
324	/* A disconnect will end the session so the B-Device is no
325	* longer a B-host. */
326	((struct usb_hcd *)p)->self.is_b_host = 0;
327	return 1;
328	}
329
330	/**
331	* Connection timeout function. An OTG host is required to display a
332	* message if the device does not connect within 10 seconds.
333	*/
334	void dwc_otg_hcd_connect_timeout(unsigned long ptr)
335	{
336	DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr);
337	DWC_PRINT("Connect Timeout\n");
338	DWC_ERROR("Device Not Connected/Responding\n");
339	}
340
341	/**
342	* Start the connection timer. An OTG host is required to display a
343	* message if the device does not connect within 10 seconds. The
344	* timer is deleted if a port connect interrupt occurs before the
345	* timer expires.
346	*/
347	static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
348	{
349	init_timer(&hcd->conn_timer);
350	hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
351	hcd->conn_timer.data = 0;
352	hcd->conn_timer.expires = jiffies + (HZ * 10);
353	add_timer(&hcd->conn_timer);
354	}
355
356	/**
357	* HCD Callback function for disconnect of the HCD.
358	*
359	* @param p void pointer to the <code>struct usb_hcd</code>
360	*/
361	static int32_t dwc_otg_hcd_session_start_cb(void *p)
362	{
363	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
364	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
365	dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
366	return 1;
367	}
368
369	/**
370	* HCD Callback structure for handling mode switching.
371	*/
372	static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
373	.start = dwc_otg_hcd_start_cb,
374	.stop = dwc_otg_hcd_stop_cb,
375	.disconnect = dwc_otg_hcd_disconnect_cb,
376	.session_start = dwc_otg_hcd_session_start_cb,
377	.p = 0,
378	};
379
380	/**
381	* Reset tasklet function
382	*/
383	static void reset_tasklet_func(unsigned long data)
384	{
385	dwc_otg_hcd_t dwc_otg_hcd = (dwc_otg_hcd_t )data;
386	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
387	hprt0_data_t hprt0;
388
389	DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
390
391	hprt0.d32 = dwc_otg_read_hprt0(core_if);
392	hprt0.b.prtrst = 1;
393	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
394	mdelay(60);
395
396	hprt0.b.prtrst = 0;
397	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
398	dwc_otg_hcd->flags.b.port_reset_change = 1;
399	}
400
401	static struct tasklet_struct reset_tasklet = {
402	.next = NULL,
403	.state = 0,
404	.count = ATOMIC_INIT(0),
405	.func = reset_tasklet_func,
406	.data = 0,
407	};
408
409	/**
410	* Initializes the HCD. This function allocates memory for and initializes the
411	* static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
412	* USB bus with the core and calls the hc_driver->start() function. It returns
413	* a negative error on failure.
414	*/
415	int dwc_otg_hcd_init(struct lm_device *lmdev)
416	{
417	struct usb_hcd *hcd = NULL;
418	dwc_otg_hcd_t *dwc_otg_hcd = NULL;
419	dwc_otg_device_t *otg_dev = lm_get_drvdata(lmdev);
420
421	int num_channels;
422	int i;
423	dwc_hc_t *channel;
424
425	int retval = 0;
426
427	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
428
429	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
430	/* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */
431
432	/* Set device flags indicating whether the HCD supports DMA. */
433	if (otg_dev->core_if->dma_enable) {
434	DWC_PRINT("Using DMA mode\n");
435	lmdev->dev.dma_mask = (void *)~0;
436	lmdev->dev.coherent_dma_mask = ~0;
437
438	if (otg_dev->core_if->dma_desc_enable) {
439	DWC_PRINT("Device using Descriptor DMA mode\n");
440	} else {
441	DWC_PRINT("Device using Buffer DMA mode\n");
442	}
443	} else {
444	DWC_PRINT("Using Slave mode\n");
445	lmdev->dev.dma_mask = (void *)0;
446	lmdev->dev.coherent_dma_mask = 0;
447	}
448	#endif
449	/*
450	* Allocate memory for the base HCD plus the DWC OTG HCD.
451	* Initialize the base HCD.
452	*/
453	hcd = usb_create_hcd(&dwc_otg_hc_driver, &lmdev->dev, lmdev->dev.bus_id);
454	if (!hcd) {
455	retval = -ENOMEM;
456	goto error1;
457	}
458
459	hcd->regs = otg_dev->base;
460	hcd->self.otg_port = 1;
461
462	/* Initialize the DWC OTG HCD. */
463	dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
464	dwc_otg_hcd->core_if = otg_dev->core_if;
465	otg_dev->hcd = dwc_otg_hcd;
466
467	/* */
468	spin_lock_init(&dwc_otg_hcd->lock);
469
470	/* Register the HCD CIL Callbacks */
471	dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
472	&hcd_cil_callbacks, hcd);
473
474	/* Initialize the non-periodic schedule. */
475	INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
476	INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
477
478	/* Initialize the periodic schedule. */
479	INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
480	INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
481	INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
482	INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
483
484	/*
485	* Create a host channel descriptor for each host channel implemented
486	* in the controller. Initialize the channel descriptor array.
487	*/
488	INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
489	num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
490	memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array));
491	for (i = 0; i < num_channels; i++) {
492	channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
493	if (channel == NULL) {
494	retval = -ENOMEM;
495	DWC_ERROR("%s: host channel allocation failed\n", __func__);
496	goto error2;
497	}
498	memset(channel, 0, sizeof(dwc_hc_t));
499	channel->hc_num = i;
500	dwc_otg_hcd->hc_ptr_array[i] = channel;
501	#ifdef DEBUG
502	init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
503	#endif
504	DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
505	}
506
507	/* Initialize the Connection timeout timer. */
508	init_timer(&dwc_otg_hcd->conn_timer);
509
510	/* Initialize reset tasklet. */
511	reset_tasklet.data = (unsigned long) dwc_otg_hcd;
512	dwc_otg_hcd->reset_tasklet = &reset_tasklet;
513
514	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
515	/* Set device flags indicating whether the HCD supports DMA. */
516	if (otg_dev->core_if->dma_enable) {
517	DWC_PRINT("Using DMA mode\n");
518	lmdev->dev.dma_mask = (void *)~0;
519	lmdev->dev.coherent_dma_mask = ~0;
520
521	if (otg_dev->core_if->dma_desc_enable){
522	DWC_PRINT("Device using Descriptor DMA mode\n");
523	} else {
524	DWC_PRINT("Device using Buffer DMA mode\n");
525	}
526	} else {
527	DWC_PRINT("Using Slave mode\n");
528	lmdev->dev.dma_mask = (void *)0;
529	lmdev->dev.coherent_dma_mask = 0;
530	}
531	#endif
532	/*
533	* Finish generic HCD initialization and start the HCD. This function
534	* allocates the DMA buffer pool, registers the USB bus, requests the
535	* IRQ line, and calls dwc_otg_hcd_start method.
536	*/
537	retval = usb_add_hcd(hcd, lmdev->irq, SA_SHIRQ);
538	if (retval < 0) {
539	goto error2;
540	}
541
542	/*
543	* Allocate space for storing data on status transactions. Normally no
544	* data is sent, but this space acts as a bit bucket. This must be
545	* done after usb_add_hcd since that function allocates the DMA buffer
546	* pool.
547	*/
548	if (otg_dev->core_if->dma_enable) {
549	dwc_otg_hcd->status_buf =
550	dma_alloc_coherent(&lmdev->dev,
551	DWC_OTG_HCD_STATUS_BUF_SIZE,
552	&dwc_otg_hcd->status_buf_dma,
553	GFP_KERNEL \| GFP_DMA);
554	} else {
555	dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
556	GFP_KERNEL);
557	}
558	if (!dwc_otg_hcd->status_buf) {
559	retval = -ENOMEM;
560	DWC_ERROR("%s: status_buf allocation failed\n", __func__);
561	goto error3;
562	}
563
564	dwc_otg_hcd->otg_dev = otg_dev;
565
566	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
567	lmdev->dev.bus_id, hcd->self.busnum);
568
569	return 0;
570
571	/* Error conditions */
572	error3:
573	usb_remove_hcd(hcd);
574	error2:
575	dwc_otg_hcd_free(hcd);
576	usb_put_hcd(hcd);
577
578	/* FIXME: 2008/05/03 by Steven
579	* write back to lmdev:
580	* dwc_otg_hcd has already been released by dwc_otg_hcd_free()
581	*/
582	lm_set_drvdata( lmdev, otg_dev);
583
584	error1:
585	return retval;
586	}
587
588	/**
589	* Removes the HCD.
590	* Frees memory and resources associated with the HCD and deregisters the bus.
591	*/
592	void dwc_otg_hcd_remove(struct lm_device *lmdev)
593	{
594	dwc_otg_device_t *otg_dev = lm_get_drvdata(lmdev);
595	dwc_otg_hcd_t *dwc_otg_hcd;
596	struct usb_hcd *hcd;
597
598	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
599
600	if (!otg_dev) {
601	DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
602	return;
603	}
604
605	dwc_otg_hcd = otg_dev->hcd;
606
607	if (!dwc_otg_hcd) {
608	DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
609	return;
610	}
611
612	hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
613
614	if (!hcd) {
615	DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__);
616	return;
617	}
618
619	/* Turn off all interrupts */
620	dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
621	dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
622
623	usb_remove_hcd(hcd);
624	dwc_otg_hcd_free(hcd);
625	usb_put_hcd(hcd);
626	}
627
628	/* =========================================================================
629	* Linux HC Driver Functions
630	* ========================================================================= */
631
632	/**
633	* Initializes dynamic portions of the DWC_otg HCD state.
634	*/
635	static void hcd_reinit(dwc_otg_hcd_t *hcd)
636	{
637	struct list_head *item;
638	int num_channels;
639	int i;
640	dwc_hc_t *channel;
641
642	hcd->flags.d32 = 0;
643
644	hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
645	hcd->non_periodic_channels = 0;
646	hcd->periodic_channels = 0;
647
648	/*
649	* Put all channels in the free channel list and clean up channel
650	* states.
651	*/
652	item = hcd->free_hc_list.next;
653	while (item != &hcd->free_hc_list) {
654	list_del(item);
655	item = hcd->free_hc_list.next;
656	}
657	num_channels = hcd->core_if->core_params->host_channels;
658	for (i = 0; i < num_channels; i++) {
659	channel = hcd->hc_ptr_array[i];
660	list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list);
661	dwc_otg_hc_cleanup(hcd->core_if, channel);
662	}
663
664	/* Initialize the DWC core for host mode operation. */
665	dwc_otg_core_host_init(hcd->core_if);
666	}
667
668	/** Initializes the DWC_otg controller and its root hub and prepares it for host
669	* mode operation. Activates the root port. Returns 0 on success and a negative
670	* error code on failure. */
671	int dwc_otg_hcd_start(struct usb_hcd *hcd)
672	{
673	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
674	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
675	struct usb_bus *bus;
676
677	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
678	struct usb_device *udev;
679	int retval;
680	#endif
681
682	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
683
684	bus = hcd_to_bus(hcd);
685
686	/* Initialize the bus state. If the core is in Device Mode
687	* HALT the USB bus and return. */
688	if (dwc_otg_is_device_mode(core_if)) {
689	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
690	hcd->state = HC_STATE_HALT;
691	#else
692	hcd->state = HC_STATE_RUNNING;
693	#endif
694	return 0;
695	}
696	hcd->state = HC_STATE_RUNNING;
697
698	/* Initialize and connect root hub if one is not already attached */
699	if (bus->root_hub) {
700	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
701	/* Inform the HUB driver to resume. */
702	usb_hcd_resume_root_hub(hcd);
703	}
704	else {
705	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n");
706
707	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
708	udev = usb_alloc_dev(NULL, bus, 0);
709	udev->speed = USB_SPEED_HIGH;
710	if (!udev) {
711	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
712	return -ENODEV;
713	}
714	if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) {
715	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
716	return -ENODEV;
717	}
718	#endif
719	}
720
721	hcd_reinit(dwc_otg_hcd);
722
723	return 0;
724	}
725
726	static void qh_list_free(dwc_otg_hcd_t hcd, struct list_head qh_list)
727	{
728	struct list_head *item;
729	dwc_otg_qh_t *qh;
730
731	if (!qh_list->next) {
732	/* The list hasn't been initialized yet. */
733	return;
734	}
735
736	/* Ensure there are no QTDs or URBs left. */
737	kill_urbs_in_qh_list(hcd, qh_list);
738
739	for (item = qh_list->next; item != qh_list; item = qh_list->next) {
740	qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
741	dwc_otg_hcd_qh_remove_and_free(hcd, qh);
742	}
743	}
744
745	/**
746	* Halts the DWC_otg host mode operations in a clean manner. USB transfers are
747	* stopped.
748	*/
749	void dwc_otg_hcd_stop(struct usb_hcd *hcd)
750	{
751	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
752	hprt0_data_t hprt0 = { .d32=0 };
753
754	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
755
756	/* Turn off all host-specific interrupts. */
757	dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
758
759	/*
760	* The root hub should be disconnected before this function is called.
761	* The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
762	* and the QH lists (via ..._hcd_endpoint_disable).
763	*/
764
765	/* Turn off the vbus power */
766	DWC_PRINT("PortPower off\n");
767	hprt0.b.prtpwr = 0;
768	dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
769	}
770
771	/** Returns the current frame number. */
772	int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd)
773	{
774	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
775	hfnum_data_t hfnum;
776
777	hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
778	host_if->host_global_regs->hfnum);
779
780	#ifdef DEBUG_SOF
781	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
782	#endif
783	return hfnum.b.frnum;
784	}
785
786	/**
787	* Frees secondary storage associated with the dwc_otg_hcd structure contained
788	* in the struct usb_hcd field.
789	*/
790	void dwc_otg_hcd_free(struct usb_hcd *hcd)
791	{
792	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
793	int i;
794
795	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
796
797	del_timers(dwc_otg_hcd);
798
799	/* Free memory for QH/QTD lists */
800	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
801	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
802	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
803	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
804	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
805	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
806
807	/* Free memory for the host channels. */
808	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
809	dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
810	if (hc != NULL) {
811	DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
812	kfree(hc);
813	}
814	}
815
816	if (dwc_otg_hcd->core_if->dma_enable) {
817	if (dwc_otg_hcd->status_buf_dma) {
818	dma_free_coherent(hcd->self.controller,
819	DWC_OTG_HCD_STATUS_BUF_SIZE,
820	dwc_otg_hcd->status_buf,
821	dwc_otg_hcd->status_buf_dma);
822	}
823	} else if (dwc_otg_hcd->status_buf != NULL) {
824	kfree(dwc_otg_hcd->status_buf);
825	}
826	}
827
828	#ifdef DEBUG
829	static void dump_urb_info(struct urb urb, char fn_name)
830	{
831	DWC_PRINT("%s, urb %p\n", fn_name, urb);
832	DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe));
833	DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
834	(usb_pipein(urb->pipe) ? "IN" : "OUT"));
835	DWC_PRINT(" Endpoint type: %s\n",
836	({char *pipetype;
837	switch (usb_pipetype(urb->pipe)) {
838	case PIPE_CONTROL: pipetype = "CONTROL"; break;
839	case PIPE_BULK: pipetype = "BULK"; break;
840	case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
841	case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
842	default: pipetype = "UNKNOWN"; break;
843	}; pipetype;}));
844	DWC_PRINT(" Speed: %s\n",
845	({char *speed;
846	switch (urb->dev->speed) {
847	case USB_SPEED_HIGH: speed = "HIGH"; break;
848	case USB_SPEED_FULL: speed = "FULL"; break;
849	case USB_SPEED_LOW: speed = "LOW"; break;
850	default: speed = "UNKNOWN"; break;
851	}; speed;}));
852	DWC_PRINT(" Max packet size: %d\n",
853	usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
854	DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length);
855	DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
856	urb->transfer_buffer, (void *)urb->transfer_dma);
857	DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
858	urb->setup_packet, (void *)urb->setup_dma);
859	DWC_PRINT(" Interval: %d\n", urb->interval);
860	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
861	int i;
862	for (i = 0; i < urb->number_of_packets; i++) {
863	DWC_PRINT(" ISO Desc %d:\n", i);
864	DWC_PRINT(" offset: %d, length %d\n",
865	urb->iso_frame_desc[i].offset,
866	urb->iso_frame_desc[i].length);
867	}
868	}
869	}
870
871	static void dump_channel_info(dwc_otg_hcd_t *hcd,
872	dwc_otg_qh_t *qh)
873	{
874	if (qh->channel != NULL) {
875	dwc_hc_t *hc = qh->channel;
876	struct list_head *item;
877	dwc_otg_qh_t *qh_item;
878	int num_channels = hcd->core_if->core_params->host_channels;
879	int i;
880
881	dwc_otg_hc_regs_t *hc_regs;
882	hcchar_data_t hcchar;
883	hcsplt_data_t hcsplt;
884	hctsiz_data_t hctsiz;
885	uint32_t hcdma;
886
887	hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
888	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
889	hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
890	hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
891	hcdma = dwc_read_reg32(&hc_regs->hcdma);
892
893	DWC_PRINT(" Assigned to channel %p:\n", hc);
894	DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
895	DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
896	DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
897	hc->dev_addr, hc->ep_num, hc->ep_is_in);
898	DWC_PRINT(" ep_type: %d\n", hc->ep_type);
899	DWC_PRINT(" max_packet: %d\n", hc->max_packet);
900	DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
901	DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
902	DWC_PRINT(" halt_status: %d\n", hc->halt_status);
903	DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
904	DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
905	DWC_PRINT(" qh: %p\n", hc->qh);
906	DWC_PRINT(" NP inactive sched:\n");
907	list_for_each(item, &hcd->non_periodic_sched_inactive) {
908	qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
909	DWC_PRINT(" %p\n", qh_item);
910	}
911	DWC_PRINT(" NP active sched:\n");
912	list_for_each(item, &hcd->non_periodic_sched_active) {
913	qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
914	DWC_PRINT(" %p\n", qh_item);
915	}
916	DWC_PRINT(" Channels: \n");
917	for (i = 0; i < num_channels; i++) {
918	dwc_hc_t *hc = hcd->hc_ptr_array[i];
919	DWC_PRINT(" %2d: %p\n", i, hc);
920	}
921	}
922	}
923	#endif
924
925	/** Starts processing a USB transfer request specified by a USB Request Block
926	* (URB). mem_flags indicates the type of memory allocation to use while
927	* processing this URB. */
928	int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
929	struct usb_host_endpoint *ep,
930	struct urb *urb,
931	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
932	int mem_flags
933	#else
934	gfp_t mem_flags
935	#endif
936	)
937	{
938	int retval = 0;
939	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
940	dwc_otg_qtd_t *qtd;
941
942	#ifdef DEBUG
943	if (CHK_DEBUG_LEVEL(DBG_HCDV \| DBG_HCD_URB)) {
944	dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
945	}
946	#endif
947	if (!dwc_otg_hcd->flags.b.port_connect_status) {
948	/* No longer connected. */
949	return -ENODEV;
950	}
951
952	qtd = dwc_otg_hcd_qtd_create(urb);
953	if (qtd == NULL) {
954	DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
955	return -ENOMEM;
956	}
957
958	retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
959	if (retval < 0) {
960	DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
961	"Error status %d\n", retval);
962	dwc_otg_hcd_qtd_free(qtd);
963	}
964
965	return retval;
966	}
967
968	/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
969	* success. */
970	int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
971	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
972	struct usb_host_endpoint *ep,
973	#endif
974	struct urb *urb)
975	{
976	unsigned long flags;
977	dwc_otg_hcd_t *dwc_otg_hcd;
978	dwc_otg_qtd_t *urb_qtd;
979	dwc_otg_qh_t *qh;
980	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
981	struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
982	#endif
983
984	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
985
986	dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
987
988	SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
989
990	urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
991	qh = (dwc_otg_qh_t *)ep->hcpriv;
992
993	#ifdef DEBUG
994	if (CHK_DEBUG_LEVEL(DBG_HCDV \| DBG_HCD_URB)) {
995	dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
996	if (urb_qtd == qh->qtd_in_process) {
997	dump_channel_info(dwc_otg_hcd, qh);
998	}
999	}
1000	#endif
1001
1002	if (urb_qtd == qh->qtd_in_process) {
1003	/* The QTD is in process (it has been assigned to a channel). */
1004
1005	if (dwc_otg_hcd->flags.b.port_connect_status) {
1006	/*
1007	* If still connected (i.e. in host mode), halt the
1008	* channel so it can be used for other transfers. If
1009	* no longer connected, the host registers can't be
1010	* written to halt the channel since the core is in
1011	* device mode.
1012	*/
1013	dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1014	DWC_OTG_HC_XFER_URB_DEQUEUE);
1015	}
1016	}
1017
1018	/*
1019	* Free the QTD and clean up the associated QH. Leave the QH in the
1020	* schedule if it has any remaining QTDs.
1021	*/
1022	dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
1023	if (urb_qtd == qh->qtd_in_process) {
1024	dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1025	qh->channel = NULL;
1026	qh->qtd_in_process = NULL;
1027	} else if (list_empty(&qh->qtd_list)) {
1028	dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1029	}
1030
1031	SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
1032
1033	urb->hcpriv = NULL;
1034
1035	/* Higher layer software sets URB status. */
1036	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1037	usb_hcd_giveback_urb(hcd, urb);
1038	#else
1039	usb_hcd_giveback_urb(hcd, urb, NULL);
1040	#endif
1041	if (CHK_DEBUG_LEVEL(DBG_HCDV \| DBG_HCD_URB)) {
1042	DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1043	DWC_PRINT(" urb->status = %d\n", urb->status);
1044	}
1045
1046	return 0;
1047	}
1048
1049	/** Frees resources in the DWC_otg controller related to a given endpoint. Also
1050	* clears state in the HCD related to the endpoint. Any URBs for the endpoint
1051	* must already be dequeued. */
1052	void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
1053	struct usb_host_endpoint *ep)
1054	{
1055	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1056	dwc_otg_qh_t *qh;
1057
1058	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1059	unsigned long flags;
1060	int retry = 0;
1061	#endif
1062
1063	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1064	"endpoint=%d\n", ep->desc.bEndpointAddress,
1065	dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
1066
1067	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1068	rescan:
1069	SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
1070	qh = (dwc_otg_qh_t *)(ep->hcpriv);
1071	if (!qh)
1072	goto done;
1073
1074	/** Check that the QTD list is really empty */
1075	if (!list_empty(&qh->qtd_list)) {
1076	if (retry++ < 250) {
1077	SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
1078	schedule_timeout_uninterruptible(1);
1079	goto rescan;
1080	}
1081
1082	DWC_WARN("DWC OTG HCD EP DISABLE:"
1083	" QTD List for this endpoint is not empty\n");
1084	}
1085
1086	dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1087	ep->hcpriv = NULL;
1088	done:
1089	SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
1090
1091	#else // LINUX_VERSION_CODE
1092
1093	qh = (dwc_otg_qh_t *)(ep->hcpriv);
1094	if (qh != NULL) {
1095	#ifdef DEBUG
1096	/** Check that the QTD list is really empty */
1097	if (!list_empty(&qh->qtd_list)) {
1098	DWC_WARN("DWC OTG HCD EP DISABLE:"
1099	" QTD List for this endpoint is not empty\n");
1100	}
1101	#endif
1102	dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1103	ep->hcpriv = NULL;
1104	}
1105	#endif // LINUX_VERSION_CODE
1106	}
1107
1108	/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1109	* there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1110	* interrupt.
1111	*
1112	* This function is called by the USB core when an interrupt occurs */
1113	irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd
1114	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
1115	, struct pt_regs *regs
1116	#endif
1117	)
1118	{
1119	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1120	return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1121	}
1122
1123	/** Creates Status Change bitmap for the root hub and root port. The bitmap is
1124	* returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1125	* is the status change indicator for the single root port. Returns 1 if either
1126	* change indicator is 1, otherwise returns 0. */
1127	int dwc_otg_hcd_hub_status_data(struct usb_hcd hcd, char buf)
1128	{
1129	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1130
1131	buf[0] = 0;
1132	buf[0] \|= (dwc_otg_hcd->flags.b.port_connect_status_change \|\|
1133	dwc_otg_hcd->flags.b.port_reset_change \|\|
1134	dwc_otg_hcd->flags.b.port_enable_change \|\|
1135	dwc_otg_hcd->flags.b.port_suspend_change \|\|
1136	dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1137
1138	#ifdef DEBUG
1139	if (buf[0]) {
1140	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1141	" Root port status changed\n");
1142	DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
1143	dwc_otg_hcd->flags.b.port_connect_status_change);
1144	DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
1145	dwc_otg_hcd->flags.b.port_reset_change);
1146	DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
1147	dwc_otg_hcd->flags.b.port_enable_change);
1148	DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
1149	dwc_otg_hcd->flags.b.port_suspend_change);
1150	DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
1151	dwc_otg_hcd->flags.b.port_over_current_change);
1152	}
1153	#endif
1154	return (buf[0] != 0);
1155	}
1156
1157	#ifdef DWC_HS_ELECT_TST
1158	/*
1159	* Quick and dirty hack to implement the HS Electrical Test
1160	* SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1161	*
1162	* This code was copied from our userspace app "hset". It sends a
1163	* Get Device Descriptor control sequence in two parts, first the
1164	* Setup packet by itself, followed some time later by the In and
1165	* Ack packets. Rather than trying to figure out how to add this
1166	* functionality to the normal driver code, we just hijack the
1167	* hardware, using these two function to drive the hardware
1168	* directly.
1169	*/
1170
1171	dwc_otg_core_global_regs_t *global_regs;
1172	dwc_otg_host_global_regs_t *hc_global_regs;
1173	dwc_otg_hc_regs_t *hc_regs;
1174	uint32_t *data_fifo;
1175
1176	static void do_setup(void)
1177	{
1178	gintsts_data_t gintsts;
1179	hctsiz_data_t hctsiz;
1180	hcchar_data_t hcchar;
1181	haint_data_t haint;
1182	hcint_data_t hcint;
1183
1184	/* Enable HAINTs */
1185	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1186
1187	/* Enable HCINTs */
1188	dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1189
1190	/* Read GINTSTS */
1191	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1192	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1193
1194	/* Read HAINT */
1195	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1196	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1197
1198	/* Read HCINT */
1199	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1200	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1201
1202	/* Read HCCHAR */
1203	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1204	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1205
1206	/* Clear HCINT */
1207	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1208
1209	/* Clear HAINT */
1210	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1211
1212	/* Clear GINTSTS */
1213	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1214
1215	/* Read GINTSTS */
1216	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1217	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1218
1219	/*
1220	* Send Setup packet (Get Device Descriptor)
1221	*/
1222
1223	/* Make sure channel is disabled */
1224	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1225	if (hcchar.b.chen) {
1226	//fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1227	hcchar.b.chdis = 1;
1228	// hcchar.b.chen = 1;
1229	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1230	//sleep(1);
1231	mdelay(1000);
1232
1233	/* Read GINTSTS */
1234	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1235	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1236
1237	/* Read HAINT */
1238	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1239	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1240
1241	/* Read HCINT */
1242	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1243	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1244
1245	/* Read HCCHAR */
1246	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1247	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1248
1249	/* Clear HCINT */
1250	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1251
1252	/* Clear HAINT */
1253	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1254
1255	/* Clear GINTSTS */
1256	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1257
1258	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1259	//if (hcchar.b.chen) {
1260	// fprintf(stderr, " Channel _still_ enabled 1, HCCHAR = %08x \n", hcchar.d32);
1261	//}
1262	}
1263
1264	/* Set HCTSIZ */
1265	hctsiz.d32 = 0;
1266	hctsiz.b.xfersize = 8;
1267	hctsiz.b.pktcnt = 1;
1268	hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1269	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1270
1271	/* Set HCCHAR */
1272	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1273	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1274	hcchar.b.epdir = 0;
1275	hcchar.b.epnum = 0;
1276	hcchar.b.mps = 8;
1277	hcchar.b.chen = 1;
1278	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1279
1280	/* Fill FIFO with Setup data for Get Device Descriptor */
1281	data_fifo = (uint32_t )((char )global_regs + 0x1000);
1282	dwc_write_reg32(data_fifo++, 0x01000680);
1283	dwc_write_reg32(data_fifo++, 0x00080000);
1284
1285	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1286	//fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1287
1288	/* Wait for host channel interrupt */
1289	do {
1290	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1291	} while (gintsts.b.hcintr == 0);
1292
1293	//fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1294
1295	/* Disable HCINTs */
1296	dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1297
1298	/* Disable HAINTs */
1299	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1300
1301	/* Read HAINT */
1302	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1303	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1304
1305	/* Read HCINT */
1306	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1307	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1308
1309	/* Read HCCHAR */
1310	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1311	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1312
1313	/* Clear HCINT */
1314	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1315
1316	/* Clear HAINT */
1317	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1318
1319	/* Clear GINTSTS */
1320	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1321
1322	/* Read GINTSTS */
1323	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1324	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1325	}
1326
1327	static void do_in_ack(void)
1328	{
1329	gintsts_data_t gintsts;
1330	hctsiz_data_t hctsiz;
1331	hcchar_data_t hcchar;
1332	haint_data_t haint;
1333	hcint_data_t hcint;
1334	host_grxsts_data_t grxsts;
1335
1336	/* Enable HAINTs */
1337	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1338
1339	/* Enable HCINTs */
1340	dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1341
1342	/* Read GINTSTS */
1343	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1344	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1345
1346	/* Read HAINT */
1347	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1348	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1349
1350	/* Read HCINT */
1351	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1352	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1353
1354	/* Read HCCHAR */
1355	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1356	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1357
1358	/* Clear HCINT */
1359	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1360
1361	/* Clear HAINT */
1362	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1363
1364	/* Clear GINTSTS */
1365	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1366
1367	/* Read GINTSTS */
1368	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1369	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1370
1371	/*
1372	* Receive Control In packet
1373	*/
1374
1375	/* Make sure channel is disabled */
1376	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1377	if (hcchar.b.chen) {
1378	//fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1379	hcchar.b.chdis = 1;
1380	hcchar.b.chen = 1;
1381	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1382	//sleep(1);
1383	mdelay(1000);
1384
1385	/* Read GINTSTS */
1386	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1387	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1388
1389	/* Read HAINT */
1390	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1391	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1392
1393	/* Read HCINT */
1394	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1395	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1396
1397	/* Read HCCHAR */
1398	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1399	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1400
1401	/* Clear HCINT */
1402	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1403
1404	/* Clear HAINT */
1405	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1406
1407	/* Clear GINTSTS */
1408	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1409
1410	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1411	//if (hcchar.b.chen) {
1412	// fprintf(stderr, " Channel _still_ enabled 2, HCCHAR = %08x \n", hcchar.d32);
1413	//}
1414	}
1415
1416	/* Set HCTSIZ */
1417	hctsiz.d32 = 0;
1418	hctsiz.b.xfersize = 8;
1419	hctsiz.b.pktcnt = 1;
1420	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1421	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1422
1423	/* Set HCCHAR */
1424	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1425	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1426	hcchar.b.epdir = 1;
1427	hcchar.b.epnum = 0;
1428	hcchar.b.mps = 8;
1429	hcchar.b.chen = 1;
1430	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1431
1432	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1433	//fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
1434
1435	/* Wait for receive status queue interrupt */
1436	do {
1437	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1438	} while (gintsts.b.rxstsqlvl == 0);
1439
1440	//fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
1441
1442	/* Read RXSTS */
1443	grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
1444	//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
1445
1446	/* Clear RXSTSQLVL in GINTSTS */
1447	gintsts.d32 = 0;
1448	gintsts.b.rxstsqlvl = 1;
1449	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1450
1451	switch (grxsts.b.pktsts) {
1452	case DWC_GRXSTS_PKTSTS_IN:
1453	/* Read the data into the host buffer */
1454	if (grxsts.b.bcnt > 0) {
1455	int i;
1456	int word_count = (grxsts.b.bcnt + 3) / 4;
1457
1458	data_fifo = (uint32_t )((char )global_regs + 0x1000);
1459
1460	for (i = 0; i < word_count; i++) {
1461	(void)dwc_read_reg32(data_fifo++);
1462	}
1463	}
1464
1465	//fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
1466	break;
1467
1468	default:
1469	//fprintf(stderr, " Unexpected GRXSTS packet status 1 \n");
1470	break;
1471	}
1472
1473	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1474	//fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
1475
1476	/* Wait for receive status queue interrupt */
1477	do {
1478	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1479	} while (gintsts.b.rxstsqlvl == 0);
1480
1481	//fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
1482
1483	/* Read RXSTS */
1484	grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
1485	//fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
1486
1487	/* Clear RXSTSQLVL in GINTSTS */
1488	gintsts.d32 = 0;
1489	gintsts.b.rxstsqlvl = 1;
1490	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1491
1492	switch (grxsts.b.pktsts) {
1493	case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1494	break;
1495
1496	default:
1497	//fprintf(stderr, " Unexpected GRXSTS packet status 2 \n");
1498	break;
1499	}
1500
1501	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1502	//fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
1503
1504	/* Wait for host channel interrupt */
1505	do {
1506	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1507	} while (gintsts.b.hcintr == 0);
1508
1509	//fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
1510
1511	/* Read HAINT */
1512	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1513	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1514
1515	/* Read HCINT */
1516	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1517	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1518
1519	/* Read HCCHAR */
1520	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1521	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1522
1523	/* Clear HCINT */
1524	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1525
1526	/* Clear HAINT */
1527	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1528
1529	/* Clear GINTSTS */
1530	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1531
1532	/* Read GINTSTS */
1533	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1534	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1535
1536	// usleep(100000);
1537	// mdelay(100);
1538	mdelay(1);
1539
1540	/*
1541	* Send handshake packet
1542	*/
1543
1544	/* Read HAINT */
1545	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1546	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1547
1548	/* Read HCINT */
1549	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1550	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1551
1552	/* Read HCCHAR */
1553	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1554	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1555
1556	/* Clear HCINT */
1557	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1558
1559	/* Clear HAINT */
1560	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1561
1562	/* Clear GINTSTS */
1563	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1564
1565	/* Read GINTSTS */
1566	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1567	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1568
1569	/* Make sure channel is disabled */
1570	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1571	if (hcchar.b.chen) {
1572	//fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
1573	hcchar.b.chdis = 1;
1574	hcchar.b.chen = 1;
1575	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1576	//sleep(1);
1577	mdelay(1000);
1578
1579	/* Read GINTSTS */
1580	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1581	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1582
1583	/* Read HAINT */
1584	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1585	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1586
1587	/* Read HCINT */
1588	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1589	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1590
1591	/* Read HCCHAR */
1592	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1593	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1594
1595	/* Clear HCINT */
1596	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1597
1598	/* Clear HAINT */
1599	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1600
1601	/* Clear GINTSTS */
1602	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1603
1604	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1605	//if (hcchar.b.chen) {
1606	// fprintf(stderr, " Channel _still_ enabled 3, HCCHAR = %08x \n", hcchar.d32);
1607	//}
1608	}
1609
1610	/* Set HCTSIZ */
1611	hctsiz.d32 = 0;
1612	hctsiz.b.xfersize = 0;
1613	hctsiz.b.pktcnt = 1;
1614	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1615	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1616
1617	/* Set HCCHAR */
1618	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1619	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1620	hcchar.b.epdir = 0;
1621	hcchar.b.epnum = 0;
1622	hcchar.b.mps = 8;
1623	hcchar.b.chen = 1;
1624	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1625
1626	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1627	//fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
1628
1629	/* Wait for host channel interrupt */
1630	do {
1631	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1632	} while (gintsts.b.hcintr == 0);
1633
1634	//fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
1635
1636	/* Disable HCINTs */
1637	dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1638
1639	/* Disable HAINTs */
1640	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1641
1642	/* Read HAINT */
1643	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1644	//fprintf(stderr, "HAINT: %08x\n", haint.d32);
1645
1646	/* Read HCINT */
1647	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1648	//fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1649
1650	/* Read HCCHAR */
1651	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1652	//fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1653
1654	/* Clear HCINT */
1655	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1656
1657	/* Clear HAINT */
1658	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1659
1660	/* Clear GINTSTS */
1661	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1662
1663	/* Read GINTSTS */
1664	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1665	//fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1666	}
1667	#endif /* DWC_HS_ELECT_TST */
1668
1669	/** Handles hub class-specific requests. */
1670	int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
1671	u16 typeReq,
1672	u16 wValue,
1673	u16 wIndex,
1674	char *buf,
1675	u16 wLength)
1676	{
1677	int retval = 0;
1678
1679	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1680	dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if;
1681	struct usb_hub_descriptor *desc;
1682	hprt0_data_t hprt0 = {.d32 = 0};
1683
1684	uint32_t port_status;
1685
1686	switch (typeReq) {
1687	case ClearHubFeature:
1688	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1689	"ClearHubFeature 0x%x\n", wValue);
1690	switch (wValue) {
1691	case C_HUB_LOCAL_POWER:
1692	case C_HUB_OVER_CURRENT:
1693	/* Nothing required here */
1694	break;
1695	default:
1696	retval = -EINVAL;
1697	DWC_ERROR("DWC OTG HCD - "
1698	"ClearHubFeature request %xh unknown\n", wValue);
1699	}
1700	break;
1701	case ClearPortFeature:
1702	if (!wIndex \|\| wIndex > 1)
1703	goto error;
1704
1705	switch (wValue) {
1706	case USB_PORT_FEAT_ENABLE:
1707	DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
1708	"ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1709	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1710	hprt0.b.prtena = 1;
1711	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1712	break;
1713	case USB_PORT_FEAT_SUSPEND:
1714	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1715	"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1716	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1717	hprt0.b.prtres = 1;
1718	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1719	/* Clear Resume bit */
1720	mdelay(100);
1721	hprt0.b.prtres = 0;
1722	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1723	break;
1724	case USB_PORT_FEAT_POWER:
1725	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1726	"ClearPortFeature USB_PORT_FEAT_POWER\n");
1727	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1728	hprt0.b.prtpwr = 0;
1729	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1730	break;
1731	case USB_PORT_FEAT_INDICATOR:
1732	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1733	"ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1734	/* Port inidicator not supported */
1735	break;
1736	case USB_PORT_FEAT_C_CONNECTION:
1737	/* Clears drivers internal connect status change
1738	* flag */
1739	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1740	"ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1741	dwc_otg_hcd->flags.b.port_connect_status_change = 0;
1742	break;
1743	case USB_PORT_FEAT_C_RESET:
1744	/* Clears the driver's internal Port Reset Change
1745	* flag */
1746	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1747	"ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1748	dwc_otg_hcd->flags.b.port_reset_change = 0;
1749	break;
1750	case USB_PORT_FEAT_C_ENABLE:
1751	/* Clears the driver's internal Port
1752	* Enable/Disable Change flag */
1753	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1754	"ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1755	dwc_otg_hcd->flags.b.port_enable_change = 0;
1756	break;
1757	case USB_PORT_FEAT_C_SUSPEND:
1758	/* Clears the driver's internal Port Suspend
1759	* Change flag, which is set when resume signaling on
1760	* the host port is complete */
1761	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1762	"ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1763	dwc_otg_hcd->flags.b.port_suspend_change = 0;
1764	break;
1765	case USB_PORT_FEAT_C_OVER_CURRENT:
1766	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1767	"ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1768	dwc_otg_hcd->flags.b.port_over_current_change = 0;
1769	break;
1770	default:
1771	retval = -EINVAL;
1772	DWC_ERROR("DWC OTG HCD - "
1773	"ClearPortFeature request %xh "
1774	"unknown or unsupported\n", wValue);
1775	}
1776	break;
1777	case GetHubDescriptor:
1778	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1779	"GetHubDescriptor\n");
1780	desc = (struct usb_hub_descriptor *)buf;
1781	desc->bDescLength = 9;
1782	desc->bDescriptorType = 0x29;
1783	desc->bNbrPorts = 1;
1784	desc->wHubCharacteristics = 0x08;
1785	desc->bPwrOn2PwrGood = 1;
1786	desc->bHubContrCurrent = 0;
1787	desc->bitmap[0] = 0;
1788	desc->bitmap[1] = 0xff;
1789	break;
1790	case GetHubStatus:
1791	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1792	"GetHubStatus\n");
1793	memset(buf, 0, 4);
1794	break;
1795	case GetPortStatus:
1796	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1797	"GetPortStatus\n");
1798
1799	if (!wIndex \|\| wIndex > 1)
1800	goto error;
1801
1802	port_status = 0;
1803
1804	if (dwc_otg_hcd->flags.b.port_connect_status_change)
1805	port_status \|= (1 << USB_PORT_FEAT_C_CONNECTION);
1806
1807	if (dwc_otg_hcd->flags.b.port_enable_change)
1808	port_status \|= (1 << USB_PORT_FEAT_C_ENABLE);
1809
1810	if (dwc_otg_hcd->flags.b.port_suspend_change)
1811	port_status \|= (1 << USB_PORT_FEAT_C_SUSPEND);
1812
1813	if (dwc_otg_hcd->flags.b.port_reset_change)
1814	port_status \|= (1 << USB_PORT_FEAT_C_RESET);
1815
1816	if (dwc_otg_hcd->flags.b.port_over_current_change) {
1817	DWC_ERROR("Device Not Supported\n");
1818	port_status \|= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
1819	}
1820
1821	if (!dwc_otg_hcd->flags.b.port_connect_status) {
1822	/*
1823	* The port is disconnected, which means the core is
1824	* either in device mode or it soon will be. Just
1825	* return 0's for the remainder of the port status
1826	* since the port register can't be read if the core
1827	* is in device mode.
1828	*/
1829	((__le32 ) buf) = cpu_to_le32(port_status);
1830	break;
1831	}
1832
1833	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
1834	DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
1835
1836	if (hprt0.b.prtconnsts)
1837	port_status \|= (1 << USB_PORT_FEAT_CONNECTION);
1838
1839	if (hprt0.b.prtena)
1840	port_status \|= (1 << USB_PORT_FEAT_ENABLE);
1841
1842	if (hprt0.b.prtsusp)
1843	port_status \|= (1 << USB_PORT_FEAT_SUSPEND);
1844
1845	if (hprt0.b.prtovrcurract)
1846	port_status \|= (1 << USB_PORT_FEAT_OVER_CURRENT);
1847
1848	if (hprt0.b.prtrst)
1849	port_status \|= (1 << USB_PORT_FEAT_RESET);
1850
1851	if (hprt0.b.prtpwr)
1852	port_status \|= (1 << USB_PORT_FEAT_POWER);
1853
1854	if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
1855	port_status \|= (1 << USB_PORT_FEAT_HIGHSPEED);
1856	else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
1857	port_status \|= (1 << USB_PORT_FEAT_LOWSPEED);
1858
1859	if (hprt0.b.prttstctl)
1860	port_status \|= (1 << USB_PORT_FEAT_TEST);
1861
1862	/* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1863
1864	((__le32 ) buf) = cpu_to_le32(port_status);
1865
1866	break;
1867	case SetHubFeature:
1868	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1869	"SetHubFeature\n");
1870	/* No HUB features supported */
1871	break;
1872	case SetPortFeature:
1873	if (wValue != USB_PORT_FEAT_TEST && (!wIndex \|\| wIndex > 1))
1874	goto error;
1875
1876	if (!dwc_otg_hcd->flags.b.port_connect_status) {
1877	/*
1878	* The port is disconnected, which means the core is
1879	* either in device mode or it soon will be. Just
1880	* return without doing anything since the port
1881	* register can't be written if the core is in device
1882	* mode.
1883	*/
1884	break;
1885	}
1886
1887	switch (wValue) {
1888	case USB_PORT_FEAT_SUSPEND:
1889	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1890	"SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1891	if (hcd->self.otg_port == wIndex &&
1892	hcd->self.b_hnp_enable) {
1893	gotgctl_data_t gotgctl = {.d32=0};
1894	gotgctl.b.hstsethnpen = 1;
1895	dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
1896	0, gotgctl.d32);
1897	core_if->op_state = A_SUSPEND;
1898	}
1899	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1900	hprt0.b.prtsusp = 1;
1901	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1902	//DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32);
1903	/* Suspend the Phy Clock */
1904	{
1905	pcgcctl_data_t pcgcctl = {.d32=0};
1906	pcgcctl.b.stoppclk = 1;
1907	dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
1908	}
1909
1910	/* For HNP the bus must be suspended for at least 200ms. */
1911	if (hcd->self.b_hnp_enable) {
1912	mdelay(200);
1913	//DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);
1914	}
1915	break;
1916	case USB_PORT_FEAT_POWER:
1917	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1918	"SetPortFeature - USB_PORT_FEAT_POWER\n");
1919	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1920	hprt0.b.prtpwr = 1;
1921	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1922	break;
1923	case USB_PORT_FEAT_RESET:
1924	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1925	"SetPortFeature - USB_PORT_FEAT_RESET\n");
1926	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1927	/* When B-Host the Port reset bit is set in
1928	* the Start HCD Callback function, so that
1929	* the reset is started within 1ms of the HNP
1930	* success interrupt. */
1931	if (!hcd->self.is_b_host) {
1932	hprt0.b.prtrst = 1;
1933	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1934	}
1935	/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1936	MDELAY(60);
1937	hprt0.b.prtrst = 0;
1938	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1939	break;
1940
1941	#ifdef DWC_HS_ELECT_TST
1942	case USB_PORT_FEAT_TEST:
1943	{
1944	uint32_t t;
1945	gintmsk_data_t gintmsk;
1946
1947	t = (wIndex >> 8); /* MSB wIndex USB */
1948	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
1949	"SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
1950	warn("USB_PORT_FEAT_TEST %d\n", t);
1951	if (t < 6) {
1952	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1953	hprt0.b.prttstctl = t;
1954	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1955	} else {
1956	/* Setup global vars with reg addresses (quick and
1957	* dirty hack, should be cleaned up)
1958	*/
1959	global_regs = core_if->core_global_regs;
1960	hc_global_regs = core_if->host_if->host_global_regs;
1961	hc_regs = (dwc_otg_hc_regs_t )((char )global_regs + 0x500);
1962	data_fifo = (uint32_t )((char )global_regs + 0x1000);
1963
1964	if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
1965	/* Save current interrupt mask */
1966	gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
1967
1968	/* Disable all interrupts while we muck with
1969	* the hardware directly
1970	*/
1971	dwc_write_reg32(&global_regs->gintmsk, 0);
1972
1973	/* 15 second delay per the test spec */
1974	mdelay(15000);
1975
1976	/* Drive suspend on the root port */
1977	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1978	hprt0.b.prtsusp = 1;
1979	hprt0.b.prtres = 0;
1980	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1981
1982	/* 15 second delay per the test spec */
1983	mdelay(15000);
1984
1985	/* Drive resume on the root port */
1986	hprt0.d32 = dwc_otg_read_hprt0(core_if);
1987	hprt0.b.prtsusp = 0;
1988	hprt0.b.prtres = 1;
1989	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1990	mdelay(100);
1991
1992	/* Clear the resume bit */
1993	hprt0.b.prtres = 0;
1994	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
1995
1996	/* Restore interrupts */
1997	dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
1998	} else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
1999	/* Save current interrupt mask */
2000	gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2001
2002	/* Disable all interrupts while we muck with
2003	* the hardware directly
2004	*/
2005	dwc_write_reg32(&global_regs->gintmsk, 0);
2006
2007	/* 15 second delay per the test spec */
2008	mdelay(15000);
2009
2010	/* Send the Setup packet */
2011	do_setup();
2012
2013	/* 15 second delay so nothing else happens for awhile */
2014	mdelay(15000);
2015
2016	/* Restore interrupts */
2017	dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2018	} else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2019	/* Save current interrupt mask */
2020	gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2021
2022	/* Disable all interrupts while we muck with
2023	* the hardware directly
2024	*/
2025	dwc_write_reg32(&global_regs->gintmsk, 0);
2026
2027	/* Send the Setup packet */
2028	do_setup();
2029
2030	/* 15 second delay so nothing else happens for awhile */
2031	mdelay(15000);
2032
2033	/* Send the In and Ack packets */
2034	do_in_ack();
2035
2036	/* 15 second delay so nothing else happens for awhile */
2037	mdelay(15000);
2038
2039	/* Restore interrupts */
2040	dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2041	}
2042	}
2043	break;
2044	}
2045	#endif /* DWC_HS_ELECT_TST */
2046
2047	case USB_PORT_FEAT_INDICATOR:
2048	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2049	"SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2050	/* Not supported */
2051	break;
2052	default:
2053	retval = -EINVAL;
2054	DWC_ERROR("DWC OTG HCD - "
2055	"SetPortFeature request %xh "
2056	"unknown or unsupported\n", wValue);
2057	break;
2058	}
2059	break;
2060	default:
2061	error:
2062	retval = -EINVAL;
2063	DWC_WARN("DWC OTG HCD - "
2064	"Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2065	typeReq, wIndex, wValue);
2066	break;
2067	}
2068
2069	return retval;
2070	}
2071
2072	/**
2073	* Assigns transactions from a QTD to a free host channel and initializes the
2074	* host channel to perform the transactions. The host channel is removed from
2075	* the free list.
2076	*
2077	* @param hcd The HCD state structure.
2078	* @param qh Transactions from the first QTD for this QH are selected and
2079	* assigned to a free host channel.
2080	*/
2081	static void assign_and_init_hc(dwc_otg_hcd_t hcd, dwc_otg_qh_t qh)
2082	{
2083	dwc_hc_t *hc;
2084	dwc_otg_qtd_t *qtd;
2085	struct urb *urb;
2086
2087	DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
2088
2089	hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2090
2091	/* Remove the host channel from the free list. */
2092	list_del_init(&hc->hc_list_entry);
2093
2094	qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2095	urb = qtd->urb;
2096	qh->channel = hc;
2097	qh->qtd_in_process = qtd;
2098
2099	/*
2100	* Use usb_pipedevice to determine device address. This address is
2101	* 0 before the SET_ADDRESS command and the correct address afterward.
2102	*/
2103	hc->dev_addr = usb_pipedevice(urb->pipe);
2104	hc->ep_num = usb_pipeendpoint(urb->pipe);
2105
2106	if (urb->dev->speed == USB_SPEED_LOW) {
2107	hc->speed = DWC_OTG_EP_SPEED_LOW;
2108	} else if (urb->dev->speed == USB_SPEED_FULL) {
2109	hc->speed = DWC_OTG_EP_SPEED_FULL;
2110	} else {
2111	hc->speed = DWC_OTG_EP_SPEED_HIGH;
2112	}
2113
2114	hc->max_packet = dwc_max_packet(qh->maxp);
2115
2116	hc->xfer_started = 0;
2117	hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2118	hc->error_state = (qtd->error_count > 0);
2119	hc->halt_on_queue = 0;
2120	hc->halt_pending = 0;
2121	hc->requests = 0;
2122
2123	/*
2124	* The following values may be modified in the transfer type section
2125	* below. The xfer_len value may be reduced when the transfer is
2126	* started to accommodate the max widths of the XferSize and PktCnt
2127	* fields in the HCTSIZn register.
2128	*/
2129	hc->do_ping = qh->ping_state;
2130	hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2131	hc->data_pid_start = qh->data_toggle;
2132	hc->multi_count = 1;
2133
2134	if (hcd->core_if->dma_enable) {
2135	hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2136	} else {
2137	hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2138	}
2139	hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2140	hc->xfer_count = 0;
2141
2142	/*
2143	* Set the split attributes
2144	*/
2145	hc->do_split = 0;
2146	if (qh->do_split) {
2147	hc->do_split = 1;
2148	hc->xact_pos = qtd->isoc_split_pos;
2149	hc->complete_split = qtd->complete_split;
2150	hc->hub_addr = urb->dev->tt->hub->devnum;
2151	hc->port_addr = urb->dev->ttport;
2152	}
2153
2154	switch (usb_pipetype(urb->pipe)) {
2155	case PIPE_CONTROL:
2156	hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2157	switch (qtd->control_phase) {
2158	case DWC_OTG_CONTROL_SETUP:
2159	DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
2160	hc->do_ping = 0;
2161	hc->ep_is_in = 0;
2162	hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2163	if (hcd->core_if->dma_enable) {
2164	hc->xfer_buff = (uint8_t *)urb->setup_dma;
2165	} else {
2166	hc->xfer_buff = (uint8_t *)urb->setup_packet;
2167	}
2168	hc->xfer_len = 8;
2169	break;
2170	case DWC_OTG_CONTROL_DATA:
2171	DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
2172	hc->data_pid_start = qtd->data_toggle;
2173	break;
2174	case DWC_OTG_CONTROL_STATUS:
2175	/*
2176	* Direction is opposite of data direction or IN if no
2177	* data.
2178	*/
2179	DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
2180	if (urb->transfer_buffer_length == 0) {
2181	hc->ep_is_in = 1;
2182	} else {
2183	hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2184	}
2185	if (hc->ep_is_in) {
2186	hc->do_ping = 0;
2187	}
2188	hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2189	hc->xfer_len = 0;
2190	if (hcd->core_if->dma_enable) {
2191	hc->xfer_buff = (uint8_t *)hcd->status_buf_dma;
2192	} else {
2193	hc->xfer_buff = (uint8_t *)hcd->status_buf;
2194	}
2195	break;
2196	}
2197	break;
2198	case PIPE_BULK:
2199	hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2200	break;
2201	case PIPE_INTERRUPT:
2202	hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2203	break;
2204	case PIPE_ISOCHRONOUS:
2205	{
2206	struct usb_iso_packet_descriptor *frame_desc;
2207	frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2208	hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2209	if (hcd->core_if->dma_enable) {
2210	hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2211	} else {
2212	hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2213	}
2214	hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2215	hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2216
2217	if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2218	if (hc->xfer_len <= 188) {
2219	hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2220	}
2221	else {
2222	hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2223	}
2224	}
2225	}
2226	break;
2227	}
2228
2229	if (hc->ep_type == DWC_OTG_EP_TYPE_INTR \|\|
2230	hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2231	/*
2232	* This value may be modified when the transfer is started to
2233	* reflect the actual transfer length.
2234	*/
2235	hc->multi_count = dwc_hb_mult(qh->maxp);
2236	}
2237
2238	dwc_otg_hc_init(hcd->core_if, hc);
2239	hc->qh = qh;
2240	}
2241
2242	/**
2243	* This function selects transactions from the HCD transfer schedule and
2244	* assigns them to available host channels. It is called from HCD interrupt
2245	* handler functions.
2246	*
2247	* @param hcd The HCD state structure.
2248	*
2249	* @return The types of new transactions that were assigned to host channels.
2250	*/
2251	dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
2252	{
2253	struct list_head *qh_ptr;
2254	dwc_otg_qh_t *qh;
2255	int num_channels;
2256	dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
2257
2258	#ifdef DEBUG_SOF
2259	DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
2260	#endif
2261
2262	/* Process entries in the periodic ready list. */
2263	qh_ptr = hcd->periodic_sched_ready.next;
2264	while (qh_ptr != &hcd->periodic_sched_ready &&
2265	!list_empty(&hcd->free_hc_list)) {
2266
2267	qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2268	assign_and_init_hc(hcd, qh);
2269
2270	/*
2271	* Move the QH from the periodic ready schedule to the
2272	* periodic assigned schedule.
2273	*/
2274	qh_ptr = qh_ptr->next;
2275	list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned);
2276
2277	ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2278	}
2279
2280	/*
2281	* Process entries in the inactive portion of the non-periodic
2282	* schedule. Some free host channels may not be used if they are
2283	* reserved for periodic transfers.
2284	*/
2285	qh_ptr = hcd->non_periodic_sched_inactive.next;
2286	num_channels = hcd->core_if->core_params->host_channels;
2287	while (qh_ptr != &hcd->non_periodic_sched_inactive &&
2288	(hcd->non_periodic_channels <
2289	num_channels - hcd->periodic_channels) &&
2290	!list_empty(&hcd->free_hc_list)) {
2291
2292	qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2293	assign_and_init_hc(hcd, qh);
2294
2295	/*
2296	* Move the QH from the non-periodic inactive schedule to the
2297	* non-periodic active schedule.
2298	*/
2299	qh_ptr = qh_ptr->next;
2300	list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
2301
2302	if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2303	ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2304	} else {
2305	ret_val = DWC_OTG_TRANSACTION_ALL;
2306	}
2307
2308	hcd->non_periodic_channels++;
2309	}
2310
2311	return ret_val;
2312	}
2313
2314	/**
2315	* Attempts to queue a single transaction request for a host channel
2316	* associated with either a periodic or non-periodic transfer. This function
2317	* assumes that there is space available in the appropriate request queue. For
2318	* an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2319	* is available in the appropriate Tx FIFO.
2320	*
2321	* @param hcd The HCD state structure.
2322	* @param hc Host channel descriptor associated with either a periodic or
2323	* non-periodic transfer.
2324	* @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
2325	* FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2326	* transfers.
2327	*
2328	* @return 1 if a request is queued and more requests may be needed to
2329	* complete the transfer, 0 if no more requests are required for this
2330	* transfer, -1 if there is insufficient space in the Tx FIFO.
2331	*/
2332	static int queue_transaction(dwc_otg_hcd_t *hcd,
2333	dwc_hc_t *hc,
2334	uint16_t fifo_dwords_avail)
2335	{
2336	int retval;
2337
2338	if (hcd->core_if->dma_enable) {
2339	if (!hc->xfer_started) {
2340	dwc_otg_hc_start_transfer(hcd->core_if, hc);
2341	hc->qh->ping_state = 0;
2342	}
2343	retval = 0;
2344	} else if (hc->halt_pending) {
2345	/* Don't queue a request if the channel has been halted. */
2346	retval = 0;
2347	} else if (hc->halt_on_queue) {
2348	dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
2349	retval = 0;
2350	} else if (hc->do_ping) {
2351	if (!hc->xfer_started) {
2352	dwc_otg_hc_start_transfer(hcd->core_if, hc);
2353	}
2354	retval = 0;
2355	} else if (!hc->ep_is_in \|\|
2356	hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2357	if ((fifo_dwords_avail * 4) >= hc->max_packet) {
2358	if (!hc->xfer_started) {
2359	dwc_otg_hc_start_transfer(hcd->core_if, hc);
2360	retval = 1;
2361	} else {
2362	retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
2363	}
2364	} else {
2365	retval = -1;
2366	}
2367	} else {
2368	if (!hc->xfer_started) {
2369	dwc_otg_hc_start_transfer(hcd->core_if, hc);
2370	retval = 1;
2371	} else {
2372	retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
2373	}
2374	}
2375
2376	return retval;
2377	}
2378
2379	/**
2380	* Processes active non-periodic channels and queues transactions for these
2381	* channels to the DWC_otg controller. After queueing transactions, the NP Tx
2382	* FIFO Empty interrupt is enabled if there are more transactions to queue as
2383	* NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2384	* FIFO Empty interrupt is disabled.
2385	*/
2386	static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
2387	{
2388	gnptxsts_data_t tx_status;
2389	struct list_head *orig_qh_ptr;
2390	dwc_otg_qh_t *qh;
2391	int status;
2392	int no_queue_space = 0;
2393	int no_fifo_space = 0;
2394	int more_to_do = 0;
2395
2396	dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs;
2397
2398	DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
2399	#ifdef DEBUG
2400	tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2401	DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
2402	tx_status.b.nptxqspcavail);
2403	DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
2404	tx_status.b.nptxfspcavail);
2405	#endif
2406	/*
2407	* Keep track of the starting point. Skip over the start-of-list
2408	* entry.
2409	*/
2410	if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
2411	hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
2412	}
2413	orig_qh_ptr = hcd->non_periodic_qh_ptr;
2414
2415	/*
2416	* Process once through the active list or until no more space is
2417	* available in the request queue or the Tx FIFO.
2418	*/
2419	do {
2420	tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2421	if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
2422	no_queue_space = 1;
2423	break;
2424	}
2425
2426	qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
2427	status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail);
2428
2429	if (status > 0) {
2430	more_to_do = 1;
2431	} else if (status < 0) {
2432	no_fifo_space = 1;
2433	break;
2434	}
2435
2436	/* Advance to next QH, skipping start-of-list entry. */
2437	hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
2438	if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
2439	hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
2440	}
2441
2442	} while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
2443
2444	if (!hcd->core_if->dma_enable) {
2445	gintmsk_data_t intr_mask = {.d32 = 0};
2446	intr_mask.b.nptxfempty = 1;
2447
2448	#ifdef DEBUG
2449	tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2450	DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
2451	tx_status.b.nptxqspcavail);
2452	DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
2453	tx_status.b.nptxfspcavail);
2454	#endif
2455	if (more_to_do \|\| no_queue_space \|\| no_fifo_space) {
2456	/*
2457	* May need to queue more transactions as the request
2458	* queue or Tx FIFO empties. Enable the non-periodic
2459	* Tx FIFO empty interrupt. (Always use the half-empty
2460	* level to ensure that new requests are loaded as
2461	* soon as possible.)
2462	*/
2463	dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
2464	} else {
2465	/*
2466	* Disable the Tx FIFO empty interrupt since there are
2467	* no more transactions that need to be queued right
2468	* now. This function is called from interrupt
2469	* handlers to queue more transactions as transfer
2470	* states change.
2471	*/
2472	dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
2473	}
2474	}
2475	}
2476
2477	/**
2478	* Processes periodic channels for the next frame and queues transactions for
2479	* these channels to the DWC_otg controller. After queueing transactions, the
2480	* Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2481	* to queue as Periodic Tx FIFO or request queue space becomes available.
2482	* Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2483	*/
2484	static void process_periodic_channels(dwc_otg_hcd_t *hcd)
2485	{
2486	hptxsts_data_t tx_status;
2487	struct list_head *qh_ptr;
2488	dwc_otg_qh_t *qh;
2489	int status;
2490	int no_queue_space = 0;
2491	int no_fifo_space = 0;
2492
2493	dwc_otg_host_global_regs_t *host_regs;
2494	host_regs = hcd->core_if->host_if->host_global_regs;
2495
2496	DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
2497	#ifdef DEBUG
2498	tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
2499	DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
2500	tx_status.b.ptxqspcavail);
2501	DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
2502	tx_status.b.ptxfspcavail);
2503	#endif
2504
2505	qh_ptr = hcd->periodic_sched_assigned.next;
2506	while (qh_ptr != &hcd->periodic_sched_assigned) {
2507	tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
2508	if (tx_status.b.ptxqspcavail == 0) {
2509	no_queue_space = 1;
2510	break;
2511	}
2512
2513	qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2514
2515	/*
2516	* Set a flag if we're queuing high-bandwidth in slave mode.
2517	* The flag prevents any halts to get into the request queue in
2518	* the middle of multiple high-bandwidth packets getting queued.
2519	*/
2520	if (!hcd->core_if->dma_enable &&
2521	qh->channel->multi_count > 1)
2522	{
2523	hcd->core_if->queuing_high_bandwidth = 1;
2524	}
2525
2526	status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail);
2527	if (status < 0) {
2528	no_fifo_space = 1;
2529	break;
2530	}
2531
2532	/*
2533	* In Slave mode, stay on the current transfer until there is
2534	* nothing more to do or the high-bandwidth request count is
2535	* reached. In DMA mode, only need to queue one request. The
2536	* controller automatically handles multiple packets for
2537	* high-bandwidth transfers.
2538	*/
2539	if (hcd->core_if->dma_enable \|\| status == 0 \|\|
2540	qh->channel->requests == qh->channel->multi_count) {
2541	qh_ptr = qh_ptr->next;
2542	/*
2543	* Move the QH from the periodic assigned schedule to
2544	* the periodic queued schedule.
2545	*/
2546	list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued);
2547
2548	/* done queuing high bandwidth */
2549	hcd->core_if->queuing_high_bandwidth = 0;
2550	}
2551	}
2552
2553	if (!hcd->core_if->dma_enable) {
2554	dwc_otg_core_global_regs_t *global_regs;
2555	gintmsk_data_t intr_mask = {.d32 = 0};
2556
2557	global_regs = hcd->core_if->core_global_regs;
2558	intr_mask.b.ptxfempty = 1;
2559	#ifdef DEBUG
2560	tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
2561	DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
2562	tx_status.b.ptxqspcavail);
2563	DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
2564	tx_status.b.ptxfspcavail);
2565	#endif
2566	if (!list_empty(&hcd->periodic_sched_assigned) \|\|
2567	no_queue_space \|\| no_fifo_space) {
2568	/*
2569	* May need to queue more transactions as the request
2570	* queue or Tx FIFO empties. Enable the periodic Tx
2571	* FIFO empty interrupt. (Always use the half-empty
2572	* level to ensure that new requests are loaded as
2573	* soon as possible.)
2574	*/
2575	dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
2576	} else {
2577	/*
2578	* Disable the Tx FIFO empty interrupt since there are
2579	* no more transactions that need to be queued right
2580	* now. This function is called from interrupt
2581	* handlers to queue more transactions as transfer
2582	* states change.
2583	*/
2584	dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
2585	}
2586	}
2587	}
2588
2589	/**
2590	* This function processes the currently active host channels and queues
2591	* transactions for these channels to the DWC_otg controller. It is called
2592	* from HCD interrupt handler functions.
2593	*
2594	* @param hcd The HCD state structure.
2595	* @param tr_type The type(s) of transactions to queue (non-periodic,
2596	* periodic, or both).
2597	*/
2598	void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
2599	dwc_otg_transaction_type_e tr_type)
2600	{
2601	#ifdef DEBUG_SOF
2602	DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
2603	#endif
2604	/* Process host channels associated with periodic transfers. */
2605	if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC \|\|
2606	tr_type == DWC_OTG_TRANSACTION_ALL) &&
2607	!list_empty(&hcd->periodic_sched_assigned)) {
2608
2609	process_periodic_channels(hcd);
2610	}
2611
2612	/* Process host channels associated with non-periodic transfers. */
2613	if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC \|\|
2614	tr_type == DWC_OTG_TRANSACTION_ALL) {
2615	if (!list_empty(&hcd->non_periodic_sched_active)) {
2616	process_non_periodic_channels(hcd);
2617	} else {
2618	/*
2619	* Ensure NP Tx FIFO empty interrupt is disabled when
2620	* there are no non-periodic transfers to process.
2621	*/
2622	gintmsk_data_t gintmsk = {.d32 = 0};
2623	gintmsk.b.nptxfempty = 1;
2624	dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk,
2625	gintmsk.d32, 0);
2626	}
2627	}
2628	}
2629
2630	/**
2631	* Sets the final status of an URB and returns it to the device driver. Any
2632	* required cleanup of the URB is performed.
2633	*/
2634	void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t hcd, struct urb urb, int status)
2635	{
2636	#ifdef DEBUG
2637	if (CHK_DEBUG_LEVEL(DBG_HCDV \| DBG_HCD_URB)) {
2638	DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
2639	__func__, urb, usb_pipedevice(urb->pipe),
2640	usb_pipeendpoint(urb->pipe),
2641	usb_pipein(urb->pipe) ? "IN" : "OUT", status);
2642	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2643	int i;
2644	for (i = 0; i < urb->number_of_packets; i++) {
2645	DWC_PRINT(" ISO Desc %d status: %d\n",
2646	i, urb->iso_frame_desc[i].status);
2647	}
2648	}
2649	}
2650	#endif
2651
2652	urb->status = status;
2653	urb->hcpriv = NULL;
2654	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2655	usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
2656	#else
2657	usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL);
2658	#endif
2659	}
2660
2661	/*
2662	* Returns the Queue Head for an URB.
2663	*/
2664	dwc_otg_qh_t dwc_urb_to_qh(struct urb urb)
2665	{
2666	struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
2667	return (dwc_otg_qh_t *)ep->hcpriv;
2668	}
2669
2670	#ifdef DEBUG
2671	void dwc_print_setup_data(uint8_t *setup)
2672	{
2673	int i;
2674	if (CHK_DEBUG_LEVEL(DBG_HCD)){
2675	DWC_PRINT("Setup Data = MSB ");
2676	for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]);
2677	DWC_PRINT("\n");
2678	DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device");
2679	DWC_PRINT(" bmRequestType Type = ");
2680	switch ((setup[0] & 0x60) >> 5) {
2681	case 0: DWC_PRINT("Standard\n"); break;
2682	case 1: DWC_PRINT("Class\n"); break;
2683	case 2: DWC_PRINT("Vendor\n"); break;
2684	case 3: DWC_PRINT("Reserved\n"); break;
2685	}
2686	DWC_PRINT(" bmRequestType Recipient = ");
2687	switch (setup[0] & 0x1f) {
2688	case 0: DWC_PRINT("Device\n"); break;
2689	case 1: DWC_PRINT("Interface\n"); break;
2690	case 2: DWC_PRINT("Endpoint\n"); break;
2691	case 3: DWC_PRINT("Other\n"); break;
2692	default: DWC_PRINT("Reserved\n"); break;
2693	}
2694	DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
2695	DWC_PRINT(" wValue = 0x%0x\n", ((uint16_t )&setup[2]));
2696	DWC_PRINT(" wIndex = 0x%0x\n", ((uint16_t )&setup[4]));
2697	DWC_PRINT(" wLength = 0x%0x\n\n", ((uint16_t )&setup[6]));
2698	}
2699	}
2700	#endif
2701
2702	void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) {
2703	#if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
2704	DWC_PRINT("Frame remaining at SOF:\n");
2705	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2706	hcd->frrem_samples, hcd->frrem_accum,
2707	(hcd->frrem_samples > 0) ?
2708	hcd->frrem_accum/hcd->frrem_samples : 0);
2709
2710	DWC_PRINT("\n");
2711	DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
2712	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2713	hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum,
2714	(hcd->core_if->hfnum_7_samples > 0) ?
2715	hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0);
2716	DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
2717	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2718	hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum,
2719	(hcd->core_if->hfnum_0_samples > 0) ?
2720	hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0);
2721	DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
2722	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2723	hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum,
2724	(hcd->core_if->hfnum_other_samples > 0) ?
2725	hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0);
2726
2727	DWC_PRINT("\n");
2728	DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
2729	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2730	hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
2731	(hcd->hfnum_7_samples_a > 0) ?
2732	hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0);
2733	DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
2734	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2735	hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
2736	(hcd->hfnum_0_samples_a > 0) ?
2737	hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0);
2738	DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
2739	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2740	hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
2741	(hcd->hfnum_other_samples_a > 0) ?
2742	hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0);
2743
2744	DWC_PRINT("\n");
2745	DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
2746	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2747	hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
2748	(hcd->hfnum_7_samples_b > 0) ?
2749	hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0);
2750	DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
2751	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2752	hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
2753	(hcd->hfnum_0_samples_b > 0) ?
2754	hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0);
2755	DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
2756	DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
2757	hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
2758	(hcd->hfnum_other_samples_b > 0) ?
2759	hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0);
2760	#endif
2761	}
2762
2763	void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
2764	{
2765	#ifdef DEBUG
2766	int num_channels;
2767	int i;
2768	gnptxsts_data_t np_tx_status;
2769	hptxsts_data_t p_tx_status;
2770
2771	num_channels = hcd->core_if->core_params->host_channels;
2772	DWC_PRINT("\n");
2773	DWC_PRINT("************************************************************\n");
2774	DWC_PRINT("HCD State:\n");
2775	DWC_PRINT(" Num channels: %d\n", num_channels);
2776	for (i = 0; i < num_channels; i++) {
2777	dwc_hc_t *hc = hcd->hc_ptr_array[i];
2778	DWC_PRINT(" Channel %d:\n", i);
2779	DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
2780	hc->dev_addr, hc->ep_num, hc->ep_is_in);
2781	DWC_PRINT(" speed: %d\n", hc->speed);
2782	DWC_PRINT(" ep_type: %d\n", hc->ep_type);
2783	DWC_PRINT(" max_packet: %d\n", hc->max_packet);
2784	DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
2785	DWC_PRINT(" multi_count: %d\n", hc->multi_count);
2786	DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
2787	DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
2788	DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
2789	DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
2790	DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
2791	DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
2792	DWC_PRINT(" halt_status: %d\n", hc->halt_status);
2793	DWC_PRINT(" do_split: %d\n", hc->do_split);
2794	DWC_PRINT(" complete_split: %d\n", hc->complete_split);
2795	DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
2796	DWC_PRINT(" port_addr: %d\n", hc->port_addr);
2797	DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
2798	DWC_PRINT(" requests: %d\n", hc->requests);
2799	DWC_PRINT(" qh: %p\n", hc->qh);
2800	if (hc->xfer_started) {
2801	hfnum_data_t hfnum;
2802	hcchar_data_t hcchar;
2803	hctsiz_data_t hctsiz;
2804	hcint_data_t hcint;
2805	hcintmsk_data_t hcintmsk;
2806	hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
2807	hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar);
2808	hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz);
2809	hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint);
2810	hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk);
2811	DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
2812	DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
2813	DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
2814	DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
2815	DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
2816	}
2817	if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) {
2818	dwc_otg_qtd_t *qtd;
2819	struct urb *urb;
2820	qtd = hc->qh->qtd_in_process;
2821	urb = qtd->urb;
2822	DWC_PRINT(" URB Info:\n");
2823	DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
2824	if (urb) {
2825	DWC_PRINT(" Dev: %d, EP: %d %s\n",
2826	usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
2827	usb_pipein(urb->pipe) ? "IN" : "OUT");
2828	DWC_PRINT(" Max packet size: %d\n",
2829	usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2830	DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
2831	DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
2832	DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
2833	DWC_PRINT(" actual_length: %d\n", urb->actual_length);
2834	}
2835	}
2836	}
2837	DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
2838	DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels);
2839	DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs);
2840	np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
2841	DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
2842	DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
2843	p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
2844	DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
2845	DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
2846	dwc_otg_hcd_dump_frrem(hcd);
2847	dwc_otg_dump_global_registers(hcd->core_if);
2848	dwc_otg_dump_host_registers(hcd->core_if);
2849	DWC_PRINT("************************************************************\n");
2850	DWC_PRINT("\n");
2851	#endif
2852	}
2853	#endif /* DWC_DEVICE_ONLY */

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root/src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd.c

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