Changeset 12433

Timestamp:

07/03/09 16:48:37 (5 months ago)

Author:

BrainSlayer

Message:

fixes usb issues with some devices

Files:

• src/linux/rt2880/linux-2.6.23/.config (modified) (21 diffs)
• src/linux/rt2880/linux-2.6.23/.config_rt3052 (modified) (6 diffs)
• src/linux/rt2880/linux-2.6.23/arch/mips/Makefile (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/arch/mips/kernel/module.c (modified) (10 diffs)
• src/linux/rt2880/linux-2.6.23/arch/mips/kernel/scall32-o32.S (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/arch/mips/kernel/vmlinux.lds.S (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/arch/mips/mm/c-r4k.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/arch/mips/rt2880/init.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/net/Makefile (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/net/usb/Kconfig (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/net/usb/Makefile (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/core/hub.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/Kconfig (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/Makefile (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dummy_audio.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c (modified) (31 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.h (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_cil.c (modified) (142 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_cil.h (modified) (24 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_cil_intr.c (modified) (36 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_driver.c (modified) (65 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_driver.h (modified) (3 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd.c (modified) (122 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd.h (modified) (30 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c (modified) (100 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c (modified) (35 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_pcd.c (modified) (81 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_pcd.h (modified) (9 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_pcd_intr.c (modified) (108 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_regs.h (modified) (15 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/serial/Makefile (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/serial/option.c (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/serial/sierra.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/storage/Makefile (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/storage/transport.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/drivers/usb/storage/unusual_devs.h (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/drivers/usb/storage/usb.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/fs/squashfs/LzmaDecode.c (modified) (9 diffs)
• src/linux/rt2880/linux-2.6.23/fs/squashfs/LzmaDecode.h (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/include/asm-mips/module.h (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/include/asm-mips/string.h (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/include/linux/jhash.h (modified) (5 diffs)
• src/linux/rt2880/linux-2.6.23/kernel/module.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/mm/page_alloc.c (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/net/ipv6/inet6_connection_sock.c (modified) (2 diffs)
• src/linux/rt2880/linux-2.6.23/net/ipv6/netfilter/nf_conntrack_reasm.c (modified) (1 diff)
• src/linux/rt2880/linux-2.6.23/net/ipv6/reassembly.c (modified) (2 diffs)

src/linux/rt2880/linux-2.6.23/.config

@@ -2 +2 @@
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23.17
-Mon Apr  6 12:18:07
+Fri Jul  3 16:08:30
-#
-CONFIG_MIPS=y
@@ -9 +9 @@
-# Machine selection
-#
-2880_MP
-
+3052_MP2
+
-# CONFIG_RALINK_RT2883 is not set
-
+
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_BASLER_EXCITE is not set
@@ -48 +48 @@
-# CONFIG_TOSHIBA_RBTX4938 is not set
-# CONFIG_WR_PPMC is not set
-
-
+
-# CONFIG_RT2880_DRAM_8M is not set
-# CONFIG_RT2880_DRAM_16M is not set
-CONFIG_RT2880_DRAM_32M=y
-# CONFIG_RT2880_DRAM_64M is not set
-
-
-
-
+
-CONFIG_RALINK_RAM_SIZE=32
-CONFIG_MTD_PHYSMAP_START=0xBF000000
-8
+10
-CONFIG_MTD_PHYSMAP_BUSWIDTH=2
-# CONFIG_RT2880_ROOTFS_IN_RAM is not set
@@ -194 +190 @@
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-
+
+
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
@@ -241 +238 @@
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-# CONFIG_PCI is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_MMU=y
@@ -261 +256 @@
-# Power management options
-#
-
+
+
+
-CONFIG_SUSPEND_UP_POSSIBLE=y
+# CONFIG_SUSPEND is not set
-
-#
@@ -555 +553 @@
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-
+
+
-# CONFIG_NET_9P is not set
-
@@ -597 +596 @@
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-
+
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
@@ -638 +637 @@
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CFI_AMDSTD=y
-
-
+
+
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
@@ -682 +681 @@
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
@@ -692 +692 @@
-#
-# CONFIG_RAID_ATTRS is not set
-
-
+
+
+
-# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
@@ -731 +762 @@
-CONFIG_RAETH=y
-CONFIG_RAETH_NAPI=y
-
-
-
-
-
+
+
+
+
+
+
+
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
@@ -749 +782 @@
-CONFIG_WLAN_80211=y
-# CONFIG_LIBERTAS is not set
+# CONFIG_USB_ZD1201 is not set
-# CONFIG_HOSTAP is not set
-CONFIG_RT2860V2_AP=m
-
+
+
-CONFIG_RT2860V2_AP_LED=y
-CONFIG_RT2860V2_AP_WSC=y
@@ -758 +793 @@
-CONFIG_RT2860V2_AP_MBSS=y
-CONFIG_RT2860V2_AP_APCLI=y
-
+
-# CONFIG_RT2860V2_AP_NETIF_BLOCK is not set
-# CONFIG_RT2860V2_AP_DFS is not set
@@ -768 +803 @@
-# CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION is not set
-CONFIG_RT2860V2_STA=m
-
+
+
-CONFIG_RT2860V2_STA_LED=y
-CONFIG_RT2860V2_STA_WPA_SUPPLICANT=y
@@ -776 +812 @@
-CONFIG_RT2860V2_STA_DLS=y
-# CONFIG_RT2860V2_STA_MESH is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_HSO=m
-# CONFIG_WAN is not set
-CONFIG_PPP=y
@@ -838 +885 @@
-# CONFIG_RALINK_PCM is not set
-# CONFIG_RALINK_I2S is not set
-
-
+
+
+
+
+
-# CONFIG_MOXA is not set
+# CONFIG_MOXA_SMARTIO is not set
+CONFIG_N_HDLC=m
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
-
-#
@@ -871 +927 @@
-#
-# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
@@ -913 +974 @@
-
-#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
-# Sound
-#
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-
+
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-# CONFIG_MMC is not set
-# CONFIG_NEW_LEDS is not set
@@ -1018 +1228 @@
-# CONFIG_NFSD is not set
-# CONFIG_SMB_FS is not set
-
+
+
+
+
+
+
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
@@ -1032 +1247 @@
-# Native Language Support
-#
-
+
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-
-#

src/linux/rt2880/linux-2.6.23/.config_rt3052

@@ -2 +2 @@
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23.17
-Mon Jan  5 14:47:41
+Tue May 19 13:55:15
-#
-CONFIG_MIPS=y
@@ -415 +415 @@
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_IMQ=m
+CONFIG_IP_NF_TARGET_ROUTE=y
-CONFIG_IP_NF_TARGET_LOG=y
-CONFIG_IP_NF_TARGET_ULOG=y
@@ -559 +560 @@
-# Ralink Common Flash Driver
-#
-
+
-
-#
-# 2MB Flash
-#
-# CONFIG_FLASH_EN29LV160 is not set
-# CONFIG_FLASH_MX29LV160 is not set
-# CONFIG_FLASH_S29AL016X is not set
-# CONFIG_FLASH_K8D3X16U is not set
-
-#
-# 4MB Flash
-#
-CONFIG_FLASH_MX29LV320=y
-# CONFIG_FLASH_EN29LV320 is not set
-# CONFIG_FLASH_S29AL032X is not set
-# CONFIG_FLASH_S29GL032N is not set
-# CONFIG_FLASH_F49L320 is not set
-
-#
-# 8MB Flash
-#
-# CONFIG_FLASH_MX29LV640 is not set
-# CONFIG_FLASH_S29GL064N is not set
-# CONFIG_FLASH_ST_M29W640 is not set
-
-#
-# 16MB Flash
-#
-# CONFIG_FLASH_MX29LV128 is not set
-
-#
-# 32MB Flash
-#
-# CONFIG_FLASH_S29GL256 is not set
-
-#
@@ -657 +644 @@
-#
-CONFIG_MTD_RALINK=y
+# CONFIG_MTD_ESR6650 is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
@@ -738 +726 @@
-CONFIG_RAETH=y
-CONFIG_RAETH_NAPI=y
-CONFIG_RAETH_CHECKSUM_OFFLOAD=y
-# CONFIG_RAETH_QOS is not set
-# CONFIG_RAETH_ROUTER is not set
-# CONFIG_MAC_TO_MAC_MODE is not set
-CONFIG_RT_3052_ESW=y
-# CONFIG_GIGAPHY is not set
-CONFIG_LAN_WAN_SUPPORT=y
-# CONFIG_WAN_AT_P4 is not set
@@ -1141 +1125 @@
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_IP_NF_TARGET_ROUTE=y
-# CONFIG_MTD_ESR6650 is not set

src/linux/rt2880/linux-2.6.23/arch/mips/Makefile

@@ -84 +84 @@
-cflags-y                        += -msoft-float
-LDFLAGS_vmlinux                 += -G 0 -static -n -nostdlib
-
+no-
-
-cflags-y += -ffreestanding

src/linux/rt2880/linux-2.6.23/arch/mips/kernel/module.c

@@ -30 +30 @@
-#include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/mm.h>
-#include <asm/pgtable.h>        /* MODULE_START */
-
@@ -43 +44 @@
-static DEFINE_SPINLOCK(dbe_lock);
-
+static void *alloc_phys(unsigned long size)
+{
+        unsigned order;
+        struct page *page;
+        struct page *p;
+
+        size = PAGE_ALIGN(size);
+        order = get_order(size);
+
+        page = alloc_pages(
+                GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | __GFP_THISNODE,
+                order);
+        if (!page)
+                return 0;
+
+        split_page(page, order);
+
+        for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)
+                __free_page(p);
+
+        return page_address(page);
+}
+
+static void free_phys(void *ptr, unsigned long size)
+{
+        struct page *page;
+        struct page *end;
+
+        page = virt_to_page(ptr);
+        end = page + (PAGE_ALIGN(size) >> PAGE_SHIFT);
+
+        for (; page < end; ++page)
+                __free_pages(page, 0);
+}
+
-void *module_alloc(unsigned long size)
-{
@@ -58 +94 @@
-        return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
-#else
+        unsigned addr;
+        void *ptr;
+
+        size = PAGE_ALIGN(size);
-        if (size == 0)
-                return NULL;
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-#endif
+}
+
+static inline int is_phys(void *ptr)
+{
+        unsigned addr = (unsigned) ptr;
+        return addr && (addr < VMALLOC_START || addr > VMALLOC_END);
-}
-
@@ -67 +134 @@
-void module_free(struct module *mod, void *module_region)
-{
+        if (is_phys(module_region)) {
+                if (mod->module_init == module_region)
+                        free_phys(module_region, mod->init_size);
+                else if (mod->module_core == module_region)
+                        free_phys(module_region, mod->core_size);
+                else
+                    BUG();
+                return;
+        }
+
-        vfree(module_region);
-        /* FIXME: If module_region == mod->init_region, trim exception
@@ -78 +155 @@
-}
-
+/* Get the potential trampolines size required of the init and
+   non-init sections */
+static unsigned get_plt_size(const Elf32_Ehdr *hdr,
+                             const Elf32_Shdr *sechdrs,
+                             const char *secstrings,
+                             unsigned symindex,
+                             int is_init)
+{
+        unsigned long ret = 0;
+        unsigned i, j;
+        Elf_Sym *syms;
+
+        /* Everything marked ALLOC (this includes the exported symbols) */
+        for (i = 1; i < hdr->e_shnum; ++i) {
+                unsigned int info = sechdrs[i].sh_info;
+
+                if (sechdrs[i].sh_type != SHT_REL
+                    && sechdrs[i].sh_type != SHT_RELA)
+                        continue;
+
+                /* Not a valid relocation section? */
+                if (info >= hdr->e_shnum)
+                        continue;
+
+                /* Don't bother with non-allocated sections */
+                if (!(sechdrs[info].sh_flags & SHF_ALLOC))
+                        continue;
+
+                /* If it's called *.init*, and we're not init, we're
+                   not interested */
+                if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0)
+                    != is_init)
+                        continue;
+
+                syms = (Elf_Sym *) sechdrs[symindex].sh_addr;
+                if (sechdrs[i].sh_type == SHT_REL) {
+                        Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;
+                        unsigned size = sechdrs[i].sh_size / sizeof(*rel);
+
+                        for (j = 0; j < size; ++j) {
+                                Elf_Sym *sym;
+
+                                if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)
+                                        continue;
+                                sym = syms + ELF_MIPS_R_SYM(rel[j]);
+                                if (!is_init && sym->st_shndx != SHN_UNDEF)
+                                        continue;
+
+                                ret += sizeof(unsigned[4]);
+                        }
+                } else {
+                        Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;
+                        unsigned size = sechdrs[i].sh_size / sizeof(*rela);
+
+                        for (j = 0; j < size; ++j) {
+                                Elf_Sym *sym;
+
+                                if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)
+                                        continue;
+                                sym = syms + ELF_MIPS_R_SYM(rela[j]);
+                                if (!is_init && sym->st_shndx != SHN_UNDEF)
+                                        continue;
+
+                                ret += sizeof(unsigned[4]);
+                        }
+                }
+
+        }
+
+        return ret;
+}
+
+int module_relayout(Elf32_Ehdr *hdr,
+                    Elf32_Shdr *sechdrs,
+                    char *secstrings,
+                    unsigned symindex,
+                    struct module *me)
+{
+        unsigned core_plt_size = get_plt_size(
+            hdr, sechdrs, secstrings, symindex, 0);
+        unsigned init_plt_size = get_plt_size(
+            hdr, sechdrs, secstrings, symindex, 1);
+
+        if (core_plt_size > 0)
+                me->core_size = PAGE_ALIGN(me->core_size);
+        me->arch.core_plt_offset = me->core_size;
+        me->core_size = me->core_size + core_plt_size;
+
+        me->arch.init_plt_offset = me->init_size;
+        me->init_size = me->init_size + init_plt_size;
+
+        return 0;
+}
+
-static int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v)
-{
@@ -94 +265 @@
-        *location = v;
-
+        return 0;
+}
+
+static Elf_Addr add_plt_entry_to(unsigned *plt_offset,
+                                 void *start, unsigned size, Elf_Addr v)
+{
+        unsigned *tramp = start + *plt_offset;
+        if (*plt_offset == size) return 0;
+
+        *plt_offset += sizeof(unsigned[4]);
+
+        /* adjust carry for addiu */
+        if (v & 0x00008000) 
+                v += 0x10000;
+        
+        tramp[0] = 0x3c190000 | (v >> 16);      /* lui t9, hi16 */
+        tramp[1] = 0x27390000 | (v & 0xffff);   /* addiu t9, t9, lo16 */
+        tramp[2] = 0x03200008;                  /* jr t9 */
+        tramp[3] = 0x00000000;                  /* nop */
+        
+        return (Elf_Addr) tramp;
+}
+
+static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)
+{
+        if (location >= me->module_core
+            && location < me->module_core + me->core_size) {
+                return add_plt_entry_to(&me->arch.core_plt_offset,
+                                        me->module_core, me->core_size, v);
+        } else if (location > me->module_init
+                   && location < me->module_init + me->init_size) {
+                return add_plt_entry_to(&me->arch.init_plt_offset,
+                                        me->module_init, me->init_size, v);
+        } else {
+                printk(KERN_ERR "module %s: "
+                       "relocation to unknown segment %u\n",
+                       me->name, v);
+        }
-        return 0;
-}
@@ -105 +314 @@
-
-        if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
+                v = add_plt_entry(me, location,
+                                  v + ((*location & 0x03ffffff) << 2));
+                if (v == 0) {
-                printk(KERN_ERR
-                       "module %s: relocation overflow\n",
@@ -110 +322 @@
-                return -ENOEXEC;
-        }
+                *location = (*location & ~0x03ffffff) |
+                            ((v >> 2) & 0x03ffffff);
+                return 0;
+        }
-
-        *location = (*location & ~0x03ffffff) |
@@ -125 +341 @@
-
-        if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
+                v = add_plt_entry(me, location, v);
+                if (v == 0) {
-                printk(KERN_ERR
-                       "module %s: relocation overflow\n",
-                       me->name);
-                return -ENOEXEC;
+        }
-        }
-
@@ -400 +619 @@
-                spin_unlock_irq(&dbe_lock);
-        }
+
+        if (me->arch.core_plt_offset < me->core_size
+            && PAGE_ALIGN(me->arch.core_plt_offset) == me->arch.core_plt_offset
+            && is_phys(me->module_core)) {
+                free_phys(me->module_core + me->arch.core_plt_offset,
+                          me->core_size - me->arch.core_plt_offset);
+                me->core_size = me->arch.core_plt_offset;
+        }
-        return 0;
-}

src/linux/rt2880/linux-2.6.23/arch/mips/kernel/scall32-o32.S

@@ -647 +647 @@
-        sys     sys_ppoll               5
-        sys     sys_unshare             1
-4
+6
-        sys     sys_sync_file_range     7       /* 4305 */
-        sys     sys_tee                 4

src/linux/rt2880/linux-2.6.23/arch/mips/kernel/vmlinux.lds.S

@@ -135 +135 @@
-    *(.bss)
-    *(COMMON)
-
+
+
-  __bss_stop = .;
-

src/linux/rt2880/linux-2.6.23/arch/mips/mm/c-r4k.c

@@ -929 +929 @@
-                c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
-
+#ifdef CONFIG_CPU_HAS_PREFETCH
-                c->options |= MIPS_CPU_PREFETCH;
+#endif
-                break;
-        }

src/linux/rt2880/linux-2.6.23/arch/mips/rt2880/init.c

@@ -351 +351 @@
-        prom_meminit();
-        prom_setup_printf(prom_get_ttysnum());
+//      *(unsigned long *)(KSEG1ADDR(RALINK_USB_OTG_BASE+0xE00)) = 0x0; //Enable USB Port
-        prom_printf("\nLINUX started...\n");
-#if defined(CONFIG_RT2880_FPGA) || defined(CONFIG_RT3052_FPGA) || defined(CONFIG_RT2883_FPGA)

src/linux/rt2880/linux-2.6.23/drivers/net/Makefile

@@ -285 +285 @@
-obj-$(CONFIG_USB_PEGASUS)       += usb/
-obj-$(CONFIG_USB_RTL8150)       += usb/
+obj-$(CONFIG_USB_HSO)           += usb/
-obj-$(CONFIG_USB_USBNET)        += usb/
-obj-$(CONFIG_USB_ZD1201)        += usb/

src/linux/rt2880/linux-2.6.23/drivers/net/usb/Kconfig

@@ -160 +160 @@
-          what other networking devices you have in use.
-
+config USB_HSO
+        tristate "Option USB High Speed Mobile Devices"
+        depends on USB && RFKILL
+        default n
+        help
+          Choose this option if you have an Option HSDPA/HSUPA card.
+          These cards support downlink speeds of 7.2Mbps or greater.
+
+          To compile this driver as a module, choose M here: the
+          module will be called hso.
-
-config USB_NET_CDCETHER

src/linux/rt2880/linux-2.6.23/drivers/net/usb/Makefile

@@ -7 +7 @@
-obj-$(CONFIG_USB_PEGASUS)       += pegasus.o
-obj-$(CONFIG_USB_RTL8150)       += rtl8150.o
+obj-$(CONFIG_USB_HSO)           += hso.o
-obj-$(CONFIG_USB_NET_AX8817X)   += asix.o
-obj-$(CONFIG_USB_NET_CDCETHER)  += cdc_ether.o
@@ -22 +23 @@
-EXTRA_CFLAGS += -DDEBUG
-endif
+
+ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
+EXTRA_CFLAGS   += -DDWC_HOST_ONLY
+endif

src/linux/rt2880/linux-2.6.23/drivers/usb/core/hub.c

@@ -31 +31 @@
-#include "hcd.h"
-#include "hub.h"
+
+#ifdef ENABLE_HOT_PLUG_RESET
+extern void ralink_reset(int reset_pin);
+extern int usb_hotplug_flag;
+enum
+{
+    USB_PLUG_RESET   = 1<<0,
+    USB_UNPLUG_RESET = 1<<1,
+};
+#endif
-
-#ifdef  CONFIG_USB_PERSIST

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/Kconfig

@@ -1 +1 @@
-config DWC_OTG
-ALINK
+alink
-        ---help---
- 
+
-
-onfig DWC_OTG_DEBUG
-bool "enable debug m
+hoice
+prompt "USB Operation M
-        depends on DWC_OTG
-
+
-
-config DWC_OTG_HOST_ONLY
@@ -17 +17 @@
-        depends on DWC_OTG
-
+endchoice
+
+
+config DWC_OTG_DEBUG
+        bool "Enable debug mode"
+        depends on DWC_OTG

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/Makefile

@@ -9 +9 @@
-# Use one of the following flags to compile the software in host-only or
-# device-only mode.
-
-ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
-EXTRA_CFLAGS   += -DDWC_HOST_ONLY
+EXTRA_CFLAGS   += -DDWC_EN_ISOC 
-endif
-
@@ -18 +18 @@
-endif
-
-#EXTRA_CFLAGS += -Dlinux
+EXTRA_CFLAGS   +=
-
- +
+  :
-
-    := dwc_otg_driver.o dwc_otg_attr.o
-    += dwc_otg_cil.o dwc_otg_cil_intr.o
-    += dwc_otg_pcd.o dwc_otg_pcd_intr.o
-    
+   := dwc_otg_driver.o dwc_otg_attr.o 
+   += dwc_otg_cil.o dwc_otg_cil_intr.o 
+   += dwc_otg_pcd.o dwc_otg_pcd_intr.o 
+   
-

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dummy_audio.c

@@ -85 +85 @@
-#include <asm/unaligned.h>
-
-
+
+
+
+
+
+
-#include <linux/usb_gadget.h>
-

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c

@@ -1 +1 @@
-/* ==========================================================================
-_ipmate
-1
-7-11-19 05:39:07
-537387
+
+2
+8-11-21 05:39:15
+1064918
- *
- * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
@@ -207 +207 @@
- 
- <tr>
+ <td> spramdump </td>
+ <td> Dumps the contents of core registers.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
- <td> hcddump </td>
- <td> Dumps the current HCD state.</td>
@@ -255 +261 @@
-#include <linux/types.h>
-#include <linux/stat.h>  /* permission constants */
+#include <linux/version.h>
-
-//#include <asm/sizes.h>
@@ -268 +275 @@
-#include "dwc_otg_hcd.h"
-
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-/*
- * MACROs for defining sysfs attribute
- */
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-
+struct device_attribute *attr, 
-{ \
-
+
+
-        uint32_t val; \
-        val = dwc_read_reg32 (_addr_); \
@@ -281 +290 @@
-}
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-
+
+
-{ \
-
+
+
-        uint32_t set = simple_strtoul(buf, NULL, 16); \
-        uint32_t clear = set; \
@@ -293 +304 @@
-}
-
+/*
+ * MACROs for defining sysfs attribute for 32-bit registers
+ */
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+                                        const char *buf, size_t count) \
+{ \
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+        uint32_t val = simple_strtoul(buf, NULL, 16); \
+        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
+        dwc_write_reg32(_addr_, val); \
+        return count; \
+}
+
+#else
+
+/*
+ * MACROs for defining sysfs attribute
+ */
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        val = (val & (_mask_)) >> _shift_; \
+        return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t set = simple_strtoul(buf, NULL, 16); \
+        uint32_t clear = set; \
+        clear = ((~clear) << _shift_) & _mask_; \
+        set = (set << _shift_) & _mask_; \
+        dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
+        dwc_modify_reg32(_addr_, clear, set); \
+        return count; \
+}
+
+/*
+ * MACROs for defining sysfs attribute for 32-bit registers
+ */
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val = simple_strtoul(buf, NULL, 16); \
+        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
+        dwc_write_reg32(_addr_, val); \
+        return count; \
+}
+
+#endif
+
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
@@ -302 +387 @@
-DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-
-/*
- * MACROs for defining sysfs attribute for 32-bit registers
- */
-#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
-{ \
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-        uint32_t val; \
-        val = dwc_read_reg32 (_addr_); \
-        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-}
-#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
-static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
-{ \
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-        uint32_t val = simple_strtoul(buf, NULL, 16); \
-        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
-        dwc_write_reg32(_addr_, val); \
-        return count; \
-}
-
-#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
@@ -339 +403 @@
- * Show the register offset of the Register Access.
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
-}
@@ -348 +421 @@
- * Set the register offset for the next Register Access         Read/Write
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t offset = simple_strtoul(buf, NULL, 16);
-        //dev_dbg(_dev, "Offset=0x%08x\n", offset);
@@ -363 +445 @@
-        return count;
-}
-
+(void *)
-
-
@@ -370 +452 @@
- * attribute.
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t val;
-        volatile uint32_t *addr;
@@ -399 +490 @@
- * 
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        volatile uint32_t * addr;
-        uint32_t val = simple_strtoul(buf, NULL, 16);
@@ -453 +553 @@
- * Show the HNP status bit
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        gotgctl_data_t val;
-        val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
@@ -464 +573 @@
- * Set the HNP Request bit
- */
-
+
+
+
+
+
-                          size_t count ) 
-{
-
+
+
+
+
+
+
-        uint32_t in = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
@@ -485 +603 @@
- * Show the SRP status bit
- */
-
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        gotgctl_data_t val;
-        val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
@@ -502 +629 @@
- * Set the SRP Request bit
- */
-
+
+
+
+
+
-                          size_t count ) 
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-#endif
@@ -519 +655 @@
- * Show the Bus Power status
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        hprt0_data_t val;
-        val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
@@ -531 +676 @@
- * Set the Bus Power status
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t on = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
@@ -555 +709 @@
- * Show the Bus Suspend status
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        hprt0_data_t val;
-        val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
@@ -566 +729 @@
- * Set the Bus Suspend status
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t in = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
@@ -584 +756 @@
- * Show the status of Remote Wakeup.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        dctl_data_t val;
-        val.d32 = 
-                
+               
-        return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", 
-                        
+                       
-#else
-        return sprintf(buf, "Host Only Mode!\n");
@@ -603 +784 @@
- * 
- */
-
-
+
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
-
+
+
+
+
+
+
+
-        if (val&1) {
-                dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
@@ -619 +809 @@
-}
-DEVICE_ATTR(remote_wakeup,  S_IRUGO|S_IWUSR, remote_wakeup_show, 
-        
+       
-
-/**
@@ -625 +815 @@
- * current mode of the core).
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        dwc_otg_dump_global_registers( otg_dev->core_if);
-        if (dwc_otg_is_host_mode(otg_dev->core_if)) {
@@ -634 +832 @@
-        } else {
-                dwc_otg_dump_dev_registers( otg_dev->core_if);
+
-        }
-        return sprintf( buf, "Register Dump\n" );
@@ -641 +840 @@
-
-/**
+ * Dump global registers and either host or device registers (depending on the
+ * current mode of the core).
+ */
+static ssize_t spramdump_show( struct device *_dev,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+                               struct device_attribute *attr,
+#endif
+                               char *buf) 
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#else
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#endif
+        dwc_otg_dump_spram( otg_dev->core_if);
+
+        return sprintf( buf, "SPRAM Dump\n" );
+}
+
+DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
+
+/**
- * Dump the current hcd state.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_DEVICE_ONLY
-
+
+
+
+
+
+
-        dwc_otg_hcd_dump_state(otg_dev->hcd);
-#endif
@@ -659 +890 @@
- * start transfer and two additional sample points.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_DEVICE_ONLY
-
+
+
+
+
+
+
-        dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-#endif
@@ -676 +916 @@
-#define RW_REG_COUNT 10000000
-#define MSEC_PER_JIFFIE 1000/HZ 
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        int i;
-        int time;
-        int start_jiffies;
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-
-        printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
@@ -700 +949 @@
- * output shows the number of times the register is written).
- */
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        int i;
-        int time;
-        int start_jiffies;
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-        uint32_t reg_val;
-
-        printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
@@ -728 +986 @@
-void dwc_otg_attr_create (struct lm_device *lmdev)
-{
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-}
-
@@ -787 +1048 @@
-        device_remove_file(&lmdev->dev, &dev_attr_remote_wakeup);      
-        device_remove_file(&lmdev->dev, &dev_attr_regdump);
+        device_remove_file(&lmdev->dev, &dev_attr_spramdump);
-        device_remove_file(&lmdev->dev, &dev_attr_hcddump);
-        device_remove_file(&lmdev->dev, &dev_attr_hcd_frrem);

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.h

@@ -1 +1 @@
-/* ==========================================================================
-_ipmate
-1
-7-11-19 05:39:07
-510275
+
+2
+8-11-21 05:39:15
+477051
- *
- * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_cil.c

@@ -1 +1 @@
-/* ==========================================================================
-_ipmate
-4
-07-03 07:05:18
-791271
+
+7
+12-22 11:43:05
+1117667
- *
- * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
@@ -58 +58 @@
- */
-#include <asm/unaligned.h>
+#include <linux/dma-mapping.h>
-#ifdef DEBUG
-#include <linux/jiffies.h>
@@ -65 +66 @@
-#include "dwc_otg_regs.h"
-#include "dwc_otg_cil.h"
+                
+/* Included only to access hc->qh for non-dword buffer handling 
+ * TODO: account it
+ */
+#include "dwc_otg_hcd.h"                
-
-/** 
@@ -75 +81 @@
- * configured.
- *
-_
-_
-
-
-_
-                               dwc_otg_core_params_t *_
+
+
+
+
+
+dwc_otg_core_params_t *
-{
-        dwc_otg_core_if_t *core_if = 0;
-        dwc_otg_dev_if_t *dev_if = 0;
-        dwc_otg_host_if_t *host_if = 0;
-_
+
-        int i = 0;
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-        }
-        
-        memset(core_if, 0, sizeof(dwc_otg_core_if_t));
-        
-_
+
-        core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
-        
@@ -106 +111 @@
-         * Allocate the Device Mode structures.
-         */
-
-
-
-
+
+
+
-                DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
- core_if 
+core_if
-                return 0;
-        }
@@ -140 +144 @@
-         * Allocate the Host Mode structures.
-         */
-
-
-
-
+
+
+
-                DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
- dev_if 
- core_if 
+dev_if
+core_if
-                return 0;
-        }
@@ -192 +195 @@
-        DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
-                
+        core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
+        core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+
+        DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
+        DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
+
-        DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
-        DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
@@ -209 +218 @@
-        core_if->srp_timer_started = 0;
-        
+
+        /*
+         * Create new workqueue and init works
+         */
+        core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
+        if(core_if->wq_otg == 0) {
+                DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
+                kfree(host_if);
+                kfree(dev_if);
+                kfree(core_if);
+                return 0 * HZ;
+        }
+                
+                        
+        
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
+         
+        INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
+        INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
+                
+#else
+         
+        INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
+        INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
+                
+#endif          
-        return core_if;
-}
@@ -215 +250 @@
- * This function frees the structures allocated by dwc_otg_cil_init().
- * 
-_
+
- * dwc_otg_cil_init().
- *
- */
- dwc_otg_core_if_t *_core_if 
+dwc_otg_core_if_t *core_if
-{
-        /* Disable all interrupts */
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-}
-
@@ -238 +276 @@
- * register.
- *
-_
-
-extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if 
+
+
+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if
-{
-        gahbcfg_data_t ahbcfg = { .d32 = 0};
-        ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-_
+
-}
-
@@ -251 +289 @@
- * register.
- *
-_
-
-extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if 
+
+
+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if
-{
-        gahbcfg_data_t ahbcfg = { .d32 = 0};
-        ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-_
+
-}
-
@@ -264 +302 @@
- * device and host modes.
- *
-_
-
-
-_
+
+
+
+
-{
-        dwc_otg_core_global_regs_t *global_regs = 
-_
+
-        gintmsk_data_t intr_mask = { .d32 = 0};
-        
-        /* Clear any pending OTG Interrupts */
- 
+
-        
-        /* Clear any pending interrupts */
- 
+
-        
-        /* 
@@ -285 +323 @@
-        intr_mask.b.otgintr = 1;
-        
-
-
+
-                intr_mask.b.rxstsqlvl = 1;
-        }
@@ -295 +332 @@
-        intr_mask.b.usbsuspend = 1;
-        intr_mask.b.sessreqintr = 1;
- 
+
-}
-
@@ -302 +339 @@
- * type.
- */
-_
+
-{
-        uint32_t        val;
-        hcfg_data_t             hcfg;
-
-
-
-
-
-
+
+
+
+
-                /* Full speed PHY */
-                val = DWC_HCFG_48_MHZ;
-        } 
-
-
+
-                /* High speed PHY running at full speed or high speed */
-                val = DWC_HCFG_30_60_MHZ;
@@ -322 +357 @@
-
-        DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
-_
+
-        hcfg.b.fslspclksel = val;
-_
+
-}
-
@@ -331 +366 @@
- * and the enumeration speed of the device.
- */
-_
+
-{
-        uint32_t        val;
-        dcfg_data_t             dcfg;
-
-
-
-
-
-
+
+
+
+
-                /* Full speed PHY */
-                val = 0x3;
-        }
-
-
+
-                /* High speed PHY running at full speed */
-                val = 0x1;
-        } 
-
-
+
-                /* High speed PHY running at high speed */
-                val = 0x0;
@@ -357 +389 @@
-        DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
-        
-_
+
-        dcfg.b.devspd = val;
-_
+
-}
-
@@ -366 +398 @@
- * using GHWCFG1 and GHWCFG2 registers values 
- *
-_pcd the pcd structure.
-
-_
+core_if Programming view of the DWC_otg controller
+
+
-{
-        uint32_t num_in_eps = 0;
-_
-_
-_
+
+
+
-        int i;
-        
@@ -385 +417 @@
-        }
-        
-
-
+
-                num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; 
-        }
@@ -398 +429 @@
- * using GHWCFG1 and GHWCFG2 registers values 
- *
-_pcd the pcd structure.
-
-_
+core_if Programming view of the DWC_otg controller
+
+
-{
-        uint32_t num_out_eps = 0;
-_
-_
+
+
-        int i;
-        
@@ -420 +451 @@
- * prepares the core for device mode or host mode operation.
- *
-_
-
-
-_
+
+
+
+
-{
-        int i = 0;
-        dwc_otg_core_global_regs_t *global_regs = 
-_
-_
-
+
+
+ 
-        gusbcfg_data_t usbcfg = { .d32 = 0 };
-.d32 = 0
-
-_
+ .d32 = 0 
+
+ 
-
-        /* Common Initialization */
@@ -439 +470 @@
-        usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-
+//      usbcfg.b.tx_end_delay = 1;
-        /* Program the ULPI External VBUS bit if needed */
-        usbcfg.b.ulpi_ext_vbus_drv = 
-_
+
-
-        /* Set external TS Dline pulsing */
-_
+
-        dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
-
+        
-        /* Reset the Controller */
- _core_if 
+core_if
-
-        /* Initialize parameters from Hardware configuration registers. */
-_
-_
-
-
-_
-
-_
+
+
+
+
+ 
+
+
-        {
-                dev_if->perio_tx_fifo_size[i] =
- 
+
-                DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
-                                i, dev_if->perio_tx_fifo_size[i]);      
-        }
-                
-_
+
-        {
-                dev_if->tx_fifo_size[i] =
- 
+
-                DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-
-        /* This programming sequence needs to happen in FS mode before any other
-         * programming occurs */
-
-
-
+
+
-                        /* If FS mode with FS PHY */
-
+
-                        /* core_init() is now called on every switch so only call the
-                         * following for the first time through. */
-
-
-
+
+
-                                DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
-                                usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
@@ -502 +532 @@
-        
-                                /* Reset after a PHY select */
- _core_if 
+core_if
-                        }
-
@@ -508 +538 @@
-                         * do this on HNP Dev/Host mode switches (done in dev_init and
-                         * host_init). */
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-                                DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
-                                /* Program GUSBCFG.OtgUtmifsSel to I2C */
@@ -536 +563 @@
-                } /* endif speed == DWC_SPEED_PARAM_FULL */
-
-
-
+
-                        /* High speed PHY. */
-
-
-
+
+
-                                /* HS PHY parameters.  These parameters are preserved
-                                 * during soft reset so only program the first time.  Do
-                                 * a soft reset immediately after setting phyif.  */
-
-
-
+
+
-                                        /* ULPI interface */
-                                        usbcfg.b.phyif = 0;
-_
+
-                                } 
-
-
+
-                                        /* UTMI+ interface */
-_
+
-                                                usbcfg.b.phyif = 1;
-                                } 
-
-
+
-                                        usbcfg.b.phyif = 0;
-                                }
-                        }
-
- 
+
-
-                        /* Reset after setting the PHY parameters */
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-                DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
-                usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
@@ -581 +602 @@
-                dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
-        }
-
-
+
-                usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
-                usbcfg.b.ulpi_fsls = 0;
@@ -590 +610 @@
-
-        /* Program the GAHBCFG Register.*/
-
-
+
-
-        case DWC_SLAVE_ONLY_ARCH:
@@ -597 +616 @@
-                ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-                ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-
+
+
-                break;
-
-        case DWC_EXT_DMA_ARCH:
-                DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
-
-
+
+
+
-                break;
-
-        case DWC_INT_DMA_ARCH:
-                DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
-
-
+
+
+
-                break;
-
-        }
-
-
+
-        dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
-
-
-
+
+
+
+
+
+
-        
-        /* 
-         * Program the GUSBCFG register. 
-         */
-
-
-
-
+
+
+
-        case DWC_MODE_HNP_SRP_CAPABLE:
-_
+
-                   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-_
+
-                   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-                break;
@@ -636 +660 @@
-        case DWC_MODE_SRP_ONLY_CAPABLE:
-                usbcfg.b.hnpcap = 0;
-_
+
-                   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-                break;
@@ -647 +671 @@
-        case DWC_MODE_SRP_CAPABLE_DEVICE:
-                usbcfg.b.hnpcap = 0;
-_
+
-                DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-                break;
@@ -658 +682 @@
-        case DWC_MODE_SRP_CAPABLE_HOST:
-                usbcfg.b.hnpcap = 0;
-_
+
-                DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-                break;
@@ -668 +692 @@
-        }
-
- 
+
-        
-        /* Enable common interrupts */
- _core_if 
+core_if
-
-        /* Do device or host intialization based on mode during PCD
-         * and HCD initialization  */
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-#ifdef DWC_DEVICE_ONLY
- _core_if 
+core_if
-#endif
-        }
@@ -694 +716 @@
- * This function enables the Device mode interrupts.
- *
-_
-
-_
+
+
+
-{
-        gintmsk_data_t intr_mask = { .d32 = 0};
-        dwc_otg_core_global_regs_t *global_regs = 
-_
-
+
+
-        DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-
-        /* Disable all interrupts. */
- 
+
-        
-        /* Clear any pending interrupts */
- 
+
-
-        /* Enable the common interrupts */
- _core_if 
+core_if
-
-        /* Enable interrupts */
-        intr_mask.b.usbreset = 1;
-        intr_mask.b.enumdone = 1;
-
-
+
+
+
+
+
+
-        intr_mask.b.erlysuspend = 1;
-                
-
-
+
-                intr_mask.b.epmismatch = 1;
-        }
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-#ifdef USE_PERIODIC_EP
-        intr_mask.b.isooutdrop = 1;
@@ -733 +777 @@
-#endif
-
- 
+
-
-        DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, 
- 
+
-}
-
@@ -743 +787 @@
- * device mode.
- * 
-_
-
-
-_
+
+
+
+
-{
-        int i;
-        dwc_otg_core_global_regs_t *global_regs = 
-_
-_
-_
-
-=
+
+
+
+ 
+ = 
-        uint32_t rx_fifo_size;
-        fifosize_data_t nptxfifosize;
@@ -762 +806 @@
-                        
-        /* Restart the Phy Clock */
-_
+
-        
-        /* Device configuration register */
-
-
+
+
+
-        dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
-
+
+
-
-        /* Configure data FIFO sizes */
-
-
-
+
+
-                DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
-                DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
@@ -782 +827 @@
-                
-                rx_fifo_size = params->dev_rx_fifo_size;
- &global_regs->grxfsiz, rx_fifo_size 
+&global_regs->grxfsiz, rx_fifo_size
-                
-                DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", 
@@ -788 +833 @@
-                
-                /** Set Periodic Tx FIFO Mask all bits 0 */
-_
+
-                
-                /** Set Tx FIFO Mask all bits 0 */
-
-
-
-
+
+
+
-                        /* Non-periodic Tx FIFO */
-                        DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", 
@@ -802 +846 @@
-                        nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-                        
- &global_regs->gnptxfsiz, nptxfifosize.d32 
+&global_regs->gnptxfsiz, nptxfifosize.d32
-                        
-                        DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", 
@@ -816 +860 @@
-                        /** @todo Finish debug of this */       
-                        ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-_
+
-                        {
-                                ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
-                                DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, 
-                                                        dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
- 
- 
+
+
-                                DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, 
-                                                        dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
@@ -828 +872 @@
-                        }
-                }
-
-
+
-                        /*
-                         * Tx FIFOs These FIFOs are numbered from 1 to 15.
@@ -845 +888 @@
-                        nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-                        
- &global_regs->gnptxfsiz, nptxfifosize.d32 
+&global_regs->gnptxfsiz, nptxfifosize.d32
-                        
-                        DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", 
@@ -865 +908 @@
-#endif
-                        {
-//Modify by kaiker,
+
-                                txfifosize.b.depth = params->dev_tx_fifo_size[i];
-                                //txfifosize.b.depth = dev_if->tx_fifo_size[i];
-                                
-                                DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i, 
-                                        dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
-                          
- 
- 
+
+
-
-                                DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i, 
@@ -883 +925 @@
-        }
-        /* Flush the FIFOs */
-_
-_
+
+
-
-        /* Flush the Learning Queue. */
-        resetctl.b.intknqflsh = 1;
- &_
+&
-
-        /* Clear all pending Device Interrupts */
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-        for (i=0; i <= dev_if->num_in_eps; i++) 
-        {
-                depctl_data_t depctl;
-                depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
-
-
+
-                        depctl.d32 = 0;
-                        depctl.b.epdis = 1;
-                        depctl.b.snak = 1;
-                } 
-
-
+
-                        depctl.d32 = 0;
-                }
-                
- 
-
-
- 
- 
- 
+
+
+
+
+
+
-        }
-        
@@ -923 +983 @@
-                depctl_data_t depctl;
-                depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
-
-
+
-                        depctl.d32 = 0;
-                        depctl.b.epdis = 1;
-                        depctl.b.snak = 1;
-                } 
-
-
+
-                        depctl.d32 = 0;
-                }
-                
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
-                        
-
-
-
+
+
+
+
-                        
-                dthrctl.d32 = 0;
@@ -958 +1016 @@
-                dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
-                        
- 
+
-
-                DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
@@ -965 +1023 @@
-        }
-                
- _core_if 
+core_if
-
-        {
-.d32 = 0
+ .d32 = 0 
-                msk.b.txfifoundrn = 1;
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-}
-
@@ -979 +1047 @@
- * This function enables the Host mode interrupts.
- *
-_
-
-_
-
-_
-.d32 = 0
+
+
+
+
+
+ .d32 = 0 
-
-        DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
@@ -995 +1063 @@
-
-        /* Enable the common interrupts */
-_
+
-
-        /*
@@ -1011 +1079 @@
- * This function disables the Host Mode interrupts.
- *
-_
-
-_
+
+
+
-{
-        dwc_otg_core_global_regs_t *global_regs =
-_
-.d32 = 0
+
+ .d32 = 0 
-
-        DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
@@ -1042 +1110 @@
- * performing transfers.
- *
-_
-
-
-_
-
-_
-_
-_
-.d32 = 0
+
+
+
+
+
+
+
+
+ .d32 = 0 
-        fifosize_data_t         nptxfifosize;
-        fifosize_data_t         ptxfifosize;
@@ -1058 +1126 @@
-        dwc_otg_hc_regs_t       *hc_regs;
-        int                     num_channels;
-.d32 = 0
-
-_
+ .d32 = 0 
+
+
-
-        /* Restart the Phy Clock */
-_
+
-        
-        /* Initialize Host Configuration Register */
-_
-_
+
+
-        {
-                hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
@@ -1075 +1143 @@
-
-        /* Configure data FIFO sizes */
-
-
-
+
+
-                DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
-                DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
-                DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
-
- 
+
+
-                DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
-                dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
@@ -1104 +1171 @@
-        /* Clear Host Set HNP Enable in the OTG Control Register */
-        gotgctl.b.hstsethnpen = 1;
- 
+
-
-        /* Make sure the FIFOs are flushed. */
-_
-_
+
+
-
-        /* Flush out any leftover queued requests. */
-_
+
-        for (i = 0; i < num_channels; i++) 
-        {
-_
+
-                hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-                hcchar.b.chen = 0;
@@ -1126 +1193 @@
-        {
-                int count = 0;
-_
+
-                hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-                hcchar.b.chen = 1;
@@ -1133 +1200 @@
-                dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-                DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
-
-
+
-                        hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-                        if (++count > 1000) 
@@ -1147 +1213 @@
-
-        /* Turn on the vbus power. */
-
-
-
-
+
+
+
-                DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
-
-
+
-                        hprt0.b.prtpwr = 1;
-                        dwc_write_reg32(host_if->hprt0, hprt0.d32);
@@ -1159 +1223 @@
-        }
-
- _core_if 
+core_if
-}
-
@@ -1168 +1232 @@
- * transfer is in progress are enabled.
- *
-_
-_
-
-_core_if, dwc_hc_t *_
+
+
+
+core_if, dwc_hc_t *
-{
-        uint32_t intr_enable;
-        hcintmsk_data_t hc_intr_mask;
-.d32 = 0
+ .d32 = 0 
-        hcchar_data_t hcchar;
-        hcsplt_data_t hcsplt;
-
-_
-_
+
+
-        dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
-
@@ -1191 +1255 @@
-        hc_intr_mask.d32 = 0;
-        hc_intr_mask.b.chhltd = 1;
-
-
+
-                hc_intr_mask.b.ahberr = 1;
-
-
-
+
+
-                        hc_intr_mask.b.ack = 1;
-
-
+
-                                hc_intr_mask.b.datatglerr = 1;
-
-
+
-                                        hc_intr_mask.b.nak = 1;
-                                }
@@ -1208 +1268 @@
-                }
-        } 
-
-
-
-
+
+
-                case DWC_OTG_EP_TYPE_CONTROL:
-                case DWC_OTG_EP_TYPE_BULK:
@@ -1218 +1276 @@
-                        hc_intr_mask.b.xacterr = 1;
-                        hc_intr_mask.b.datatglerr = 1;
-
-
+
-                                hc_intr_mask.b.bblerr = 1;
-                        } 
-
-
+
-                                hc_intr_mask.b.nak = 1;
-                                hc_intr_mask.b.nyet = 1;
-
-
+
-                                        hc_intr_mask.b.ack = 1;
-                                }
-                        }
-
-
-
+
-                                hc_intr_mask.b.nak = 1;
-
-
+
-                                        hc_intr_mask.b.nyet = 1;
-                                }
-
-
+
-                                        hc_intr_mask.b.ack = 1;
-                                }
-                        }
-
-
-
+
-                                hc_intr_mask.b.ack = 1;
-                        }
@@ -1258 +1309 @@
-                        hc_intr_mask.b.frmovrun = 1;
-
-
-
+
-                                hc_intr_mask.b.bblerr = 1;
-                        }
-
-
+
-                                hc_intr_mask.b.ack = 1;
-                        }
-
-
-
-
+
+
-                                        hc_intr_mask.b.nyet = 1;
-                                }
-
-
+
-                                        hc_intr_mask.b.ack = 1;
-                                }
@@ -1283 +1329 @@
-                        hc_intr_mask.b.ack = 1;
-
-
-
+
-                                hc_intr_mask.b.xacterr = 1;
-                                hc_intr_mask.b.bblerr = 1;
@@ -1293 +1338 @@
-        dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
-
+//      if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
+//                      hc->max_packet = 512;
-        /* Enable the top level host channel interrupt. */
-        intr_enable = (1 << hc_num);
@@ -1299 +1346 @@
-        /* Make sure host channel interrupts are enabled. */
-        gintmsk.b.hcintr = 1;
-_
+
-        
-        /*
@@ -1306 +1353 @@
-         */
-        hcchar.d32 = 0;
-_
-_
-_
-_
-_
-_
+
+
+
+
+
+
-
-        dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
-
-_
+
-        DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
-        DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
@@ -1328 +1375 @@
-         */
-        hcsplt.d32 = 0;
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-                DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
-_
+
-        }
-        dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
@@ -1371 +1417 @@
- * deactivation of the host channel.
- *
-_
-_
-_
-
-_
-_
-_
+
+
+
+
+
+
+
-{
-        gnptxsts_data_t                 nptxsts;
@@ -1386 +1432 @@
-        dwc_otg_host_global_regs_t      *host_global_regs;
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-                /*
-                 * Disable all channel interrupts except Ch Halted. The QTD
@@ -1418 +1463 @@
-                 * reason.
-                 */
-_hc->halt_status = _
+hc->halt_status = 
-
-                hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-
-
+
-                        /*
-                         * The channel is either already halted or it hasn't
@@ -1438 +1482 @@
-        }
-
-
-
+
-                /*
-                 * A halt has already been issued for this channel. This might
@@ -1447 +1490 @@
-#ifdef DEBUG
-                DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
-_
-
-_
-_
+
+
+
+
-#endif          
-                return;
@@ -1459 +1502 @@
-        hcchar.b.chdis = 1;
-
-
-
+
-                /* Check for space in the request queue to issue the halt. */
-
-
-
+
+
-                        nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
-
-
+
-                                hcchar.b.chen = 0;
-                        }
-                } 
-
-
+
-                        hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
-
-
+
-                                hcchar.b.chen = 0;
-                        }
@@ -1483 +1521 @@
-        dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
-
-
-
-
-
-
-
+
+
+
+
+
-        } 
-
-
-
-
-
-
+
+
+
+
+
-        DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
-_
-_
-_
+
+
+
-
-        return;
@@ -1508 +1544 @@
- * called after a transfer is done and the host channel is being released.
- *
-_
-_
-
-_core_if, dwc_hc_t *_
+
+
+
+core_if, dwc_hc_t *
-{
-        dwc_otg_hc_regs_t *hc_regs;
-
-_
+
-
-        /*
@@ -1521 +1557 @@
-         * conditions.
-         */
-_core_if->host_if->hc_regs[_
+core_if->host_if->hc_regs[
-        dwc_write_reg32(&hc_regs->hcintmsk, 0);
-        dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
-
-#ifdef DEBUG
-_core_if->hc_xfer_timer[_
+core_if->hc_xfer_timer[
-        {
-                hcchar_data_t hcchar;
-                hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
-
-
+
-                        DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-_
+
-                }
-        }
@@ -1544 +1579 @@
- * effect on non-periodic transfers.
- *
-_
-_
-_
+
+
+
- * channel.
- */
-
-
-
-
-
-
-
+
+
+
+
+
+
-                hfnum_data_t    hfnum;
-_
+
-                
-                /* 1 if _next_ frame is odd, 0 if it's even */
-_
+
-#ifdef DEBUG
-
-
-
-
+
+
-                        case 7:
-_
-_
+
+
-                                break;
-                        case 0:
-_
-_
+
+
-                                break;
-                        default:
-_
-_
+
+
-                                break;
-                        }
@@ -1585 +1617 @@
-
-#ifdef DEBUG
-_
-
-_
+
+
+
-        int hc_num = xfer_info->hc->hc_num;
-        DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
@@ -1608 +1640 @@
- * additional data packets are requested in the Host ISR.
- *
-
+
+
+
+
- * register along with a packet count of 1 and the channel is enabled. This
- * causes a single PING transaction to occur. Other fields in HCTSIZ are
@@ -1619 +1654 @@
- * transfer.
- *
-_
-_
+
+
- * value may be reduced to accommodate the max widths of the XferSize and
- * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
- * to reflect the final xfer_len value.
- */
-_core_if, dwc_hc_t *_
+core_if, dwc_hc_t *
-{
-        hcchar_data_t hcchar;
-        hctsiz_data_t hctsiz;
-        uint16_t num_packets;
-_
-_
-_core_if->host_if->hc_regs[_
+
+
+core_if->host_if->hc_regs[
-
-        hctsiz.d32 = 0;
-
-
-
-
-
-
-
+
+
+
+
-                        return;
-                } 
-
-
+
-                        hctsiz.b.dopng = 1;
-                }
-        }
-
-
-
+
-                num_packets = 1;
-
-
-
+
-                        /* For CSPLIT OUT Transfer, set the size to 0 so the
-                         * core doesn't expect any data written to the FIFO */
-_
+
-                } 
-
-
-
+
+
-                } 
-
-
-
-
-
-
+
+
+
+
+
-        } 
-
-
+
-                /*
-                 * Ensure that the transfer length and packet count will fit
-                 * in the widths allocated for them in the HCTSIZn register.
-                 */
-
-
-
+
+
-                        /*
-                         * Make sure the transfer size is no larger than one
@@ -1687 +1713 @@
-                         * programmed into a channel.)
-                         */
-
-
-
-
+
+
+
-                        } 
-
-{
-
+{
+}
+
-                } 
-
-
+
-                        /* Make sure that xfer_len is a multiple of max packet size. */
-
-
-
-
-
-
-
-
+
+
+
+
+
+
-                                num_packets = max_hc_pkt_count;
-_hc->xfer_len = num_packets * _
+hc->xfer_len = num_packets * 
-                        }
-                } 
-
-
+
-                        /* Need 1 packet for transfer length of 0. */
-                        num_packets = 1;
-                }
-
-
-
+
-                        /* Always program an integral # of max packets for IN transfers. */
-
-
-
-
-
-
+
+
+
+
+
-                        /*
-                         * Make sure that the multi_count field matches the
-                         * actual transfer length.
-                         */
-
-
-
-
-
+
+
+
+
-                        /* Set up the initial PID for the transfer. */
-
-
-
-
-
-
-
+
+
+
+
-                                        } 
-
-
-
+
+
-                                        } 
-
-
-
+
+
-                                        }
-                                } 
-
-
-
-
-
+
+
+
-                                        } 
-
-
-
+
+
-                                        }
-                                }
-                        } 
-
-
-
-
-
-
-
-
-
-
+
+
+