Changeset 12433 for src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c

Timestamp:

07/03/2009 04:48:37 PM (8 months ago)

Author:

BrainSlayer

Message:

fixes usb issues with some devices

Files:

• src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c (modified) (31 diffs)

src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_attr.c

@@ -1 +1 @@
-/* ==========================================================================
-_ipmate
-1
-7-11-19 05:39:07
-537387
+
+2
+8-11-21 05:39:15
+1064918
- *
- * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
@@ -207 +207 @@
- 
- <tr>
+ <td> spramdump </td>
+ <td> Dumps the contents of core registers.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
- <td> hcddump </td>
- <td> Dumps the current HCD state.</td>
@@ -255 +261 @@
-#include <linux/types.h>
-#include <linux/stat.h>  /* permission constants */
+#include <linux/version.h>
-
-//#include <asm/sizes.h>
@@ -268 +275 @@
-#include "dwc_otg_hcd.h"
-
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-/*
- * MACROs for defining sysfs attribute
- */
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-
+struct device_attribute *attr, 
-{ \
-
+
+
-        uint32_t val; \
-        val = dwc_read_reg32 (_addr_); \
@@ -281 +290 @@
-}
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-
+
+
-{ \
-
+
+
-        uint32_t set = simple_strtoul(buf, NULL, 16); \
-        uint32_t clear = set; \
@@ -293 +304 @@
-}
-
+/*
+ * MACROs for defining sysfs attribute for 32-bit registers
+ */
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+                                        const char *buf, size_t count) \
+{ \
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+        uint32_t val = simple_strtoul(buf, NULL, 16); \
+        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
+        dwc_write_reg32(_addr_, val); \
+        return count; \
+}
+
+#else
+
+/*
+ * MACROs for defining sysfs attribute
+ */
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        val = (val & (_mask_)) >> _shift_; \
+        return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t set = simple_strtoul(buf, NULL, 16); \
+        uint32_t clear = set; \
+        clear = ((~clear) << _shift_) & _mask_; \
+        set = (set << _shift_) & _mask_; \
+        dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
+        dwc_modify_reg32(_addr_, clear, set); \
+        return count; \
+}
+
+/*
+ * MACROs for defining sysfs attribute for 32-bit registers
+ */
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val; \
+        val = dwc_read_reg32 (_addr_); \
+        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
+{ \
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
+        uint32_t val = simple_strtoul(buf, NULL, 16); \
+        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
+        dwc_write_reg32(_addr_, val); \
+        return count; \
+}
+
+#endif
+
-#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
-DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
@@ -302 +387 @@
-DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-
-/*
- * MACROs for defining sysfs attribute for 32-bit registers
- */
-#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
-static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
-{ \
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-        uint32_t val; \
-        val = dwc_read_reg32 (_addr_); \
-        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-}
-#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
-static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
-{ \
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
-        uint32_t val = simple_strtoul(buf, NULL, 16); \
-        dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
-        dwc_write_reg32(_addr_, val); \
-        return count; \
-}
-
-#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
@@ -339 +403 @@
- * Show the register offset of the Register Access.
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
-}
@@ -348 +421 @@
- * Set the register offset for the next Register Access         Read/Write
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t offset = simple_strtoul(buf, NULL, 16);
-        //dev_dbg(_dev, "Offset=0x%08x\n", offset);
@@ -363 +445 @@
-        return count;
-}
-
+(void *)
-
-
@@ -370 +452 @@
- * attribute.
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t val;
-        volatile uint32_t *addr;
@@ -399 +490 @@
- * 
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        volatile uint32_t * addr;
-        uint32_t val = simple_strtoul(buf, NULL, 16);
@@ -453 +553 @@
- * Show the HNP status bit
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        gotgctl_data_t val;
-        val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
@@ -464 +573 @@
- * Set the HNP Request bit
- */
-
+
+
+
+
+
-                          size_t count ) 
-{
-
+
+
+
+
+
+
-        uint32_t in = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
@@ -485 +603 @@
- * Show the SRP status bit
- */
-
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        gotgctl_data_t val;
-        val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
@@ -502 +629 @@
- * Set the SRP Request bit
- */
-
+
+
+
+
+
-                          size_t count ) 
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-#endif
@@ -519 +655 @@
- * Show the Bus Power status
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        hprt0_data_t val;
-        val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
@@ -531 +676 @@
- * Set the Bus Power status
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t on = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
@@ -555 +709 @@
- * Show the Bus Suspend status
- */
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        hprt0_data_t val;
-        val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
@@ -566 +729 @@
- * Set the Bus Suspend status
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        uint32_t in = simple_strtoul(buf, NULL, 16);
-        uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
@@ -584 +756 @@
- * Show the status of Remote Wakeup.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
+
+
+
+
+
+
-        dctl_data_t val;
-        val.d32 = 
-                
+               
-        return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", 
-                        
+                       
-#else
-        return sprintf(buf, "Host Only Mode!\n");
@@ -603 +784 @@
- * 
- */
-
-
+
+
+
+
+
+
-{
-#ifndef DWC_HOST_ONLY
-
-
+
+
+
+
+
+
+
-        if (val&1) {
-                dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
@@ -619 +809 @@
-}
-DEVICE_ATTR(remote_wakeup,  S_IRUGO|S_IWUSR, remote_wakeup_show, 
-        
+       
-
-/**
@@ -625 +815 @@
- * current mode of the core).
- */
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        dwc_otg_dump_global_registers( otg_dev->core_if);
-        if (dwc_otg_is_host_mode(otg_dev->core_if)) {
@@ -634 +832 @@
-        } else {
-                dwc_otg_dump_dev_registers( otg_dev->core_if);
+
-        }
-        return sprintf( buf, "Register Dump\n" );
@@ -641 +840 @@
-
-/**
+ * Dump global registers and either host or device registers (depending on the
+ * current mode of the core).
+ */
+static ssize_t spramdump_show( struct device *_dev,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+                               struct device_attribute *attr,
+#endif
+                               char *buf) 
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#else
+        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#endif
+        dwc_otg_dump_spram( otg_dev->core_if);
+
+        return sprintf( buf, "SPRAM Dump\n" );
+}
+
+DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
+
+/**
- * Dump the current hcd state.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_DEVICE_ONLY
-
+
+
+
+
+
+
-        dwc_otg_hcd_dump_state(otg_dev->hcd);
-#endif
@@ -659 +890 @@
- * start transfer and two additional sample points.
- */
-
+
+
+
+
+
-{
-#ifndef DWC_DEVICE_ONLY
-
+
+
+
+
+
+
-        dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-#endif
@@ -676 +916 @@
-#define RW_REG_COUNT 10000000
-#define MSEC_PER_JIFFIE 1000/HZ 
-
-
+
+
+
+
+
+
+
+
+
+
+
+
-        int i;
-        int time;
-        int start_jiffies;
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-
-        printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
@@ -700 +949 @@
- * output shows the number of times the register is written).
- */
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-        int i;
-        int time;
-        int start_jiffies;
-        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
-        uint32_t reg_val;
-
-        printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
@@ -728 +986 @@
-void dwc_otg_attr_create (struct lm_device *lmdev)
-{
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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+
+
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+
+
+
+
+
+
+
+
-}
-
@@ -787 +1048 @@
-        device_remove_file(&lmdev->dev, &dev_attr_remote_wakeup);      
-        device_remove_file(&lmdev->dev, &dev_attr_regdump);
+        device_remove_file(&lmdev->dev, &dev_attr_spramdump);
-        device_remove_file(&lmdev->dev, &dev_attr_hcddump);
-        device_remove_file(&lmdev->dev, &dev_attr_hcd_frrem);