- Timestamp:
- 07/03/2009 04:48:37 PM (9 months ago)
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src/linux/rt2880/linux-2.6.23/drivers/usb/dwc_otg/dwc_otg_hcd.c
r11800 r12433 1 1 /* ========================================================================== 2 * $File: //dwh/usb_iip/dev/software/otg _ipmate/linux/drivers/dwc_otg_hcd.c $3 * $Revision: 1. 3$4 * $Date: 2008- 05-30 11:56:59$5 * $Change: 762293$2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ 3 * $Revision: 1.4 $ 4 * $Date: 2008-11-21 05:39:15 $ 5 * $Change: 1064940 $ 6 6 * 7 7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 8 8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 9 9 * otherwise expressly agreed to in writing between Synopsys and you. 10 * 10 * 11 11 * The Software IS NOT an item of Licensed Software or Licensed Product under 12 12 * any End User Software License Agreement or Agreement for Licensed Product … … 18 18 * Synopsys. If you do not agree with this notice, including the disclaimer 19 19 * below, then you are not authorized to use the Software. 20 * 20 * 21 21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 22 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE … … 49 49 #include <linux/string.h> 50 50 #include <linux/dma-mapping.h> 51 #include <linux/version.h> 52 51 53 //#include <asm/arch/lm.h> 52 54 #include <asm/rt2880/lm.h> … … 57 59 #include "dwc_otg_regs.h" 58 60 59 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";61 static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; 60 62 61 63 static const struct hc_driver dwc_otg_hc_driver = { … … 69 71 .flags = HCD_MEMORY | HCD_USB2, 70 72 71 //.reset = 73 //.reset = 72 74 .start = dwc_otg_hcd_start, 73 75 //.suspend = … … 83 85 .hub_status_data = dwc_otg_hcd_hub_status_data, 84 86 .hub_control = dwc_otg_hcd_hub_control, 85 //.hub_suspend = 87 //.hub_suspend = 86 88 //.hub_resume = 87 89 }; 88 89 90 90 91 91 /** … … 93 93 * The dwc_otg_hcd_start() must be called in a process context. 94 94 */ 95 static void hcd_start_func(struct work_struct *work) 96 { 97 dwc_otg_hcd_t *priv = container_of(work, dwc_otg_hcd_t, start_work); 98 struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(priv); 99 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); 100 if (usb_hcd) { 101 dwc_otg_hcd_start(usb_hcd); 102 } 95 static void hcd_start_func( 96 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 97 void *_vp 98 #else 99 struct work_struct *_work 100 #endif 101 ) 102 { 103 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 104 struct usb_hcd *usb_hcd = (struct usb_hcd *)_vp; 105 #else 106 struct delayed_work *dw = container_of(_work, struct delayed_work, work); 107 struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work); 108 struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv); 109 #endif 110 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); 111 if (usb_hcd) { 112 dwc_otg_hcd_start(usb_hcd); 113 } 103 114 } 104 115 … … 107 118 * connected. 108 119 * 109 * @param _p void pointer to the <code>struct usb_hcd</code>120 * @param p void pointer to the <code>struct usb_hcd</code> 110 121 */ 111 static int32_t dwc_otg_hcd_start_cb(void * _p)112 { 113 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);114 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;115 hprt0_data_t hprt0;116 117 if (core_if->op_state == B_HOST) {118 /* 119 * Reset the port. During a HNP mode switch the reset120 * needs to occur within 1ms and have a duration of at121 * least 50ms. 122 */123 hprt0.d32 = dwc_otg_read_hprt0(core_if);124 hprt0.b.prtrst = 1;125 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);126 ((struct usb_hcd *)_p)->self.is_b_host = 1;127 } else {128 ((struct usb_hcd *)_p)->self.is_b_host = 0;129 }130 122 static int32_t dwc_otg_hcd_start_cb(void *p) 123 { 124 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); 125 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; 126 hprt0_data_t hprt0; 127 128 if (core_if->op_state == B_HOST) { 129 /* 130 * Reset the port. During a HNP mode switch the reset 131 * needs to occur within 1ms and have a duration of at 132 * least 50ms. 133 */ 134 hprt0.d32 = dwc_otg_read_hprt0(core_if); 135 hprt0.b.prtrst = 1; 136 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 137 ((struct usb_hcd *)p)->self.is_b_host = 1; 138 } else { 139 ((struct usb_hcd *)p)->self.is_b_host = 0; 140 } 141 131 142 /* Need to start the HCD in a non-interrupt context. */ 132 //INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p); 133 INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); 134 schedule_work(&dwc_otg_hcd->start_work); 135 136 return 1; 137 } 138 143 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 144 INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); 145 // INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func, p); 146 #else 147 // INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); 148 INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func); 149 #endif 150 // schedule_work(&dwc_otg_hcd->start_work); 151 queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000); 152 153 return 1; 154 } 139 155 140 156 /** 141 157 * HCD Callback function for stopping the HCD. 142 158 * 143 * @param _p void pointer to the <code>struct usb_hcd</code>159 * @param p void pointer to the <code>struct usb_hcd</code> 144 160 */ 145 static int32_t dwc_otg_hcd_stop_cb( void *_p)146 { 147 struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;148 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);149 dwc_otg_hcd_stop( usb_hcd);150 return 1;151 } 152 153 static void del_xfer_timers(dwc_otg_hcd_t * _hcd)161 static int32_t dwc_otg_hcd_stop_cb(void *p) 162 { 163 struct usb_hcd *usb_hcd = (struct usb_hcd *)p; 164 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); 165 dwc_otg_hcd_stop(usb_hcd); 166 return 1; 167 } 168 169 static void del_xfer_timers(dwc_otg_hcd_t *hcd) 154 170 { 155 171 #ifdef DEBUG 156 172 int i; 157 int num_channels = _hcd->core_if->core_params->host_channels;173 int num_channels = hcd->core_if->core_params->host_channels; 158 174 for (i = 0; i < num_channels; i++) { 159 del_timer(& _hcd->core_if->hc_xfer_timer[i]);160 } 161 #endif 162 } 163 164 static void del_timers(dwc_otg_hcd_t * _hcd)165 { 166 del_xfer_timers( _hcd);167 del_timer(& _hcd->conn_timer);175 del_timer(&hcd->core_if->hc_xfer_timer[i]); 176 } 177 #endif 178 } 179 180 static void del_timers(dwc_otg_hcd_t *hcd) 181 { 182 del_xfer_timers(hcd); 183 del_timer(&hcd->conn_timer); 168 184 } 169 185 … … 172 188 * -ETIMEDOUT and frees the QTD. 173 189 */ 174 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd, struct list_head *_qh_list)190 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list) 175 191 { 176 192 struct list_head *qh_item; … … 179 195 dwc_otg_qtd_t *qtd; 180 196 181 list_for_each(qh_item, _qh_list) {197 list_for_each(qh_item, qh_list) { 182 198 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); 183 199 for (qtd_item = qh->qtd_list.next; … … 186 202 qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); 187 203 if (qtd->urb != NULL) { 188 dwc_otg_hcd_complete_urb( _hcd, qtd->urb,204 dwc_otg_hcd_complete_urb(hcd, qtd->urb, 189 205 -ETIMEDOUT); 190 206 } 191 dwc_otg_hcd_qtd_remove_and_free( qtd);207 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd); 192 208 } 193 209 } … … 200 216 * detected or when the HCD is being stopped. 201 217 */ 202 static void kill_all_urbs(dwc_otg_hcd_t * _hcd)203 { 204 kill_urbs_in_qh_list( _hcd, &_hcd->non_periodic_sched_inactive);205 kill_urbs_in_qh_list( _hcd, &_hcd->non_periodic_sched_active);206 kill_urbs_in_qh_list( _hcd, &_hcd->periodic_sched_inactive);207 kill_urbs_in_qh_list( _hcd, &_hcd->periodic_sched_ready);208 kill_urbs_in_qh_list( _hcd, &_hcd->periodic_sched_assigned);209 kill_urbs_in_qh_list( _hcd, &_hcd->periodic_sched_queued);218 static void kill_all_urbs(dwc_otg_hcd_t *hcd) 219 { 220 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); 221 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); 222 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); 223 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); 224 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); 225 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); 210 226 } 211 227 … … 213 229 * HCD Callback function for disconnect of the HCD. 214 230 * 215 * @param _p void pointer to the <code>struct usb_hcd</code>231 * @param p void pointer to the <code>struct usb_hcd</code> 216 232 */ 217 static int32_t dwc_otg_hcd_disconnect_cb( void *_p)233 static int32_t dwc_otg_hcd_disconnect_cb(void *p) 218 234 { 219 235 gintsts_data_t intr; 220 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);221 222 //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);223 224 /* 225 * Set status flags for the hub driver.226 */227 dwc_otg_hcd->flags.b.port_connect_status_change = 1;236 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); 237 238 //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); 239 240 /* 241 * Set status flags for the hub driver. 242 */ 243 dwc_otg_hcd->flags.b.port_connect_status_change = 1; 228 244 dwc_otg_hcd->flags.b.port_connect_status = 0; 229 245 230 /*231 * Shutdown any transfers in process by clearing the Tx FIFO Empty232 * interrupt mask and status bits and disabling subsequent host233 * channel interrupts.234 */235 intr.d32 = 0;236 intr.b.nptxfempty = 1;237 intr.b.ptxfempty = 1;246 /* 247 * Shutdown any transfers in process by clearing the Tx FIFO Empty 248 * interrupt mask and status bits and disabling subsequent host 249 * channel interrupts. 250 */ 251 intr.d32 = 0; 252 intr.b.nptxfempty = 1; 253 intr.b.ptxfempty = 1; 238 254 intr.b.hcintr = 1; 239 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);240 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);255 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); 256 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); 241 257 242 258 del_timers(dwc_otg_hcd); … … 248 264 */ 249 265 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { 250 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { 251 hprt0_data_t hprt0 = { .d32=0 };252 DWC_PRINT("Disconnect: PortPower off\n");253 hprt0.b.prtpwr = 0;254 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);255 }256 257 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if);258 }259 266 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { 267 hprt0_data_t hprt0 = { .d32=0 }; 268 DWC_PRINT("Disconnect: PortPower off\n"); 269 hprt0.b.prtpwr = 0; 270 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); 271 } 272 273 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); 274 } 275 260 276 /* Respond with an error status to all URBs in the schedule. */ 261 277 kill_all_urbs(dwc_otg_hcd); … … 306 322 } 307 323 308 /* A disconnect will end the session so the B-Device is no309 * longer a B-host. */310 ((struct usb_hcd *)_p)->self.is_b_host = 0; 311 return 1;324 /* A disconnect will end the session so the B-Device is no 325 * longer a B-host. */ 326 ((struct usb_hcd *)p)->self.is_b_host = 0; 327 return 1; 312 328 } 313 329 … … 316 332 * message if the device does not connect within 10 seconds. 317 333 */ 318 void dwc_otg_hcd_connect_timeout( unsigned long _ptr)319 { 320 DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int) _ptr);321 DWC_PRINT("Connect Timeout\n");322 DWC_ERROR( "Device Not Connected/Responding\n");334 void dwc_otg_hcd_connect_timeout(unsigned long ptr) 335 { 336 DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr); 337 DWC_PRINT("Connect Timeout\n"); 338 DWC_ERROR("Device Not Connected/Responding\n"); 323 339 } 324 340 … … 329 345 * timer expires. 330 346 */ 331 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)332 { 333 init_timer( &_hcd->conn_timer);334 _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;335 _hcd->conn_timer.data = (unsigned long)0;336 _hcd->conn_timer.expires = jiffies + (HZ*10);337 add_timer( &_hcd->conn_timer);347 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd) 348 { 349 init_timer(&hcd->conn_timer); 350 hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; 351 hcd->conn_timer.data = 0; 352 hcd->conn_timer.expires = jiffies + (HZ * 10); 353 add_timer(&hcd->conn_timer); 338 354 } 339 355 … … 341 357 * HCD Callback function for disconnect of the HCD. 342 358 * 343 * @param _p void pointer to the <code>struct usb_hcd</code>359 * @param p void pointer to the <code>struct usb_hcd</code> 344 360 */ 345 static int32_t dwc_otg_hcd_session_start_cb( void *_p)346 { 347 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);348 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);349 dwc_otg_hcd_start_connect_timer( dwc_otg_hcd);350 return 1;361 static int32_t dwc_otg_hcd_session_start_cb(void *p) 362 { 363 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p); 364 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); 365 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); 366 return 1; 351 367 } 352 368 … … 355 371 */ 356 372 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { 357 .start = dwc_otg_hcd_start_cb,358 .stop = dwc_otg_hcd_stop_cb,359 .disconnect = dwc_otg_hcd_disconnect_cb,360 .session_start = dwc_otg_hcd_session_start_cb,361 .p = 0,373 .start = dwc_otg_hcd_start_cb, 374 .stop = dwc_otg_hcd_stop_cb, 375 .disconnect = dwc_otg_hcd_disconnect_cb, 376 .session_start = dwc_otg_hcd_session_start_cb, 377 .p = 0, 362 378 }; 363 364 379 365 380 /** 366 381 * Reset tasklet function 367 382 */ 368 static void reset_tasklet_func (unsigned long data)369 { 370 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data;383 static void reset_tasklet_func(unsigned long data) 384 { 385 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data; 371 386 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; 372 387 hprt0_data_t hprt0; … … 374 389 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); 375 390 376 hprt0.d32 = dwc_otg_read_hprt0 (core_if);391 hprt0.d32 = dwc_otg_read_hprt0(core_if); 377 392 hprt0.b.prtrst = 1; 378 393 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 379 mdelay (60);394 mdelay(60); 380 395 381 396 hprt0.b.prtrst = 0; 382 397 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 383 dwc_otg_hcd->flags.b.port_reset_change = 1; 384 385 return; 386 } 387 388 static struct tasklet_struct reset_tasklet = { 398 dwc_otg_hcd->flags.b.port_reset_change = 1; 399 } 400 401 static struct tasklet_struct reset_tasklet = { 389 402 .next = NULL, 390 403 .state = 0, … … 400 413 * a negative error on failure. 401 414 */ 402 int dwc_otg_hcd_init(struct lm_device * _lmdev)415 int dwc_otg_hcd_init(struct lm_device *lmdev) 403 416 { 404 417 struct usb_hcd *hcd = NULL; 405 418 dwc_otg_hcd_t *dwc_otg_hcd = NULL; 406 dwc_otg_device_t *otg_dev = lm_get_drvdata(_lmdev);419 dwc_otg_device_t *otg_dev = lm_get_drvdata(lmdev); 407 420 408 421 int num_channels; … … 414 427 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); 415 428 416 #if 1 //kaiker .these code must execute before usb_create_hcd 429 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 430 /* 2.6.20+ requires dev.dma_mask to be set prior to calling usb_create_hcd() */ 431 417 432 /* Set device flags indicating whether the HCD supports DMA. */ 418 433 if (otg_dev->core_if->dma_enable) { 419 434 DWC_PRINT("Using DMA mode\n"); 420 _lmdev->dev.dma_mask = (void *)~0; 421 _lmdev->dev.coherent_dma_mask = ~0; 435 lmdev->dev.dma_mask = (void *)~0; 436 lmdev->dev.coherent_dma_mask = ~0; 437 438 if (otg_dev->core_if->dma_desc_enable) { 439 DWC_PRINT("Device using Descriptor DMA mode\n"); 440 } else { 441 DWC_PRINT("Device using Buffer DMA mode\n"); 442 } 422 443 } else { 423 444 DWC_PRINT("Using Slave mode\n"); 424 _lmdev->dev.dma_mask = (void *)0; 425 _lmdev->dev.coherent_dma_mask = 0; 426 } 427 #endif 428 445 lmdev->dev.dma_mask = (void *)0; 446 lmdev->dev.coherent_dma_mask = 0; 447 } 448 #endif 429 449 /* 430 450 * Allocate memory for the base HCD plus the DWC OTG HCD. 431 451 * Initialize the base HCD. 432 452 */ 433 hcd = usb_create_hcd(&dwc_otg_hc_driver, & _lmdev->dev, _lmdev->dev.bus_id);434 if ( hcd == NULL) {453 hcd = usb_create_hcd(&dwc_otg_hc_driver, &lmdev->dev, lmdev->dev.bus_id); 454 if (!hcd) { 435 455 retval = -ENOMEM; 436 456 goto error1; 437 457 } 458 438 459 hcd->regs = otg_dev->base; 439 hcd->self.otg_port = 1; 460 hcd->self.otg_port = 1; 440 461 441 462 /* Initialize the DWC OTG HCD. */ … … 444 465 otg_dev->hcd = dwc_otg_hcd; 445 466 446 /* Register the HCD CIL Callbacks */ 447 dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, 467 /* */ 468 spin_lock_init(&dwc_otg_hcd->lock); 469 470 /* Register the HCD CIL Callbacks */ 471 dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, 448 472 &hcd_cil_callbacks, hcd); 449 473 … … 464 488 INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); 465 489 num_channels = dwc_otg_hcd->core_if->core_params->host_channels; 490 memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array)); 466 491 for (i = 0; i < num_channels; i++) { 467 492 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); … … 476 501 #ifdef DEBUG 477 502 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); 478 #endif 479 503 #endif 480 504 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); 481 505 } 482 483 /* Initialize the Connection timeout timer. */484 init_timer( &dwc_otg_hcd->conn_timer);506 507 /* Initialize the Connection timeout timer. */ 508 init_timer(&dwc_otg_hcd->conn_timer); 485 509 486 510 /* Initialize reset tasklet. */ 487 511 reset_tasklet.data = (unsigned long) dwc_otg_hcd; 488 512 dwc_otg_hcd->reset_tasklet = &reset_tasklet; 489 #if 0 // mask by kaiker .these code must execute before usb_create_hcd 490 513 514 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 491 515 /* Set device flags indicating whether the HCD supports DMA. */ 492 516 if (otg_dev->core_if->dma_enable) { 493 517 DWC_PRINT("Using DMA mode\n"); 494 _lmdev->dev.dma_mask = (void *)~0; 495 _lmdev->dev.coherent_dma_mask = ~0; 518 lmdev->dev.dma_mask = (void *)~0; 519 lmdev->dev.coherent_dma_mask = ~0; 520 521 if (otg_dev->core_if->dma_desc_enable){ 522 DWC_PRINT("Device using Descriptor DMA mode\n"); 523 } else { 524 DWC_PRINT("Device using Buffer DMA mode\n"); 525 } 496 526 } else { 497 527 DWC_PRINT("Using Slave mode\n"); 498 _lmdev->dev.dma_mask = (void *)0;499 _lmdev->dev.coherent_dma_mask = 0;528 lmdev->dev.dma_mask = (void *)0; 529 lmdev->dev.coherent_dma_mask = 0; 500 530 } 501 531 #endif … … 505 535 * IRQ line, and calls dwc_otg_hcd_start method. 506 536 */ 507 retval = usb_add_hcd(hcd, _lmdev->irq, SA_SHIRQ);537 retval = usb_add_hcd(hcd, lmdev->irq, SA_SHIRQ); 508 538 if (retval < 0) { 509 539 goto error2; … … 518 548 if (otg_dev->core_if->dma_enable) { 519 549 dwc_otg_hcd->status_buf = 520 dma_alloc_coherent(& _lmdev->dev,550 dma_alloc_coherent(&lmdev->dev, 521 551 DWC_OTG_HCD_STATUS_BUF_SIZE, 522 552 &dwc_otg_hcd->status_buf_dma, … … 526 556 GFP_KERNEL); 527 557 } 528 if ( dwc_otg_hcd->status_buf == NULL) {558 if (!dwc_otg_hcd->status_buf) { 529 559 retval = -ENOMEM; 530 560 DWC_ERROR("%s: status_buf allocation failed\n", __func__); … … 532 562 } 533 563 534 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", 535 _lmdev->dev.bus_id, hcd->self.busnum); 536 564 dwc_otg_hcd->otg_dev = otg_dev; 565 566 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", 567 lmdev->dev.bus_id, hcd->self.busnum); 568 537 569 return 0; 538 570 … … 548 580 * dwc_otg_hcd has already been released by dwc_otg_hcd_free() 549 581 */ 550 lm_set_drvdata( _lmdev, otg_dev);582 lm_set_drvdata( lmdev, otg_dev); 551 583 552 584 error1: … … 558 590 * Frees memory and resources associated with the HCD and deregisters the bus. 559 591 */ 560 void dwc_otg_hcd_remove(struct lm_device * _lmdev)561 { 562 dwc_otg_device_t *otg_dev = lm_get_drvdata( _lmdev);563 dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;564 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);592 void dwc_otg_hcd_remove(struct lm_device *lmdev) 593 { 594 dwc_otg_device_t *otg_dev = lm_get_drvdata(lmdev); 595 dwc_otg_hcd_t *dwc_otg_hcd; 596 struct usb_hcd *hcd; 565 597 566 598 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); 567 599 600 if (!otg_dev) { 601 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); 602 return; 603 } 604 605 dwc_otg_hcd = otg_dev->hcd; 606 607 if (!dwc_otg_hcd) { 608 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); 609 return; 610 } 611 612 hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); 613 614 if (!hcd) { 615 DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__); 616 return; 617 } 618 568 619 /* Turn off all interrupts */ 569 dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);570 dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);620 dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); 621 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); 571 622 572 623 usb_remove_hcd(hcd); 573 624 dwc_otg_hcd_free(hcd); 574 625 usb_put_hcd(hcd); 575 576 return; 577 } 578 626 } 579 627 580 628 /* ========================================================================= … … 585 633 * Initializes dynamic portions of the DWC_otg HCD state. 586 634 */ 587 static void hcd_reinit(dwc_otg_hcd_t * _hcd)635 static void hcd_reinit(dwc_otg_hcd_t *hcd) 588 636 { 589 637 struct list_head *item; … … 592 640 dwc_hc_t *channel; 593 641 594 _hcd->flags.d32 = 0;595 596 _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;597 _hcd->non_periodic_channels = 0;598 _hcd->periodic_channels = 0;642 hcd->flags.d32 = 0; 643 644 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; 645 hcd->non_periodic_channels = 0; 646 hcd->periodic_channels = 0; 599 647 600 648 /* … … 602 650 * states. 603 651 */ 604 item = _hcd->free_hc_list.next;605 while (item != & _hcd->free_hc_list) {652 item = hcd->free_hc_list.next; 653 while (item != &hcd->free_hc_list) { 606 654 list_del(item); 607 item = _hcd->free_hc_list.next;608 } 609 num_channels = _hcd->core_if->core_params->host_channels;655 item = hcd->free_hc_list.next; 656 } 657 num_channels = hcd->core_if->core_params->host_channels; 610 658 for (i = 0; i < num_channels; i++) { 611 channel = _hcd->hc_ptr_array[i];612 list_add_tail(&channel->hc_list_entry, & _hcd->free_hc_list);613 dwc_otg_hc_cleanup( _hcd->core_if, channel);659 channel = hcd->hc_ptr_array[i]; 660 list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list); 661 dwc_otg_hc_cleanup(hcd->core_if, channel); 614 662 } 615 663 616 664 /* Initialize the DWC core for host mode operation. */ 617 dwc_otg_core_host_init( _hcd->core_if);665 dwc_otg_core_host_init(hcd->core_if); 618 666 } 619 667 … … 621 669 * mode operation. Activates the root port. Returns 0 on success and a negative 622 670 * error code on failure. */ 623 extern int register_root_hub(struct usb_hcd *hcd); 624 int dwc_otg_hcd_start(struct usb_hcd *_hcd) 625 { 626 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); 627 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; 628 671 int dwc_otg_hcd_start(struct usb_hcd *hcd) 672 { 673 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 674 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; 675 struct usb_bus *bus; 676 677 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 629 678 struct usb_device *udev; 630 struct usb_bus *bus;631 632 679 int retval; 680 #endif 633 681 634 682 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); 635 683 636 bus = hcd_to_bus( _hcd);684 bus = hcd_to_bus(hcd); 637 685 638 686 /* Initialize the bus state. If the core is in Device Mode 639 687 * HALT the USB bus and return. */ 640 if (dwc_otg_is_device_mode (core_if)) { 641 _hcd->state = HC_STATE_HALT; 688 if (dwc_otg_is_device_mode(core_if)) { 689 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 690 hcd->state = HC_STATE_HALT; 691 #else 692 hcd->state = HC_STATE_RUNNING; 693 #endif 642 694 return 0; 643 695 } 644 _hcd->state = HC_STATE_RUNNING;696 hcd->state = HC_STATE_RUNNING; 645 697 646 698 /* Initialize and connect root hub if one is not already attached */ 647 699 if (bus->root_hub) { 648 700 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); 649 /* Inform the HUB driver to resume. */650 usb_hcd_resume_root_hub( _hcd);651 }701 /* Inform the HUB driver to resume. */ 702 usb_hcd_resume_root_hub(hcd); 703 } 652 704 else { 705 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n"); 706 707 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 653 708 udev = usb_alloc_dev(NULL, bus, 0); 654 709 udev->speed = USB_SPEED_HIGH; … … 657 712 return -ENODEV; 658 713 } 659 if ((retval = register_root_hub(_hcd)) != 0) {714 if ((retval = usb_hcd_register_root_hub(udev, hcd)) != 0) { 660 715 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); 661 return -ENODEV; 662 } 716 return -ENODEV; 717 } 718 #endif 663 719 } 664 720 … … 668 724 } 669 725 670 static void qh_list_free(dwc_otg_hcd_t * _hcd, struct list_head *_qh_list)726 static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list) 671 727 { 672 728 struct list_head *item; 673 729 dwc_otg_qh_t *qh; 674 730 675 if ( _qh_list->next == NULL) {731 if (!qh_list->next) { 676 732 /* The list hasn't been initialized yet. */ 677 733 return; … … 679 735 680 736 /* Ensure there are no QTDs or URBs left. */ 681 kill_urbs_in_qh_list( _hcd, _qh_list);682 683 for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {737 kill_urbs_in_qh_list(hcd, qh_list); 738 739 for (item = qh_list->next; item != qh_list; item = qh_list->next) { 684 740 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); 685 dwc_otg_hcd_qh_remove_and_free( _hcd, qh);741 dwc_otg_hcd_qh_remove_and_free(hcd, qh); 686 742 } 687 743 } … … 691 747 * stopped. 692 748 */ 693 void dwc_otg_hcd_stop(struct usb_hcd * _hcd)694 { 695 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);749 void dwc_otg_hcd_stop(struct usb_hcd *hcd) 750 { 751 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 696 752 hprt0_data_t hprt0 = { .d32=0 }; 697 753 … … 699 755 700 756 /* Turn off all host-specific interrupts. */ 701 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if);757 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); 702 758 703 759 /* … … 711 767 hprt0.b.prtpwr = 0; 712 768 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); 713 714 return; 715 } 716 769 } 717 770 718 771 /** Returns the current frame number. */ 719 int dwc_otg_hcd_get_frame_number(struct usb_hcd * _hcd)720 { 721 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);772 int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd) 773 { 774 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 722 775 hfnum_data_t hfnum; 723 776 … … 727 780 #ifdef DEBUG_SOF 728 781 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); 729 #endif 782 #endif 730 783 return hfnum.b.frnum; 731 784 } … … 735 788 * in the struct usb_hcd field. 736 789 */ 737 void dwc_otg_hcd_free(struct usb_hcd * _hcd)738 { 739 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd( _hcd);790 void dwc_otg_hcd_free(struct usb_hcd *hcd) 791 { 792 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 740 793 int i; 741 794 … … 763 816 if (dwc_otg_hcd->core_if->dma_enable) { 764 817 if (dwc_otg_hcd->status_buf_dma) { 765 dma_free_coherent( _hcd->self.controller,818 dma_free_coherent(hcd->self.controller, 766 819 DWC_OTG_HCD_STATUS_BUF_SIZE, 767 820 dwc_otg_hcd->status_buf, … … 771 824 kfree(dwc_otg_hcd->status_buf); 772 825 } 773 774 return; 775 } 776 826 } 777 827 778 828 #ifdef DEBUG 779 static void dump_urb_info(struct urb * _urb, char* _fn_name)780 { 781 DWC_PRINT("%s, urb %p\n", _fn_name, _urb);782 DWC_PRINT(" Device address: %d\n", usb_pipedevice( _urb->pipe));783 DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint( _urb->pipe),784 (usb_pipein( _urb->pipe) ? "IN" : "OUT"));829 static void dump_urb_info(struct urb *urb, char* fn_name) 830 { 831 DWC_PRINT("%s, urb %p\n", fn_name, urb); 832 DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe)); 833 DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), 834 (usb_pipein(urb->pipe) ? "IN" : "OUT")); 785 835 DWC_PRINT(" Endpoint type: %s\n", 786 836 ({char *pipetype; 787 switch (usb_pipetype(_urb->pipe)) {788 case PIPE_CONTROL: pipetype = "CONTROL"; break;789 case PIPE_BULK: pipetype = "BULK"; break;790 case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;791 case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;792 default: pipetype = "UNKNOWN"; break;793 }; pipetype;}));837 switch (usb_pipetype(urb->pipe)) { 838 case PIPE_CONTROL: pipetype = "CONTROL"; break; 839 case PIPE_BULK: pipetype = "BULK"; break; 840 case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; 841 case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; 842 default: pipetype = "UNKNOWN"; break; 843 }; pipetype;})); 794 844 DWC_PRINT(" Speed: %s\n", 795 845 ({char *speed; 796 switch (_urb->dev->speed) {797 case USB_SPEED_HIGH: speed = "HIGH"; break;798 case USB_SPEED_FULL: speed = "FULL"; break;799 case USB_SPEED_LOW: speed = "LOW"; break;800 default: speed = "UNKNOWN"; break;801 }; speed;}));846 switch (urb->dev->speed) { 847 case USB_SPEED_HIGH: speed = "HIGH"; break; 848 case USB_SPEED_FULL: speed = "FULL"; break; 849 case USB_SPEED_LOW: speed = "LOW"; break; 850 default: speed = "UNKNOWN"; break; 851 }; speed;})); 802 852 DWC_PRINT(" Max packet size: %d\n", 803 usb_maxpacket( _urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));804 DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length);853 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 854 DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length); 805 855 DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", 806 _urb->transfer_buffer, (void *)_urb->transfer_dma);856 urb->transfer_buffer, (void *)urb->transfer_dma); 807 857 DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", 808 _urb->setup_packet, (void *)_urb->setup_dma);809 DWC_PRINT(" Interval: %d\n", _urb->interval);810 if (usb_pipetype( _urb->pipe) == PIPE_ISOCHRONOUS) {858 urb->setup_packet, (void *)urb->setup_dma); 859 DWC_PRINT(" Interval: %d\n", urb->interval); 860 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 811 861 int i; 812 for (i = 0; i < _urb->number_of_packets; i++) {862 for (i = 0; i < urb->number_of_packets; i++) { 813 863 DWC_PRINT(" ISO Desc %d:\n", i); 814 864 DWC_PRINT(" offset: %d, length %d\n", 815 _urb->iso_frame_desc[i].offset,816 _urb->iso_frame_desc[i].length);817 } 818 } 819 } 820 821 static void dump_channel_info(dwc_otg_hcd_t * _hcd,865 urb->iso_frame_desc[i].offset, 866 urb->iso_frame_desc[i].length); 867 } 868 } 869 } 870 871 static void dump_channel_info(dwc_otg_hcd_t *hcd, 822 872 dwc_otg_qh_t *qh) 823 873 { … … 826 876 struct list_head *item; 827 877 dwc_otg_qh_t *qh_item; 828 int num_channels = _hcd->core_if->core_params->host_channels;878 int num_channels = hcd->core_if->core_params->host_channels; 829 879 int i; 830 880 … … 835 885 uint32_t hcdma; 836 886 837 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];887 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; 838 888 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); 839 889 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); … … 855 905 DWC_PRINT(" qh: %p\n", hc->qh); 856 906 DWC_PRINT(" NP inactive sched:\n"); 857 list_for_each(item, & _hcd->non_periodic_sched_inactive) {907 list_for_each(item, &hcd->non_periodic_sched_inactive) { 858 908 qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); 859 909 DWC_PRINT(" %p\n", qh_item); 860 910 } 861 911 DWC_PRINT(" NP active sched:\n"); 862 list_for_each(item, & _hcd->non_periodic_sched_active) {912 list_for_each(item, &hcd->non_periodic_sched_active) { 863 913 qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); 864 914 DWC_PRINT(" %p\n", qh_item); … … 866 916 DWC_PRINT(" Channels: \n"); 867 917 for (i = 0; i < num_channels; i++) { 868 dwc_hc_t *hc = _hcd->hc_ptr_array[i];918 dwc_hc_t *hc = hcd->hc_ptr_array[i]; 869 919 DWC_PRINT(" %2d: %p\n", i, hc); 870 920 } … … 876 926 * (URB). mem_flags indicates the type of memory allocation to use while 877 927 * processing this URB. */ 878 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd, 879 struct usb_host_endpoint *_ep, 880 struct urb *_urb, 881 gfp_t _mem_flags) 928 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, 929 struct usb_host_endpoint *ep, 930 struct urb *urb, 931 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 932 int mem_flags 933 #else 934 gfp_t mem_flags 935 #endif 936 ) 882 937 { 883 938 int retval = 0; 884 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);939 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 885 940 dwc_otg_qtd_t *qtd; 886 941 887 942 #ifdef DEBUG 888 943 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { 889 dump_urb_info( _urb, "dwc_otg_hcd_urb_enqueue");890 } 891 #endif 944 dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue"); 945 } 946 #endif 892 947 if (!dwc_otg_hcd->flags.b.port_connect_status) { 893 948 /* No longer connected. */ … … 895 950 } 896 951 897 qtd = dwc_otg_hcd_qtd_create (_urb);952 qtd = dwc_otg_hcd_qtd_create(urb); 898 953 if (qtd == NULL) { 899 954 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); … … 901 956 } 902 957 903 retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd);958 retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd); 904 959 if (retval < 0) { 905 960 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " … … 913 968 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate 914 969 * success. */ 915 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, 916 struct urb *_urb) 970 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, 971 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 972 struct usb_host_endpoint *ep, 973 #endif 974 struct urb *urb) 917 975 { 918 976 unsigned long flags; … … 920 978 dwc_otg_qtd_t *urb_qtd; 921 979 dwc_otg_qh_t *qh; 922 struct usb_host_endpoint *_ep = dwc_urb_to_endpoint(_urb); 923 980 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 981 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); 982 #endif 924 983 925 984 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); 926 985 927 local_irq_save(flags); 928 929 dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); 930 urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv; 931 qh = (dwc_otg_qh_t *)_ep->hcpriv; 986 dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 987 988 SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); 989 990 urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv; 991 qh = (dwc_otg_qh_t *)ep->hcpriv; 932 992 933 993 #ifdef DEBUG 934 994 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { 935 dump_urb_info( _urb, "dwc_otg_hcd_urb_dequeue");995 dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue"); 936 996 if (urb_qtd == qh->qtd_in_process) { 937 997 dump_channel_info(dwc_otg_hcd, qh); 938 998 } 939 999 } 940 #endif 1000 #endif 941 1001 942 1002 if (urb_qtd == qh->qtd_in_process) { … … 960 1020 * schedule if it has any remaining QTDs. 961 1021 */ 962 dwc_otg_hcd_qtd_remove_and_free( urb_qtd);1022 dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd); 963 1023 if (urb_qtd == qh->qtd_in_process) { 964 1024 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); … … 969 1029 } 970 1030 971 local_irq_restore(flags);972 973 _urb->hcpriv = NULL;1031 SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); 1032 1033 urb->hcpriv = NULL; 974 1034 975 1035 /* Higher layer software sets URB status. */ 976 usb_hcd_giveback_urb(_hcd, _urb); 1036 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 1037 usb_hcd_giveback_urb(hcd, urb); 1038 #else 1039 usb_hcd_giveback_urb(hcd, urb, NULL); 1040 #endif 977 1041 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { 978 1042 DWC_PRINT("Called usb_hcd_giveback_urb()\n"); 979 DWC_PRINT(" urb->status = %d\n", _urb->status);1043 DWC_PRINT(" urb->status = %d\n", urb->status); 980 1044 } 981 1045 982 1046 return 0; 983 1047 } 984 985 1048 986 1049 /** Frees resources in the DWC_otg controller related to a given endpoint. Also 987 1050 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 988 1051 * must already be dequeued. */ 989 void dwc_otg_hcd_endpoint_disable(struct usb_hcd * _hcd,990 struct usb_host_endpoint * _ep)991 992 { 1052 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, 1053 struct usb_host_endpoint *ep) 1054 { 1055 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 993 1056 dwc_otg_qh_t *qh; 994 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); 1057 1058 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 1059 unsigned long flags; 1060 int retry = 0; 1061 #endif 995 1062 996 1063 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " 997 "endpoint=%d\n", _ep->desc.bEndpointAddress, 998 dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress)); 999 1000 qh = (dwc_otg_qh_t *)(_ep->hcpriv); 1064 "endpoint=%d\n", ep->desc.bEndpointAddress, 1065 dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); 1066 1067 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 1068 rescan: 1069 SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); 1070 qh = (dwc_otg_qh_t *)(ep->hcpriv); 1071 if (!qh) 1072 goto done; 1073 1074 /** Check that the QTD list is really empty */ 1075 if (!list_empty(&qh->qtd_list)) { 1076 if (retry++ < 250) { 1077 SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); 1078 schedule_timeout_uninterruptible(1); 1079 goto rescan; 1080 } 1081 1082 DWC_WARN("DWC OTG HCD EP DISABLE:" 1083 " QTD List for this endpoint is not empty\n"); 1084 } 1085 1086 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); 1087 ep->hcpriv = NULL; 1088 done: 1089 SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); 1090 1091 #else // LINUX_VERSION_CODE 1092 1093 qh = (dwc_otg_qh_t *)(ep->hcpriv); 1001 1094 if (qh != NULL) { 1002 1095 #ifdef DEBUG … … 1007 1100 } 1008 1101 #endif 1009 1010 1102 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); 1011 _ep->hcpriv = NULL; 1012 } 1013 1014 return; 1103 ep->hcpriv = NULL; 1104 } 1105 #endif // LINUX_VERSION_CODE 1015 1106 } 1016 1107 … … 1020 1111 * 1021 1112 * This function is called by the USB core when an interrupt occurs */ 1022 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd) 1023 { 1024 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); 1113 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd 1114 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) 1115 , struct pt_regs *regs 1116 #endif 1117 ) 1118 { 1119 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 1025 1120 return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); 1026 1121 } … … 1030 1125 * is the status change indicator for the single root port. Returns 1 if either 1031 1126 * change indicator is 1, otherwise returns 0. */ 1032 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, 1033 char *_buf) 1034 { 1035 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); 1036 1037 _buf[0] = 0; 1038 _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || 1127 int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 1128 { 1129 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 1130 1131 buf[0] = 0; 1132 buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || 1039 1133 dwc_otg_hcd->flags.b.port_reset_change || 1040 1134 dwc_otg_hcd->flags.b.port_enable_change || 1041 1135 dwc_otg_hcd->flags.b.port_suspend_change || 1042 1136 dwc_otg_hcd->flags.b.port_over_current_change) << 1; 1043 1137 1044 1138 #ifdef DEBUG 1045 if ( _buf[0]) {1139 if (buf[0]) { 1046 1140 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" 1047 1141 " Root port status changed\n"); … … 1058 1152 } 1059 1153 #endif 1060 return ( _buf[0] != 0);1154 return (buf[0] != 0); 1061 1155 } 1062 1156 … … 1573 1667 #endif /* DWC_HS_ELECT_TST */ 1574 1668 1575 /** Handles hub class-specific requests. */1576 int dwc_otg_hcd_hub_control(struct usb_hcd * _hcd,1577 u16 _typeReq,1578 u16 _wValue,1579 u16 _wIndex,1580 char * _buf,1581 u16 _wLength)1669 /** Handles hub class-specific requests. */ 1670 int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, 1671 u16 typeReq, 1672 u16 wValue, 1673 u16 wIndex, 1674 char *buf, 1675 u16 wLength) 1582 1676 { 1583 1677 int retval = 0; 1584 1678 1585 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);1586 dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;1679 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); 1680 dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if; 1587 1681 struct usb_hub_descriptor *desc; 1588 1682 hprt0_data_t hprt0 = {.d32 = 0}; … … 1590 1684 uint32_t port_status; 1591 1685 1592 switch ( _typeReq) {1686 switch (typeReq) { 1593 1687 case ClearHubFeature: 1594 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1595 "ClearHubFeature 0x%x\n", _wValue);1596 switch ( _wValue) {1688 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1689 "ClearHubFeature 0x%x\n", wValue); 1690 switch (wValue) { 1597 1691 case C_HUB_LOCAL_POWER: 1598 1692 case C_HUB_OVER_CURRENT: … … 1601 1695 default: 1602 1696 retval = -EINVAL; 1603 DWC_ERROR ("DWC OTG HCD - "1604 "ClearHubFeature request %xh unknown\n", _wValue);1697 DWC_ERROR("DWC OTG HCD - " 1698 "ClearHubFeature request %xh unknown\n", wValue); 1605 1699 } 1606 1700 break; 1607 1701 case ClearPortFeature: 1608 if (! _wIndex || _wIndex > 1)1702 if (!wIndex || wIndex > 1) 1609 1703 goto error; 1610 1704 1611 switch ( _wValue) {1705 switch (wValue) { 1612 1706 case USB_PORT_FEAT_ENABLE: 1613 DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "1614 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");1615 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1707 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " 1708 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1709 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1616 1710 hprt0.b.prtena = 1; 1617 1711 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1618 1712 break; 1619 1713 case USB_PORT_FEAT_SUSPEND: 1620 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1621 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");1622 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1714 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1715 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1716 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1623 1717 hprt0.b.prtres = 1; 1624 1718 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1625 1719 /* Clear Resume bit */ 1626 mdelay (100);1720 mdelay(100); 1627 1721 hprt0.b.prtres = 0; 1628 1722 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1629 1723 break; 1630 1724 case USB_PORT_FEAT_POWER: 1631 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1632 "ClearPortFeature USB_PORT_FEAT_POWER\n");1633 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1725 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1726 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1727 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1634 1728 hprt0.b.prtpwr = 0; 1635 1729 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1636 1730 break; 1637 1731 case USB_PORT_FEAT_INDICATOR: 1638 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1639 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");1732 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1733 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1640 1734 /* Port inidicator not supported */ 1641 1735 break; … … 1643 1737 /* Clears drivers internal connect status change 1644 1738 * flag */ 1645 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1646 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");1739 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1740 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1647 1741 dwc_otg_hcd->flags.b.port_connect_status_change = 0; 1648 1742 break; … … 1650 1744 /* Clears the driver's internal Port Reset Change 1651 1745 * flag */ 1652 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1653 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");1746 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1747 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1654 1748 dwc_otg_hcd->flags.b.port_reset_change = 0; 1655 1749 break; … … 1657 1751 /* Clears the driver's internal Port 1658 1752 * Enable/Disable Change flag */ 1659 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1660 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");1753 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1754 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1661 1755 dwc_otg_hcd->flags.b.port_enable_change = 0; 1662 1756 break; … … 1665 1759 * Change flag, which is set when resume signaling on 1666 1760 * the host port is complete */ 1667 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1668 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");1761 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1762 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1669 1763 dwc_otg_hcd->flags.b.port_suspend_change = 0; 1670 1764 break; 1671 1765 case USB_PORT_FEAT_C_OVER_CURRENT: 1672 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1673 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");1766 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1767 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1674 1768 dwc_otg_hcd->flags.b.port_over_current_change = 0; 1675 1769 break; 1676 1770 default: 1677 1771 retval = -EINVAL; 1678 DWC_ERROR ("DWC OTG HCD - "1679 "ClearPortFeature request %xh "1680 "unknown or unsupported\n", _wValue);1772 DWC_ERROR("DWC OTG HCD - " 1773 "ClearPortFeature request %xh " 1774 "unknown or unsupported\n", wValue); 1681 1775 } 1682 1776 break; 1683 1777 case GetHubDescriptor: 1684 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1685 "GetHubDescriptor\n");1686 desc = (struct usb_hub_descriptor *) _buf;1778 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1779 "GetHubDescriptor\n"); 1780 desc = (struct usb_hub_descriptor *)buf; 1687 1781 desc->bDescLength = 9; 1688 1782 desc->bDescriptorType = 0x29; … … 1695 1789 break; 1696 1790 case GetHubStatus: 1697 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1698 "GetHubStatus\n");1699 memset (_buf, 0, 4);1791 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1792 "GetHubStatus\n"); 1793 memset(buf, 0, 4); 1700 1794 break; 1701 1795 case GetPortStatus: 1702 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1703 "GetPortStatus\n");1704 1705 if (! _wIndex || _wIndex > 1)1796 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1797 "GetPortStatus\n"); 1798 1799 if (!wIndex || wIndex > 1) 1706 1800 goto error; 1707 1801 … … 1733 1827 * is in device mode. 1734 1828 */ 1735 *((__le32 *) _buf) = cpu_to_le32(port_status);1829 *((__le32 *) buf) = cpu_to_le32(port_status); 1736 1830 break; 1737 1831 } … … 1740 1834 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); 1741 1835 1742 if (hprt0.b.prtconnsts) 1836 if (hprt0.b.prtconnsts) 1743 1837 port_status |= (1 << USB_PORT_FEAT_CONNECTION); 1744 1838 … … 1768 1862 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1769 1863 1770 *((__le32 *) _buf) = cpu_to_le32(port_status);1864 *((__le32 *) buf) = cpu_to_le32(port_status); 1771 1865 1772 1866 break; 1773 1867 case SetHubFeature: 1774 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1775 "SetHubFeature\n");1868 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1869 "SetHubFeature\n"); 1776 1870 /* No HUB features supported */ 1777 1871 break; 1778 1872 case SetPortFeature: 1779 if ( _wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))1873 if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1)) 1780 1874 goto error; 1781 1875 … … 1791 1885 } 1792 1886 1793 switch ( _wValue) {1887 switch (wValue) { 1794 1888 case USB_PORT_FEAT_SUSPEND: 1795 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1796 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");1797 if (_hcd->self.otg_port == _wIndex &&1798 _hcd->self.b_hnp_enable) {1799 gotgctl_data_t gotgctl = {.d32=0};1800 gotgctl.b.hstsethnpen = 1;1801 dwc_modify_reg32(&core_if->core_global_regs->gotgctl,1802 0, gotgctl.d32);1803 core_if->op_state = A_SUSPEND;1804 }1805 hprt0.d32 = dwc_otg_read_hprt0(core_if);1806 hprt0.b.prtsusp = 1;1889 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1890 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1891 if (hcd->self.otg_port == wIndex && 1892 hcd->self.b_hnp_enable) { 1893 gotgctl_data_t gotgctl = {.d32=0}; 1894 gotgctl.b.hstsethnpen = 1; 1895 dwc_modify_reg32(&core_if->core_global_regs->gotgctl, 1896 0, gotgctl.d32); 1897 core_if->op_state = A_SUSPEND; 1898 } 1899 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1900 hprt0.b.prtsusp = 1; 1807 1901 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1808 //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); 1809 /* Suspend the Phy Clock */1810 {1811 pcgcctl_data_t pcgcctl = {.d32=0};1812 pcgcctl.b.stoppclk = 1;1813 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);1814 }1815 1816 /* For HNP the bus must be suspended for at least 200ms.*/1817 if (_hcd->self.b_hnp_enable) {1818 mdelay(200);1819 //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);1820 }1902 //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32); 1903 /* Suspend the Phy Clock */ 1904 { 1905 pcgcctl_data_t pcgcctl = {.d32=0}; 1906 pcgcctl.b.stoppclk = 1; 1907 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); 1908 } 1909 1910 /* For HNP the bus must be suspended for at least 200ms. */ 1911 if (hcd->self.b_hnp_enable) { 1912 mdelay(200); 1913 //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state); 1914 } 1821 1915 break; 1822 1916 case USB_PORT_FEAT_POWER: 1823 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1824 "SetPortFeature - USB_PORT_FEAT_POWER\n");1825 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1917 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1918 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1919 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1826 1920 hprt0.b.prtpwr = 1; 1827 1921 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1828 1922 break; 1829 1923 case USB_PORT_FEAT_RESET: 1830 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1831 "SetPortFeature - USB_PORT_FEAT_RESET\n");1832 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1833 /* When B-Host the Port reset bit is set in1834 * the Start HCD Callback function, so that1835 * the reset is started within 1ms of the HNP1836 * success interrupt. */1837 if (!_hcd->self.is_b_host) {1838 hprt0.b.prtrst = 1;1839 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);1840 }1924 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1925 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1926 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1927 /* When B-Host the Port reset bit is set in 1928 * the Start HCD Callback function, so that 1929 * the reset is started within 1ms of the HNP 1930 * success interrupt. */ 1931 if (!hcd->self.is_b_host) { 1932 hprt0.b.prtrst = 1; 1933 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); 1934 } 1841 1935 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1842 MDELAY (60);1936 MDELAY(60); 1843 1937 hprt0.b.prtrst = 0; 1844 1938 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); … … 1851 1945 gintmsk_data_t gintmsk; 1852 1946 1853 t = ( _wIndex >> 8); /* MSB wIndex USB */1854 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1855 "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);1947 t = (wIndex >> 8); /* MSB wIndex USB */ 1948 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 1949 "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); 1856 1950 warn("USB_PORT_FEAT_TEST %d\n", t); 1857 1951 if (t < 6) { 1858 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1952 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1859 1953 hprt0.b.prttstctl = t; 1860 1954 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); … … 1881 1975 1882 1976 /* Drive suspend on the root port */ 1883 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1977 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1884 1978 hprt0.b.prtsusp = 1; 1885 1979 hprt0.b.prtres = 0; … … 1890 1984 1891 1985 /* Drive resume on the root port */ 1892 hprt0.d32 = dwc_otg_read_hprt0 (core_if);1986 hprt0.d32 = dwc_otg_read_hprt0(core_if); 1893 1987 hprt0.b.prtsusp = 0; 1894 1988 hprt0.b.prtres = 1; … … 1952 2046 1953 2047 case USB_PORT_FEAT_INDICATOR: 1954 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "1955 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");2048 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " 2049 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1956 2050 /* Not supported */ 1957 2051 break; 1958 2052 default: 1959 2053 retval = -EINVAL; 1960 DWC_ERROR ("DWC OTG HCD - "1961 "SetPortFeature request %xh "1962 "unknown or unsupported\n", _wValue);2054 DWC_ERROR("DWC OTG HCD - " 2055 "SetPortFeature request %xh " 2056 "unknown or unsupported\n", wValue); 1963 2057 break; 1964 2058 } … … 1967 2061 error: 1968 2062 retval = -EINVAL; 1969 DWC_WARN ("DWC OTG HCD - "1970 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", 1971 _typeReq, _wIndex, _wValue);2063 DWC_WARN("DWC OTG HCD - " 2064 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", 2065 typeReq, wIndex, wValue); 1972 2066 break; 1973 2067 } … … 1975 2069 return retval; 1976 2070 } 1977 1978 2071 1979 2072 /** … … 1982 2075 * the free list. 1983 2076 * 1984 * @param _hcd The HCD state structure.1985 * @param _qh Transactions from the first QTD for this QH are selected and2077 * @param hcd The HCD state structure. 2078 * @param qh Transactions from the first QTD for this QH are selected and 1986 2079 * assigned to a free host channel. 1987 2080 */ 1988 static void assign_and_init_hc(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t *_qh)2081 static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) 1989 2082 { 1990 2083 dwc_hc_t *hc; … … 1992 2085 struct urb *urb; 1993 2086 1994 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);1995 1996 hc = list_entry( _hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);2087 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh); 2088 2089 hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); 1997 2090 1998 2091 /* Remove the host channel from the free list. */ 1999 2092 list_del_init(&hc->hc_list_entry); 2000 2093 2001 qtd = list_entry( _qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);2094 qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); 2002 2095 urb = qtd->urb; 2003 _qh->channel = hc;2004 _qh->qtd_in_process = qtd;2096 qh->channel = hc; 2097 qh->qtd_in_process = qtd; 2005 2098 2006 2099 /* … … 2019 2112 } 2020 2113 2021 hc->max_packet = dwc_max_packet( _qh->maxp);2114 hc->max_packet = dwc_max_packet(qh->maxp); 2022 2115 2023 2116 hc->xfer_started = 0; … … 2034 2127 * fields in the HCTSIZn register. 2035 2128 */ 2036 hc->do_ping = _qh->ping_state;2129 hc->do_ping = qh->ping_state; 2037 2130 hc->ep_is_in = (usb_pipein(urb->pipe) != 0); 2038 hc->data_pid_start = _qh->data_toggle;2131 hc->data_pid_start = qh->data_toggle; 2039 2132 hc->multi_count = 1; 2040 2133 2041 if ( _hcd->core_if->dma_enable) {2134 if (hcd->core_if->dma_enable) { 2042 2135 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length; 2043 2136 } else { … … 2051 2144 */ 2052 2145 hc->do_split = 0; 2053 if ( _qh->do_split) {2146 if (qh->do_split) { 2054 2147 hc->do_split = 1; 2055 2148 hc->xact_pos = qtd->isoc_split_pos; … … 2068 2161 hc->ep_is_in = 0; 2069 2162 hc->data_pid_start = DWC_OTG_HC_PID_SETUP; 2070 if ( _hcd->core_if->dma_enable) {2163 if (hcd->core_if->dma_enable) { 2071 2164 hc->xfer_buff = (uint8_t *)urb->setup_dma; 2072 2165 } else { … … 2095 2188 hc->data_pid_start = DWC_OTG_HC_PID_DATA1; 2096 2189 hc->xfer_len = 0; 2097 if ( _hcd->core_if->dma_enable) {2098 hc->xfer_buff = (uint8_t *) _hcd->status_buf_dma;2190 if (hcd->core_if->dma_enable) { 2191 hc->xfer_buff = (uint8_t *)hcd->status_buf_dma; 2099 2192 } else { 2100 hc->xfer_buff = (uint8_t *) _hcd->status_buf;2193 hc->xfer_buff = (uint8_t *)hcd->status_buf; 2101 2194 } 2102 2195 break; … … 2114 2207 frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; 2115 2208 hc->ep_type = DWC_OTG_EP_TYPE_ISOC; 2116 if ( _hcd->core_if->dma_enable) {2209 if (hcd->core_if->dma_enable) { 2117 2210 hc->xfer_buff = (uint8_t *)urb->transfer_dma; 2118 2211 } else { … … 2140 2233 * reflect the actual transfer length. 2141 2234 */ 2142 hc->multi_count = dwc_hb_mult( _qh->maxp);2143 } 2144 2145 dwc_otg_hc_init( _hcd->core_if, hc);2146 hc->qh = _qh;2235 hc->multi_count = dwc_hb_mult(qh->maxp); 2236 } 2237 2238 dwc_otg_hc_init(hcd->core_if, hc); 2239 hc->qh = qh; 2147 2240 } 2148 2241 … … 2152 2245 * handler functions. 2153 2246 * 2154 * @param _hcd The HCD state structure.2247 * @param hcd The HCD state structure. 2155 2248 * 2156 2249 * @return The types of new transactions that were assigned to host channels. 2157 2250 */ 2158 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * _hcd)2251 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd) 2159 2252 { 2160 2253 struct list_head *qh_ptr; … … 2168 2261 2169 2262 /* Process entries in the periodic ready list. */ 2170 qh_ptr = _hcd->periodic_sched_ready.next;2171 while (qh_ptr != & _hcd->periodic_sched_ready &&2172 !list_empty(& _hcd->free_hc_list)) {2263 qh_ptr = hcd->periodic_sched_ready.next; 2264 while (qh_ptr != &hcd->periodic_sched_ready && 2265 !list_empty(&hcd->free_hc_list)) { 2173 2266 2174 2267 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); 2175 assign_and_init_hc( _hcd, qh);2268 assign_and_init_hc(hcd, qh); 2176 2269 2177 2270 /* … … 2180 2273 */ 2181 2274 qh_ptr = qh_ptr->next; 2182 list_move(&qh->qh_list_entry, & _hcd->periodic_sched_assigned);2275 list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned); 2183 2276 2184 2277 ret_val = DWC_OTG_TRANSACTION_PERIODIC; … … 2190 2283 * reserved for periodic transfers. 2191 2284 */ 2192 qh_ptr = _hcd->non_periodic_sched_inactive.next;2193 num_channels = _hcd->core_if->core_params->host_channels;2194 while (qh_ptr != & _hcd->non_periodic_sched_inactive &&2195 ( _hcd->non_periodic_channels <2196 num_channels - _hcd->periodic_channels) &&2197 !list_empty(& _hcd->free_hc_list)) {2285 qh_ptr = hcd->non_periodic_sched_inactive.next; 2286 num_channels = hcd->core_if->core_params->host_channels; 2287 while (qh_ptr != &hcd->non_periodic_sched_inactive && 2288 (hcd->non_periodic_channels < 2289 num_channels - hcd->periodic_channels) && 2290 !list_empty(&hcd->free_hc_list)) { 2198 2291 2199 2292 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); 2200 assign_and_init_hc( _hcd, qh);2293 assign_and_init_hc(hcd, qh); 2201 2294 2202 2295 /* … … 2205 2298 */ 2206 2299 qh_ptr = qh_ptr->next; 2207 list_move(&qh->qh_list_entry, & _hcd->non_periodic_sched_active);2300 list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active); 2208 2301 2209 2302 if (ret_val == DWC_OTG_TRANSACTION_NONE) { … … 2213 2306 } 2214 2307 2215 _hcd->non_periodic_channels++;2308 hcd->non_periodic_channels++; 2216 2309 } 2217 2310 … … 2226 2319 * is available in the appropriate Tx FIFO. 2227 2320 * 2228 * @param _hcd The HCD state structure.2229 * @param _hc Host channel descriptor associated with either a periodic or2321 * @param hcd The HCD state structure. 2322 * @param hc Host channel descriptor associated with either a periodic or 2230 2323 * non-periodic transfer. 2231 * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx2324 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx 2232 2325 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic 2233 2326 * transfers. … … 2237 2330 * transfer, -1 if there is insufficient space in the Tx FIFO. 2238 2331 */ 2239 static int queue_transaction(dwc_otg_hcd_t * _hcd,2240 dwc_hc_t * _hc,2241 uint16_t _fifo_dwords_avail)2332 static int queue_transaction(dwc_otg_hcd_t *hcd, 2333 dwc_hc_t *hc, 2334 uint16_t fifo_dwords_avail) 2242 2335 { 2243 2336 int retval; 2244 2337 2245 if ( _hcd->core_if->dma_enable) {2246 if (! _hc->xfer_started) {2247 dwc_otg_hc_start_transfer( _hcd->core_if, _hc);2248 _hc->qh->ping_state = 0;2338 if (hcd->core_if->dma_enable) { 2339 if (!hc->xfer_started) { 2340 dwc_otg_hc_start_transfer(hcd->core_if, hc); 2341 hc->qh->ping_state = 0; 2249 2342 } 2250 2343 retval = 0; 2251 } else if (_hc->halt_pending) {2344 } else if (hc->halt_pending) { 2252 2345 /* Don't queue a request if the channel has been halted. */ 2253 2346 retval = 0; 2254 } else if ( _hc->halt_on_queue) {2255 dwc_otg_hc_halt( _hcd->core_if, _hc, _hc->halt_status);2347 } else if (hc->halt_on_queue) { 2348 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); 2256 2349 retval = 0; 2257 } else if ( _hc->do_ping) {2258 if (! _hc->xfer_started) {2259 dwc_otg_hc_start_transfer( _hcd->core_if, _hc);2350 } else if (hc->do_ping) { 2351 if (!hc->xfer_started) { 2352 dwc_otg_hc_start_transfer(hcd->core_if, hc); 2260 2353 } 2261 2354 retval = 0; 2262 } else if (! _hc->ep_is_in ||2263 _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {2264 if (( _fifo_dwords_avail * 4) >= _hc->max_packet) {2265 if (! _hc->xfer_started) {2266 dwc_otg_hc_start_transfer( _hcd->core_if, _hc);2355 } else if (!hc->ep_is_in || 2356 hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { 2357 if ((fifo_dwords_avail * 4) >= hc->max_packet) { 2358 if (!hc->xfer_started) { 2359 dwc_otg_hc_start_transfer(hcd->core_if, hc); 2267 2360 retval = 1; 2268 2361 } else { 2269 retval = dwc_otg_hc_continue_transfer( _hcd->core_if, _hc);2362 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); 2270 2363 } 2271 2364 } else { 2272 2365 retval = -1; 2273 2366 } 2274 } else { 2275 if (! _hc->xfer_started) {2276 dwc_otg_hc_start_transfer( _hcd->core_if, _hc);2367 } else { 2368 if (!hc->xfer_started) { 2369 dwc_otg_hc_start_transfer(hcd->core_if, hc); 2277 2370 retval = 1; 2278 2371 } else { 2279 retval = dwc_otg_hc_continue_transfer( _hcd->core_if, _hc);2372 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); 2280 2373 } 2281 2374 } … … 2291 2384 * FIFO Empty interrupt is disabled. 2292 2385 */ 2293 static void process_non_periodic_channels(dwc_otg_hcd_t * _hcd)2386 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd) 2294 2387 { 2295 2388 gnptxsts_data_t tx_status; … … 2301 2394 int more_to_do = 0; 2302 2395 2303 dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;2396 dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs; 2304 2397 2305 2398 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); 2306 #ifdef DEBUG 2399 #ifdef DEBUG 2307 2400 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); 2308 2401 DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", … … 2315 2408 * entry. 2316 2409 */ 2317 if ( _hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {2318 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;2319 } 2320 orig_qh_ptr = _hcd->non_periodic_qh_ptr;2410 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { 2411 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; 2412 } 2413 orig_qh_ptr = hcd->non_periodic_qh_ptr; 2321 2414 2322 2415 /* … … 2326 2419 do { 2327 2420 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); 2328 if (! _hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {2421 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { 2329 2422 no_queue_space = 1; 2330 2423 break; 2331 2424 } 2332 2425 2333 qh = list_entry( _hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);2334 status = queue_transaction( _hcd, qh->channel, tx_status.b.nptxfspcavail);2426 qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); 2427 status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail); 2335 2428 2336 2429 if (status > 0) { … … 2342 2435 2343 2436 /* Advance to next QH, skipping start-of-list entry. */ 2344 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;2345 if ( _hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {2346 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;2347 } 2348 2349 } while ( _hcd->non_periodic_qh_ptr != orig_qh_ptr);2350 2351 if (! _hcd->core_if->dma_enable) {2437 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; 2438 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { 2439 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; 2440 } 2441 2442 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); 2443 2444 if (!hcd->core_if->dma_enable) { 2352 2445 gintmsk_data_t intr_mask = {.d32 = 0}; 2353 2446 intr_mask.b.nptxfempty = 1; 2354 2447 2355 #ifdef DEBUG 2448 #ifdef DEBUG 2356 2449 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); 2357 2450 DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", … … 2389 2482 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2390 2483 */ 2391 static void process_periodic_channels(dwc_otg_hcd_t * _hcd)2484 static void process_periodic_channels(dwc_otg_hcd_t *hcd) 2392 2485 { 2393 2486 hptxsts_data_t tx_status; … … 2399 2492 2400 2493 dwc_otg_host_global_regs_t *host_regs; 2401 host_regs = _hcd->core_if->host_if->host_global_regs;2494 host_regs = hcd->core_if->host_if->host_global_regs; 2402 2495 2403 2496 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); 2404 #ifdef DEBUG 2497 #ifdef DEBUG 2405 2498 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); 2406 2499 DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", … … 2410 2503 #endif 2411 2504 2412 qh_ptr = _hcd->periodic_sched_assigned.next;2413 while (qh_ptr != & _hcd->periodic_sched_assigned) {2505 qh_ptr = hcd->periodic_sched_assigned.next; 2506 while (qh_ptr != &hcd->periodic_sched_assigned) { 2414 2507 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); 2415 2508 if (tx_status.b.ptxqspcavail == 0) { … … 2425 2518 * the middle of multiple high-bandwidth packets getting queued. 2426 2519 */ 2427 if ( (!_hcd->core_if->dma_enable) &&2428 (qh->channel->multi_count > 1))2520 if (!hcd->core_if->dma_enable && 2521 qh->channel->multi_count > 1) 2429 2522 { 2430 _hcd->core_if->queuing_high_bandwidth = 1;2431 } 2432 2433 status = queue_transaction( _hcd, qh->channel, tx_status.b.ptxfspcavail);2523 hcd->core_if->queuing_high_bandwidth = 1; 2524 } 2525 2526 status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail); 2434 2527 if (status < 0) { 2435 2528 no_fifo_space = 1; … … 2444 2537 * high-bandwidth transfers. 2445 2538 */ 2446 if (_hcd->core_if->dma_enable || 2447 (status == 0 || 2448 qh->channel->requests == qh->channel->multi_count)) { 2539 if (hcd->core_if->dma_enable || status == 0 || 2540 qh->channel->requests == qh->channel->multi_count) { 2449 2541 qh_ptr = qh_ptr->next; 2450 2542 /* … … 2452 2544 * the periodic queued schedule. 2453 2545 */ 2454 list_move(&qh->qh_list_entry, & _hcd->periodic_sched_queued);2546 list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued); 2455 2547 2456 2548 /* done queuing high bandwidth */ 2457 _hcd->core_if->queuing_high_bandwidth = 0;2458 } 2459 } 2460 2461 if (! _hcd->core_if->dma_enable) {2549 hcd->core_if->queuing_high_bandwidth = 0; 2550 } 2551 } 2552 2553 if (!hcd->core_if->dma_enable) { 2462 2554 dwc_otg_core_global_regs_t *global_regs; 2463 2555 gintmsk_data_t intr_mask = {.d32 = 0}; 2464 2556 2465 global_regs = _hcd->core_if->core_global_regs;2557 global_regs = hcd->core_if->core_global_regs; 2466 2558 intr_mask.b.ptxfempty = 1; 2467 #ifdef DEBUG 2559 #ifdef DEBUG 2468 2560 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); 2469 2561 DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", … … 2472 2564 tx_status.b.ptxfspcavail); 2473 2565 #endif 2474 if (! (list_empty(&_hcd->periodic_sched_assigned)) ||2566 if (!list_empty(&hcd->periodic_sched_assigned) || 2475 2567 no_queue_space || no_fifo_space) { 2476 2568 /* … … 2492 2584 dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); 2493 2585 } 2494 } 2586 } 2495 2587 } 2496 2588 … … 2500 2592 * from HCD interrupt handler functions. 2501 2593 * 2502 * @param _hcd The HCD state structure.2503 * @param _tr_type The type(s) of transactions to queue (non-periodic,2594 * @param hcd The HCD state structure. 2595 * @param tr_type The type(s) of transactions to queue (non-periodic, 2504 2596 * periodic, or both). 2505 2597 */ 2506 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * _hcd,2507 dwc_otg_transaction_type_e _tr_type)2598 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, 2599 dwc_otg_transaction_type_e tr_type) 2508 2600 { 2509 2601 #ifdef DEBUG_SOF … … 2511 2603 #endif 2512 2604 /* Process host channels associated with periodic transfers. */ 2513 if (( _tr_type == DWC_OTG_TRANSACTION_PERIODIC ||2514 _tr_type == DWC_OTG_TRANSACTION_ALL) &&2515 !list_empty(& _hcd->periodic_sched_assigned)) {2516 2517 process_periodic_channels( _hcd);2605 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || 2606 tr_type == DWC_OTG_TRANSACTION_ALL) && 2607 !list_empty(&hcd->periodic_sched_assigned)) { 2608 2609 process_periodic_channels(hcd); 2518 2610 } 2519 2611 2520 2612 /* Process host channels associated with non-periodic transfers. */ 2521 if ( (_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||2522 _tr_type == DWC_OTG_TRANSACTION_ALL)) {2523 if (!list_empty(& _hcd->non_periodic_sched_active)) {2524 process_non_periodic_channels( _hcd);2613 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || 2614 tr_type == DWC_OTG_TRANSACTION_ALL) { 2615 if (!list_empty(&hcd->non_periodic_sched_active)) { 2616 process_non_periodic_channels(hcd); 2525 2617 } else { 2526 2618 /* … … 2530 2622 gintmsk_data_t gintmsk = {.d32 = 0}; 2531 2623 gintmsk.b.nptxfempty = 1; 2532 dwc_modify_reg32(& _hcd->core_if->core_global_regs->gintmsk,2624 dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk, 2533 2625 gintmsk.d32, 0); 2534 2626 } … … 2540 2632 * required cleanup of the URB is performed. 2541 2633 */ 2542 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb, int _status)2634 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status) 2543 2635 { 2544 2636 #ifdef DEBUG 2545 2637 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { 2546 2638 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", 2547 __func__, _urb, usb_pipedevice(_urb->pipe),2548 usb_pipeendpoint( _urb->pipe),2549 usb_pipein( _urb->pipe) ? "IN" : "OUT", _status);2550 if (usb_pipetype( _urb->pipe) == PIPE_ISOCHRONOUS) {2639 __func__, urb, usb_pipedevice(urb->pipe), 2640 usb_pipeendpoint(urb->pipe), 2641 usb_pipein(urb->pipe) ? "IN" : "OUT", status); 2642 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2551 2643 int i; 2552 for (i = 0; i < _urb->number_of_packets; i++) {2644 for (i = 0; i < urb->number_of_packets; i++) { 2553 2645 DWC_PRINT(" ISO Desc %d status: %d\n", 2554 i, _urb->iso_frame_desc[i].status);2646 i, urb->iso_frame_desc[i].status); 2555 2647 } 2556 2648 } … … 2558 2650 #endif 2559 2651 2560 _urb->status = _status; 2561 _urb->hcpriv = NULL; 2562 usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb); 2652 urb->status = status; 2653 urb->hcpriv = NULL; 2654 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) 2655 usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); 2656 #else 2657 usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, NULL); 2658 #endif 2563 2659 } 2564 2660 … … 2566 2662 * Returns the Queue Head for an URB. 2567 2663 */ 2568 dwc_otg_qh_t *dwc_urb_to_qh(struct urb * _urb)2569 { 2570 struct usb_host_endpoint *ep = dwc_urb_to_endpoint( _urb);2664 dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb) 2665 { 2666 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); 2571 2667 return (dwc_otg_qh_t *)ep->hcpriv; 2572 2668 } 2573 2669 2574 2670 #ifdef DEBUG 2575 void dwc_print_setup_data (uint8_t *setup)2671 void dwc_print_setup_data(uint8_t *setup) 2576 2672 { 2577 2673 int i; 2578 2674 if (CHK_DEBUG_LEVEL(DBG_HCD)){ 2579 2675 DWC_PRINT("Setup Data = MSB "); 2580 for (i =7; i>=0; i--) DWC_PRINT("%02x ", setup[i]);2676 for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]); 2581 2677 DWC_PRINT("\n"); 2582 DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] &0x80) ? "Device-to-Host" : "Host-to-Device");2678 DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device"); 2583 2679 DWC_PRINT(" bmRequestType Type = "); 2584 switch ((setup[0] &0x60) >> 5) {2680 switch ((setup[0] & 0x60) >> 5) { 2585 2681 case 0: DWC_PRINT("Standard\n"); break; 2586 2682 case 1: DWC_PRINT("Class\n"); break; … … 2589 2685 } 2590 2686 DWC_PRINT(" bmRequestType Recipient = "); 2591 switch (setup[0] &0x1f) {2687 switch (setup[0] & 0x1f) { 2592 2688 case 0: DWC_PRINT("Device\n"); break; 2593 2689 case 1: DWC_PRINT("Interface\n"); break; … … 2604 2700 #endif 2605 2701 2606 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * _hcd) {2607 #if def DEBUG2702 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) { 2703 #if defined(DEBUG) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) 2608 2704 DWC_PRINT("Frame remaining at SOF:\n"); 2609 2705 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2610 _hcd->frrem_samples, _hcd->frrem_accum,2611 ( _hcd->frrem_samples > 0) ?2612 _hcd->frrem_accum/_hcd->frrem_samples : 0);2706 hcd->frrem_samples, hcd->frrem_accum, 2707 (hcd->frrem_samples > 0) ? 2708 hcd->frrem_accum/hcd->frrem_samples : 0); 2613 2709 2614 2710 DWC_PRINT("\n"); 2615 2711 DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); 2616 2712 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2617 _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,2618 ( _hcd->core_if->hfnum_7_samples > 0) ?2619 _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);2713 hcd->core_if->hfnum_7_samples, hcd->core_if->hfnum_7_frrem_accum, 2714 (hcd->core_if->hfnum_7_samples > 0) ? 2715 hcd->core_if->hfnum_7_frrem_accum/hcd->core_if->hfnum_7_samples : 0); 2620 2716 DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); 2621 2717 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2622 _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,2623 ( _hcd->core_if->hfnum_0_samples > 0) ?2624 _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);2718 hcd->core_if->hfnum_0_samples, hcd->core_if->hfnum_0_frrem_accum, 2719 (hcd->core_if->hfnum_0_samples > 0) ? 2720 hcd->core_if->hfnum_0_frrem_accum/hcd->core_if->hfnum_0_samples : 0); 2625 2721 DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); 2626 2722 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2627 _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,2628 ( _hcd->core_if->hfnum_other_samples > 0) ?2629 _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);2723 hcd->core_if->hfnum_other_samples, hcd->core_if->hfnum_other_frrem_accum, 2724 (hcd->core_if->hfnum_other_samples > 0) ? 2725 hcd->core_if->hfnum_other_frrem_accum/hcd->core_if->hfnum_other_samples : 0); 2630 2726 2631 2727 DWC_PRINT("\n"); 2632 2728 DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); 2633 2729 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2634 _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,2635 ( _hcd->hfnum_7_samples_a > 0) ?2636 _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);2730 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, 2731 (hcd->hfnum_7_samples_a > 0) ? 2732 hcd->hfnum_7_frrem_accum_a/hcd->hfnum_7_samples_a : 0); 2637 2733 DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); 2638 2734 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2639 _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,2640 ( _hcd->hfnum_0_samples_a > 0) ?2641 _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);2735 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, 2736 (hcd->hfnum_0_samples_a > 0) ? 2737 hcd->hfnum_0_frrem_accum_a/hcd->hfnum_0_samples_a : 0); 2642 2738 DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); 2643 2739 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2644 _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,2645 ( _hcd->hfnum_other_samples_a > 0) ?2646 _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);2740 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, 2741 (hcd->hfnum_other_samples_a > 0) ? 2742 hcd->hfnum_other_frrem_accum_a/hcd->hfnum_other_samples_a : 0); 2647 2743 2648 2744 DWC_PRINT("\n"); 2649 2745 DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); 2650 2746 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2651 _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,2652 ( _hcd->hfnum_7_samples_b > 0) ?2653 _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);2747 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, 2748 (hcd->hfnum_7_samples_b > 0) ? 2749 hcd->hfnum_7_frrem_accum_b/hcd->hfnum_7_samples_b : 0); 2654 2750 DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); 2655 2751 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2656 _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,2657 ( _hcd->hfnum_0_samples_b > 0) ?2658 _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);2752 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, 2753 (hcd->hfnum_0_samples_b > 0) ? 2754 hcd->hfnum_0_frrem_accum_b/hcd->hfnum_0_samples_b : 0); 2659 2755 DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); 2660 2756 DWC_PRINT(" samples %u, accum %llu, avg %llu\n", 2661 _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,2662 ( _hcd->hfnum_other_samples_b > 0) ?2663 _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);2664 #endif 2665 } 2666 2667 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * _hcd)2757 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, 2758 (hcd->hfnum_other_samples_b > 0) ? 2759 hcd->hfnum_other_frrem_accum_b/hcd->hfnum_other_samples_b : 0); 2760 #endif 2761 } 2762 2763 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd) 2668 2764 { 2669 2765 #ifdef DEBUG … … 2673 2769 hptxsts_data_t p_tx_status; 2674 2770 2675 num_channels = _hcd->core_if->core_params->host_channels;2771 num_channels = hcd->core_if->core_params->host_channels; 2676 2772 DWC_PRINT("\n"); 2677 2773 DWC_PRINT("************************************************************\n"); … … 2679 2775 DWC_PRINT(" Num channels: %d\n", num_channels); 2680 2776 for (i = 0; i < num_channels; i++) { 2681 dwc_hc_t *hc = _hcd->hc_ptr_array[i];2777 dwc_hc_t *hc = hcd->hc_ptr_array[i]; 2682 2778 DWC_PRINT(" Channel %d:\n", i); 2683 2779 DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", … … 2708 2804 hcint_data_t hcint; 2709 2805 hcintmsk_data_t hcintmsk; 2710 hfnum.d32 = dwc_read_reg32(& _hcd->core_if->host_if->host_global_regs->hfnum);2711 hcchar.d32 = dwc_read_reg32(& _hcd->core_if->host_if->hc_regs[i]->hcchar);2712 hctsiz.d32 = dwc_read_reg32(& _hcd->core_if->host_if->hc_regs[i]->hctsiz);2713 hcint.d32 = dwc_read_reg32(& _hcd->core_if->host_if->hc_regs[i]->hcint);2714 hcintmsk.d32 = dwc_read_reg32(& _hcd->core_if->host_if->hc_regs[i]->hcintmsk);2806 hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); 2807 hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar); 2808 hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz); 2809 hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint); 2810 hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk); 2715 2811 DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); 2716 2812 DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); … … 2719 2815 DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); 2720 2816 } 2721 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {2817 if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) { 2722 2818 dwc_otg_qtd_t *qtd; 2723 2819 struct urb *urb; … … 2726 2822 DWC_PRINT(" URB Info:\n"); 2727 2823 DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); 2728 if (urb != NULL) {2824 if (urb) { 2729 2825 DWC_PRINT(" Dev: %d, EP: %d %s\n", 2730 2826 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), … … 2739 2835 } 2740 2836 } 2741 DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels);2742 DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels);2743 DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs);2744 np_tx_status.d32 = dwc_read_reg32(& _hcd->core_if->core_global_regs->gnptxsts);2837 DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels); 2838 DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels); 2839 DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs); 2840 np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts); 2745 2841 DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); 2746 2842 DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); 2747 p_tx_status.d32 = dwc_read_reg32(& _hcd->core_if->host_if->host_global_regs->hptxsts);2843 p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts); 2748 2844 DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); 2749 2845 DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); 2750 dwc_otg_hcd_dump_frrem( _hcd);2751 dwc_otg_dump_global_registers( _hcd->core_if);2752 dwc_otg_dump_host_registers( _hcd->core_if);2846 dwc_otg_hcd_dump_frrem(hcd); 2847 dwc_otg_dump_global_registers(hcd->core_if); 2848 dwc_otg_dump_host_registers(hcd->core_if); 2753 2849 DWC_PRINT("************************************************************\n"); 2754 2850 DWC_PRINT("\n");
